NEC uPD75P3116 инструкция обслуживания

1994 DATA SHEET The µ PD75P3116 replaces the µ PD753108’s internal mask ROM with a one-time PROM, and features expanded ROM capacity. Because the µ PD75P3116 supports programming by users, it is suitable for use in evaluation of systems in the development stage using the µ PD753104, 753106, or 753108, and for use in small-scale production. De[...]

µ PD75P31 16 2 Data Sheet U11369EJ3V0DS FUNCTION OUTLINE Item Function Instruction execution time • 0.95, 1.91, 3.81, or 15.3 µ s (main system clock: @ 4.19 MHz) • 0.67, 1.33, 2.67, or 10.7 µ s (main system clock: @ 6.0 MHz) • 122 µ s (subsystem clock: @ 32.768 kHz) Internal memory PROM 16384 × 8 bits RAM 512 × 4 bits General-purpose re[...]

µ PD75P31 16 3 Data Sheet U11369EJ3V0DS CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ................................................................................................. 4 2. BLOCK DIAGRAM ................................................................................................................ ............ 6 3. PIN FUNCTIONS ......[...]

µ PD75P31 16 4 Data Sheet U11369EJ3V0DS 1. PIN CONFIGURATION (TOP VIEW) • 64-pin plastic QFP (14 × 14): µ PD75P3116GC-AB8 • 64-pin plastic LQFP (12 × 12): µ PD75P3116GK-8A8 • 64-pin plastic LQFP (14 × 14): µ PD75P3116GC-8BS Note Always connect the V PP pin directly to V DD during normal operation. 48 S12 47 S13 46 S14 45 S15 44 P93/S16[...]

µ PD75P31 16 5 Data Sheet U11369EJ3V0DS PIN IDENTIFICATIONS P00 to P03: Port 0 COM0 to COM3: Common output 0 to 3 P10 to P13: Port 1 V LC0 to V LC2 : LCD power supply 0 to 2 P20 to P23: Port 2 BIAS: LCD power supply bias control P30 to P33: Port 3 LCDCL: LCD clock P50 to P53: Port 5 SYNC: LCD synchronization P60 to P63: Port 6 TI0 to TI2: Timer in[...]

µ PD75P31 16 6 Data Sheet U11369EJ3V0DS 2. BLOCK DIAGRAM P20 to P23 P00 to P03 S0 to S15 16 4 4 4 4 4 4 4 4 COM0 to COM3 4 BIAS f LCD V PP V DD RESET Vss CPU clock Φ Standby control X2 X1 XT2 XT1 System clock generator Main Sub Clock divider Clock output control fx/2 N PCL/PTO2/P22 General- purpose register Data memory (RAM) 512 × 4 bits Bank SB[...]

µ PD75P31 16 7 Data Sheet U11369EJ3V0DS 3. PIN FUNCTIONS 3.1 Port Pins (1/2) Pin Name I/O Alternate Function 8-Bit Status I/O Circuit Function I/O After Reset Type Note 1 P00 Input INT4 4-bit input port (Port 0) — Input <B> Connection of an internal pull-up resistor can be P01 SCK specified by a software setting in 3-bit units. <F>-A[...]

µ PD75P3116 8 Data Sheet U11369EJ3V0DS 3.1 Port Pins (2/2) Pin Name I/O Alternate Function 8-Bit Status I/O Circuit Function I/O After Reset Type Note 1 P60 I/O KR0/D0 Programmable 4-bit I/O port (Port 6) — Input <F>-A Input and output can be specified in 1-bit units. P61 KR1/D1 Connection of an internal pull-up resistor can be specified b[...]

µ PD75P31 16 9 Data Sheet U11369EJ3V0DS 3.2 Non-Port Pins (1/2) Pin Name I/O Alternate Function Status I/O Circuit Function After Reset Type Note 1 TI0 Input P13 External event pulse input to timer/event counter Input <B>-C TI1 P12/INT2/TI2 TI2 P12/INT2/TI1 PTO0 Output P20 Timer/event counter output Input E-B PTO1 P21 PTO2 P22/PCL PCL P22/PT[...]

µ PD75P31 16 10 Data Sheet U11369EJ3V0DS 3.2 Non-Port Pins (2/2) Pin Name I/O Alternate Function Status I/O Circuit Function After Reset Type S0 to S15 Output — Segment signal output Note 1 G-A S16 to S19 Output P93 to P90 Segment signal output Input H S20 to S23 Output P83 to P80 Segment signal output Input H COM0 to COM3 Output — Common sign[...]

µ PD75P3116 11 Data Sheet U11369EJ3V0DS 3.3 Pin I/O Circuits The I/O circuits for the µ PD75P3116’s pins are shown in abbreviated form below. IN V DD P-ch N-ch V DD P-ch N-ch OUT Data Output disable IN V DD P-ch IN/OUT P.U.R. enable Data P.U.R. Type D Output disable P.U.R. : Pull-Up Resistor Type A V DD P-ch P.U.R. enable P.U.R. P.U.R. : Pull-U[...]

µ PD75P31 16 12 Data Sheet U11369EJ3V0DS (Continued) Type F-B Type H Type M-C Type G-A Type G-B Type M-E Output disable V DD P-ch N-ch IN/OUT Data V DD P-ch P.U.R. enable P.U.R. Output disable (N) Output disable (P) P.U.R. : Pull-Up Resistor IN/OUT Type G-A Type E-B SEG data Output disable Data V DD P-ch IN/OUT P.U.R. enable Data P.U.R. Output dis[...]

µ PD75P3116 13 Data Sheet U11369EJ3V0DS 3.4 Recommended Connection of Unused Pins Table 3-1. List of Unused Pin Connections Pin Recommended Connection P00/INT4 Connect to Vss or V DD . P01/SCK Input: Independently connect to Vss or V DD via a resistor. P02/SO/SB0 Output: Leave open. P03/SI/SB1 Connect to Vss. P10/INT0 and P11/INT1 Connect to Vss o[...]

µ PD75P3116 14 Data Sheet U11369EJ3V0DS 4. Mk I AND Mk II MODE SELECTION FUNCTION Setting the stack bank selection (SBS) register for the µ PD75P3116 enables the program memory to be switched between the Mk I mode and Mk II mode. This function is applicable when using the µ PD75P3116 to evaluate the µ PD753104, 753106, or 753108. When bit 3 of [...]

µ PD75P3116 15 Data Sheet U11369EJ3V0DS 4.2 Setting of Stack Bank Selection (SBS) Register Use the stack bank selection register to switch between the Mk I mode and Mk II mode. Figure 4-1 shows the format of the stack bank selection register. The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk [...]

µ PD75P3116 16 Data Sheet U11369EJ3V0DS 5. DIFFERENCES BETWEEN µ PD75P3116 AND µ PD753104, 753106, 753108 The µ PD75P3116 replaces the internal mask ROM in the µ PD753104, 753106, and 753108 with a one-time PROM and features expanded ROM capacity. The µ PD75P3116’s Mk I mode supports the Mk I mode in the µ PD753104, 753106, and 753108 and [...]

µ PD75P31 16 17 Data Sheet U11369EJ3V0DS 6. MEMORY CONFIGURATION Figure 6-1. Program Memory Map Note Can only be used in the Mk II mode. Remark For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to branch to addresses with changes in the PC’s lower 8 bits only. MBE MBE MBE MBE MBE MBE MBE RBE RBE RBE [...]

µ PD75P31 16 18 Data Sheet U11369EJ3V0DS Figure 6-2. Data Memory Map Note Memory bank 0 or 1 can be selected as the stack area. (32 × 4) 256 × 4 (224 × 4) 128 × 4 0 1 15 000H 01FH 020H 0FFH 100H 1E0H 1DFH 1F7H 1F8H F80H FFFH General-purpose register area Display data memory Data area static RAM (512 × 4) Stack area Note Peripheral hardware ar[...]

µ PD75P3116 19 Data Sheet U11369EJ3V0DS 7. INSTRUCTION SET (1) Representation and coding formats for operands In the instruction’s operand area, use the following coding format to describe operands corresponding to the instruction’s operand representations (for further details, refer to the RA75X Assembler Package Language User’s Manual (U12[...]

µ PD75P31 16 20 Data Sheet U11369EJ3V0DS (2) Operation conventions A: A register; 4-bit accumulator B: B register C: C register D: D register E: E register H: H register L: L register X: X register XA: Register pair (XA); 8-bit accumulator BC: Register pair (BC) DE: Register pair (DE) HL: Register pair (HL) XA ’ : Expansion register pair (XA ’[...]

µ PD75P3116 21 Data Sheet U11369EJ3V0DS (3) Description of symbols used in addressing area Remarks 1. MB indicates access-enabled memory banks. 2. In area *2, MB = 0 for both MBE and MBS. 3. In areas *4 and *5, MB = 15 for both MBE and MBS. 4. Areas *6 to *11 indicate corresponding address-enabled areas. (4) Description of machine cycles S indicat[...]

µ PD75P3116 22 Data Sheet U11369EJ3V0DS Instruction Mnemonic Operand No. of Machine Operation Addressing Skip Group Bytes Cycle Area Condition Transfer MOV A, #n4 1 1 A ← n4 String-effect A reg1, #n4 2 2 reg1 ← n4 XA, #n8 2 2 XA ← n8 String-effect A HL, #n8 2 2 HL ← n8 String-effect B rp2, #n8 2 2 rp2 ← n8 A, @HL 1 1 A ← (HL) *1 A, @HL[...]

µ PD75P3116 23 Data Sheet U11369EJ3V0DS Instruction Mnemonic Operand No. of Machine Operation Addressing Skip Group Bytes Cycle Area Condition Bit transfer MOV1 CY, fmem.bit 2 2 CY ← (fmem.bit) *4 CY, pmem.@L 2 2 CY ← (pmem 7-2 +L 3-2 .bit(L 1-0 )) *5 CY, @H+mem.bit 2 2 CY ← (H+mem 3-0 .bit) *1 fmem.bit, CY 2 2 (fmem.bit) ← CY *4 pmem.@L, [...]

µ PD75P3116 24 Data Sheet U11369EJ3V0DS Instruction Mnemonic Operand No. of Machine Operation Addressing Skip Group Bytes Cycle Area Condition Comparison SKE reg, #n4 2 2+S Skip if reg=n4 reg = n4 @HL, #n4 2 2+S Skip if (HL)=n4 *1 (HL) = n4 A, @HL 1 1+S Skip if A=(HL) *1 A = (HL) XA, @HL 2 2+S Skip if XA=(HL) *1 XA = (HL) A, reg 2 2+S Skip if A=re[...]

µ PD75P31 16 25 Data Sheet U11369EJ3V0DS Instruction Mnemonic Operand No. of Machine Operation Addressing Skip Group Bytes Cycle Area Condition Branch BR Note 1 addr —— PC 13-0 ← addr *6 Use the assembler to select the most appropriate instruction among the following. • BR !addr • BRCB !caddr • BR $addr addr1 —— PC 13-0 ← addr1 *[...]

µ PD75P31 16 26 Data Sheet U11369EJ3V0DS Instruction Mnemonic Operand No. of Machine Operation Addressing Skip Group Bytes Cycle Area Condition Subroutine CALLA Note !addr1 3 3 (SP–6)(SP–3)(SP–4) ← PC 11-0 *11 stack control (SP–5) ← 0, 0, PC 13 , 12 (SP–2) ← X, X, MBE, RBE PC 13-0 ← addr1, SP ← SP–6 CALL Note !addr 3 3 (SP–[...]

µ PD75P31 16 27 Data Sheet U11369EJ3V0DS Instruction Mnemonic Operand No. of Machine Operation Addressing Skip Group Bytes Cycle Area Condition Subroutine PUSH rp 1 1 (SP–1)(SP–2) ← rp, SP ← SP–2 stack control BS 2 2 (SP–1) ← MBS, (SP–2) ← RBS, SP ← SP–2 POP rp 1 1 rp ← (SP+1)(SP), SP ← SP+2 BS 2 2 MBS ← (SP+1), RBS ←[...]

µ PD75P3116 28 Data Sheet U11369EJ3V0DS 8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY The program memory contained in the µ PD75P3116 is a 16384 × 8-bit one-time PROM that can be electrically written one time only. The pins listed in the table below are used for this PROM’s write/verify operations. Clock input from the X1 pin is used inst[...]

µ PD75P3116 29 Data Sheet U11369EJ3V0DS 8.2 Program Memory Write Procedure Program memory can be written at high speed using the following procedure. (1) Pull down unused pins to Vss via resistors. Set the X1 pin to low. (2) Supply 5 V to the V DD and V PP pins. (3) Wait 10 µ s. (4) Select the program memory address zero-clear mode. (5) Supply 6 [...]

µ PD75P31 16 30 Data Sheet U11369EJ3V0DS V PP V DD V DD + 1 V DD V PP V DD X1 Data output Data output MD0/P30 MD2/P32 MD3/P33 MD1/P31 “ L ” D0/P60 to D3/P63 D4/P50 to D7/P53 8.3 Program Memory Read Procedure The µ PD75P3116 can read program memory contents using the following procedure. (1) Pull down unused pins to V SS via resistors. Set the[...]

µ PD75P3116 31 Data Sheet U11369EJ3V0DS 8.4 One-Time PROM Screening Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC. Therefore, NEC recommends that after the required data is written and the PROM is stored under the temperature and time conditions shown below, the PROM should be verified via screening. Storage[...]

µ µ µ µ µ PD75P31 16 32 Data Sheet U11369EJ3V0DS 9. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T A = 25˚C) Parameter Symbol Test Conditions Rating Unit Power supply voltage V DD –0.3 to +7.0 V PROM power supply V PP –0.3 to +13.5 V voltage Input voltage V I1 Except port 5 –0.3 to V DD + 0.3 V V I2 Port 5 (N-ch open drain) –0.[...]

µ µ µ µ µ PD75P31 16 33 Data Sheet U11369EJ3V0DS Main System Clock Oscillator Characteristics (T A = –40 to +85 ° C, V DD = 1.8 to 5.5 V) Resonator Recommended Constant Parameter Test Conditions MIN. TYP. MAX. Unit Ceramic Oscillation 1.0 6.0 Note 2 MHz resonator frequency (fx) Note 1 Oscillation After V DD reaches oscil- 4 ms stabilization[...]

µ PD75P31 16 34 Data Sheet U11369EJ3V0DS Subsystem Clock Oscillator Characteristics (T A = –40 to +85˚C, V DD = 1.8 to 5.5 V) Resonator Recommended Constant Parameter Test Conditions MIN. TYP. MAX. Unit Crystal Oscillation 32 32.768 35 kHz resonator frequency (f XT ) Note 1 Oscillation V DD = 4.5 to 5.5 V 1.0 2 s stabilization time Note 2 V DD [...]

µ µ µ µ µ PD75P31 16 35 Data Sheet U11369EJ3V0DS DC Characteristics (T A = –40 to +85˚C, V DD = 1.8 to 5.5 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Output current, low I OL Per pin 15 mA Total of all pins 150 mA Input voltage, high V IH1 Ports 2, 3, 8, and 9 2.7 ≤ V DD ≤ 5.5 V 0.7V DD V DD V 1.8 ≤ V DD < 2.7 V 0.9V D[...]

µ µ µ µ µ PD75P31 16 36 Data Sheet U11369EJ3V0DS DC Characteristics (T A = –40 to +85˚C, V DD = 1.8 to 5.5 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit LCD drive voltage V LCD VAC0 = 0 T A = – 40 to +85 ° C 2.7 V DD V T A = – 10 to +85 ° C 2.2 V DD V VAC0 = 1 1.8 V DD V VAC current Note 1 I VAC VAC0 = 1, V DD = 2.0 V ± 10%[...]

µ PD75P3116 37 Data Sheet U11369EJ3V0DS AC Characteristics (T A = –40 to +85˚C, V DD = 1.8 to 5.5 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit CPU clock cycle t CY Operating on V DD = 2.7 to 5.5 V 0.67 64 µ s time Note 1 main system clock V DD = 1.8 to 5.5 V 0.95 64 µ s (Min. instruction execution Operating on subsystem clock 114 1[...]

µ µ µ µ µ PD75P31 16 38 Data Sheet U11369EJ3V0DS Serial Transfer Operation 2-wire and 3-wire serial I/O mode (SCK...Internal clock output): (T A = –40 to +85˚C, V DD = 1.8 to 5.5 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit SCK cycle time t KCY1 V DD = 2.7 to 5.5 V 1300 ns V DD = 1.8 to 5.5 V 3800 ns SCK high-/low-level t KL1 , t[...]

µ µ µ µ µ PD75P31 16 39 Data Sheet U11369EJ3V0DS SBI mode (SCK...Internal clock output (master)): (T A = –40 to +85˚C, V DD = 1.8 to 5.5 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit SCK cycle time t KCY3 V DD = 2.7 to 5.5 V 1300 ns V DD = 1.8 to 5.5 V 3800 ns SCK high-/low-level t KL3 , t KH3 V DD = 2.7 to 5.5 V t KCY3 /2 – 50 [...]

µ PD75P31 16 40 Data Sheet U11369EJ3V0DS AC Timing Test Points (Excluding X1, XT1 Input) Clock Timing TI0, TI1, TI2 Timing TI0, TI1, TI2 1/f TI t TIL t TIH X1 input 1/f X t XL t XH 0.1 V V DD – 0.1 V XT1 input 1/f XT t XTL t XTH 0.1 V V DD – 0.1 V V IH (MIN.) V IL (MAX.) V IH (MIN.) V IL (MAX.) V OH (MIN.) V OL (MAX.) V OH (MIN.) V OL (MAX.)[...]

µ PD75P31 16 41 Data Sheet U11369EJ3V0DS Serial Transfer Timing 3-wire serial I/O mode 2-wire serial I/O mode t KCY1, 2 t KL1, 2 t KH1, 2 SCK SI SO t SIK1, 2 t KSI1, 2 t KSO1, 2 Input data Output data t KSO1, 2 t SIK1, 2 t KL1, 2 t KH1, 2 SCK t KSI1, 2 SB0, 1 t KCY1, 2[...]

µ PD75P31 16 42 Data Sheet U11369EJ3V0DS t KCY3, 4 t KH3, 4 t KSI3, 4 t SIK3, 4 t KSO3, 4 SCK SB0, 1 t KL3, 4 t SBK t KSB t KCY3, 4 t KH3, 4 t KSI3, 4 t SIK3, 4 t KSO3, 4 SCK SB0, 1 t KL3, 4 t SBK t SBH t SBL t KSB Serial Transfer Timing Bus release signal transfer Command signal transfer Interrupt input timing RESET input timing t RSL RESET t INT[...]

µ PD75P31 16 43 Data Sheet U11369EJ3V0DS Data Memory Stop Mode Low Supply Voltage Data Retention Characteristics (T A = –40 to +85˚C) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Release signal set time t SREL 0 µ s Oscillation stabilization t WAIT Release by RESET 2 15 /f X ms wait time Note 1 Release by interrupt request Note 2 ms No[...]

µ PD75P31 16 44 Data Sheet U11369EJ3V0DS Data Retention Timing (STOP Mode Release by RESET) Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal) V DD RESET STOP instruction execution STOP mode Data retention mode Internal reset operation HALT mode Operating mode t SREL t WAIT t SREL t WAIT V DD STOP instruction exe[...]

µ µ µ µ µ PD75P31 16 45 Data Sheet U11369EJ3V0DS DC Programming Characteristics (T A = 25 ± 5˚C, V DD = 6.0 ± 0.25 V, V PP = 12.5 ± 0.3 V, V SS = 0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Input voltage, high V IH1 Except X1 and X2 pins 0.7V DD V DD V V IH2 X1, X2 V DD – 0.5 V DD V Input voltage, low V IL1 Except X1 and X2[...]

µ PD75P31 16 46 Data Sheet U11369EJ3V0DS Program Memory Write Timing Program Memory Read Timing t VPS t VDS t XH t XL t I t DS t DH t DV t DF t DS t DH t AH t AS t PW t M1R t M0S t OPW t M1S t M1H t PCR t M3S t M3H Data input Data output Data input Data input V PP V DD V DD + 1 V DD V PP V DD X1 D0/P60 to D3/P60 D4/P50 to D7/P53 MD0/P30 MD1/P31 MD[...]

µ µ µ µ µ PD75P31 16 47 Data Sheet U11369EJ3V0DS 10. CHARACTERISTIC CURVES (REFERENCE VALUES) 10 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 012345678 (T A = 25 ° C) Supply voltage V DD (V) Supply current I DD (mA) PCC = 0010 PCC = 0001 PCC = 0000 Main system clock HALT mode + 32 kHz oscillation XT1 XT2 X1 X2 Crystal resonator 6.0 MHz Crystal reson[...]

µ µ µ µ µ PD75P31 16 48 Data Sheet U11369EJ3V0DS 10 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 012345678 XT1 XT2 X1 X2 Crystal resonator 4.19 MHz Crystal resonator 32.768 kHz 330 k Ω 22 pF 22 pF 22 pF 22 pF Supply voltage V DD (V) Supply current I DD (mA) V DD V DD PCC = 0010 Main system clock HALT mode + 32 kHz oscillation Subsystem clock HALT m[...]

µ PD75P31 16 49 Data Sheet U11369EJ3V0DS 48 49 32 64 1 17 16 33 64-PIN PLASTIC QFP (14x14) NOTE Each lead centerline is located within 0.15 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A B D G 17.6 ± 0.4 14.0 ± 0.2 0.8 (T.P.) 1.0 J 17.6 ± 0.4 K P64GC-80-AB8-5 C 14.0 ± 0.2 I 0.15 1.8 ± 0.2 L 0.8 ± 0.2 F 1.0 N[...]

µ PD75P31 16 50 Data Sheet U11369EJ3V0DS 64-PIN PLASTIC LQFP (12x12) NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A B D G 14.8 ± 0.4 12.0 ± 0.2 0.13 1.125 I 14.8 ± 0.4 J C 12.0 ± 0.2 H 0.32 ± 0.08 0.65 (T.P.) K 1.4 ± 0.2 L 0.6 ± 0.2 F 1.125 P64GK-65-8A8-3 N P[...]

µ PD75P31 16 51 Data Sheet U11369EJ3V0DS 64-PIN PLASTIC LQFP (14x14) NOTE Each lead centerline is located within 0.20 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A B D G 17.2 ± 0.2 14.0 ± 0.2 0.8 (T.P.) 1.0 J 17.2 ± 0.2 K C 14.0 ± 0.2 I 0.20 1.6 ± 0.2 L 0.8 F 1.0 N P Q 0.10 1.4 ± 0.1 0.127 ± 0.075 U 0.886 [...]

µ PD75P31 16 52 Data Sheet U11369EJ3V0DS 12. RECOMMENDED SOLDERING CONDITIONS The µ PD75P3116 should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and co[...]

µ PD75P31 16 53 Data Sheet U11369EJ3V0DS Table 12-1. Surface Mounting Type Soldering Conditions (2/2) (3) µ PD75P3116GC-8BS: 64-pin plastic LQFP (14 × 14) Soldering Soldering Conditions Recommended Method Condition Symbol Infrared reflow Package peak temperature: 235 ° C, Time: 30 seconds max. (at 210 ° C or higher), IR35-00-2 Count: Twice or [...]

µ PD75P31 16 54 Data Sheet U11369EJ3V0DS APPENDIX A. LIST OF µ PD75308B, 753108, AND 75P3116 FUNCTIONS Parameter µ PD75308B µ PD753108 µ PD75P3116 Program memory Mask ROM Mask ROM One-time PROM 0000H to 1F7FH 0000H to 1FFFH 0000H to 3FFFH (8064 × 8 bits) (8192 × 8 bits) (16384 × 8 bits) Data memory 000H to 1FFH (512 × 4 bits) CPU 75X Stand[...]

µ PD75P31 16 55 Data Sheet U11369EJ3V0DS Parameter µ PD75308B µ PD753108 µ PD75P3116 Clock output (PCL) Φ , 524, 262, 65.5 kHz • Φ , 524, 262, 65.5 kHz (Main system clock: (Main system clock: during 4.19 MHz operation) during 4.19 MHz operation) • Φ , 750, 375, 93.8 kHz (Main system clock: during 6.0 MHz operation) BUZ output (BUZ) 2 kHz[...]

µ PD75P3116 56 Data Sheet U11369EJ3V0DS APPENDIX B. DEVELOPMENT TOOLS The following development tools have been provided for system development using the µ PD75P3116. In the 75XL Series, a common relocatable assembler is used in combination with a device file dedicated to each model. RA75X relocatable assembler Host Machine Part Number OS Supply [...]

µ PD75P31 16 57 Data Sheet U11369EJ3V0DS PROM Write Tools Hardware PG-1500 This is a PROM writer that can program a single-chip microcontroller with PROM in stand-alone mode or under the control of a host machine when connected with the supplied accessory board and optional programmer adapter. It can also program typical PROMs in capacities rangin[...]

µ PD75P3116 58 Data Sheet U11369EJ3V0DS Debugging Tools An in-circuit emulator (IE-75001-R) is provided as a program debugging tool for the µ PD75P3116. The system configuration using this in-circuit emulator is shown below. Hardware IE-75001-R The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging during developm[...]

µ PD75P3116 59 Data Sheet U11369EJ3V0DS OS for IBM PCs The following operating systems for IBM PCs are supported. OS Version PC DOS TM Ver.3.1 to 6.3 J6.1/V Note to J6.3/V Note MS-DOS Ver.5.0 to 6.2 5.0/V Note to 6.2/V Note IBM DOS TM J5.02/V Note Note Only English mode is supported. Caution Ver. 5.0 and later include a task swapping function, but[...]

µ PD75P31 16 60 Data Sheet U11369EJ3V0DS Package Drawing and Recommended Footprint of Conversion Socket (EV-9200GC-64) Figure B-1. EV-9200GC-64 Package Drawing (For Reference Only) A F 1 E EV-9200GC-64 B D C M N L K R Q I H P O S T J G No.1 pin index EV-9200GC-64-G0E ITEM MILLIMETERS INCHES A B C D E F G H I J K L M N O P Q R S T 18.8 14.1 14.1 18[...]

µ PD75P31 16 61 Data Sheet U11369EJ3V0DS Figure B-2. EV-9200GC-64 Recommended Footprint (For Reference Only) F E D G H I J K L C B A 0.031 × 0.591=0.472 0.031 × 0.591=0.472 EV-9200GC-64-P1E ITEM MILLIMETERS INCHES A B C D E F G H I J K L 19.5 14.8 14.8 19.5 6.00 ± 0.08 6.00 ± 0.08 0.5 ± 0.02 2.36 ± 0.03 2.2 ± 0.1 1.57 ± 0.03 0.768 0.583 0.[...]

µ PD75P31 16 62 Data Sheet U11369EJ3V0DS Package Drawing of Conversion Adapter (TGK-064SBW) Figure B-3. TGK-064SBW Package Drawing (For Reference Only) ITEM MILLIMETERS INCHES b 1.85 0.073 c 3.5 0.138 a 0.3 0.012 d 2.0 0.079 h 5.9 0.232 i 0.8 0.031 j 2.4 0.094 e 3.9 0.154 f 1.325 g 1.325 0.052 0.052 ITEM MILLIMETERS INCHES B 0.65x15=9.75 0.026x0.5[...]

µ PD75P31 16 63 Data Sheet U11369EJ3V0DS Notes on Target System Design The following shows a diagram of the connection conditions between the emulation probe, conversion connector and conversion socket or conversion adapter. Design your system making allowances for conditions such as the form of parts mounted on the target system, as shown below. [...]

µ PD75P31 16 64 Data Sheet U11369EJ3V0DS Figure B-6. Connection Conditions of Target System (1) Figure B-7. Connection Conditions of Target System (2) In-circuit emulator IE-75001-R External sense clips Target system Conversion socket EV-9200GC-64 64-pin GC EP-753108GC-R Ground clip 35 mm 35 mm 18.5 mm 18.5 mm 8 mm Target system Conversion adapter[...]

µ PD75P31 16 65 Data Sheet U11369EJ3V0DS APPENDIX C. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. µ PD753104, 753106, 753108 Data Sheet U10086E µ PD75P3116 Data Sheet This docume[...]

µ PD75P31 16 66 Data Sheet U11369EJ3V0DS Other Related Documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE – Products & Packages – X13769E Semiconductor Device Mounting Technology Manual C10535E Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Pr[...]

µ PD75P31 16 67 Data Sheet U11369EJ3V0DS [MEMO][...]

µ PD75P3116 68 Data Sheet U11369EJ3V0DS NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly diss[...]

µ PD75P3116 69 Data Sheet U11369EJ3V0DS Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ord[...]

µ PD75P3116 QTOP is a trademark of NEC Corporation. MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. The export of this product from Japan is regulated by the Japanese government. To [...]