NXP Semiconductors UM10237 инструкция обслуживания

UM10237 LPC24XX User manual Rev . 02 — 19 December 2 008 User manual Documen t informat ion Info Content Keywords LPC2400, LPC2458, LPC2420, LPC24 60, LPC2468, LPC2470, LPC24 78, ARM, ARM7, 32-bit, Single -chip, External memory interface, USB 2.0, Device, Host, OTG, Ethernet, CAN, I2S, I2C, SPI, UART, PWM, IRC, Microcontroller Abstract LPC24XX Us[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 2 of 792 Cont act information For more in formation, please visit: http://www .nxp. com For sales of fice addresses, please send an email to : salesaddresses@nxp.com NXP Semiconductors UM10237 LPC24XX User manual Revision hi story Rev Date Description 02 2008[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 3 of 792 1. Introduction NXP Semiconductor designed the LPC2400 microcontrollers around a 16-bit/32-bit ARM7TDMI-S CPU core with real-time debug interfaces that include both JT AG and embedded T race. The LPC2400 micr ocontro llers have 512 kB of on-chip high[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 4 of 792 NXP Semiconductors UM10237 Chapter 1: LPC24XX Introductor y information Most featur es and periphe rals are identica l for all LPC240 0 parts. All dif ferences a re listed in T able 1 –2 . 3. LPC2400 features • ARM7TDMI-S processor , running at u[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 5 of 792 NXP Semiconductors UM10237 Chapter 1: LPC24XX Introductor y information – SPI controller . – T wo SSP controllers, with FIFO and multi-protocol capabilit ies. One is an alternate for the SPI port, sharing it s interrupt. SSPs can be used with the[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 6 of 792 NXP Semiconductors UM10237 Chapter 1: LPC24XX Introductor y information • Boundary sc an for simplifie d board testin g. • V ersatile pin function selections allow mo re possibilities for using on-chip peripheral functions. 4. Applications • In[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 7 of 792 NXP Semiconductors UM10237 Chapter 1: LPC24XX Introductor y information 5.3 LPC2468 ordering options 5.4 LPC2470 ordering options T able 6. LPC2420/60 orderin g op tion s Ty p e n u m b e r Flash (kB) SRAM (kB) External bus Ethernet USB OTG/ OHCI/ DE[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 8 of 792 NXP Semiconductors UM10237 Chapter 1: LPC24XX Introductor y information 5.5 LPC2478 ordering options 6. Architectural overview The LPC2400 microcontroller consist s of an ARM7TDMI-S CPU with emulation support, the ARM7 local bus for close ly cou p le[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 9 of 792 NXP Semiconductors UM10237 Chapter 1: LPC24XX Introductor y information The second AHB, referred to as AHB2, in cludes only the Ethernet block and an associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary AHB to be a b[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 10 of 792 NXP Semiconductors UM10237 Chapter 1: LPC24XX Introductor y information 8. On-chip SRAM The LPC2400 includes a SRAM memor y of 64 kB reserved for the ARM processor exclusive use. This RAM may be used for code and/or dat a storage and ma y be accesse[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 1 1 of 792 NXP Semiconductors UM10237 Chapter 1: LPC24XX Introductor y information 9. LPC2458 block diagram Fig 1. L PC2458 block di agram power domain 2 LPC2458 A[19:0] D[15:0] EXTERNAL MEMOR Y CONTROLLER ALARM 002aad093 PWM0, PWM1 ARM7TDMI-S PLL EINT3 to EI[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 12 of 792 NXP Semiconductors UM10237 Chapter 1: LPC24XX Introductor y information 10. LPC2420/60 block diagram (1) LPC24 60 only . Fig 2. L PC2460 block di agram power domain 2 LPC2420/2460 A[23:0] D[31:0] EXTERNAL MEMOR Y CONTROLLER ALARM 002aad313 PWM0, PWM[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 13 of 792 NXP Semiconductors UM10237 Chapter 1: LPC24XX Introductor y information 1 1. LPC2468 block diagram Fig 3. L PC2468 block di agram power domain 2 LPC2468 A[23:0] D[31:0] EXTERNAL MEMORY CONTROLLER ALARM 002aac721 PWM0, PWM1 ARM7TDMI-S PLL EINT3 to EI[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 14 of 792 NXP Semiconductors UM10237 Chapter 1: LPC24XX Introductor y information 12. LPC2470 block diagram Fig 4. L PC2470 block di agram power domain 2 LPC2470 A[23:0] D[31:0] EXTERNAL MEMOR Y CONTROLLER ALARM 002aad317 PWM0, PWM1 ARM7TDMI-S PLL EINT3 to EI[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 15 of 792 NXP Semiconductors UM10237 Chapter 1: LPC24XX Introductor y information 13. LPC2478 block diagram Fig 5. L PC2478 block di agram power domain 2 LPC2478 A[23:0] D[31:0] EXTERNAL MEMOR Y CONTROLLER ALARM 002aac805 PWM0, PWM1 ARM7TDMI-S PLL EINT3 to EI[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 16 of 792 1. How to read this chapter The memory addressing and ma ppin g fo r dif f erent LPC2400 part s depends on flash size, EMC size, and the LCD periphera l, see T able 2–13 . 2. Memory map and peripheral addressing ARM processors have a single 4 GB a[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 17 of 792 NXP Semiconductors UM10237 Chapter 2: LPC24XX Memor y mapping T able 15 . LPC242 0/60/70 memory usage and details Address ran ge General u se Address range det ails and descriptio n 0x0000 0000 to 0x3FFF FFFF Fast I/O 0x0000 0000 - 0x0007 FFFF Reser[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 18 of 792 NXP Semiconductors UM10237 Chapter 2: LPC24XX Memor y mapping 3. Memory map s The LPC2400 incorporates several distinct memory regions, shown in the followin g figures. Figure 2–6 shows the overall ma p of the entire address sp ace from the user p[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 19 of 792 NXP Semiconductors UM10237 Chapter 2: LPC24XX Memor y mapping Fig 6. LPC2400 system memory m ap 0.0 GB 1.0 GB ON-CHIP NON-V OLA TILE MEMOR Y OR RESERVED 0x0000 0000 RESER VED ADDRESS SP ACE SPECIAL REGISTERS ON-CHIP ST A TIC RAM RESER VED ADDRESS SP[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 20 of 792 NXP Semiconductors UM10237 Chapter 2: LPC24XX Memor y mapping Figure 8 and T able 2–17 show dif ferent views of the peripheral a ddress space. Both the AHB and APB peripheral areas ar e 2 megabyte spaces which are divided up into 128 peripherals .[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 21 of 792 NXP Semiconductors UM10237 Chapter 2: LPC24XX Memor y mapping All peripheral register addresses are word aligne d (to 32 bit boundaries) regardless of their size. This elim inates the n eed for byte lan e mapping har dware that w ould be require d t[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 22 of 792 NXP Semiconductors UM10237 Chapter 2: LPC24XX Memor y mapping 4. APB peripheral addresses The following table shows the APB address map. No APB periph eral uses all of the 16 kB space alloca ted to it. T ypically each device’s registers are "[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 23 of 792 NXP Semiconductors UM10237 Chapter 2: LPC24XX Memor y mapping 5. LPC2400 memory re-m apping and boot ROM 5.1 Memory map concept s and operating modes The basic concept on the LPC240 0 is that ea ch memory area h as a "natural" location in [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 24 of 792 NXP Semiconductors UM10237 Chapter 2: LPC24XX Memor y mapping [1] See EMCControl register address mirro r bit in T able 5–68 for address of external memory bank 0. [2] Connect external boot memory to chip select 1. Dur ing boot from external memor[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 25 of 792 NXP Semiconductors UM10237 Chapter 2: LPC24XX Memor y mapping Re-mapped memory areas, includin g the Boot ROM and interrupt vectors, contin ue to appear in their original location in addition to the re -mapped address. Details on re-mapping and exam[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 26 of 792 NXP Semiconductors UM10237 Chapter 2: LPC24XX Memor y mapping read/fetch from 0x0000 0008 will provide data stored in 0x4000 0008. In case of MEMMAP[1:0] = 00 (Boot Loader Mode), read /fetch from 0x0000 0008 will provide data available also at 0x7FF[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 27 of 792 NXP Semiconductors UM10237 Chapter 2: LPC24XX Memor y mapping 7. Prefetch abort and da t a abort exceptions The LPC2400 generates the ap propriate bu s cycle abort exception if an ac cess is attempted for an address that is in a reserv ed or unass i[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 28 of 792 1. Summary of system co ntrol block func tions The System Control Block incl udes several system features and control registers for a number of functions that are not related to specific periphera l devices. These includ e: • Reset • Brown-Out D[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 29 of 792 NXP Semiconductors UM10237 Chapter 3: LPC24XX System control [1] Reset V alue reflects the data stored in used bits only . It does not include reserved bits content. 3.1 External interrupt input s The LPC2400 includes four External Inter rup t Input[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 30 of 792 NXP Semiconductors UM10237 Chapter 3: LPC24XX System control Once a bit from EINT0 to EINT3 is set an d an appropriate code st arts to execute (h andling wakeup and/or external in terrupt), this bit in EXTINT register must be cleared. Otherwise even[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 31 of 792 NXP Semiconductors UM10237 Chapter 3: LPC24XX System control 3.1.3 External Interrupt Mode register (EXTMODE - 0xE01F C148) The bit s in this register select whether each EI NT pin is level- or edge-se nsitive. Only pins that are selected for the EI[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 32 of 792 NXP Semiconductors UM10237 Chapter 3: LPC24XX System control 3.2 Reset Reset has four so urces on the LPC 2400: the RESET pin, the W atchdog Reset, Power On Reset (POR) and the Brown Out De tection circuit (BOD). The RESET pin is a Schmitt trigger i[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 33 of 792 NXP Semiconductors UM10237 Chapter 3: LPC24XX System control On the assertion of any of reset sources ( POR, BOD reset, External rese t and W atchdog reset), the following two sequence s start simultaneously: 1. After IRC-st art-up time (maximum of [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 34 of 792 NXP Semiconductors UM10237 Chapter 3: LPC24XX System control The various Reset s have some small dif ference s. For example, a Power On Reset causes the value of certa in pins to be latched to configure the par t. For more det ails on Reset, PLL and[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 35 of 792 NXP Semiconductors UM10237 Chapter 3: LPC24XX System control 3.3 Other system contro ls and st atus flags Some aspects of contro lling LPC2400 operation that do not fit in to peripher al or other registers are grou ped here. 3.3.1 System Controls an[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 36 of 792 NXP Semiconductors UM10237 Chapter 3: LPC24XX System control [1] The state of this bit is preserved through a software reset, and only a POR or a BOD event will reset it to its default value. 3.4 AHB Configuration The AHB configuration register allo[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 37 of 792 NXP Semiconductors UM10237 Chapter 3: LPC24XX System control [1] Allowed values for nnn are: 101 (highest pr iority), 100, 01 1, 010, 001 (lowest priority). 3.4.1.1 Examples of AHB1 settings The following examples use the LPC2478 to illustrate how t[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 38 of 792 NXP Semiconductors UM10237 Chapter 3: LPC24XX System control [1] Sequence based on round-robin. [1] Sequence based on round-robin. 3.4.2 AHB Arbiter Configuration register 2 (AHBCFG2 - 0xE01F C18C) By default, t he AHB2 acces s is schedul ed round-r[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 39 of 792 NXP Semiconductors UM10237 Chapter 3: LPC24XX System control [1] Allowed values for nn are: 10 (h igh priority) and 01 (low priority). 3.4.2.1 Examples of AHB2 settings T able 36. AHB Arbiter Configur at ion register 2 (AHBCFG2 - address 0xE01F C18C[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 40 of 792 NXP Semiconductors UM10237 Chapter 3: LPC24XX System control [1] Sequence based on round-robin. 4. Brown-out detection The LPC2400 includes 2-st age monitoring of the voltage on the V DD(3V3) pins. If this voltage falls below 2.95 V , the Brown-Out [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 41 of 792 1. Summary of clocking an d power control functions This section de scribes the generation of the vari ous clocks ne eded by the LPC2400 an d options of clock source se lection, as well as power control and wa keup from reduced power modes. Fun c ti[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 42 of 792 NXP Semiconductors UM10237 Chapter 4: LPC24XX Clock ing and power control Fig 12. Clock generati on for the LPC2400 MAIN OSCILLA T OR INTERNAL RC OSCILLA T OR RTC OSCILLA T OR PLL W A TCHDOG TIMER RTC PRESCALER REAL-TIME CLOCK BYP ASS SYNCHRO- NIZER[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 43 of 792 NXP Semiconductors UM10237 Chapter 4: LPC24XX Clock ing and power control 2. Oscillators The LPC2400 includes three independe nt oscillators. These are the Main Oscillator , the Internal RC Oscillator , and the RTC oscillator . Each oscillator can b[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 44 of 792 NXP Semiconductors UM10237 Chapter 4: LPC24XX Clock ing and power control Since chip operation always begins using th e Internal RC Oscillator , and the main oscillator may never be used in some applications, it will on ly be started by software req[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 45 of 792 NXP Semiconductors UM10237 Chapter 4: LPC24XX Clock ing and power control register) so that software can determine when the o scillator is running an d stable. At that point, software can cont rol switching to the ma in os cillator as a clock sourc [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 46 of 792 NXP Semiconductors UM10237 Chapter 4: LPC24XX Clock ing and power control • The IRC oscillator cannot be used as cloc k source for the USB block. • The IRC oscillator cannot be used as clock source for the CAN c ontrollers if the CAN baud rate i[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 47 of 792 NXP Semiconductors UM10237 Chapter 4: LPC24XX Clock ing and power control PLL activatio n is controlle d via the PLL CON register . The PLL m ultiplier and d ivider values are controlled b y the PLLCF G register . These two registers are protected i[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 48 of 792 NXP Semiconductors UM10237 Chapter 4: LPC24XX Clock ing and power control [1] Reset V alue reflects the data stored in used bits only . It does not include reserved bits content. 3.2.4 PLL Control register (PLLCON - 0xE01F C080) The PLLCON register [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 49 of 792 NXP Semiconductors UM10237 Chapter 4: LPC24XX Clock ing and power control disconnect the PLL if lock is lost during ope rati on. In the event of loss of PLL lock, it is likely that the oscillator clock has become unstable and disconnecting the PLL w[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 50 of 792 NXP Semiconductors UM10237 Chapter 4: LPC24XX Clock ing and power control 6836 1 448.0041 6866 1 449.9702 6958 1 455.9995 7050 1 462.0288 7324 1 479.9857 7425 1 486.6048 7690 1 503.9718 7813 1 512.0328 7935 1 520.0282 8057 1 528.0236 8100 1 530.8416[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 51 of 792 NXP Semiconductors UM10237 Chapter 4: LPC24XX Clock ing and power control 3.2.6 PLL St atus register (PLLST A T - 0xE01F C088) The read-only PLLST A T register provides the ac tual PLL pa rameters that are in effect at the time it is read, as well a[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 52 of 792 NXP Semiconductors UM10237 Chapter 4: LPC24XX Clock ing and power control connected for use. The value of PLOCK may not be stable when the PLL refe rence frequency (F REF , the frequency of REFCLK, which is equal to the PLL input frequen cy divided [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 53 of 792 NXP Semiconductors UM10237 Chapter 4: LPC24XX Clock ing and power control 3.2.1 1 PLL frequency calculation The PLL equations use the following parameters: The PLL output frequency ( w hen the PLL is both active and conn ected) is given by: F CCO = [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 54 of 792 NXP Semiconductors UM10237 Chapter 4: LPC24XX Clock ing and power control 3.2.12 Procedure for determining PLL settings PLL parameter determination can be simplified by using a sp readsheet available from NXP . T o determine PLL parameters by hand, [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 55 of 792 NXP Semiconductors UM10237 Chapter 4: LPC24XX Clock ing and power control M = (F CCO × N) / (2 × F IN ) S tart by assuming N = 1, since this produces the smallest multiplier ne ede d for the PLL. So, M = 288 × 10 6 /( 2 × 4 × 10 6 ) = 36. Since[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 56 of 792 NXP Semiconductors UM10237 Chapter 4: LPC24XX Clock ing and power control In general, larger vlaues of F REF result in a more stable PLL when the input clock is a low frequency . Even the first table entry shows a ve ry small erro r of just over 1 h[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 57 of 792 NXP Semiconductors UM10237 Chapter 4: LPC24XX Clock ing and power control 3.3.1 CPU Clock Configuration register (CCLKCFG - 0xE01F C104) The CCLKCF G register con trols the divis ion of the PLL output before it is used by the CPU. When the PL L is b[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 58 of 792 NXP Semiconductors UM10237 Chapter 4: LPC24XX Clock ing and power control 3.3.4 Peripheral Clock Selection registers 0 and 1 (PCLKSEL0 - 0xE01F C1A8 and PCLKSEL1 - 0xE01F C1AC) A pair of bit s in a Peripheral Clock Selection register controls the ra[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 59 of 792 NXP Semiconductors UM10237 Chapter 4: LPC24XX Clock ing and power control [1] For PCLK_RTC only , the value ’01’ is illegal. Do not write ’01’ to the PCLK_RTC. Attempting to write ’01’ results in the previous value being unchanged. 3.4 P[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 60 of 792 NXP Semiconductors UM10237 Chapter 4: LPC24XX Clock ing and power control In Idle mode, execution of instructions is suspended until either a Reset or inte rrupt occurs. Periphera l functions continue opera tion during Idle mod e and may generate in[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 61 of 792 NXP Semiconductors UM10237 Chapter 4: LPC24XX Clock ing and power control 3.4.5 Power control register description The Power Control fun ction uses registers shown in T able 4–59 . More det ailed descriptions follow . [1] Reset V alue reflects the[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 62 of 792 NXP Semiconductors UM10237 Chapter 4: LPC24XX Clock ing and power control Encoding of Reduced Power Modes The PM2, PM1, and PM0 bits in PCON allow entering redu ced power modes as needed. The encoding of these bit s allows backward co mpatibili ty w[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 63 of 792 NXP Semiconductors UM10237 Chapter 4: LPC24XX Clock ing and power control 3.4.8 Power Control for Peripherals register (PCONP - 0xE01F C0C4) The PCONP register allows turning of f select ed peripheral functions for the p urp ose of saving power . Th[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 64 of 792 NXP Semiconductors UM10237 Chapter 4: LPC24XX Clock ing and power control Some peripherals, particu larly those that in clude analog fu nctions, may consume power that is not clock dependent. Th ese peripherals may cont ain a separ ate disable contr[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 65 of 792 NXP Semiconductors UM10237 Chapter 4: LPC24XX Clock ing and power control [1] LPC247x only . 3.4.9 Power control usage notes After every reset, the PCONP re gister cont ains the value that enables sele cted i n terfaces and peripherals contro lled b[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 66 of 792 NXP Semiconductors UM10237 Chapter 4: LPC24XX Clock ing and power control whenever any of the aforemen tioned function s are turned of f for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wakeup of th[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 67 of 792 1. How to read this chapter This chapter describes th e external memory con troller for all L PC2400 parts. For EMC configurations that are specific to LPC2458 and LPC24 20/60/68/70/78, see T able 5–64 . 2. Basic configuration The EMC is configure[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 68 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) 3. Pins: Select data, address, a nd control pin s and their m odes in PINSEL 6/8/9 and PINMODE6/8/9 (see Section 9–5 ). 4. Configuration: see T able 5–68 to Ta b l e[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 69 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) The functions of the EMC blocks are described in the following sections: • AHB slave register inte rf ac e. • AHB slave memory interface s. • Data buffers. • Mem[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 70 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) 5.2 AHB slave memory interface The AHB slave memory interface allo ws access to external memories. 5.2.1 Memory transaction endianness The endianness of the dat a transf[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 71 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) • If the buffers are enable d, an AHB write operat ion writes into the Least Recently Used (LRU) buffer , if empty . If the LRU buffer is not e mpty , the contents of [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 72 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) Self-refresh mode can be entered by soft war e by se tting the SREFREQ bit in the EMCDynamicControl Register and polling the SREF A CK bit in the EMCS tatus Register . A[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 73 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) 8. Reset The EMC receives two reset signals. On e is Power-On Reset (POR), asserted when chip power is applied, and when a brown-out co ndition is detected (see the Syst[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 74 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) 10. Register description This chapter describes the EMC register s and provides details required whe n programming the micr oc on tr olle r . The EMC re gis ter s ar e s[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 75 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) 0xFFE0 8124 EMCDyna mic RasCas1 Selects the RAS and CAS latencies for dynami c memory chip select 1. - 0x303 R/W 0xFFE0 8140 EMCDyna mic Config2 Selects the configuratio[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 76 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) [1] Reset V alue reflects the data stored in used bi ts only . It does not include reserved bits content. 10.1 EMC Control register (EMCControl - 0xFFE0 80 00) The EMCCo[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 77 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) [1] The external memory cannot be accessed in low-power or disabled state. If a memo ry access is performed an AHB error response is generated. T he EMC register s can b[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 78 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) 10.3 EMC Configuration regist er (EMCConfig - 0xFFE0 8008) The EMCConfig register configur es the ope ration of the memory controller . It is recommended that this regis[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 79 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) [1] Clock enable must be HIGH during SDRAM initialization. [2] The memory controller exits from power-on reset w ith the self-refresh bit HIGH. T o enter normal function[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 80 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) 10.5 Dynamic Memory Refresh Ti mer register (EMCDynamicRefresh - 0xFFE0 8024) The EMCDynamicRefresh register configures dyna mic memory operation. It is recommended that[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 81 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) 10.6 Dynamic Memory Read Configuration register (EMCDynamicReadConfig - 0xFFE0 8028) The EMCDynamicReadConfig register config ures the dynamic memor y read strategy . Th[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 82 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) 10.8 Dynamic Memory Ac tive to Precharge Comm and Period register (EMCDynamictRAS - 0xFFE0 8034) The EMCDynamicTRAS register enables you to progr am the active to precha[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 83 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) 10.10 Dynamic Memory Last Dat a Out to Active Time register (EMCDynamictAPR - 0xFFE0 803C) The EMCDynamicT APR register enables you to progra m the last-dat a- out to ac[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 84 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) 10.12 Dynamic Memory Wr ite Recovery Time register (EMCDynamictWR - 0xFFE0 8044) The EMCDynamicTWR register enables you to pr ogram the write recovery time, tWR. It is r[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 85 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) 10.14 Dynamic Memory Auto-refresh Pe riod register (EMCDynamictRFC - 0xFFE0 804C) The EMCDynam icTRFC regis ter enables you to program the auto-refresh period, and auto-[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 86 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) 10.16 Dynamic Memory Ac tive Bank A to Active Ba nk B Time register (EMCDynamictRRD - 0xFFE0 8054) The EMCDynamicTRRD register en ables you to program the active bank A [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 87 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) 10.18 St atic Memory Extended W ait re gister (EMCSt aticExtendedW ait - 0xFFE0 8080) ExtendedW ait (EW) bit in the EMCS taticConfig registe r is set. It is recommended [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 88 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) [1] The SDRAM column and row w idth and number of banks are computed automatically from the address mapping. [2] The buffers must be disabled duri ng SDRAM and SyncFlash[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 89 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) 0 0 01 1 00 256 MB (32Mx8), 4 banks, row length = 13, column length = 10 0 0 01 1 01 256 MB (16Mx16) , 4 ban ks, row length = 13, column length = 9 0 0 10 0 00 512 MB (6[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 90 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) A chip select can be connected to a single memo ry device, in this ca se the chip select data bus width is the sam e as the de vice wi dth. Alternatively the chip select[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 91 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) 10.21 St atic Memory Configuration registers (EMCSt aticConfig0-3 - 0xFFE0 8200, 220 , 240, 260) The EMCS taticConfig0-3 re gisters configure th e static memory configur[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 92 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) [1] Extended wait and page mode cannot be selected simultaneously . [2] EMC may perform burst read access eve n when the buffer enable bit is cleared. 10.22 St atic Memo[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 93 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) T able 5–90 shows the bit assignment s for the EMCS taticW aitWen0-3 re gisters. 10.23 St atic Memory Output Enable De lay registers (EMCS taticW aitOen0-3 - 0xFFE0 82[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 94 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) 10.25 St atic Memory Page Mode Read Delay registers (EMCSt aticwaitPage0-3 - 0xFFE0 8210, 230, 250, 270) The EMCS taticW aitPage0-3 reg isters enable you to program the [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 95 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) 10.27 St atic Memory T urn Round Del ay registers (EMCS taticW aitT urn0-3 - 0xFFE0 8218, 238 , 258, 278) The EMCS taticW aitT urn0-3 registers enab le you to program th[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 96 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) Symbol "a_b" in the following figures refe rs to the highest order ad dr ess line in the dat a bus. Symbol "a_m" refers to the h ighest order address[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 97 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) 1 1.2 16-bit wide memory bank connection c. 32 b it wide memory bank interfaced to one 8 bit memory chip Fig 16. 32 bit bank external memo ry interfaces ( bit s MW = 10)[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 98 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) 1 1.3 8-bit wide memory bank connection Fig 18. 8 bit bank external memory interface (bits MW = 00) OE CS BLS[0] D[7:0] CE OE WE IO[7:0] A[a_m:0] A[a_b:0][...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 99 of 792 NXP Semiconductors UM10237 Chapter 5: LPC2 4XX External Memory Controller (EMC) 1 1.4 Memory configuration example Fig 19. T ypical memo ry configuration dia gr a m nCE nOE Q[31:0] A[20:0] nCE nOE IO[15:0] A[15: 0] nWE nUB nLB nCE nOE IO[15:0] A[15:[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 100 o f 792 1. How to read this chapter The Memory Accelerator Modu le operates in combination with the flash controller and is available in pa rts LPC2458/68/78. 2. Introduction The MAM block i n the LPC2400 maximizes the performance of the ARM p rocessor wh[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 101 o f 792 NXP Semiconductors UM10237 Chapter 6: L PC24XX Memory Acceler ator Module ( MAM) Branches and other progra m flow changes ca use a break in the sequential flow of instruction fetches described above. The Branc h T rail buffer captures the line to [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 102 o f 792 NXP Semiconductors UM10237 Chapter 6: L PC24XX Memory Acceler ator Module ( MAM) 4.2 Instruction latches and dat a latches Code and Dat a accesses are treated separa tely by the Memory Accelerator Module. There is a 128 bit Latch, a 15 bit Address[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 103 o f 792 NXP Semiconductors UM10237 Chapter 6: L PC24XX Memory Acceler ator Module ( MAM) Mode 1: MAM partially enabled. Sequential instru ction accesse s are fulfilled from the holding latches if the data is present. Instruction prefet ch is enabled. No n[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 104 o f 792 NXP Semiconductors UM10237 Chapter 6: L PC24XX Memory Acceler ator Module ( MAM) 7. Register description The MAM is controlled by the registe rs shown in T able 6–98 . More detailed description s follow . Writes to any unused bits are ignored. A[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 105 o f 792 NXP Semiconductors UM10237 Chapter 6: L PC24XX Memory Acceler ator Module ( MAM) T able 100. MAM Timing register (MAMTIM - address 0xE01F C 004) bit description Bit Symbol Va l u e Descr iption Reset value 2:0 MAM_fetch_ cycle_timing These bits se[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 106 o f 792 NXP Semiconductors UM10237 Chapter 6: L PC24XX Memory Acceler ator Module ( MAM) 8. MAM usage notes When changing MAM timing, the MAM must fi rst be turned of f by writing a zero to MAMCR. A new value may then be written to MAMTIM. Finally , the M[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 107 o f 792 NXP Semiconductors UM10237 Chapter 6: L PC24XX Memory Acceler ator Module ( MAM) T able 101 . Sugge stions for MAM timing selectio n system clock Number of MA M fetch cycles in MAMTIM (see T able 6–100 ) < 20 MHz 1 CCL K 20 MHz to 40 MHz 2 CC[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 108 o f 792 1. Features • ARM PrimeCell V ect ored Interrupt Controller • Mapped to AHB address sp ace for fast access • Supports 32 vect ored IRQ int errupts • 16 progra mmable in terrupt pr iority levels • Fixed hardware priori ty within each prog[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 109 o f 792 NXP Semiconductors UM10237 Chapter 7: LPC24XX V ectored Interrupt Controller ( VIC) T able 102. Su mmary of VIC registers Name Description Access Reset value [1] Ad dress VICIRQS tatus IR Q S tatus Register . This register reads ou t th e st ate o[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 1 10 of 792 NXP Semiconductors UM10237 Chapter 7: LPC24XX V ectored Interrupt Controller ( VIC) VICV ectAddr19 V ector address 19 register . R/W 0 0xFFFF F14C VICV ectAddr20 V ector address 20 register . R/W 0 0xFFFF F150 VICV ectAddr21 V ector address 21 reg[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 1 1 1 of 792 NXP Semiconductors UM10237 Chapter 7: LPC24XX V ectored Interrupt Controller ( VIC) [1] Reset V alue reflects the data stored in used bi ts only . It does not include reserved bits content. The following section descri bes the VIC registers in th[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 1 12 of 792 NXP Semiconductors UM10237 Chapter 7: LPC24XX V ectored Interrupt Controller ( VIC) 3.4 Interrupt Enable Register (VICIntEnable - 0xFFFF F010) This is a read/write accessible register . This register controls which of the 32 combined hardware an d[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 1 13 of 792 NXP Semiconductors UM10237 Chapter 7: LPC24XX V ectored Interrupt Controller ( VIC) 3.7 IRQ St atus Register (VICIRQSt atus - 0xFFFF F000) This is a read only register . This register re ads out the st ate of those interrupt requests that are enab[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 1 14 of 792 NXP Semiconductors UM10237 Chapter 7: LPC24XX V ectored Interrupt Controller ( VIC) 3.10 V ector Priority Registers 0-31 (VICV ectPriority0-31 - 0xFFFF F200 to 27C) These registers select a priority level for t he 32 vectored IRQs. There are 16 pr[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 1 15 of 792 NXP Semiconductors UM10237 Chapter 7: LPC24XX V ectored Interrupt Controller ( VIC) 3.13 Protection Enable Register (VICProtection - 0xFFFF F020) This is a read/write accessible register . This one bit register cont rols access to the VIC register[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 1 16 of 792 NXP Semiconductors UM10237 Chapter 7: LPC24XX V ectored Interrupt Controller ( VIC) UART1 Rx Line St atus (RLS) T ransmit Hold ing Re gister Empty (THRE) Rx Data A v ail able (RDA) Character T ime-out Indicator (CTI) Modem Control Change End of Au[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 1 17 of 792 NXP Semiconductors UM10237 Chapter 7: LPC24XX V ectored Interrupt Controller ( VIC) [1] LPC247x only . CAN CAN Common, CAN 0 Tx, CAN 0 Rx, CAN 1 Tx, CAN 1 Rx 23 0x0080 0000 SD/ MMC interface RxDataAvlbl, TxDat aAvlbl, RxFifoEmpty , TxFifoEmpty , R[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 1 18 of 792 NXP Semiconductors UM10237 Chapter 7: LPC24XX V ectored Interrupt Controller ( VIC) Fig 22. Block diagram of the V ectored Inte rrupt Con troller IntEnableClear [31:0] SoftIntClear [31:0] IntEnable [31:0] SoftInt [31:0] VICINT SOURCE [31:0] IntSel[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 1 19 of 792 1. How to read this chapter For information about the ind ividual LPC2400 parts, r efer to table T able 8–1 18 . Parts LPC2460 and LPC2 470 are flashless and use pi n s P3[15] and P3[14] for boot control. See the PINSEL registers ( Section 9–3[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 120 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration 2.2 LPC2400 208-pin p ackages 3. LPC2458 pinning information Fig 24. LPC2400 pinning L QFP208 package LPC2400FBD208 15 6 53 10 4 208 15 7 105 1 52 Fig 25. LPC2400 pinning T FBGA208 pa[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 121 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration 1T D O 2P 3 [ 1 1 ] / D 1 1 3P 3 [ 1 0 ] / D 1 0 4V SSIO 5 P1[0]/ENET_TXD0 6 P1[8]/ENET_CRS_DV/ ENET_CRS 7 P1[2]/ENET_TXD2/ MCICLK/PWM0[1] 8 P1[16]/ENET_MDC 9 P4[29]/BLS3/ MA T2[1]/RX[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 122 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration 1 NC 2 RSTOUT 3V SSCORE 4V SSIO 5A L A R M 6 7 8 9 10 P4[5]/A5 1 1 P2[9]/ USB_CONNECT1/ RXD2/EXTIN0 12 P4[9]/A9 13 P0[15]/TXD1/ SCK0/SCK 14 P0[16]/RXD1/ SSEL0/SSEL 15 - 16 - Row J 1 R[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 123 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration 5 P2[19]/CLKOUT1 6 P1 [21]/USB_TX_DM1/ PWM1[3]/SSEL0 7 P1[23]/USB_RX_DP1/ PWM1[4]/MISO0 8 P2[ 21]/DYCS 1 9V DD(DCDC)(3V3) 10 P1[29]/USB_SDA1/ PCAP1[1]/MA T0[1] 1 1 P0[1]/TD1/RXD3/SCL1[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 124 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P0[6]/ I2SRX_SDA/ SSEL1/MA T2[0] D1 1 [1] I/O P0[6] — Genera l purpose digital input/output pin. I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the rece[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 125 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P0[14]/ USB_HSTEN2 / USB_CONNECT 2 / SSEL1 M5 [1] I/O P0[14] — General purpose digi tal input/output pin. O USB_HSTEN2 — Host Enabled status for USB port 2. O USB_CONNECT2 — Sof[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 126 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P0[23]/AD0[0] / I2SRX_CLK/ CAP3[0] F5 [2] I/O P0[23] — General purpose digital input/output pin. I AD0[0] — A/D converter 0, input 0. I/O I2SRX_CLK — Receiv e Clock. It is drive[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 127 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P1[3]/ ENET_TXD3/ MCICMD/ PWM0[2] A9 [1] I/O P1[3] — General purpo se digital input/output pin. O ENET_TXD3 — Ethernet transmit data 3 (MII interface). I/O MCICMD — C ommand lin[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 128 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P1[16]/ ENET_MDC B8 [1] I/O P1[16] — General purpose digital input/output pin . O ENET_MDC — Ethernet MIIM clock. P1[17]/ ENET_MDIO C9 [1] I/O P1[17] — General purpose digital i[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 129 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P1[26]/ USB_SSPND1 / PWM1[6]/ CAP0[0] P8 [1] I/O P1[26] — General purpose digi tal input/output pin. O USB_SSPND1 — USB port 1 Bus Suspend status (OTG transceiver). O PWM1[6] — [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 130 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P2[3]/PWM1[4]/ DCD1/ PIPEST A T2 E13 [1] I/O P2[3] — General purpo se digital input/output pin. O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I DCD1 — Data Carrier Dete[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 131 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P2[12]/EINT2 / MCIDA T2/ I2STX_WS N14 [6] I/O P2[12] — General purpose digital input/output pin. I EINT2 — External interrupt 2 input. I/O MCIDA T2 — Data line 2 for SD/MMC inte[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 132 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P3[4]/D4 D3 [1 ] I/O P3[4] — General purpose digital input/output pin. I/O D4 — External memory data line 4. P3[5]/D5 E3 [1 ] I/O P3[5] — General purpose digital input/output pi[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 133 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P4[0]/A0 L6 [1 ] I/O P4[0] — General purpose digital input/output pin. I/O A0 — External memory address line 0. P4[1]/A1 M7 [1] I/ O P4[1] — General purpose digital input/output[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 134 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P4[24]/OE C8 [1] I/O P4[24] — General purpose digital input/output pin . O OE — LOW active Output Enable signal. P4[25]/WE D9 [1] I/O P4[25] — General purpose digital input/outp[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 135 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration [1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis. [2] 5 V tolerant pad providing digital I/O functions (with TTL levels an d hysteresis) and analog [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 136 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration 4. LPC2460/68 pinning information T able 12 1. LPC2420/60/68 pin allocatio n table CAN and Ethernet p ins for LPC2460/6 8 only . Pin Symbol Pin Symbol Pin Symbol Pin Symbol Row A 1 P3[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 137 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration 14 P2[1]/PWM1[2]/RXD1/ PIPEST A T0 15 V SSIO 16 P2[3]/PWM1[4]/ DCD1/PIPEST A T2 17 P2[6]/PCAP1[0]/ RI1/TRACEPKT1 Row F 1 P0[25]/AD0[2 ]/ I2SRX_SDA/TXD3 2 P3[4]/D4 3 P3[29]/D29/ MA T1[[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 138 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration 9 P1[23]/USB_RX_DP1/ PWM1[4]/MISO0 10 V SSCORE 11 V DD(DCDC)(3V3) 12 V SSIO 13 P2[15]/CS3 / CAP2[1]/SCL1 14 P4[17]/A17 15 P4[18]/A18 16 P4[19]/A19 17 V DD(3V3) --- Row R 1 P0[12]/USB_[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 139 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration T able 12 2. LPC2420/60/ 68 pin description Symbol Pin Ball Ty p e Description P0[0] to P0[31] I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for ea ch bit[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 140 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P0[9]/ I2STX_SDA/ MOSI1/MA T2[3] 158 [1] C14 [1] I/O P0[9] — General purpose digital input/output pin. I/O I2STX_SDA — T ransmit data. It is driven by the transmitter and read by [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 141 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P0[18]/DCD1/ MOSI0/MOSI 124 [1] K15 [1] I/O P0[18] — General purpose digital input/output pin. I DCD1 — Data Carrier Detect input for UART1. I/O MOSI0 — Master Out Slave In for [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 142 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P0[27]/SDA0 50 [4 ] T1 [4] I/O P0[27] — General purpose digital input/output pin. I/O SDA0 — I 2 C0 data input/output. Open-drain output (for I 2 C-bus compliance). P0[28]/SCL0 48[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 143 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P1[7]/ ENET_COL/ MCIDA T1/ PWM0[5] 153 [1] D14 [1] I/O P1[7] — General purpose digital input/output pin. I ENET_COL — Ethernet Collision detect (MII interface) (L PC2460 only). I/[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 144 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P1[19]/ USB_TX_E1 / USB_PPWR1 / CAP1[1] 68 [1] U6 [1] I/O P1[19] — General purpose digital input/output pin. O USB_TX_E1 — T ransmit Enable signal for USB port 1 (OTG transceiver)[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 145 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P1[29]/ USB_SDA1/ PCAP1[1] / MA T0[1] 92 [1] U14 [1] I/O P1[29] — General purpose digi tal input/output pin. I/O USB_SDA1 — USB port 1 I 2 C serial data (OTG transceiver). I PCAP1[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 146 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P2[6]/PCAP1[0]/ RI1/TRACEPKT1 138 [1] E17 [1] I/O P2[6] — General purpose digital input/output pin. I PCAP1[0] — Capture input for PWM1, channel 0. I RI1 — Ring Indicator input [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 147 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P2[15]/CS3 / CAP2[1 ]/SCL1 99 [6] P13 [6] I/O P2[15] — General purpose digital input/output pin . O CS3 — LOW active Chip Select 3 signal. I CAP2[1] — Capture input for T imer 2[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 148 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P2[30]/ DQMOUT2 / MA T3[2]/SDA2 31 [1] L4 [1] I/O P2[30] — General purpose digital input/output pin. O DQMOUT2 — Data mask 2 used with SDRAM and static devices. O MA T3[2] — Mat[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 149 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P3[15]/D15 28 [1] M1 [1] I/O P3[15] — General purpose digital input/output pin. I/O D15 — External memory data line 15. On POR, this pin serves as the BOOT1 pin (flashless part s [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 150 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P3[24]/D24/ CAP0[1 ]/ PWM1[1] 58 [1] R5 [1] I/O P3[24] — General purpose digital input/output pin. I/O D24 — External memory data line 24. I CAP0[1] — Capture input for T imer 0[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 151 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P4[3]/A3 97 [1 ] U16 [1] I/O P4[3] — General purpose digital input/output pin. I/O A3 — External memory address line 3. P4[4]/A4 103 [1] R15 [1] I/O P4[4] — General p urpose dig[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 152 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P4[21]/A21/ SCL2/SSEL1 11 5 [1] M15 [1] I/O P4[21] — General purpose digital input/output pin. I/O A21 — External m emory address l ine 21. I/O SCL2 — I 2 C2 clock input/output [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 153 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration [1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis. TCK 10 [1] E2 [1] I TCK — T est Clock for JT AG interface. Th is clock must be slower than 1 ⁄[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 154 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration [2] 5 V tolerant pad providing digital I/O functions (with TTL levels an d hysteresis) and analog input. When configured as a ADC input, digital section of the pad is disabled. [3] 5 [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 155 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration 13 P0[7]/I2STX_CLK/ LCDVD[9]/SCK1/ MA T2[1] 14 P0[9]/I2STX_SDA/ LCDVD[17]/MOSI1/ MA T2[3] 15 P3[18]/D18/ PWM0[3]/CTS1 16 P4[12]/A12 17 V DD(3V3) --- Row D 1T R S T 2 P3[28]/D 28/ CAP1[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 156 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration 14 P4[22]/A22 / TXD2/MISO1 15 P0[18]/DCD1 / MOSI0/MOSI 16 V DD(3V3) 17 P0[17]/CTS 1/ MISO0/MISO Row L 1 P3[7]/D7 2 RTCX2 3 V SSIO 4 P2[30]/DQMOUT2/ MA T3[2]/SDA2 14 NC 15 P4[26 ]/BLS0[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 157 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration 9 P1[24]/USB_RX_DM1/ LCDVD[10]/LCDVD[14]/ PWM1[5]/MOSI0 10 P1[25]/USB_LS1 / LCDVD[1 1]/LCDVD[15]/ USB_HSTEN1 /MA T1[1] 1 1 P4[2]/A2 12 P1[27]/USB_INT1 / LCDVD[13]/LCDVD[21]/ USB_OVRCR[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 158 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P0[4]/I2SRX_CLK/ LCDVD[0]/RD2/ CAP2[0] 168 [1] B12 [1] I/O P0[4] — General purpose digital input/output pin. I/O I2SRX_CLK — I 2 S Receive clock. It is driven by the master and re[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 159 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P0[10]/TXD2/ SDA2/MA T3[0] 98 [1] T15 [1] I/O P0[10] — General purpose digital input/outp ut pin. O TXD2 — Transmitter output for UAR T 2. I/O SDA2 — I 2 C2 data input/output (t[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 160 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P0[19]/DSR1/ MCICLK/SDA1 122 [1] L17 [1] I/O P0[19] — General purpose digital input/output pin. I DSR1 — Data Set Ready input fo r UART1. O MCICLK — Clock output line for SD/MMC[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 161 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P0[29]/USB_D+1 61 [5] U4 [5] I/O P0[29] — General purpose digital input/output pi n. I/O USB_D+1 — USB port 1 bidirectional D+ line. P0[30]/USB_D − 16 2 [5] R6 [5] I/O P0[30] ?[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 162 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P1[1 1]/ ENET_RXD2/ MCIDA T2/ PWM0[6] 163 [1] A14 [1] I/O P1[1 1] — General purpose digital input/output pin. I ENET_RXD2 — Ethernet Receive Data 2 (MII interface). I/O MCIDA T2 ?[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 163 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P1[22]/USB_RCV1/ LCDVD[8]/ LCDVD[12]/ USB_PWRD1/ MA T1[0] 74 [1] U8 [1] I/O P1[22] — General purpose digital input/output pi n. I USB_RCV1 — Differential receive data for USB port[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 164 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P1[29]/USB_SDA1/ LCDVD[15]/ LCDVD[23]/ PCAP1[1]/MA T0[1 ] 92 [1] U14 [1] I/O P1[29] — General purpose digital input/output pin. I/O USB_SDA1 — USB port 1 I 2 C serial data (OTG tr[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 165 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P2[0]/PWM1[1]/ TXD1/TRACECLK/ LCDPWR 154 [1] B17 [1] I/O P2[0] — General purpose digital input/output pin. O PWM1[1] — Pulse Width Modulator 1, channel 1 output. O TXD1 — Transm[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 166 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P2[8]/TD2/T XD2/ TRACEPKT3/ LCDVD[2]/ LCDVD[6] 134 [1] H15 [1] I/O P2[8] — General purpose digital input/output pin. O TD2 — CAN2 transmitter output. O TXD2 — Transmitter output[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 167 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P2[16]/CAS 87 [1] R1 1 [1] I/O P2[16] — General purpose digital input/output pi n. O CAS — LOW active SDRAM Column Address S trobe. P2[17]/RAS 95 [1] R13 [1] I/O P2[17] — Genera[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 168 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P2[31]/ DQMOUT3 / MA T3[3]/SCL2 39 [1] N2 [1] I/O P2[31] — General purpose digital input/output pi n. O DQMOUT3 — Data mask 3 used with SDRAM and st atic devi ces. O MA T3[3] — [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 169 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P3[15]/D15 28 [1] M1 [1] I/O P3[15] — General purpose digital input/output pin. I/O D15 — External memory data line 15 . On POR, this pin se rves as the BOOT1 pin (flash l e ss pa[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 170 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P3[24]/D24/ CAP0[1 ]/ PWM1[1] 58 [1] R5 [1] I/O P3[24] — General purpose digital input/output pi n. I/O D24 — External memory data line 24. I CAP0[1] — Capture input for T imer [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 171 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P4[3]/A3 97 [1] U16 [1] I/O P4[3] — General purpose digital input/output pin. I/O A3 — External m e mory address line 3. P4[4]/A4 103 [1] R15 [1] I/O P4[4] — General purpose dig[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 172 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration P4[21]/A21/ SCL2/SSEL1 11 5 [1] M15 [1] I/O P4[21] — General purpose digital input/output pin. I/O A21 — External memory address line 21. I/O SCL2 — I 2 C2 clock inpu t/output ([...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 173 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration TMS 6 [1] E3 [1] I TMS — T est Mode Select for JT AG interface. TRST 8 [1] D1 [1] I TRST — T est Reset for JT AG interface. TCK 10 [1] E2 [1] I TCK — T est Clock for JT AG inter[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 174 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration [1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis. [2] 5 V tolerant pad providing digital I/O functions (with TTL levels an d hysteresis) and analog [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 175 o f 792 NXP Semiconductors UM10237 Chapter 8: LPC24XX Pin configuration the address mirror bit is se t in the EMCControl register during POR, see Ta b l e 5 – 6 8 . Therefore, the user code residi ng in the ex ternal boot memory must be linked to execut[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 176 o f 792 1. How to read this chapter The LPC2400 p arts have dif ferent pin configur ations depending on the numbe r of pins. See T abl e 9–126 for the PINSEL registers needed to configure the dif ferent LPC2400 par ts: • Only LPC2470 and LPC247 8 have[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 177 o f 792 NXP Semiconductors UM10237 Chapter 9: LPC24XX Pin connect 3. Pin function select register values The PINSEL regis ters contro l the function s of device pi ns as shown b elow . Pairs of bits in these registers correspond to specifi c device pins. [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 178 o f 792 NXP Semiconductors UM10237 Chapter 9: LPC24XX Pin connect [1] Reset V alue reflects the data stored in used bits only . It does not include reserved bits content. Pin control module register reset values On power-o n reset and BOD re set, all regi[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 179 o f 792 NXP Semiconductors UM10237 Chapter 9: LPC24XX Pin connect 5.2 Pin Function Select Regi ster 1 (PINSEL1 - 0xE002 C004) The PINSEL1 re gister contr ols the func tions of the pins as per the settings listed in T able 9–131 . The direction control b[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 180 o f 792 NXP Semiconductors UM10237 Chapter 9: LPC24XX Pin connect [1] Pins P027] and P0[28] are open-drain for I 2 C0 and GPIO functionality for I 2 C-bus compliance. 5.3 Pin Function Select regi ster 2 (PINSEL2 - 0xE002 C008) The PINSEL2 re gister contr [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 181 o f 792 NXP Semiconductors UM10237 Chapter 9: LPC24XX Pin connect 5.5 Pin Function Select Regi ster 4 (PINSEL4 - 0xE002 C010) The PINSEL4 re gister contr ols the func tions of the pins as per the settings listed in T able 9–134 . The direction control b[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 182 o f 792 NXP Semiconductors UM10237 Chapter 9: LPC24XX Pin connect [1] See Section 9–5.1 1 “ Pin Function Select Register 10 (PINSEL10 - 0xE002 C028) ” fo r details on using the ETM functionality . T able 134 . LPC2458 pin fu nction select regi ster [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 183 o f 792 NXP Semiconductors UM10237 Chapter 9: LPC24XX Pin connect [1] See Section 9–5.1 1 “ Pin Function Select Register 10 (PINSEL10 - 0xE002 C028) ” fo r details on using the ETM functionality . 5.6 Pin Function Select Regi ster 5 (PINSEL5 - 0xE00[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 184 o f 792 NXP Semiconductors UM10237 Chapter 9: LPC24XX Pin connect T able 136 . LPC2458 pin fu nction select regi ster 5 (PINSEL5 - ad dress 0xE002 C014) bit description PINSEL5 Pin name Function w hen 00 Function when 01 Function when 10 Function when 1 1[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 185 o f 792 NXP Semiconductors UM10237 Chapter 9: LPC24XX Pin connect 5.7 Pin Function Select Regi ster 6 (PINSEL6 - 0xE002 C018) The PINSEL6 re gister contr ols the func tions of the pins as per the settings listed in T able 9–138 . The direction control b[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 186 o f 792 NXP Semiconductors UM10237 Chapter 9: LPC24XX Pin connect 5.9 Pin Function Select Regi ster 8 (PINSEL8 - 0xE002 C020) The PINSEL8 re gister contr ols the func tions of the pins as per the settings listed in T able 9–141 . The direction control b[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 187 o f 792 NXP Semiconductors UM10237 Chapter 9: LPC24XX Pin connect 5.10 Pin Function Select Regi ster 9 (PINSEL9 - 0xE002 C024) The PINSEL9 re gister contr ols the func tions of the pins as per the settings listed in T able 9–142 . The direction control [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 188 o f 792 NXP Semiconductors UM10237 Chapter 9: LPC24XX Pin connect 5.1 1 Pin Function Select Regist er 10 (PINSEL10 - 0xE002 C028) Only bit 3 of this register is used to con tr ol th e ETM inte rfa c e pin s. The value of the RTCK I/O pi n is sampled when [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 189 o f 792 NXP Semiconductors UM10237 Chapter 9: LPC24XX Pin connect 5.12 Pin Function Select Register 1 1 (PINSEL1 1 - 0xE002 C02C) This register is used to select the LCD function and th e LCD mode on the LPC247x. 5.13 Pin Mode select regist er 0 (PINMODE0[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 190 o f 792 NXP Semiconductors UM10237 Chapter 9: LPC24XX Pin connect 5.14 Pin Mode select regist er 1 (PINMODE1 - 0xE002 C044) This register cont rols pull-up/pu ll-down resistor co nfiguration for PO RT0 pins 16 to 26. For details see Section 9–4 “ Pin [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 191 o f 792 NXP Semiconductors UM10237 Chapter 9: LPC24XX Pin connect 5.18 Pin Mode select regist er 5 (PINMODE5 - 0xE002 C054) This register cont rols pull-up/pu ll-down resistor co nfiguration for PO RT2 pins 16 to 31. For details see Section 9–4 “ Pin [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 192 o f 792 NXP Semiconductors UM10237 Chapter 9: LPC24XX Pin connect 5.22 Pin Mode select regist er 9 (PINMODE9 - 0xE002 C064) This register cont rols pull-up/pu ll-down resistor co nfiguration for PO RT4 pins 16 to 31. For details see Section 9–4 “ Pin [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 193 o f 792 1. How to read this chapter The number of GPIO pins on each port is dif ferent for LPC2458 and LPC2460/68/70/78 part s. The available pins are listed in T able 10–156 for each p art. Bits corresponding to unavailable pins are r e served in all G[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 194 o f 792 NXP Semiconductors UM10237 Chapter 10: LPC24XX General Purpose In put/Output (GPIO) – Mask registers allow treating set s of port bits as a group, leaving other bits unchanged. – All GPIO registers are byte and ha lf-word addressab le. – Ent[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 195 o f 792 NXP Semiconductors UM10237 Chapter 10: LPC24XX General Purpose In put/Output (GPIO) 5. Pin description 6. Register description LPC2400 has up to five 32-bit General Purpose I/O port s. PORT0 and POR T1 are controlled via two group s of registers a[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 196 o f 792 NXP Semiconductors UM10237 Chapter 10: LPC24XX General Purpose In put/Output (GPIO) [1] Reset value reflects the data stored in used bi ts only . It does not include reserved bits content. T able 15 8. Summary of GPIO registers (legacy APB accessi[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 197 o f 792 NXP Semiconductors UM10237 Chapter 10: LPC24XX General Purpose In put/Output (GPIO) [1] Reset value reflects the data stored in used bi ts only . It does not include reserved bits content. T able 15 9. Summary of GPIO registers (local bus accessib[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 198 o f 792 NXP Semiconductors UM10237 Chapter 10: LPC24XX General Purpose In put/Output (GPIO) [1] Reset value reflects the data stored in used bi ts only . It does not include reserved bits content. 6.1 GPIO port Direction register IODIR and FIODIR(IO[0/1]D[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 199 o f 792 NXP Semiconductors UM10237 Chapter 10: LPC24XX General Purpose In put/Output (GPIO) Aside from the 32 -bit long and word only access ible FIODIR regist er , every fast GPIO port can also be controlled via several byte and half-wor d accessible r e[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 200 o f 792 NXP Semiconductors UM10237 Chapter 10: LPC24XX General Purpose In put/Output (GPIO) Legacy registers are th e IO0SET and IO1SET while the enhanced GPIOs are supported via the FIO0SET , FIO1SET , FIO2SET , FIO3SET , an d FIO4SET registers. Access t[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 201 o f 792 NXP Semiconductors UM10237 Chapter 10: LPC24XX General Purpose In put/Output (GPIO) 6.3 GPIO port output Clear register IOCLR and FIOCLR (IO[0/1]CLR - 0xE002 80[0/1]C and FIO[0/1/2/3/ 4]CLR - 0x3FFF C0[1/3/5/7/9]C) This register is used to produce[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 202 o f 792 NXP Semiconductors UM10237 Chapter 10: LPC24XX General Purpose In put/Output (GPIO) Aside from the 32-bit long an d word only accessible FIOCLR register , every fast GPIO port can also be controlled via several byte and half-word accessible regist[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 203 o f 792 NXP Semiconductors UM10237 Chapter 10: LPC24XX General Purpose In put/Output (GPIO) Writing to the IOPIN r egister stor es the valu e in the port output register , bypassing the need to use both the IOSET and IOCLR r egister s to obtain the entire[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 204 o f 792 NXP Semiconductors UM10237 Chapter 10: LPC24XX General Purpose In put/Output (GPIO) 6.5 Fast GPIO port Mask register FIOMASK(FIO[0/1/2/3/4]MASK - 0x3FFF C0[1/3/5/7/9]0) This register is availa ble in the enhanced grou p of registers only . It is u[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 205 o f 792 NXP Semiconductors UM10237 Chapter 10: LPC24XX General Purpose In put/Output (GPIO) Aside from the 32-bit long an d word only access ible FIOMASK register , every fast GPIO port can also be controlled via several byte and half-word accessible regi[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 206 o f 792 NXP Semiconductors UM10237 Chapter 10: LPC24XX General Purpose In put/Output (GPIO) 6.6 GPIO interrupt registers The following registers co nfigure the pins of port 0 and port 2 to genera te interrupt s. 6.6.1 GPIO overall Interrupt St atus regist[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 207 o f 792 NXP Semiconductors UM10237 Chapter 10: LPC24XX General Purpose In put/Output (GPIO) 6.6.4 GPIO Interrupt St atus for Rising edge register (IO0IntS tatR - 0xE002 8084 and IO2IntS tatR - 0xE002 80A4) Each bit in these read-only registe r s indicates[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 208 o f 792 NXP Semiconductors UM10237 Chapter 10: LPC24XX General Purpose In put/Output (GPIO) 7. GPIO usage notes 7.1 Example 1: sequential accesses to IOSET and IOCLR affecting the same GPIO pin/bit S tate of the output configured GPIO pin is det ermin ed [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 209 o f 792 NXP Semiconductors UM10237 Chapter 10: LPC24XX General Purpose In put/Output (GPIO) 7.3 Writing to IOSET/IOCLR vs. IOPIN Write to the IOSET/IOCLR register allows easy change of the port’s selected output pin(s) to high/low level at a time. Only [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 210 o f 792 1. How to read this chapter The Ethernet controller is avialable in p arts LPC2458 and LPC2460/68/70/78. 2. Basic configuration The Ethernet controller is configured using the following registers: 1. Power: In the PCONP register ( Ta b l e 4 – 6[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 21 1 of 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet 4. Features • Ethernet st andards support: – Supports 10 or 100 Mbps PHY devices including 10 Base-T , 100 Base-TX, 100 Base-FX , and 100 Base- T4. – Fully compliant with IEEE standard[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 212 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet – Memory traf fic optimized by buffer ing and pre-fetching. • Enhanced Ethernet featur es: – Receive filtering. – Multicast and broadcast frame suppor t for both transmit and receive[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 213 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet • The host registers module cont aining the r egisters in the software view and hand ling AHB accesses to the Ethernet block. The ho st registe rs connect to the transmit and receive datap[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 214 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet A receive filter block is used to identify rece ived frames that are not ad dressed to this Ethernet st ation, so that they can be discar ded. The Rx filters include a pe rfect address filte[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 215 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet Descriptors, which are stored in memory , contain information about fragment s of incoming or outgoing Ethernet frames. A fragment may be a n entire frame or a much smaller amount of data. E[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 216 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet A packet consist s of a preamble, a start-o f-frame delimiter and an Ethernet frame. The Ethernet frame consist s of the destinat ion address, the source address, an optional VLAN field, the[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 217 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet T able 1 1–185 sh ows the sign als used for Medi a Independent Interface Management (MIIM) of the external PHY . 7. Register description The softwa re interface of the Ethernet block c ons[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 218 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet T able 186. S ummary of Ethernet r egisters Symbol Address R/W Description MA C registers MAC1 0xFFE0 00 00 R/W MAC configuration register 1. MAC2 0xFFE0 00 04 R/W MAC configuration register[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 219 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet The third column in the table lists the accessibility of the register: read-only , write-only , read/write . All AHB register write transactions except for accesses to the interr upt registe[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 220 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet 7.1.1 MAC Configuration Register 1 (MAC1 - 0xFFE0 0000) The MAC configuration register 1 (MAC1) has an address of 0xFFE0 0000. Its bit definition is shown in T able 1 1–187 . 7.1.2 MAC Con[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 221 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet 3 DELA YED CRC This bit determin es th e number of by tes, if any , of proprietary header informatio n that exist on the front of IEEE 802.3 frames . When 1, four byte s of header (ignored b[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 222 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet 7.1.3 Back-to-Back Inter-Packet-Gap Register (IPG T - 0xFFE0 0008) The Back-to-Back Inter-Packet-Gap register (IPG T) has an add ress of 0xFFE0 0008. Its bit definiti on is shown in T able 1[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 223 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet 7.1.6 Maximum Frame Register (MAXF - 0xFFE0 0014) The Maximum Frame register (MAXF) has an ad dr ess of 0xFFE0 0014. Its bit definition is shown in T able 1 1–193 . 7.1.7 PHY Support Regis[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 224 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet 7.1.9 MII Mgmt Configuration Register (MCFG - 0xFFE0 0020) The MII Mgmt Configuration reg ister (MCFG ) has an add ress of 0xFFE0 0020. The bit definition of this register is shown in T able[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 225 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet 7.1.1 1 MII Mgmt Address Register (MADR - 0xFFE0 0028) The MII Mgmt Address regist er (MADR) has an address of 0 xFFE0 0028. The bit definition of this register is shown in T able 1 1–199 [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 226 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet Here are two exam p les to access PHY via th e MI I Management Co nt roller . For PHY Write if scan is not used: 1. Write 0 to MCM D 2. Write PHY address and regi ster address to MADR 3. Wri[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 227 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet The station ad dress is used for perfect addr ess filterin g and for sending p ause control frames. For the ordering of the octet s in the packet please refer to Figure 1 1–27 . 7.1.17 St [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 228 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet All bits can be written and re ad. The Tx/RxReset bi t s are write only , re ading will return a 0. 7.2.2 St atus Register (St atus - 0xFFE0 0104) The S tatus registe r (S tatus) is a Read O[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 229 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet The receive descriptor ba se address is a byte address aligned to a word boundary i.e . LSB 1:0 are fixed to ’00’. The registe r cont ains th e lowest address in the array of descriptors[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 230 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet The receive produce index register defines t he descriptor that is goi ng to be filled next by the hardware rece ive process. Af ter a frame has been received, h ardware in crement s the ind[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 231 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet The transmit status base address is a byte address aligned to a word boundary i.e. LSB 1:0 are fixe d to ’00’. The register co ntains the lowest address in the array of st atuses. 7.2.10[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 232 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet 7.2.12 T ransmit Consume Index Register (TxConsumeIndex - 0xF FE0 012C) The T ransmit Consume Index register (TxConsu m eIndex) is a Rea d Only registe r with an address of 0xFFE0 012C. Its [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 233 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet [1] The EMAC doesn't distinguish the fra me type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and g[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 234 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet T able 1 1–220 lists the bit definitions of the RSV register . [1] The EMAC doesn't distinguish the fra me type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets a[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 235 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet 7.2.17 Flow Control St atus Register (FlowControlSt atus - 0xFFE0 0174) The Flow Control S tatus register (Flo wContr olS tatus) is a Read Only register with an address of 0xFFE0 8174. T abl[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 236 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet 7.3.2 Receive Filter WoL S tatus Register (RxFilterW oLSt atus - 0xFFE0 0204) The Receive Filter W ake-up on LAN S tatus regi ster (RxFilterWoLS tatus) is a Read Only register with an addres[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 237 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet The bits in this regis ter are writ e-only; writing resets the corres ponding bits in th e RxFilterWoLS tatus register . 7.3.4 Hash Filter T able LSBs Register (HashFilterL - 0xFFE0 0210) Th[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 238 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet The interrupt st atus register is read-only . Setting can be done via the IntSet register . Reset can be accomplished via the IntClear register . 7.4.2 Interrupt Enable Register (IntEnable -[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 239 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet 7.4.3 Interrupt Clear Register (IntClear - 0xFFE0 0FE8) The Interru pt Clear regi ster (IntClear) is a Write Only re gister with an address o f 0xFFE0 0FE8. The interrupt clear register bit [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 240 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet The interrupt set register is write-only . Wr iting a 1 to a bit of the IntSet regis ter sets the correspond ing bit in th e status register . Writing a 0 will not affect the interrupt statu[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 241 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet Receive descriptors are stored in an array in memory . The base address of the array is stored in the RxDescriptor register , and shou ld be aligned on a 4 byte address boundary . The number[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 242 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet Each receive descriptor takes two word lo cations (8 bytes) in memory . Likewise each status field takes two words (8 bytes) in me mory . Each receive descriptor consists of a pointer to the[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 243 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet The S tatusInfo word contains flag s re turn ed by the MAC and flags generated by the receive datap ath reflecting the sta tus of the reception. T able 1 1–237 lists the bit definitions in[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 244 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet 8.2 T ransmit descriptors and statuses Figure 1 1–29 depicts the layout of the tr ansmit descriptors in memory . T ransmit d escriptors are stored in an array in memory . The lo west a ddr[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 245 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet Each transmit descriptor take s two word location s (8 bytes) in memo ry . Likewis e ea ch status field t akes one word (4 bytes) in memory . Each transmit descriptor consists of a pointer t[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 246 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet For multi-fragment frames, the value of the LateCollision, ExcessiveCollision, ExcessiveDefer , Defer and CollissionCount bit s in all but the last frag ment in the frame will be 0. The stat[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 247 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet data buf fer and receive status is returned in the receive descripto r st atus word. Optionally an interrupt can be generated to notify sof tware that a packet has been received. No te that [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 248 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet The DMA managers work with ar rays of frame descriptors and statuses that are stored in memory . The descriptors and statuses a ct as an interface betwee n the Ethernet hardware and the devi[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 249 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet Ethernet block has finished readi ng/writing the last descriptor/ st atus of the array (with the highest memory address), the next descri ptor/status it reads/writes is the first descriptor/[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 250 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet to a fragment of a frame. By using fragmen ts, scatter/gathe r DMA can be done: transmit frames are gathered fro m multiple fragments in mem ory and receive frames can be scattered to multip[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 251 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet be written to the T xDescrip torNum ber /RxDescrip torNumb er register s using a -1 e ncodin g i.e. the valu e in the regist ers is the nu mber of descriptors minus one e.g. if the descripto[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 252 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet When there is a multi-fragment tr ansmissio n for fr agment s other tha n the last, the Last bit in the descriptor mu st be set to 0; for the last fragment the Last bit must be set t o 1. T [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 253 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet Each time the Tx DMA manager commits a status word to memory it completes the transmission of a descriptor and it increm ents the TxConsumeIndex (taking wrap around into account) to hand the[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 254 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet IntS tatus register is set in the case of a Lat eCollision, ExcessiveCollision, Excess iveDefer , or NoDescriptor error; Underrun errors are reported in the TxUnderrun bi t of the IntS tatus[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 255 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet All of the above interrupt s can be enabled and disabled by setting or resetting the correspond in g bits in the IntEn abl e re gis te r . Enabl ing or disabling does not affect the IntS tat[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 256 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet (0x7FE0 1 1F8) to the TxS tatus register . The de vi ce driver writes the n umber of descriptors and statuses minu s 1(3) to the TxDescri ptorNu mber register . The descriptors and statuses [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 257 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet Since the Interrupt bit in the descriptor of t he last fragment is set, after committing the status of the last fragment to memory the Ethernet block will trigger a TxDoneInt interrupt, whic[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 258 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet descriptors to be read is determined by the total nu mber of descriptors owned by the hardware: RxConsumeI ndex - RxProduceIndex - 1. Block transfe rr ing of descriptors minimizes memory loa[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 259 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet addresses of a packet are calculated once for all the fragments belong ing to the same packet and then stored in ever y S tatusHashCRC word of the st atuses associated with the corresponding[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 260 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet The receive dat apath can gener ate four different interrupt types: • If the Interrupt bit in the descriptor Cont rol field is set, the Rx DMA will set the RxDoneInt bit in the IntS tatus [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 261 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet After reset, the values of the DMA registers will be zero. During initia lization, the device driver will allocate the descriptor and status array in memory . In this example, an array of fo[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 262 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet continuous memory space; even when a frame is distributed ov er multiple fragments it will typically be in a linear , continuous memory sp a ce; when the descriptors wrap at the end of the d[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 263 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet Each pair of nibbles transferred on the MII in terface (or four pairs of bits for RMII) is transferred as a byte on the data write in terface after bein g delayed b y 128 or 1 36 cycles for [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 264 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet The destination addr ess and source addre ss hash CRCs being written in the S tatusHashCRC word are the nine most significant bits of the 32 bit CRCs as calculated by the CRC ca lculator . 9[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 265 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet T ransmit flow control is activated by writi ng 1 to the TxFlowControl bi t of th e Command register . When the Et hernet block operat es in full duplex mode , this will result in transmissi[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 266 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet T ransmit flow control is enabled via th e ‘TX FLOW CONTROL ’ bit in the MAC1 configuration register . If the ‘TX FLOW CONTROL ’ bit is zero, then the MAC will not transmit pause con[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 267 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet In half duplex mode, when the TxFlowControl bit goes high, continuous preamble is sent until TxFlowControl is deasserted. If the m edium is idle, the Ethern et block begins transmitting prea[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 268 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet Ethernet MAC will stop writing further data in th e frame to memo ry; the FailFilter bit in the status word of the frame will be set to indicate that the software device driver can discard t[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 269 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet An imperfec t filter is availa ble, based on a hash mechanism. This filter applies a h ash function to the de stin a tion ad dr es s and uses the hash to access a table that indicates if the[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 270 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet 9.15 W ake-up on LAN Overview The Ethernet block supp orts powe r management with remote wake-up over LAN. The host system can be powered down, even includi ng pa rt of the Ethernet block it[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 271 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet The magic p acket detection unit analyzes th e Ethernet p ackets, extracts th e packet address and checks the payload for the Magic Packet patter n. The address from the packet is used for m[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 272 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet After a reset, the st at e machine is in the INACTIVE state. As soon as the RxEnable bit is set in the Com mand regis ter , the state mach ine transitions to the ACTIVE state. As soon as the[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 273 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet After reset, the st ate machine is in th e INACTI VE state. As soon as the TxEnable bit is set in the Command register and the Produce and Consume indices are n o t equal, the state machine [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 274 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet If EP ADEN is 1, then s mall frames will be p added and a CRC will alw ays be added to the padded frames. In this case if ADPEN an d VLPEN are both 0, then the frames will be padded to 60 by[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 275 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet 9.21 Reset The Ethernet block has a hard r eset input wh ich is conn ected to th e chip r eset, as well as several soft resets which can be activated by setti ng the ap prop riate bit(s) in [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 276 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet • RegReset: Resets all of the datap aths and registers in the host registers module, excluding the registers in the MAC. A soft re set of the registers will als o abort all AHB transaction[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 277 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet The flexibility of the descriptors used in the Et hernet block allows the possibility of defining memory buf fers in a range of sizes. In order to analyze bus bandwidth req u irement s, some[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 278 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet – Data to be received in an Ether net frame, th e size is varia ble. – Basic Ethernet rate = 12 .5 Mbps. This gives a tot al rate of 30.5 Mbps for th e tr af fic generated by the Etherne[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 279 o f 792 NXP Semiconductors UM10237 Chapter 1 1: LPC24XX Ethernet int crc_calc(ch ar frame_no_fcs[], int frame_len) { int i; // iterator int j; // another iterator char byte; // current byte int crc; // CRC result int q0, q1, q 2, q3; // temporar y variabl[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 280 o f 792 1. How to read this chapter The LCD controller is available on par ts LPC2 470 and LPC2 478 only . 2. Basic configuration The LCD controller is configured using the following registe rs: 1. Power: In the PCONP register ( Ta b l e 4 – 6 3 ), set [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 281 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller • 256 entry , 16-bit palette RAM, arranged as a 12 8x 32-bit RAM. • Frame, line, and pix el cloc k s ign als . • AC bias signal for STN, dat a enable signal for TFT panels. • [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 282 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller The hardwar e cursor rem oves the re quirement fo r this mana gement by pr oviding a completely sep arate image buf fer for the cursor , and superimposing the cursor image on the LCD [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 283 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller • 16 bpp, direct 4:4:4 RGB, with 4 bpp not being used. 4.6 Monochrome STN p anels Monochrome STN p anels support one or more of the following modes: • 1 bpp, palettized, 2 gray sc[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 284 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller 5.1.2 Signals used for dual panel STN disp lays The signals used for dual p anel STN displays are shown in T able 12–244 . UD refers to upper p anel data, and LD refers to lower p a[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 285 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller 6. LCD controller functional descri ption The LCD controller performs tr anslation of pixel-coded dat a into the required format s and timings to drive a variety of single or dual p a[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 286 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller • Bus error . There is als o a single com bined interru pt that is ass erted when a ny of the in dividual interrupt s become active. Figure 12–36 shows a simplified block diagram [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 287 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller 6.1.2 AMBA AHB master interface The AHB master interface transfers display da ta from a selected slave (memory) to the LCD controller DMA FIFOs. It can be configur ed to obtain dat a [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 288 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller T able 12–246 through T ab le 12–248 show the structure of the data in each DMA FIFO word corresponding to the endia nness and bpp combinations. For each of the three supported da[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 289 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller T able 247 . FIFO bits for Big-endian Byte, Big-endia n Pixel order FIFO bit 1 b pp 2 bpp 4 bpp 8 bpp 16 bpp 24 bpp 31 p0 p0 p0 p0 p0 30 p1 29 p2 p1 28 p3 27 p4 p2 p1 26 p5 25 p6 p3 2[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 290 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller T able 12–249 shows the structure of the dat a in each DMA FIFO word in RGB mode. T able 248 . FIFO bits for Little-endi an Byte, Big-endian Pixe l o rder FIFO bit 1 b pp 2 bpp 4 bp[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 291 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller 6.4 RAM p alette The RAM-based p alette is a 256 x 16 bit dual-port RAM physically structured as 128 x 32 bits. T wo entries can be written into the palette from a single wor d write [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 292 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller Pixel data value s can be written and ve ri fied through the AHB slav e int erface. For information on the suppor ted colors, refer to the section on the related pane l type earlier i[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 293 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller For monochrome STN mode , only the red palette field bit s [4:1] are used. However , in STN color mode the green and b lue [4:1] are also used. Only 4 bit s per color are used, becaus[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 294 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller When the display point is insid e the bounds of the cur so r image, the cursor replaces frame buf fer pixels with cursor pixels. When the last cur sor pixel is displaye d, an interrup[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 295 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller With FrameSync inactive, the cursor responds immediate ly to any change in the programmed CRSR_XY value. Some transient smearing ef fects may be visible if the cursor is mo ved across[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 296 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller 6.5.6 Cursor image format The LCD frame buffer supp orts three p acking formats, but the ha rdware cursor image requirement has been simplified to support only LBBP . This is little-e[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 297 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller T able 12–255 shows the buf fer to pixel mapping for Cursor 0. 64 by 64 pi xel format Only one cursor fit s in the me mory s pace in 64 x 64 m ode. T a ble 12–256 shows the 64 x 6[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 298 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller Cursor pixel encoding Each pixel of th e cursor requ ires two bits of informat ion. These a re interpreted as Color0, Color1, T ransparen t, and Transp arent inverted. In the coding s[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 299 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller Each formatter consists of thre e 3-bit (RGB) shif t left registers. RGB pixel da ta bit values from the gray scaler are concurr ently shifte d into the re spective registers. When en[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 300 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller • Next base address update inte rrupt. • FIFO underflow interrupt. Each of the four individual maskable interrupt s is enabled or disabled by changing the mask bits i n the LCD_IN[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 301 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller 6.12 LCD power up an d power down sequence The LCD controller require s the following power-up sequence to be performed : 1. When power is applied, the following signals are held LOW [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 302 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller 7. Register description T able 12–259 shows the re gisters assoc iated with the LCD cont roller and a s ummary of their functions. Following the tabl e are det ails for each registe[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 303 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller [1] Reset V alue reflects the data stored in used bi ts only . It does not include reserved bits content. 7.1 LCD Configuration register (LCD_CFG , RW - 0xE01F C1B8) The LCD_CFG regis[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 304 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller 7.2.1 Horizontal timing restrictions DMA requests ne w data at the st art of a horizontal display line. Some time must be allowed for the DMA transfer an d for data to prop agate down[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 305 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller • PCD = 5 (LCDCLK / 7) If enough time is given at the start of the line, for example, setting HSW = 6, HBP = 10 , data does not co rrupt for PCD = 4, the minimum value. 7.3 V ertica[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 306 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller 7.4 Clock and Signal Polarity regist er (LCD_POL, R W - 0xFFE1 0008) The LCD_POL register co ntrols various de t ails of clock timing and signal polarity . The content s of the LCD_PO[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 307 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller 15 re served Reserved , user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - 14 I OE Invert output enable. This bit selects the a[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 308 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller 7.5 Line End Control register (LCD_LE, RW - 0xFFE1 000C) The LCD_LE register controls the enablin g of line-end signal LCDLE. When ena bled, a positive pulse, four LCDCLK periods wide[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 309 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller 7.6 Upper Panel Frame Base Address register (LCD_UPBASE, RW - 0xFFE1 0010) The LCD_UPBASE register is th e color LCD upper p anel DMA base address register , and is used to program th[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 310 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller Optionally , the value may be chang ed mid-frame to create double- buffered video displays. These registers are copied to th e correspond ing current registers at each LCD vertical sy[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 31 1 of 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller 10 BEPO Big-Endian Pixel Ordering. Controls pixel ordering within a byte: 0 = little-endian orderin g within a byte. 1 = big-endian pixel orderin g within a byte. The BEPO bit selects[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 312 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller 7.9 Interrupt Mask register (L CD_INTMSK, RW - 0xFFE1 001C) The LCD_INTMSK register contro ls whether various LCD interrupt s occur .Setting bits in this register enables the correspo[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 313 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller 7.10 Raw Interrupt St atus regist er (LCD_INT RA W , RW - 0xFFE1 0020) The LCD_INTRA W register cont ains sta tus fl ags for various LCD contro ller events. These flags can generate a[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 314 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller 7.1 1 Masked Interrupt St atus register (LCD_INTST A T , RW - 0xFFE1 0024) The LCD_INTST A T register is Read-Only , and contains a bit-by-b it logical AND of the LCD_INTRAW register [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 315 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller 7.13 Upper Panel Current Address register (LCD _UPCURR, RW - 0xFFE1 002C) The LCD_UPCURR register is Read-Only , and contains an approximate value of the upper p anel data DMA addr es[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 316 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller Each word location contain s two palette entri es. This me ans that 128 word locations are used for the p a lette. When configured for littl e- endian byte ordering, bit s [15:0] are [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 317 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller 7.17 Cursor Control register (CRSR_CTRL, RW - 0xFFE1 0C00) The CRSR_CTRL register provides access to frequently used cursor functions, such as the display on/of f control for the cu r[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 318 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller 7.19 Cursor Palette register 0 (CRSR_P AL0, R W - 0xFFE1 0C08) The cursor palette registe r s provide color p ale tte information for the visible colors of the cursor . Color0 maps th[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 319 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller 7.21 Cursor XY Position regist er (CRSR_XY , RW - 0xFFE1 0C10) The CRSR_XY register defi nes the distan ce of the top-lef t edge of the cursor from the top-left side of the cursor ove[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 320 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller 7.23 Cursor Interrupt Mask register (CRSR_INTMSK, RW - 0xFFE1 0C20) The CRSR_INTMSK register is used to enable or disable the cursor from interrupting the processor . The content s of[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 321 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller 7.25 Cursor Raw Interrupt St atus re gister (CRSR_INTR A W , RW - 0xFFE1 0C28) The CRSR_INTRA W register is set to indicate a cursor interrupt. When enabled via the CrsrIM bit in the [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 322 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller 8. LCD timing diagrams (1) T he active data lines will vary with the type of STN panel (4-bit, 8-bit, colo r , mono) and with single or dual frames. (2) T he LCD panel clock is select[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 323 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller (1) S ignal polarities may va ry for some displays. Fig 42. V ertical timing for STN disp lays LCD_TIMV (VSW) LCDDCLK (panel clock) LCD_TIMV (VBP) LCD_TIMV(LPP) LCD_TIMV (VFP) LCDFP ([...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 324 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller 9. LCD p anel signal usage (1) Polarities may vary for some displays. Fig 44. V ertical timing for TFT displays LCD_TIMV (VSW) LCDENA (data enable) LCD_TIMV (VBP) LCD_TIMV(LPP) LCD_TI[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 325 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller [1] ETM replaced with LCD pins. [2] External interrupt pins EINT1 , EINT2 , EINT3 replaced with LCD pins. [3] Timer pins MA T2[0] and MA T2[1] replaced with LC D pins. LCDVD[8] - - - [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 326 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller [1] ETM replaced with LCD pins. [2] External interrupt pins EINT1 , EINT2 , EINT3 replaced with LCD pins. [3] Timer pins MA T2[0] and MA T2[1] replaced with LC D pins. [4] USB OTG pin[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 327 o f 792 NXP Semiconductors UM10237 Chapter 12: LPC24XX L C D controller [1] ETM replaced with LCD pins. [2] External interrupt pins EINT1 , EINT2 , EINT3 replaced with LCD pins. [3] Timer pins MA T2[0] and MA T2[1] replaced with LC D pins. [4] USB OTG pin[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 328 o f 792 1. Basic configuration The USB controller is configur ed using the following registe rs: 1. Power: In the PCONP register ( Ta b l e 4 – 6 3 ), set bit PCUSB. Remark: On reset, the USB block is disabled (PCUSB = 0). 2. Clock: see T able 4–54 . [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 329 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 3. Features • Fully compliant with the USB 2. 0 specification (full s peed). • Supports 32 physical (16 logical) end points. • Supports Control, Bulk, Interr upt and Isoch[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 330 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 5. Functional description The architecture of the USB devi ce controller is shown below in Figure 13–4 5 . 2 4 Bulk Out 8, 16, 32, 64 Y es 2 5 Bulk In 8, 16, 32, 64 Y es 3 6 I[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 331 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 5.1 Analog transceiver The USB Device Controller has a built-in analog transceiver (A TX). The USB A TX sends/receives the bi-directional D+ and D- signals of th e USB bus. 5.2 [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 332 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 5.5 DMA engine and bus master interface When enabled for an endpoint, the D MA Engine tr ansfers data betw een RAM on the AHB bus and the endpoint’ s buffer in EP_RAM. A singl[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 333 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller Once data has be en received or sent, the end point buf fer can be read or wr itten. How this is accomplished depends on the end point’s ty pe and operating mod e. The two ope[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 334 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 8.1 Power requirement s The USB protocol insist s on power management by th e device. This becomes very critica l if the device draws power from the bus (bus -powered device). T[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 335 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller After enteri ng the suspend st ate with DEV_CLK_EN and AHB_CLK_EN cleared, the DEV_CLK_ON and AHB_CLK_ON will be cleared when the corresponding clock turns off. When both bits a[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 336 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller [1] Reset value reflects the data stored in used bi ts only . It does not include reserved bits content. [2] The USBPortSel register is identical to the OTGS tC trl register (se[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 337 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 9.2 Clock control registers 9.2.1 USB Clock Control register (USBClkCtrl - 0xFFE0 CFF4) This register controls the clocking of t he USB Device Controller . Whenever softwa re wa[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 338 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 9.3 Device interrupt registers 9.3.1 USB Interrupt St atus register (USBIntSt - 0xE01F C1C0) The USB Device Controller has three interrupt lines. This r egister allows software [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 339 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 9.3.2 USB Device Interrupt St atus register (USBDevIntS t - 0xFFE0 C200) The USBDevIn tS t register holds the status of e ach interrupt. A 0 indicates no interrupt a nd 1 indica[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 340 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 9.3.3 USB Device Interrupt Enable register (USBDevIntEn - 0xFFE0 C204) Writing a one to a bit in this register enables the corresponding bit in USBDevIntS t to generate an inter[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 341 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 9.3.5 USB Device Interrupt Set register (USBDevIntSet - 0xFFE0 C20C) Writing one to a b it in this register sets the corresponding bi t in the USBDevIntS t . Writing a zero has [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 342 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 9.3.6 USB Device Interrupt Priority register (USBDevIntPri - 0xFFE0 C22C) Writing one to a bit in this registe r causes the corresponding interr upt to be routed to the USB_INT_[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 343 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 9.4.2 USB Endpoint Interrupt Enable reg ister (USBEpIntEn - 0xFFE0 C234) Setting a bit to 1 in this register causes the corresponding bit in USBEp IntS t to be set when an inter[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 344 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 9.4.3 USB Endpoint Interrupt Clear registe r (USBEpIntClr - 0xFFE0 C238) Writing a one to this a bit in this register causes the SIE Select End point/Clear Interrupt command to [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 345 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 9.4.4 USB Endpoint Interrupt Set register (USBEpIntSet - 0xFFE0 C23C) Writing a one to a bit in this register set s the correspondi ng bit in USBEpIntS t. Writing zero has no ef[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 346 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 9.5 End point realiz atio n registers The registers in this group allow realizatio n and configuration of end points at run time. 9.5.1 EP RAM requirements The USB device contr [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 347 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller Since all the realized en d point s occupy EP_ RAM space, the tot al EP_RAM requir ement is where N is the number of realized end points. T otal EP_RAM space sh ould not exceed [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 348 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller USBReEp |= (U Int32) ((0x1 << en dpt)); /* Load Endpo int index Reg with physical endpoint no.*/ USBEpIn = (UI nt32) endpointnumb er; /* load the m ax packet size Reg iste[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 349 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 9.6 USB transfer registers The registers in this group are used fo r transferring data between end point buffers and RAM in Slave mode operation. See Section 13–13 “ Slave m[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 350 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 9.6.3 USB T ransmit Dat a register (USBTxData - 0xFFE0 C21C) For an IN transactio n, the CPU wr ites the end point dat a into this register . Before writing to this register , t[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 351 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 9.6.5 USB Control register (USBCtrl - 0xFFE0 C228) This register controls the da ta transfer operat ion of the USB de vice. It selects the endpoint buffer that is a ccessed by t[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 352 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 9.7.2 USB Command Dat a register (USBCmdData - 0xFFE0 C214) This register contains th e data retr ieved af ter executing a SIE comma nd. When the dat a is ready to be read, the [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 353 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller [1] DMA can not be enabled for this endpoint and the corresponding bit in the USBDMARSt must be 0. 9.8.2 USB DMA Request Clear register (USBDMARClr - 0xFFE0 C254) Writing one to[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 354 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller Software can also use this re gister to initiate a DMA tran sfer to proactively fill an IN endpoint buf fer before an IN token packet is received from the host. USBDMARSet is a [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 355 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 9.8.6 USB EP DMA Enable register (USBEpDMAEn - 0xFFE0 C288) Writing one to a bit to this register will enable the DMA op eration for the corresponding endpoin t. Writing zero ha[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 356 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 9.8.9 USB DMA Interrupt Enable register (USBDMAIntEn - 0xFFE0 C294) Writing a one to a bit in this register enables the corresponding bit in USBDMAIntS t to generate an interrup[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 357 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 9.8.1 1 USB End of T ransfer Interrupt Clear register (USBEoTIntClr - 0xFFE0 C2A4) Writing one to a bit in this register clear s the corresponding bit in the USBEoTIntSt registe[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 358 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 9.8.14 USB New DD Request Interrupt Clear register (USBNDDRIntClr - 0xFFE0 C2B0) Writing one to a bit in this registe r clears the corresponding bit in the USBNDDRIntS t registe[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 359 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 9.8.18 USB System Error Interrupt Set register (USBSysErrIntSet - 0xFFE0 C2C0) Writing one to a bit in this register sets the co rresponding bit in the USBSysErrIntS t register [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 360 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller register to request low priori ty interr upt hand ling. Howeve r , the USBDevIntPri register can route either the FRAME or th e EP_F AST bit to the USB_INT_REQ_HP bit in the USB[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 361 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller For simplicity , USBDevIntEn and USBDMAIntEn are not shown. Fig 47. Interrupt event handling USB_INT_REQ_HP USB_INT_REQ_LP USB_INT_REQ_DMA EN_USB_INTS to VIC channel #22 . . . .[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 362 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 1 1. Serial interface engine command description The functions and registers of the Seria l Interface Engi ne (SIE) are accessed using commands, which consist of a command code [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 363 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 1 1.1 Set Address (Command: 0xD 0, Data: write 1 byte) The Set Address command is used to set the USB assign ed address and enable the (embedded) function. The address set in th[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 364 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 1 1.3 Set Mode (Command: 0xF 3, Dat a: write 1 byte) [1] This bit should be reset to 0 if the DMA is enabled for any of the Interrupt OUT endpoints. [2] This bit should be reset[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 365 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 1 1.4 Read Current Frame Nu mber (C ommand: 0xF5, Data: read 1 or 2 bytes) Returns the frame number of the last success fully re ceived SOF . The frame numbe r is eleven bit s w[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 366 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 1 1.7 Get Device St atus (Command: 0xF E, Data: read 1 byte) The Get Device S tatus comman d returns the De vice S tatus Register . Reading the device status retu rns 1 byte of [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 367 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 1 1.9 Read Error St atus (Comma nd: 0xFB, Data: read 1 byte) This command reads the 8- bit Error register from the USB device . This register records which error e vents have re[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 368 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 1 1.10 Select Endpoint (Command: 0x00 - 0x1F , Data: read 1 byte (optional)) The Select Endpoin t command initializes an in ternal pointe r to the start of the selected buffer i[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 369 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 1 1.1 1 Select End point/Clear Interrupt (Command: 0x40 - 0x5F , Data: read 1 byte) Commands 0x40 to 0x5F are identical to their Select End p oint equivalent s, with the followi[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 370 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 1 1.13 Clear Buffer (Command: 0xF2 , Data: read 1 by te (optional)) When an OUT packet sent by the ho st has be e n re ce ived suc ces sfu lly , an internal hardware FI FO statu[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 371 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller Internally , there is a hardware FIFO status fla g called Buffer_Full. This flag is set by the V alidate Buffer command and clear ed when the dat a has been sent on the USB bus [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 372 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller – Clear all DMA interrupts using USBEoTIntClr , USBNDDRIntClr , and USBSysErrIntClr . – Prepare the UDCA in system me mory . – Write the desired address for the UDCA to US[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 373 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller endpoint s, the next packet will be received ir res pectiv e of whether the buffer has been cleared. Any data not re ad from the buffer before the end of the fr ame is lost. See[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 374 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 14.2 USB device communication area The CPU and DMA controlle r communicate through a common area of memor y , called the USB Device Communication Area, or UDCA . The UDCA is a 3[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 375 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller In DMA mode, the bits correspo nding to Inte rrupt on NAK for B ulk OUT and Interrupt OUT endpoin t s (INAK_BO and INAK_IO) should be set to 0 u sing th e SIE Set Mo de co mma n[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 376 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller [1] Write only in A TLE mode Legend: R - Read; W - Write; I - Initialize 14.4.1 Next_DD_pointer Pointer to the memory location from wh ere the next DMA descri ptor will be fetch[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 377 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 14.4.6 DMA_buffer_length This indicates the depth of the DMA buf fer allocated for transferr ing the data . Th e DMA engine will stop using this descriptor when this limit is re[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 378 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 14.4.1 1 LS_byte_extracted Used in A TLE mode. When set, this bit indicates that the Least Significant Byte (LSB) of the transfer length h as been extracted. Th e extr acted siz[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 379 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller If a new descriptor has to be re ad, the DMA engine will calcul ate the location of the DDP for this endpoint and will fetch the start address of the DD from this location. A DD[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 380 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller USB transfer end complet i on - If the curr ent packet is fully tra nsferred and its size is less than the Max_packet_size field, and the end of the DM A buf fer is still not re[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 381 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller The isochronous p acket size is stored in memory as shown in figure 32. Each word in the packet size memory shown is divided into fields: Frame_number (bi ts 31 to 17), Packet_v[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 382 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 14.7 Auto Length T ransfer Extr action (A TLE) mode operation Some host drivers such as NDIS (Network Driver Interf ac e S pec ification) host drivers are capable of con catenat[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 383 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller Figure 13–50 shows a typical OUT U SB transfer in A TLE mode, wher e the host concatenat es two USB t ransfers of 16 0 bytes an d 100 byte s, respective ly . Given a MaxPacket[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 384 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller In A TLE mode, the last buffer length to be transfer red always ends with a short or emp t y packet indicating th e end of the USB transfer . If the concatenated transfer length[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 385 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 14.7.4 Ending the packet transfer The DMA engi ne proceeds with the transfer unt il the number of bytes specified in the field DMA_buffer_length is transferre d to or from the U[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 386 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 5. Software send s the SIE Select Endpoint comma nd to read the Select Endpoint Register and test the FE bit. Software fi nds that the ac tive buffer (B_2) h as data (FE=1). Sof[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 387 o f 792 NXP Semiconductors UM10237 Chapter 13: LPC24XX USB devic e controller 1 1. Both B_1 and B_2 are empty , and the acti ve buf fer is B_2. Th e next packet written b y software will go into B_2. In DMA mode, switching of the active buff er is handled[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 388 o f 792 1. Basic configuration The USB controller is configur ed using the following registe rs: 1. Power: In the PCONP register ( Ta b l e 4 – 6 3 ), set bit PCUSB. Remark: On reset, the USB block is disabled (PCUSB = 0). 2. Clock: see T able 4–54 . [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 389 o f 792 NXP Semiconductors UM10237 Chapter 14: LPC24XX USB Host controller • OpenHCI specifies the operation and in terf ace of the USB Host Controller and SW Driver – USBOperational: Process List s and generate SOF T okens. – USBReset: Forces reset[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 390 o f 792 NXP Semiconductors UM10237 Chapter 14: LPC24XX USB Host controller 3.1.1 USB host usage note Both ports can be config ured as USB host s . For det ails on how to connect the USB port s, see the USB OTG chapte r , Sectio n 15 –6 “ Pin co nf igu[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 391 o f 792 NXP Semiconductors UM10237 Chapter 14: LPC24XX USB Host controller T able 36 0. USB Host registe r add ress definitions Name Address R/W [1] Functio n Reset value HcRevision 0xFFE0 C000 R BCD representation of the version of the HCI specificati on[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 392 o f 792 NXP Semiconductors UM10237 Chapter 14: LPC24XX USB Host controller [1] The R/W column in T able 14–360 lists the accessibility of the register: a) Reg isters marked ‘R’ for access will return their current value when read. b) Reg isters mark[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 393 o f 792 1. Basic configuration The USB controller is configur ed using the following registe rs: 1. Power: In the PCONP register ( Ta b l e 4 – 6 3 ), set bit PCUSB. Remark: On reset, the USB block is disabled (PCUSB = 0). 2. Clock: see T able 4–54 . [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 394 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller support an OTG connection. The communication between the register interface and an external OTG transceiver is handled through an I 2 C interfac e and thro ugh the extern al OTG tr[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 395 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller The following figures show diff erent ways to realize connections to an USB device using ports U1 and U2. Th e example described here uses an ISP1301 (NXP) for the external OTG tra[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 396 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller 1. Use the internal USB transceiver for USB signalling and use the external OTG transceiver for OTG func tionality only (see Figure 15–53 ). This option uses the internal transce[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 397 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller Fig 54. USB OTG port configurat ion: VP_VM mode USB_TX_DP1 USB_TX_DM1 USB_RCV1 USB_RX_DP1 USB_RX_DM1 USB_SCL1 USB_SD A1 SPEED ADR/PSW SD A SCL RESET_N INT_N VP VM SUSPEND OE_N/INT_[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 398 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller 6.2 Connecting USB as a two-port host Both port s U1 and U2 are connected as host s using an embedded USB transce iver . There is no OTG functionality on eith er port. 6.3 Connecti[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 399 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller 7. Register description The OTG and I 2 C registers ar e summarized in the following t able. The Device and Host r egisters are expla ine d in Se ction 14–3.2.1 and Sect ion 13?[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 400 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller [1] Bits 0 and 1 of this register are used to contr ol t he routing of the USB pins to ports 1 and 2 in device-only applications (see Section 13–9.1.1 ). 7.1 USB Interrupt St atu[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 401 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller 7.2 OTG Interrupt St atus Re gister (OTGIntS t - 0xE01F C100) Bits is this register ar e set by hardware wh en the interrupt event occurs du ring the HNP handof f sequence. See Sec[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 402 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller 2. Free running mode: a n interrupt is generated at the end of TIMEOUT_ CNT (see Section 15–7.7 “ OTG Ti mer Register (OTG Tmr - 0xFFE0 C1 14) ” ), the TMR bit is set, and th[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 403 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller 7.7 OTG Timer Register (OTG Tmr - 0xFFE0 C1 14) 7.8 OTG Clock Control Register (OTGClkCtrl - 0xFFE0 CFF4) This register controls the clocking of the OTG controller . Whenever softw[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 404 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller 7.9 OTG Clock St atus Regist er (OTGClkSt - 0xFFE0 CFF8) This register holds the clock av ailability st atus. When enabling a clock via OTGClkCtrl, software should po ll the corres[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 405 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller 7.10 I2C Receive Re gister (I2C_RX - 0xFFE0 C300) This register is the top byte of the receive FIFO. The receive FIF O is 4 bytes deep. The Rx FIFO is flushed by a hard reset or by[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 406 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller T able 372 . I2C status register (I2C_STS - address 0xFFE0 C304) bit description Bit Symbol Va l u e Description Re set Va l u e 0 TDI T ransaction Done Interrupt. T his flag is se[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 407 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller 7.13 I2C Control Register (I2C_CTL - 0xF FE0 C308) The I2C_CTL register is used to enable interrupt s and reset the I 2 C state machine. Enabled interrupt s cause the USB_I2C_INT i[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 408 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller 7.14 I2C Clock High Register (I2C_CLKHI - 0xFFE0 C 30C) The CLK regist er holds a terminal count for counting 48 MHz clock cycles to create the high period of the slo wer I 2 C ser[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 409 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller 7.15 I2C Clock Low Register (I2C_CLKLO - 0xFF E0 C310) The CLK regist er holds a terminal count for counting 48 MHz clock cycles to create the low period of the slower I 2 C serial[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 410 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller 8. HNP support This section describes the h ardware support for the Host Negotiation Protocol (HNP) provided by the OTG contro ller . When two dual-role OTG devices are connected t[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 41 1 of 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller 8.1 B-device: peripheral to host switching In this case, the default role of the OTG contr oller is per iphera l (B-d evice), and it switches roles from Peripheral to Host. The On-[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 412 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller Figure 15–61 shows the action s that the OTG sof tware stack should take in response to the hardwa re actions s etting REMOVE_ PU , HNP_SUCCESS, AND HNP_F AILURE. The relationshi[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 413 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller Note that only the subset of B-device HN P sta t es and state transitio n s supported by hardware are shown. Sof tware is responsib le for implementing all of the HNP states. Figur[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 414 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller /* Wait for TDI to be set */ while (!(OTG_I2 C_STS & TDI)); /* Clear TDI */ OTG_I2C_STS = T DI; Add D+ pull-up /* Add D+ pull- up through ISP1301 */ OTG_I2C_TX = 0x 15A; // Sen[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 415 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller Figure 15–63 shows the action s that the OTG sof tware stack should take in response to the hardware actions se tting TMR, HNP_SUCCESS, and HN P_F AILURE. The relationship of the[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 416 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller Note that only the subset of A-device HN P sta t es and state transitio n s supported by hardware are shown. Sof tware is responsib le for implementing all of the HNP states. Figur[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 417 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller Set BDIS_ACON_EN in external OTG transceiver /* Set BDIS_ACO N_EN in ISP1301 */ OTG_I2C_TX = 0x 15A; // Send ISP13 01 address, R/W=0 OTG_I2C_TX = 0x 004; // Send Mode Control 1 (Se[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 418 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller Load and enab le OTG timer /* The followin g assumes that the OTG timer has pre viously been */ /* configured f or a time scale of 1 ms (TMR_SCALE = “10”) */ /* and monoshot mo[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 419 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller 9.1 Device clock request signals The Device controller has two clock request signals, dev_need_clk and dev_dma_need_clk. When a sserted, these sig nal s turn on the device’ s 48 [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 420 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller The dev_dma_need _clk signal is asserted on any Device controller DMA access to memory . Once asserted, it rema ins active for 2 ms (2 frames ), to help assure that DMA throughput [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 421 o f 792 NXP Semiconductors UM10237 Chapter 15: LPC24XX USB OTG contro ller 4. Enable the desired USB pin functio ns by writing to the correspo nding PINSEL registers. 5. Follow the appropriate steps in Section 13–12 “ USB device controller initializat[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 422 o f 792 1. Basic configuration The UART0 / 2/3 peripher als are configured using the following registe r s: 1. Power: In the PCONP register ( Ta b l e 4 – 6 3 ), set bits PCUART0/2/3. Remark: On reset, UAR T 0 is enabled (PCUAR T0 = 1), and UART2/3 are [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 423 o f 792 NXP Semiconductors UM10237 Chapter 16: L PC24XX Universal Asynchr onous Receiver/T ransmitter 4. Register description Each UART cont ains registers as shown in T able 16–377 . The Divisor Latch Access Bit (DLAB) is contained in UnLCR7 and enable[...]

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UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 426 o f 792 NXP Semiconductors UM10237 Chapter 16: L PC24XX Universal Asynchr onous Receiver/T ransmitter 16.4.1 U ARTn Receiver Buff er Regi ster (U0RBR - 0xE000 C000, U2RBR - 0xE007 8000, U3RBR - 0xE007 C000 when DLAB = 0, Read Only) The UnRBR is the top by[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 427 o f 792 NXP Semiconductors UM10237 Chapter 16: L PC24XX Universal Asynchr onous Receiver/T ransmitter higher 8 bits of the divisor . A 0x0000 value is treated like a 0x0001 value as division by zero is not allowed. The Divi sor Latch Access B it (DLAB) in[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 428 o f 792 NXP Semiconductors UM10237 Chapter 16: L PC24XX Universal Asynchr onous Receiver/T ransmitter 4.5 UARTn Interrupt Identification Regi ster (U0IIR - 0xE 000 C008, U2IIR - 0xE007 8008, U3IIR - 0x7008 C008, Read Only) The UnIIR provides a st atus cod[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 429 o f 792 NXP Semiconductors UM10237 Chapter 16: L PC24XX Universal Asynchr onous Receiver/T ransmitter The UARTn RDA interr upt (UnIIR[3:1] = 010) shares the second level priority with the CTI interrupt (UnIIR[3:1] = 1 10). The RDA is acti vated when the U[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 430 o f 792 NXP Semiconductors UM10237 Chapter 16: L PC24XX Universal Asynchr onous Receiver/T ransmitter THRE = 1 and there have not been at least two characters in the UnTHR at one time since the last THRE = 1 event. This delay is pr ovided to give the CPU [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 431 o f 792 NXP Semiconductors UM10237 Chapter 16: L PC24XX Universal Asynchr onous Receiver/T ransmitter 4.8 UARTn Line St atus Register (U0LSR - 0xE000 C014, U2LSR - 0xE007 8014, U3LSR - 0xE007 C014, Read Only) The UnLSR is a read-o nly register that prov i[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 432 o f 792 NXP Semiconductors UM10237 Chapter 16: L PC24XX Universal Asynchr onous Receiver/T ransmitter 2P a r i t y E r r o r (PE) 0 When the parity bit of a received character is in the wrong state, a parity error occurs. An Un LSR read clears UnLSR[2]. T[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 433 o f 792 NXP Semiconductors UM10237 Chapter 16: L PC24XX Universal Asynchr onous Receiver/T ransmitter 4.9 UARTn Scratch Pad Register (U0SCR - 0xE000 C01C, U2SCR - 0xE007 801C U3SCR - 0xE007 C01C) The UnSCR has no ef fect on the UARTn operat ion. This regi[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 434 o f 792 NXP Semiconductors UM10237 Chapter 16: L PC24XX Universal Asynchr onous Receiver/T ransmitter 16.4.10.1 Auto-baud The UAR Tn auto-baud function can be used to measure the incoming baud-rate based o n the ”A T" protocol (Hayes command). If e[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 435 o f 792 NXP Semiconductors UM10237 Chapter 16: L PC24XX Universal Asynchr onous Receiver/T ransmitter 1. On UnACR S tart bit se tting, the baud-rate measurement counte r is reset and the UARTn UnRSR is reset. The UnRSR baud ra te is switch to the highest [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 436 o f 792 NXP Semiconductors UM10237 Chapter 16: L PC24XX Universal Asynchr onous Receiver/T ransmitter 4.1 1 IrDA Control Register for UA RT3 Only (U3ICR - 0xE007 C024) The IrDA Control Register enable s and configures the IrDA mode for UAR T3 only . The v[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 437 o f 792 NXP Semiconductors UM10237 Chapter 16: L PC24XX Universal Asynchr onous Receiver/T ransmitter 4.12 UARTn Fractional Divider Regist er (U0FDR - 0xE000 C028, U2FDR - 0xE007 8028, U3FDR - 0xE007 C028) The UART0/2/3 Frac tional Divider Register (U0/ 2[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 438 o f 792 NXP Semiconductors UM10237 Chapter 16: L PC24XX Universal Asynchr onous Receiver/T ransmitter The value of MUL V AL and DIV ADDV AL shou ld comply to the following conditions: 1. 0 < MUL V AL ≤ 15 2. 0 ≤ DIV ADDV AL < 15 3 . D I VA D D V[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 439 o f 792 NXP Semiconductors UM10237 Chapter 16: L PC24XX Universal Asynchr onous Receiver/T ransmitter Fig 66. Algorit hm for setting U ART dividers PCLK, BR Calculating U ART baudrate (BR) DL est = PCLK/(16 x BR) DL est is an integer? DIV ADD V AL = 0 MUL[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 440 o f 792 NXP Semiconductors UM10237 Chapter 16: L PC24XX Universal Asynchr onous Receiver/T ransmitter 4.12.1.1 Example 1: PCLK = 14.7456 MHz, BR = 9600 According to the the provided al gorithm DL est = PCLK/(16 x BR) = 14.7456 MHz / (16 x 9600) = 96. Sinc[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 441 o f 792 NXP Semiconductors UM10237 Chapter 16: L PC24XX Universal Asynchr onous Receiver/T ransmitter T able 16–394 describes how to use TXEn bit in order to achieve sof tware flow control. 5. Architecture The architectur e of the UART s 0, 2 an d 3 ar [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 442 o f 792 NXP Semiconductors UM10237 Chapter 16: L PC24XX Universal Asynchr onous Receiver/T ransmitter Fig 67. U AR T0, 2 and 3 block diagram APB INTERFACE UnLCR UnRX DDIS UnLSR UnFCR UnBRG UnTX INTERRUPT PA[2:0] PSEL PSTB PWRITE PD[7:0] AR MR PCLK UnINTR [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 443 o f 792 1. Basic configuration The UART1 peripher al is configur ed using the f ollowing regis ters: 1. Power: In the PCONP register ( Ta b l e 4 – 6 3 ), set bits PCUAR T1. Remark: On reset, UAR T 1 is enabled (PCUAR T1 = 1). 2. Peripheral cloc k: In t[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 444 o f 792 NXP Semiconductors UM10237 Chapter 17: L PC24XX Universal Asynchr onous Receiver/T ransmitter 3. Pin description 4. Register description UART1 cont ains registers organ ized as shown in T able 17–396 . The Divisor Latch Access Bit (DLAB) is cont[...]

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UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 447 o f 792 NXP Semiconductors UM10237 Chapter 17: L PC24XX Universal Asynchr onous Receiver/T ransmitter 4.1 UART1 Receiver Buffer Regist er (U1RBR - 0xE001 0000, when DLAB = 0 Read Only) The U1RBR is the top byte of th e UAR T1 RX FIFO. The top byte of the [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 448 o f 792 NXP Semiconductors UM10237 Chapter 17: L PC24XX Universal Asynchr onous Receiver/T ransmitter (3) 4.4 UART1 Interrupt Enable Regi ster (U1IER - 0xE001 0004, when DLAB = 0) The U1IER is used to enable th e four UART1 interr upt source s. T able 399[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 449 o f 792 NXP Semiconductors UM10237 Chapter 17: L PC24XX Universal Asynchr onous Receiver/T ransmitter 4.5 UART1 Interrupt Identification Re gister (U1IIR - 0xE001 0008, Read Only) The U1IIR provides a st atus code that denot es the priority an d source of[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 450 o f 792 NXP Semiconductors UM10237 Chapter 17: L PC24XX Universal Asynchr onous Receiver/T ransmitter Bit U1IIR[9:8] are set by the au to -baud function a nd signa l a time- out or e nd of auto- baud condition. The auto-baud inte rrupt conditions are clea[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 451 o f 792 NXP Semiconductors UM10237 Chapter 17: L PC24XX Universal Asynchr onous Receiver/T ransmitter wished to send a 105 character me ssage and the trigger level wa s 10 characters, the CPU would receive 10 RDA interrupts resulting in the transfer of 10[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 452 o f 792 NXP Semiconductors UM10237 Chapter 17: L PC24XX Universal Asynchr onous Receiver/T ransmitter It is the lowest priority inter ru pt and is ac tiva te d wh enev er there is any state change on modem inputs pins, DCD, DSR or CTS. In addition, a low [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 453 o f 792 NXP Semiconductors UM10237 Chapter 17: L PC24XX Universal Asynchr onous Receiver/T ransmitter 4.8 UART1 Modem Control Regi ster (U1MCR - 0xE001 0010) The U1MCR enables the modem loopb ack mode and controls the modem outp ut sig nals. 5:4 Parity Se[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 454 o f 792 NXP Semiconductors UM10237 Chapter 17: L PC24XX Universal Asynchr onous Receiver/T ransmitter 4.9 Auto-flow control If auto-RTS mode is ena bled the UAR T 1‘s receiver FIFO hardwar e controls the RT S1 output of the UART1. If the auto-CTS mode i[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 455 o f 792 NXP Semiconductors UM10237 Chapter 17: L PC24XX Universal Asynchr onous Receiver/T ransmitter 17.4.9.2 A uto-CTS The Auto-CTS function is enabled by setting th e CTSen bit. If Auto-CTS is enabled the transmitter circuitry in the U1 TSR module chec[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 456 o f 792 NXP Semiconductors UM10237 Chapter 17: L PC24XX Universal Asynchr onous Receiver/T ransmitter 4.10 UART1 Line St atus Register (U1LSR - 0xE001 0014, Read Only) The U1LSR is a read-o nly register that prov ides status info rmation on the UAR T1 TX [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 457 o f 792 NXP Semiconductors UM10237 Chapter 17: L PC24XX Universal Asynchr onous Receiver/T ransmitter 4.1 1 UART1 Modem St atus Regi ster (U1MSR - 0xE001 0018) The U1MSR is a read-only register th at provides st a tus information on the modem input signal[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 458 o f 792 NXP Semiconductors UM10237 Chapter 17: L PC24XX Universal Asynchr onous Receiver/T ransmitter 4.12 UART1 Scratch Pad Register (U1SCR - 0xE001 001C) The U1SCR has no ef fect on the UART1 operat ion. This register can be written and/or read at user?[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 459 o f 792 NXP Semiconductors UM10237 Chapter 17: L PC24XX Universal Asynchr onous Receiver/T ransmitter 4.14 Auto-baud The UAR T1 auto-baud function can be used to measure the incoming baud-rate based o n the ”A T" protocol (Hayes command). If enabl [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 460 o f 792 NXP Semiconductors UM10237 Chapter 17: L PC24XX Universal Asynchr onous Receiver/T ransmitter 4.15 Auto-baud modes When the soft ware is expecting an ”A T" command, it configures the UART1 with the expected character format and set s the U1[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 461 o f 792 NXP Semiconductors UM10237 Chapter 17: L PC24XX Universal Asynchr onous Receiver/T ransmitter 4.16 UART1 Fractional Divider Re gister (U1FDR - 0xE001 0028) The UART1 Fractional Divider Registe r (U1F DR) controls the clock pre-scaler for the baud [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 462 o f 792 NXP Semiconductors UM10237 Chapter 17: L PC24XX Universal Asynchr onous Receiver/T ransmitter This register controls the clock p re-scaler for th e bau d rate gener ation. The r eset value of the register keeps the fractional capabilitie s of UART[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 463 o f 792 NXP Semiconductors UM10237 Chapter 17: L PC24XX Universal Asynchr onous Receiver/T ransmitter Fig 71. Algorit hm for setting U ART dividers PCLK, BR Calculating U ART baudrate (BR) DL est = PCLK/(16 x BR) DL est is an integer? DIV ADD V AL = 0 MUL[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 464 o f 792 NXP Semiconductors UM10237 Chapter 17: L PC24XX Universal Asynchr onous Receiver/T ransmitter 4.16.1.1 Example 1: PCLK = 14.7456 MHz, BR = 9600 According to the the provided al gorithm DL est = PCLK/(16 x BR) = 14.7456 MHz / (16 x 9600) = 96. Sinc[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 465 o f 792 NXP Semiconductors UM10237 Chapter 17: L PC24XX Universal Asynchr onous Receiver/T ransmitter Although T able 17–414 describes how to use TxEn bit in order to achieve ha rdware flow control, it is strongly suggested to let UAR T1 h ardware imple[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 466 o f 792 NXP Semiconductors UM10237 Chapter 17: L PC24XX Universal Asynchr onous Receiver/T ransmitter S tatus information from the U1 TX and U1RX is stored in the U1LSR. Control information for the U1 TX and U1RX is stored in the U1LCR. Fig 72. U ART1 blo[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 467 o f 792 1. How to read this chapter The CAN controller in available on p arts LPC2458 and LPC2460/68 /7 0/78. 2. Basic configuration The CAN1/2 periphe rals are configured using the following registers: 1. Power: In the PCONP register ( Ta b l e 4 – 6 3[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 468 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 4. Features 4.1 General CAN features • Compatible with CAN specification 2.0B, ISO 1 1898-1 . • Multi-master architecture with non destructive bit-wise arbitration. • Bus [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 469 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 6. CAN controller architecture The CAN Controller is a complete serial inte rface with both T ransmit and Receive Buffer s but without Acceptance Filter . CA N Identifier filter[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 470 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 6.3 T ransmit Buffers (TXB) The TXB repr esents a T riple Tra n smit Buf f er , which is the interface between the Interface Management Log ic (IML) and the Bit S tream Processo[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 471 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 6.5 Error Management Logic (EML) The EML is responsible for the error confine ment. It gets error announcement s from the BSP and then informs the BSP an d IML about error stati[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 472 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 Both self-tes ts are using the ‘Self Reception’ feature of the CAN Cont roller . With the Self Reception Request, the transmitted message is al so received and stored in the[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 473 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 7. Memory map of the CAN block The CAN Controllers and Accept ance Filter occupy a number of APB slots, as follows: 8. Register description CAN block implement s the registers s[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 474 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 [1] The error counters can only be written when RM in CANMOD is 1 . [2] These registers can on ly be written when RM in CANMOD is 1. The internal regis te rs of each CAN Con tr [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 475 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 In the following register t ables, the column “Reset V alue” shows how a hardware reset affect s each bit or field, wh ile the column “RM Set” indica tes how each bit or[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 476 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 [1] During a Hardware reset or wh en the Bus S tatus bit is set '1' (Bus-Off), the Reset Mode bit is set '1' (present). After the Reset Mode bit is set &apos[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 477 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 [1] - Setting the command bits TR and A T simultaneously results in transmitting a message once. No re-transmissi on will be perfo rmed in case of an error or arbitration lost ([...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 478 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 [2] If the Transmission Request or the Self-R eception Request bit was set '1' in a previ ous command, it cannot be can celled by r esetting the bits. The requested tr[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 479 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 [1] After reading all messages and releasing their memory space with the command 'Releas e Receive Buffer ,' this bit is cleared. [2] If there is not enough space to s[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 480 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 RX Error Counter = (CANxGSR AND 0x00FF0000) / 0x000 10000 Note that a CPU-forced content change o f t he RX Error Counter is possible only if the Reset Mode was entered previous[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 481 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 Bits 24-31 are captured w hen CAN ar bit ra tio n is lost. At the sa me time , if the ALIE bit in CANIER is 1, the ALI bit in this register is set, and a CAN inte rr upt can occ[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 482 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 8 IDI 0 (reset) 1 (set) ID Ready Interrupt -- this bit is set if t he ID IE bit in CANxIER is 1, and a CAN Identifier has been received (a message was su ccessfully transmitted [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 483 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 20:16 ERRBIT 4:0 [3] Error Code Capture: when the CAN controller detects a bus error , the locat ion of the error within the fram e is captured in this field. T he value reflect[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 484 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 [1] The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register . Giving the Command “Release Receive Buffer” will clear RI temporarily . If there [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 485 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 8.6 Bus Timing Register (C AN1BTR - 0xE004 4014, CAN2BTR - 0xE004 8014) This register controls h ow vari ous CAN timin g s are derived from the APB cloc k. It defines the values[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 486 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 Baud rate pres caler The period o f the CAN syst em clock t SCL is programmable and determines the individual bit timing. The CAN system clock t SCL is calculated using the foll[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 487 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 (9) (10) 8.7 Error W arning Limit Register (CAN1EWL - 0xE004 4018, CAN2EWL - 0xE004 8018) This register sets a limit on Tx or Rx errors at which an inte rrupt can occur . It can[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 488 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 5 TS1 Transmit S tatus 1. 1 0 0(idle) There is no transmission from Tx Buffer 1. 1(transmit) The CAN Controller is transm i tting a message from Tx Buffer 1. 6 ES Error S tatus.[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 489 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 [1] If the CPU tries to write to this Transmit Buffer when the T rans mit Buffer S tatus bit is '0' (locked), the written byte is n ot accepted and is lost without thi[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 490 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 8.9.1 ID index field The ID Index is a 10-bit field in the Info Register that cont ains the table position of the ID Look-up T able if the currently received messag e was acce p[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 491 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 8.12 Receive Dat a Register B (C AN1RDB - 0xE004 4 02C, CAN2RDB - 0xE004 802C) This register cont ains the 5th through 8th Dat a bytes of the current received message. It is rea[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 492 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 Automatic tran smit priority detection T o allow uninterrupted streams of transmit messages, the CAN Controller provides Automatic T ransmit Priority De tection for all T ransmi[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 493 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 8.14 T ransmit Iden tifier Register (CAN1 TID[1/2/3] - 0xE004 40[34/44/54], CAN2TID[1/2/3] - 0xE004 80[34/44/54]) When the corresponding TBS bit in CANxSR is 1, sof tware can wr[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 494 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 8.16 T ransmit Data Regi ster B (CAN1 TDB[1/2/3] - 0xE004 40[3C/4C/5C], CAN2TDB[1/2/3] - 0xE004 80[3C/4C/5C]) When the corresponding TBS bit in CANSR is 1, sof twar e can write [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 495 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 The CAN Controller wakes up (and sets WUI in the CAN Interrupt register if WUIE in the CAN Interrup t Enable register is 1) in respon se to a) a d ominan t bit o n the CAN b us,[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 496 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 10.2 Central Receive St atus Re gister (CANRxSR - 0xE004 0004) 10.3 Central Miscellaneous St atus Register (CANMSR - 0xE004 0008) 15:10 - Reserved, user software should n ot wri[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 497 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 1 1. Global accept ance filter This block provides lookup for received Ident ifiers (called Acceptan ce Filtering in CAN terminology) for all the CAN Controllers. It includes a [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 498 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 12.2 Accept ance filter Bypass mode The Accept ance Filter Bypa ss Mode can be used for example to change the accept a nce filter configuration during a running system, e.g. cha[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 499 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 If S tandard (1 1 bit) Ide nt ifie rs ar e us ed in t he application, at least one of 3 tables in Acceptance Filter RAM must not be empty . If the optional “fullCAN m ode” i[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 500 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 The table of ranges of Extended Ide ntifiers must contain an even numbe r of entries, of the same form as in the individual Extended Iden tifier table. Like the Individual Exte [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 501 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 [1] Acceptance Filter Bypass Mode (AccBP): By setting the AccBP bit in the Acceptance F ilter Mode Register , the Acceptance filter is put into the Acceptance Filt er Bypass mod[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 502 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 15.3 St andard Frame Individual St art Address Register (SFF_sa - 0xE003 C004) [1] Write access to the look-up table section configur ation registers are possible only dur ing t[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 503 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 15.5 Extended Frame St art Address Register (EFF_sa - 0xE003 C00C) [1] Write access to the look-up table section configur ation registers are possible only dur ing the Acceptanc[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 504 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 15.7 End of AF T ables Regist er (ENDofT able - 0xE003 C014) [1] Write access to the look-up table section configur ation registers are possible only dur ing the Acceptance filt[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 505 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 15.10 LUT Error Register (LUT err - 0xE003 C01C) 15.1 1 Global FullCANInterrupt Enable register (FCANIE - 0xE003 C020) A write access to the Global FullCAN Interrupt Enable regi[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 506 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 16. Configuration and search algorithm The CAN Identifier Look-up T able Memory can cont ain explicit identifiers and groups of CAN identifiers for S tanda rd and Extended CA N [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 507 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 The identifier 0x5A of the CAN Controller 1 with the Source CAN Channel SCC = 1, is defined in all three sectio ns . With this configuration in coming CAN messages on CAN Contro[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 508 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 receive interrupt whenever a CAN message is accepted and received. Sof tware has to move the receive d message out of the receive buffer from the accor ding CAN controller into [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 509 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 17.1 FullCAN message layout The FF , RTR, and DLC fields are as describ ed in T able 18–428 . Since the FullCAN message object section of the Look-up table RAM can be access e[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 510 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 Fig 82. Semaphore proced ure for reading an auto-sto re d message read 1 st word SEM == 01? SEM == 11? clear SEM, write back 1 s t word read 2 nd and 3 rd words read 1 st word S[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 51 1 of 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 17.2 FullCAN interrupt s The CAN Gateway Block cont ains a 2 kB ID Look-up T able RAM. With this size a maximum number of 14 6 FullCAN objects ca n be defined if the wh ole Look[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 512 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 17.2.2 Message lost bit and CAN channel number Figure 18–84 is the det ailed layout structure of one FullCAN message stored in the FullCAN message object sectio n of the Look-[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 513 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 17.2.3 Setting the interrupt pending bit s (IntPnd 63 to 0) The interrupt pe nd in g bit (I ntP nd x) gets asserte d in case of an ac cep te d FullC AN message and if the in ter[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 514 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 17.3.2 Scenario 2: Message lost In this scenario a first FullCAN Message is sto r ed and read out by Sof tware (1 st O bject write and read) . In a second course a second messag[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 515 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 17.3.3 Scenario 3: Message get s overwritten indicated by Semaphore bit s This scenario is a special case in which the lost message is indicated by the existing semaphore bit s.[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 516 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 17.3.5 Scenario 3.2: Message get s overwritten indicated by Message Los t This scenario is a sub-case to Scenario 3 in which the lost mess age is indi ca ted by Message Lost. Fi[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 517 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 17.3.6 Scenario 4: Clearing Message Lost bit This scenario is a special case in which the lost message bit of an object gets set during an overwrite of a none read messag e obje[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 518 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 18. Examples of accept ance fil ter t ables and ID index values 18.1 Example 1: only on e section is used SFF_sa < ENDofTable OR SFF_GRP_sa < ENDofTable OR EFF_sa < END[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 519 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 In cases where explicit identifiers as well as group s of the identifiers are prog rammed, a CAN identifier search has to star t in the explicit identifier section first. If no [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 520 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 18.6 Configuration example 6 The T able below shows which sections and t herefore which types of CAN identifiers are used and a ctivated. T he ID-Look-up T ab le configura tion [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 521 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 Explicit st andard frame format identifier sect ion (1 1-bit CAN ID): The star t addr ess of the Exp licit S tandard Fr ame Fo rma t sectio n is d efined in th e SF F_sa registe[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 522 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 18.7 Configuration example 7 The T able below shows which sections and t herefore which types of CAN identifiers are used and a ctivated. T he ID-Look-up T ab le configura tion [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 523 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 FullCAN explicit st andard frame format ident fier section (1 1-bit CAN ID) The start ad dress of the FullCAN Explicit S t andard Frame Format Identifier section is (automatical[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 524 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 18.8 Look-up t able prog ramming guidelines All identifier sections of the ID Look-up T abl e have to be programmed in such a way , that each active section is organized as a so[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 525 o f 792 NXP Semiconductors UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 • Each section ha s to be or ganized as a s orted list or table with an increa sing order of the Source CAN Channel (SCC ) in conjunction with the CA N Identifier (there is no[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 526 o f 792 1. Basic configuration The SPI is configured using the following registe rs: 1. Power: In the PCONP register ( Ta b l e 4 – 6 3 ), set bit PCSPI. Remark: On reset, the SPI is enabled (PCSPI = 1). 2. Clock: In PCLK_SEL0 select PCLK_SPI (see Ta b [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 527 o f 792 NXP Semiconductors UM10237 Chapter 19: LPC24XX SPI The dat a and clock phase relationship s are summarized in T able 19–459 . This table summarizes the following for each setting of CPOL and CPHA. • When the first data bit is driven. • When [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 528 o f 792 NXP Semiconductors UM10237 Chapter 19: LPC24XX SPI When a device is a slave and CPHA is set to 0, the transfer start s when the SSEL signal goes active, and en ds when SSEL goes inactive. When a device is a slave, and CPHA is set to 1, the transfe[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 529 o f 792 NXP Semiconductors UM10237 Chapter 19: LPC24XX SPI 5. Read the SPI status register . 6. Read the received dat a from the SPI data register (o ptional). 7. Go to step 3 if more data is required to transmit. Note: A read or write of the SPI dat a re[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 530 o f 792 NXP Semiconductors UM10237 Chapter 19: LPC24XX SPI If the SSEL signal goes active, when the SPI bl ock is a master , this indicate s another master has selected the device to be a slave. This conditi on is known as a mode fault. When a mode fault [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 531 o f 792 NXP Semiconductors UM10237 Chapter 19: LPC24XX SPI 7. Register description The SPI conta ins 5 registers as shown in T able 19–461 . All registers are byte , half word and word accessible. [1] Reset V alue reflects the data stored in used bits o[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 532 o f 792 NXP Semiconductors UM10237 Chapter 19: LPC24XX SPI 7.2 SPI St atus Regist er (S0SPSR - 0xE002 0004) The S0SPSR register co ntrols the operation of the SPI0 as per the conf iguration bits setting. 5M S T R 0 Master mode select. The SPI operates in [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 533 o f 792 NXP Semiconductors UM10237 Chapter 19: LPC24XX SPI 7.3 SPI Dat a Register (S0SPDR - 0xE002 0008) This bi-directional dat a register provides the transm it an d re ce ive data for the SPI. T ransmit data is provided to the SPI by writin g to this r[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 534 o f 792 NXP Semiconductors UM10237 Chapter 19: LPC24XX SPI 7.6 SPI T est S tatus Regi ster (SPTSR - 0xE002 0014) Note: The bits in this register are intended for functional verif ication only . This regis ter should not be used for normal operation. This [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 535 o f 792 NXP Semiconductors UM10237 Chapter 19: LPC24XX SPI Fig 95. SPI block diagram MOSI_IN MOSI_OUT MISO_IN MISO_OUT OUTPUT ENABLE LOGIC SPI REGISTER INTERFACE SPI Interrupt APB Bus SPI SHIFT REGISTER SCK_OUT_EN MOSI_OUT_EN MISO_OUT_EN SCK_IN SCK_OUT SS[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 536 o f 792 1. Basic configuration The SSP0/1 interfaces a re configured using the fo llowing registers: 1. Power: In the PCONP register ( Ta b l e 4 – 6 3 ), set bit PCSSP0/1. Remark: On reset, both SSP interfaces are enabled (PCSSP0/1 = 1). 2. Clock: In P[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 537 o f 792 NXP Semiconductors UM10237 Chapter 20: LPC24XX SSP interface SSP0/1 4. Pin descriptions 5. Bus description 5.1 T exas Instrument s sync hronous serial frame format Figure 20–96 shows the 4- wire T exas Instruments synchro nous serial frame fo rm[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 538 o f 792 NXP Semiconductors UM10237 Chapter 20: LPC24XX SSP interface SSP0/1 For device configured a s a master in this mode, CLK and FS are forc ed LOW , and the transmit data line DX is tris tated whenever th e SSP is idle. Once the bottom entry of the t[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 539 o f 792 NXP Semiconductors UM10237 Chapter 20: LPC24XX SSP interface SSP0/1 The CPHA control bit select s the clock edge that captures data and allo ws it to change state. It has the most imp act on the first bit tr ansmitted by either allowing or no t al[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 540 o f 792 NXP Semiconductors UM10237 Chapter 20: LPC24XX SSP interface SSP0/1 In the case of a single word transmission, after all bit s of the data word have been transferred, the SSEL line is returned to its idle HIGH state one SCK period af ter the last [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 541 o f 792 NXP Semiconductors UM10237 Chapter 20: LPC24XX SSP interface SSP0/1 In this configuration, during idle periods: • The CLK signal is forced HIGH. • SSEL is forced HIGH. • The transmit MOSI/MISO p ad is in high impedance. If the SSP is enabled[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 542 o f 792 NXP Semiconductors UM10237 Chapter 20: LPC24XX SSP interface SSP0/1 5.2.5 SPI format with CPOL = 1,CPHA = 1 The transfer signal sequence for SPI format with CPOL = 1, CPHA = 1 is shown in Figure 20–100 , which covers both single and continuous t[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 543 o f 792 NXP Semiconductors UM10237 Chapter 20: LPC24XX SSP interface SSP0/1 Microwire format is very sim ilar to SPI format, ex ce pt that tran smission is ha lf-duplex instead of full-duplex, using a master-slave messag e passing tech nique. Each serial [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 544 o f 792 NXP Semiconductors UM10237 Chapter 20: LPC24XX SSP interface SSP0/1 5.3.1 Setup and hold time requirement s on CS with respect to SK in Microwire mode In the Microwire mode, the SSP slave samples the first bit of receive data on the rising edge of[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 545 o f 792 NXP Semiconductors UM10237 Chapter 20: LPC24XX SSP interface SSP0/1 [1] Reset V alue reflects the data stored in used bi ts only . It does not include reserved bits content. 6.1 SSPn Control Register 0 (SSP 0CR0 - 0xE006 8000 , SSP1CR0 - 0xE003 00[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 546 o f 792 NXP Semiconductors UM10237 Chapter 20: LPC24XX SSP interface SSP0/1 6.2 SSPn Control Register 1 (SSP0CR1 - 0xE006 8004, SSP1CR1 - 0xE003 0004) This register contro ls certain aspect s of the op eration of the SSP controller . T able 471: SSPn Cont[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 547 o f 792 NXP Semiconductors UM10237 Chapter 20: LPC24XX SSP interface SSP0/1 6.3 SSPn Dat a Register (SSP0 DR - 0xE006 8008, S SP1DR - 0xE003 0008) Software can write dat a to be transmitted to this register , and read data that has been received. T able 4[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 548 o f 792 NXP Semiconductors UM10237 Chapter 20: LPC24XX SSP interface SSP0/1 6.4 SSPn S tatus Register (SSP 0SR - 0xE006 800C, SSP1SR - 0xE003 000C) This read-only register reflects t he current status of the SSP controller . 6.5 SSPn Clock Prescale Regist[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 549 o f 792 NXP Semiconductors UM10237 Chapter 20: LPC24XX SSP interface SSP0/1 6.7 SSPn Raw Interrupt St atus Register (SSP0RIS - 0xE006 8018, SSP1RIS - 0xE003 0018) This read-only regi ster contai ns a 1 for ea ch interrupt con dition tha t is asserted, reg[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 550 o f 792 NXP Semiconductors UM10237 Chapter 20: LPC24XX SSP interface SSP0/1 6.9 SSPn Interrupt Clear Register (SSP0ICR - 0xE006 8020, SSP1ICR - 0xE003 0020) Software can write one or more one(s) to this write-only register , to clear the corresponding int[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 551 o f 792 1. Basic configuration The SD/MMC is configured using the following registers: 1. Power: In the PCONP register ( Ta b l e 4 – 6 3 ), set bit PC_MCI. Remark: On reset, the SD/MMC is disabled (PCMCI = 0). 2. Clock: In PC LK_SEL1 se lect PCLK_MCI ([...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 552 o f 792 NXP Semiconductors UM10237 Chapter 21: LPC24XX SD/MMC card interfa ce There is one additional signa l needed in the in terface, a power control line MCIPWR, but it can be sou rced from an y GPIO sign al. 5. Functional overview The MCI may be used [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 553 o f 792 NXP Semiconductors UM10237 Chapter 21: LPC24XX SD/MMC card interfa ce 5.2.1 Secure digit al memory card bus signals The following signals are used on th e secure digital memory card bus: • CLK Host to card clock signal • CMD Bidirectional comm[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 554 o f 792 NXP Semiconductors UM10237 Chapter 21: LPC24XX SD/MMC card interfa ce 5.3.1 Adapter register block The adapter register blo ck contains all system re gisters. This block also gen erates the signals that clear the st atic flags in the mu ltimedia c[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 555 o f 792 NXP Semiconductors UM10237 Chapter 21: LPC24XX SD/MMC card interfa ce When the W AIT state is entered, the comman d timer start s running. If the timeout 1 is reached before the CPSM mo ves to the RECEI VE state, the timeout flag is set and the ID[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 556 o f 792 NXP Semiconductors UM10237 Chapter 21: LPC24XX SD/MMC card interfa ce 5.3.5 Command format The command p ath operates in a half-duplex mod e, so that command s and responses can either be sent or received. If the CPSM is not in the SEND st at e, t[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 557 o f 792 NXP Semiconductors UM10237 Chapter 21: LPC24XX SD/MMC card interfa ce The CRC generator calcul ates the CRC checks um for all bits before the CRC cod e. This includes the star t bit, transmitter bit, co mmand index, and command argument (or card s[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 558 o f 792 NXP Semiconductors UM10237 Chapter 21: LPC24XX SD/MMC card interfa ce • IDLE: The data p ath is inactive, and the MCIDA T[3:0] output s are in HI-Z. When the data control re gister is written and the enable bit is set, the DPSM loads th e data c[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 559 o f 792 NXP Semiconductors UM10237 Chapter 21: LPC24XX SD/MMC card interfa ce Note: The DPSM remains in the W AIT_S state for at least tw o clock p eriods to me et Nwr timing constraint s. • SEND: The DPSM starts sending data to a card. Depending on the[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 560 o f 792 NXP Semiconductors UM10237 Chapter 21: LPC24XX SD/MMC card interfa ce The dat a block counter determines the end of a dat a block. If the counter is zero, the end-of-dat a condition is TRUE (see Section 21–6.9 “ Dat a Control Register (MCIData[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 561 o f 792 NXP Semiconductors UM10237 Chapter 21: LPC24XX SD/MMC card interfa ce 5.3.1 1 St atus flags T able 21–487 lists the dat a path status flags (see Section 21–6.1 1 “ S tatus Register (MCIS tatus - 0xE008 C034) ” on page 569 for more informat[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 562 o f 792 NXP Semiconductors UM10237 Chapter 21: LPC24XX SD/MMC card interfa ce • The receive FIFO refers to the receive lo gic and data buffer when RxActive is asserted (s ee Section 21–5.3.15 “ Receive FIFO ” ). 5.3.14 T ransmit FIFO Data can be w[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 563 o f 792 NXP Semiconductors UM10237 Chapter 21: LPC24XX SD/MMC card interfa ce 5.3.16 APB interfaces The APB interface generate s the interrupt and DMA requests , and accesses the MCI adapter registers an d the data FIFO. It cons ist s of a data path, regi[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 564 o f 792 NXP Semiconductors UM10237 Chapter 21: LPC24XX SD/MMC card interfa ce [1] Reset V alue reflects the data stored in used bits only . It does not include reserved bits content. 6.1 Power Control Register (MCI Power - 0xE008 C000) The MCIPower regist[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 565 o f 792 NXP Semiconductors UM10237 Chapter 21: LPC24XX SD/MMC card interfa ce While the MCI is in identifi cation mode, the MCICL K frequency must be less than 400 kHz. The clock frequency can be chan ged to the maximum car d bus freq ue ncy when relative[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 566 o f 792 NXP Semiconductors UM10237 Chapter 21: LPC24XX SD/MMC card interfa ce Note: After a data write , data cannot be writt en to this reg ister for three MCLK clock periods plus two PCLK clock periods. T able 21–495 shows the re sponse types. 6.5 Com[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 567 o f 792 NXP Semiconductors UM10237 Chapter 21: LPC24XX SD/MMC card interfa ce The card st atus size can be 32 or 127 bits, depending on the response type (see T able 21–498 ). The most significant bit of the card status is received first. The MCIRespons[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 568 o f 792 NXP Semiconductors UM10237 Chapter 21: LPC24XX SD/MMC card interfa ce 6.9 Dat a Control Register (MCIDataCtrl - 0xE008 C02C) The MCIDataCtr l register controls the DPSM. T able 21–501 shows the bit assignment of the MCIDataCtrl r egister . Note:[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 569 o f 792 NXP Semiconductors UM10237 Chapter 21: LPC24XX SD/MMC card interfa ce Note: This registe r should be read only whe n the data transf er is complet e. 6.1 1 St atus Register (M CISt atus - 0xE008 C034) The MCIS tatu s register is a read-o nly re gi[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 570 o f 792 NXP Semiconductors UM10237 Chapter 21: LPC24XX SD/MMC card interfa ce 6.12 Clear Register (M CIClear - 0xE008 C038) The MCIClear register is a writ e-only register . The corresponding sta tic status flags can be cleared by writing a 1 to the corre[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 571 o f 792 NXP Semiconductors UM10237 Chapter 21: LPC24XX SD/MMC card interfa ce 6.14 FIFO Counter Register (MCIFifoCnt - 0xE008 C048) The MCIFifoCnt register contains the remaining number of word s to be written to or read from the FIF O. The FI FO counter [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 572 o f 792 1. Basic configuration The I 2 C0/1/2 interfaces are co nfigured using the following registers: 1. Power: In the PCONP register ( Ta b l e 4 – 6 3 ), set bit PCI2C0/1/2 . Remark: On reset, all I 2 C interfac es ar e en a ble d (PC I2 C0/ 1/ 2 = [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 573 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 • Data transfer from a slave tran smitter to a master receiver . The first byte (the slave address) is transmitted by the master . The slave then returns an acknowledge [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 574 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 5. Pin description 6. I 2 C operating modes In a given applica tion, the I 2 C block may operate as a m aster , a slave, or both. In the slave mode, the I 2 C har dwa r e [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 575 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 6.2 Master Receiver mode In the master receiver mo de, data is received from a slave tran smitter . The transfer is initiated in the same way as in the ma ster transmitter[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 576 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 6.3 Slave Receiver mode In the slave receiver m ode, data bytes are rece ived from a master tran smitter . T o initialize the slave receiv er mode, user writ e the Slav e [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 577 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 6.4 Slave T ransmitter mode The first byte is received an d ha nd le d as in th e slav e re ce ive r mode . How ever , in this mode, the direction bit will be 1, indicatin[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 578 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 Fig 1 17. I 2 C Bus serial interface bloc k diagram AP B BU S STATUS REGISTER CONTROL REGISTER & SCL DUTY CYCLE REGISTERS ADDRESS REGISTER COMPARATOR SHIFT REGISTER 8 [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 579 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 7.2 Address Register I2ADDR This register may be loaded with the 7 bit sl ave address (7 most significant bits) to wh ich the I 2 C block will respond when programmed as a[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 580 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 The synchronization logic will sync hronize the serial clock generator with the clock pulses on the SCL line from another d evice. If two or more ma ster device s generate[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 581 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 The content s of the I 2 C co ntrol register may be r ead as I2CONSET . Writin g to I2CONSET will set bits in the I 2 C control re gister that correspond to ones in the va[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 582 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 [1] Reset V alue reflects the data stored in used bi ts only . It does not include reserved bits content. 8.1 I 2 C Control Set Register (I2C [0/1/2]CONSET : 0xE001 C000, [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 583 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 When ST A is 1 and the I 2 C interface is not alre ady in mast er mode, it enters master mode, checks the bus a nd generates a ST ART condition if the bus is free. If the [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 584 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 8.2 I 2 C Control Clear Register (I2C [0/1/2]CONCLR: 0xE001 C018, 0xE005 C018, 0xE008 0018) The I2CONCLR register s control clearing of bits in the I2CON register that con[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 585 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 8.4 I 2 C Dat a Register (I2C[0/1/2]D A T - 0xE001 C008, 0xE005 C 008, 0xE008 0008) This register contain s the data to be trans mitted or the da ta just received. The CPU[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 586 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 (12) The values for I2SCLL an d I2SCLH should not nece ssarily be the same. Sof tware can set diff erent duty cycles on SCL by setting th ese two registers. For example, t[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 587 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 In Figures 120 to 124 , circles are used to indicate when the serial interrupt flag is se t. The numbers in the circles show the st atus code hel d in the I2 ST A T regist[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 588 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 9.2 Master Receiver mode In the master receive r mode, a number of dat a bytes ar e received from a slave tran smitter (see Figure 22–121 ). The transfer is initialized [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 589 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 If the AA bit is reset during a tran sfer , the I 2 C block will return a not acknowledge (logic 1) to SDA afte r the next received dat a byte. While AA is reset, the I 2 [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 590 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 Fig 120. Format a nd St ates in the Master T ransmitter mode DATA A R W SLA S DATA A W SLA to Master receive mode, entry = MR MT to corresponding states in Slave mode A OR[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 591 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 Fig 121. Format a nd St ates in the Master Receive r mode A to Master transmit mode, entry = MT MR to corresponding states in Slave mode A R SLA S R SLA S W A A OR A A P o[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 592 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 Fig 122. Format and St a tes in the Slave Receiver mode A A P OR S A R SLA S P OR S A A 68H 60H 80H 88H reception of the General Call address and one or more Data bytes ar[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 593 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 9.4 Slave T ransmitter mode In the slave transmitter mode, a number of dat a bytes ar e transmitted to a master receiver (see Figure 22–123 ). Dat a transfer is initiali[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 594 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 T able 52 5. Master T ransmitter mo de Status Code (I2CST A T) St a tus of the I 2 C bus and hardware Application software response Next action taken by I 2 C hardware T o[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 595 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 T able 52 6. Master Receiv er mode Status Code (I2CST A T) St a tus of the I 2 C bus and hardware Application software response Next action taken by I 2 C hardware T o/Fro[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 596 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 T able 527. Slave Receiver Mode Status Code (I2CST A T) St a tus of the I 2 C bus and hardware Application software response Next action taken by I 2 C hardware T o/From I[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 597 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 0x98 Previously addressed with General Call; DA T A byte has been received; NOT ACK has been returned. Read data byte or 0 0 0 0 Swi tched to not a ddressed SL V mode; no [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 598 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 T able 52 8. T ad_105: Slave T r ansmitter mode Status Code (I2CST A T) St a tus of the I 2 C bus and hardware Application software response Next action taken by I 2 C har[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 599 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 9.5 Miscellaneous st ates There are two I2ST A T codes that do not correspond to a de fined I 2 C hardware st ate (see T able 22–529 ). These ar e discussed below . 22.9[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 600 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 9.6 Some special cases The I 2 C hardware has facilities to handle the following spec ial cases that may occur during a serial transfer : 9.7 Simult aneous repeated ST AR [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 601 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 If an uncontrolled source generates a superfluo us ST ART or masks a STOP condition, then the I 2 C bus stays busy indefinitely . If the ST A flag is set and bus access is[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 602 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 9.12 I 2 C St ate service routines This section provides exa mples of op erations that must be perf ormed by va rious I 2 C state service routines. This includes: • Init[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 603 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 The I 2 C hardware now begins checking th e I 2 C bus fo r it s own slave address and gen eral call. If the general call or the own slave ad dre ss is detected, an in terr[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 604 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 2. Set up the Slave Address to which data will be transmitted, and add the Read bit. 3. Write 0x20 to I2CONSET to set the ST A bit. 4. Set up th e Master Re ceive buffer .[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 605 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 4. Set up Master T ransmit mode dat a buffer . 5. Set up Master Receive mode dat a buffer . 6. Initialize Master data counter . 7. Exit 10.7 Master T ransmitter states 10.[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 606 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 10.7.5 St ate : 0x38 Arbitration has been lost during Slave Address + W rite or data. The bus has been released and not addr essed Slave mode is entered. A new S tart cond[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 607 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 1. Read data byte from I2DA T into Master Receive buf fer . 2. Write 0x14 to I2CONSET to set the STO and AA bits. 3. Write 0x08 to I2CONCLR to clear the S I flag. 4. Exit [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 608 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 3. Set up Slave Receiv e mo d e da ta buffer . 4. Initialize Sla ve data counter . 5. Exit 10.9.5 St ate : 0x80 Previously addressed with ow n Slave Addre ss. Data ha s be[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 609 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 1. Write 0x04 to I2CONSET to set the AA bit. 2. Write 0x08 to I2CONCLR to clear the S I flag. 3. Exit 10.10 Slave T ransmitter St ates 10.10.1 St ate : 0xA8 Own Slave Addr[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 610 o f 792 NXP Semiconductors UM10237 Chapter 22: LPC24XX I 2 C int erfaces I 2 C0/1/2 3. Exit 10.10.5 St ate : 0xC8 The last data byte has been transmitted, ACK has been received. Not addresse d Slave mode is entered . 1. Write 0x04 to I2CONSET to set the A[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 61 1 of 792 1. Basic configuration The I 2 S interface is con figured usin g the following registers: 1. Power: In the PCONP register ( Ta b l e 4 – 6 3 ), set bit PC I2S. Remark: On reset, the I 2 S interface is disabled (PCI2S = 0). 2. Clock: In PC LK_SEL[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 612 o f 792 NXP Semiconductors UM10237 Chapter 23: LPC24XX I 2 S interface next falling edge of the transmittin g clock af ter a WS change. In stereo mode when WS is low left data is transmitted and right data when WS is hig h. In mono m ode the sam e data is[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 613 o f 792 NXP Semiconductors UM10237 Chapter 23: LPC24XX I 2 S interface 5. Register description T able 23–531 shows the registers ass oc i at ed with th e I 2 S interface and a summar y of their functions. Following the tabl e are det ails for each regis[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 614 o f 792 NXP Semiconductors UM10237 Chapter 23: LPC24XX I 2 S interface [1] Reset V alue reflects the data stored in used bits only . It does not include reserved bits content. 5.1 Digit al Audio Output Register (I2SDAO - 0xE008 8000) The I2SDAO regist er [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 615 o f 792 NXP Semiconductors UM10237 Chapter 23: LPC24XX I 2 S interface 5.3 T ransmit FIFO Register (I2STXFIFO - 0xE008 8008) The I2STXFIFO register provides access to th e tr ansmit FIFO. The function of bits in I2STXFIFO are shown in T able 23–534 . 5.[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 616 o f 792 NXP Semiconductors UM10237 Chapter 23: LPC24XX I 2 S interface 5.6 DMA Configuration Regist er 1 (I2SDMA1 - 0xE008 8014) The I2SDMA1 register controls the operatio n of DMA request 1. The function of bit s in I2SDMA1 are shown in T able 23–5 37 [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 617 o f 792 NXP Semiconductors UM10237 Chapter 23: LPC24XX I 2 S interface 5.9 T ransmit Clock Rate Regist er (I2STXRA TE - 0xE008 8020) The bit rate for the I 2 S t ransmitter is d etermined by the value of t he I2STXRA T E register . The value depends on th[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 618 o f 792 NXP Semiconductors UM10237 Chapter 23: LPC24XX I 2 S interface • Data word length is determined by the wo rdwidth value in the configu ration register . There is a sepa rate wordwidth value for the receive ch annel and the transmit channe l. –[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 619 o f 792 NXP Semiconductors UM10237 Chapter 23: LPC24XX I 2 S interface System signaling occurs when a level detection is true and enabled. T able 542 . Conditions for FIFO level comparison Level Comparison Condition dmareq_tx_1 tx_depth_d ma1 >= tx_lev[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 620 o f 792 NXP Semiconductors UM10237 Chapter 23: LPC24XX I 2 S interface Fig 128. FIFO content s for various I 2 S modes LEFT + 1 7 0 RIGHT + 1 7 0 LEFT 7 0 RIGHT 7 0 Stereo 8-bit data mode N + 3 7 0 N + 2 7 0 N + 1 7 0 N 7 0 Mono 8-bit data mode N + 1 15 0[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 621 o f 792 1. Basic configuration The T imer0/1/2/3 peripherals are configur ed using the following registe r s: 1. Power: In the PCONP register ( Ta b l e 4 – 6 3 ), set bits PCTIM0/1/2/3. Remark: On reset, T imer0/1 are enabled (PCTIM0/1 = 1), and T imer[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 622 o f 792 NXP Semiconductors UM10237 Chapter 24: LPC24XX T imer0/1/2/3 • Free running tim er . 4. Description The T imer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally-supplied clock, and can optionally genera te inter[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 623 o f 792 NXP Semiconductors UM10237 Chapter 24: LPC24XX T imer0/1/2/3 T able 546. S ummary of ti mer/counter re gisters Generic Name Description Access Reset Va l u e [1] TIMERn Register/ Name & Address IR Interrupt Regist er . The IR can be writte n t[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 624 o f 792 NXP Semiconductors UM10237 Chapter 24: LPC24XX T imer0/1/2/3 [1] Reset V alue reflects the data stored in used bits only . It does not include reserved bits content. 6.1 Interrupt Register (T[0/1/2 /3]IR - 0xE000 4000, 0xE000 8000, 0xE007 0000, 0x[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 625 o f 792 NXP Semiconductors UM10237 Chapter 24: LPC24XX T imer0/1/2/3 6.3 Count Control Register (T[0/1/2 /3]CTCR - 0xE000 4070, 0xE000 8070, 0xE007 0070, 0xE007 4070) The Count Control Register (CTCR) is used to select between T imer and Counter mo de, an[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 626 o f 792 NXP Semiconductors UM10237 Chapter 24: LPC24XX T imer0/1/2/3 6.4 Timer Counter registers (T0T C - T3TC, 0xE000 4008, 0xE000 8008, 0xE007 0008, 0xE007 4008) The 32-bit T imer Counter register is incr em ented when the prescale counter reaches its t[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 627 o f 792 NXP Semiconductors UM10237 Chapter 24: LPC24XX T imer0/1/2/3 6.8 Match Control Register (T[0/1 /2/3]MCR - 0xE000 4014, 0xE000 8014, 0xE007 0014, 0xE007 4014) The Match Control Register is used to contro l what operations are perfo rmed when one of[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 628 o f 792 NXP Semiconductors UM10237 Chapter 24: LPC24XX T imer0/1/2/3 6.9 Capture Registers (CR0 - CR3) Each Capture register is associated with a de vice pin and may be loaded with the T imer Counter value when a specified event occurs on that pin. The se[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 629 o f 792 NXP Semiconductors UM10237 Chapter 24: LPC24XX T imer0/1/2/3 6.1 1 External Match Register (T[0 /1/2/3]EMR - 0xE00 0 403C, 0xE000 803C, 0xE007 003C, 0xE007 403C) The External Match Register pr ovides both co ntrol and status of the exter nal match[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 630 o f 792 NXP Semiconductors UM10237 Chapter 24: LPC24XX T imer0/1/2/3 7. Example ti mer operation Figure 24–129 shows a timer config ured to res et the count and generat e an interr upt on match. The prescaler is set to 2 and the match register set to 6.[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 631 o f 792 NXP Semiconductors UM10237 Chapter 24: LPC24XX T imer0/1/2/3 Fig 131. Timer block diagram reset MAXVAL TIMER CONTROL REGISTER PRESCALE REGISTER PRESCALE COUNTER PCLK enable CAPTURE REGISTER 3 CAPTURE REGISTER 2 CAPTURE REGISTER 1 CAPTURE REGISTER [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 632 o f 792 1. Basic configuration The PWM is configured using the following registers: 1. Power: In the PCONP register ( Ta b l e 4 – 6 3 ), set bit PCPWM0/1. Remark: On reset, the both PWMs are en abled (PCPWM0/1 = 1). 2. Peripheral cloc k: In the PCLK_SE[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 633 o f 792 NXP Semiconductors UM10237 Chapter 25: LPC24 XX Pulse Wid th Modulator PWM0 /PWM1 3. Description The PWM is based on the st andard T imer block and inherit s all of its featur es, alth ough only the PWM function is pin ned out on the microcontroll[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 634 o f 792 NXP Semiconductors UM10237 Chapter 25: LPC24 XX Pulse Wid th Modulator PWM0 /PWM1 Fig 132. PWM block diagram MATCH REGISTER 3 MATCH REGISTER 2 MATCH REGISTER 0 MATCH REGISTER 4 MATCH REGISTER 5 MATCH REGISTER 6 SHADOW REGISTER 6 LOAD ENABLE MATCH [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 635 o f 792 NXP Semiconductors UM10237 Chapter 25: LPC24 XX Pulse Wid th Modulator PWM0 /PWM1 3.1 Rules for single edge controlled PWM output s 1. All single edge controlled PWM outpu ts go high at the beginning of a PWM cycle unless their match value is equa[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 636 o f 792 NXP Semiconductors UM10237 Chapter 25: LPC24 XX Pulse Wid th Modulator PWM0 /PWM1 5. The ma ximum numbe r of match re gisters is incre ased to 7 in order to allow suppor t for up to 3 double edge PWM channe ls. This includes the necessary match ou[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 637 o f 792 NXP Semiconductors UM10237 Chapter 25: LPC24 XX Pulse Wid th Modulator PWM0 /PWM1 [1] Identical to single edge mode in this case since Match 0 is the neighbor ing match reg ister . Essentially , PWM1 cannot be a double edged output. [2] It is gene[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 638 o f 792 NXP Semiconductors UM10237 Chapter 25: LPC24 XX Pulse Wid th Modulator PWM0 /PWM1 T able 55 7. PWM0 and PWM1 register map Generic Name Description Access Reset Va l u e [1] PWM0 Address & Name PWM1 Ad dress & Name IR Interrupt Registe r . [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 639 o f 792 NXP Semiconductors UM10237 Chapter 25: LPC24 XX Pulse Wid th Modulator PWM0 /PWM1 [1] Reset V alue relects the data stored in used bits only . It does not include reserved bits content. 6.1 PWM Interrupt Register (P WM0IR - 0xE001 4000 and PWM1IR [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 640 o f 792 NXP Semiconductors UM10237 Chapter 25: LPC24 XX Pulse Wid th Modulator PWM0 /PWM1 6.2 PWM Ti mer Control Register (PWM0TCR - 0xE001 4004 and PWM1 TCR 0xE001 8004) The PWM T imer Control Register (PWMTCR) is used to contro l the operation of the PW[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 641 o f 792 NXP Semiconductors UM10237 Chapter 25: LPC24 XX Pulse Wid th Modulator PWM0 /PWM1 6.3 PWM Count Control Regist er (PWM0CTCR - 0xE001 4070 an d PWM1CTCR 0xE001 8070) The Count Control Register (CTCR) is used to select between T imer and Counter mo [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 642 o f 792 NXP Semiconductors UM10237 Chapter 25: LPC24 XX Pulse Wid th Modulator PWM0 /PWM1 3 PWMMR1I 1 Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC. 0 0 This int errupt is disabled. 4 PWMMR1R 1 Reset on PWMMR1: [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 643 o f 792 NXP Semiconductors UM10237 Chapter 25: LPC24 XX Pulse Wid th Modulator PWM0 /PWM1 6.5 PWM Capture Control Regist er (PWM0CCR - 0xE001 4028 and PWM1CCR 0xE001 8028) The Capture Control register is used to cont rol whether any of the Capture registe[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 644 o f 792 NXP Semiconductors UM10237 Chapter 25: LPC24 XX Pulse Wid th Modulator PWM0 /PWM1 [1] Reserved for PWM0. 6.6 PWM Control Registers (PWM 0PCR - 0xE001 404C and PWM1PCR 0xE001 804C) The PWM Control register s are used to enable a nd select the type [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 645 o f 792 NXP Semiconductors UM10237 Chapter 25: LPC24 XX Pulse Wid th Modulator PWM0 /PWM1 6.7 PWM Latch Enable Register (P WM0LER - 0xE001 4050 and PWM1LER 0xE001 8050) The PWM Latch Enable registers ar e used to control the update of the PWM Match regist[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 646 o f 792 NXP Semiconductors UM10237 Chapter 25: LPC24 XX Pulse Wid th Modulator PWM0 /PWM1 5 E na ble PWM Match 5 Latch PWM MR5 regi ster update control. See bit 0 for details. 0 6 E na ble PWM Match 6 Latch PWM MR6 regi ster update control. See bit 0 for [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 647 o f 792 1. Basic configuration The RTC is co nfigured using the following registers: 1. Power: In the PCONP register ( Ta b l e 4 – 6 3 ), set bits PCR TC. Remark: On reset, the R TC is enabled. See Section 26–9 for po wer saving options. 2. Clock: Se[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 648 o f 792 NXP Semiconductors UM10237 Chapter 26: LPC24XX Real-T ime Clock (RTC) and battery RAM and resume operation. Th e alarm output has a nominal volt age swing of 1.8 V . Note that the PLL is disa bled when waking up from power down. See Section 4–3.[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 649 o f 792 NXP Semiconductors UM10237 Chapter 26: LPC24XX Real-T ime Clock (RTC) and battery RAM 6. Register description The RTC in cludes a number of registers. The ad dress space is split into four sections by functionality . The first eight addr esse s ar[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 650 o f 792 NXP Semiconductors UM10237 Chapter 26: LPC24XX Real-T ime Clock (RTC) and battery RAM [1] Registers in the RTC other than those that are part of the Prescaler a re not affected by chip Reset. These registers must be initialized by software if the [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 651 o f 792 NXP Semiconductors UM10237 Chapter 26: LPC24XX Real-T ime Clock (RTC) and battery RAM 6.2.2 Clock Tick Counter Register (CTCR - 0xE002 4004) The Clock T ick Counter is read only . It can be reset to zero through the Clock Control Register (CCR). T[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 652 o f 792 NXP Semiconductors UM10237 Chapter 26: LPC24XX Real-T ime Clock (RTC) and battery RAM 6.2.4 Counter Increment Interrupt Register (CIIR - 0xE002 400C) The Counter Increment Interrupt Register (CIIR) give s the ability to gene rate an interrupt ever[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 653 o f 792 NXP Semiconductors UM10237 Chapter 26: LPC24XX Real-T ime Clock (RTC) and battery RAM 6.2.6 Alarm Mask Register (AMR - 0xE002 4010) The Alarm Mask Regist er (AM R) allo ws th e us er to mask any of the alarm registers. T able 26–573 shows the re[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 654 o f 792 NXP Semiconductors UM10237 Chapter 26: LPC24XX Real-T ime Clock (RTC) and battery RAM 6.3 Consolidated time registers The values of the T ime Counters can optionally be read in a consolid ated format which allows the pr ogrammer to read all time c[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 655 o f 792 NXP Semiconductors UM10237 Chapter 26: LPC24XX Real-T ime Clock (RTC) and battery RAM 6.4 T ime Counter Group The time value consists of the eigh t counters shown in T able 26– 577 and T able 26–5 78 . These counters can be rea d or written at[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 656 o f 792 NXP Semiconductors UM10237 Chapter 26: LPC24XX Real-T ime Clock (RTC) and battery RAM 7. Alarm register group The alarm registers are sho w n in T able 26–5 79 . The values in these registers are compared with the time coun ters. If a ll the unm[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 657 o f 792 NXP Semiconductors UM10237 Chapter 26: LPC24XX Real-T ime Clock (RTC) and battery RAM during system operation (by reco nfiguring the PLL, the APB div ider , or the RTC prescaler) will result in some form of accumulated time er ror . Accumulated ti[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 658 o f 792 NXP Semiconductors UM10237 Chapter 26: LPC24XX Real-T ime Clock (RTC) and battery RAM PREINT = int (PCLK/32768) - 1. The value of PREI NT must be greater than or equal to 1. 10.3 Prescaler Fraction Regist er (PREFRAC - 0xE002 4084) This is the fra[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 659 o f 792 NXP Semiconductors UM10237 Chapter 26: LPC24XX Real-T ime Clock (RTC) and battery RAM 10.5 Prescaler operation The Prescaler block labelled "Combination Logic" in Figure 26–135 determines when the decrement of the 13 bit PREINT counter[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 660 o f 792 NXP Semiconductors UM10237 Chapter 26: LPC24XX Real-T ime Clock (RTC) and battery RAM 1 1. Battery RAM The Battery RAM is a 2 kbyte static RAM re siding on the APB bus. The address range is 0xE008 4000 to 0xE008 47FF .The SRAM can be accessed word[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 661 o f 792 NXP Semiconductors UM10237 Chapter 26: LPC24XX Real-T ime Clock (RTC) and battery RAM T able 26–584 gives the crystal p arameters that should be used. C L is the typical load capacit a nce of the cryst al and is usually specified by the crystal [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 662 o f 792 1. Features • Internally resets chip if not period ically reloaded. • Debug mode. • Enabled by sof tware but requires a hardwar e reset or a W atchdog reset/interrupt to be disabled. • Incorrect/Incomplete feed sequence causes reset/interr[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 663 o f 792 NXP Semiconductors UM10237 Chapter 27: LPC24XX W atchDog Timer (WDT) When the W atchdog counter un derflows, the program counter will start from 0x0000 0000 as in the case of external reset. The W atc hdog time-out flag (WDTOF) can be examined to [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 664 o f 792 NXP Semiconductors UM10237 Chapter 27: LPC24XX W atchDog Timer (WDT) Once the WDEN and/or WDRESET bits are set they can n ot be cleare d by sof twa re. Both flags are cleared by an extern al reset or a Watchdo g timer underflow . WDTOF The W atchd[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 665 o f 792 NXP Semiconductors UM10237 Chapter 27: LPC24XX W atchDog Timer (WDT) errors. After writing 0xAA to WDFEED, access to any W atchdog register other th an writing 0x55 to WDFEED causes an imm ed ia te rese t/interrupt when the W atchdog is enabled. T[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 666 o f 792 NXP Semiconductors UM10237 Chapter 27: LPC24XX W atchDog Timer (WDT) 5. Block diagram The block diagram of the W atchdog is shown below in the Figure 27–137 . The synchronization logic (PCLK - WDCLK) is not shown in the block diagram. Fig 137. W[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 667 o f 792 1. Basic configuration The ADC is configured us ing the following registers: 1. Power: In the PCONP register ( Ta b l e 4 – 6 3 ), set bits PCADC. Remark: On reset, the ADC is disabled. T o enab le the ADC, first s et the PCADC bit, and then ena[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 668 o f 792 NXP Semiconductors UM10237 Chapter 28: LPC24XX An alog-to Digit al Converter (ADC) Remark: When the ADC is not used, the V DDA and VREF pins must be conne cte d to the power supply , and pin V SSA must be grounded. These pins should not be left fl[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 669 o f 792 NXP Semiconductors UM10237 Chapter 28: LPC24XX An alog-to Digit al Converter (ADC) [1] Reset V alue reflects the data stored in used bits only . It does not include reserved bits content. 5.1 A/D Control Regi ster (AD0CR - 0xE003 4000) The A/D Con[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 670 o f 792 NXP Semiconductors UM10237 Chapter 28: LPC24XX An alog-to Digit al Converter (ADC) 5.2 A/D Global Dat a Regi ster (AD0GDR - 0xE003 4004) The A/D Global Dat a Register contains the resu lt of the most recent A/D conversion. This includes the dat a,[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 671 o f 792 NXP Semiconductors UM10237 Chapter 28: LPC24XX An alog-to Digit al Converter (ADC) 5.3 A/D St atus Regist er (AD0ST A T - 0xE003 4030) The A/D S tatus register allo ws checking the status of all A/D channels simult aneously . The DONE and OVERRUN [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 672 o f 792 NXP Semiconductors UM10237 Chapter 28: LPC24XX An alog-to Digit al Converter (ADC) 5.4 A/D Interrupt Enable Re gister (AD0INTEN - 0xE003 400C) This register allows control over which A/D ch annels generate an interrupt when a conversion is complet[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 673 o f 792 NXP Semiconductors UM10237 Chapter 28: LPC24XX An alog-to Digit al Converter (ADC) 6. Operation 6.1 Hardware-triggered conversion If the BURST bit in the ADCR is 0 and th e ST ART field cont ains 010-1 1 1, the A/D converter will start a conversio[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 674 o f 792 1. Basic configuration The DAC is configured us ing the following registers: 1. Power: The DAC is always on. 2. Clock: In th e PCLK_SEL0 re gister ( T able 4–56 ), select PCLK_DAC. 3. Pins: Select the DAC pin and pin mode in regi sters PINSEL1 a[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 675 o f 792 NXP Semiconductors UM10237 Chapter 29: LPC24XX Digit al-to Analog Converter (DAC) 5. Operation Bits 21:20 of the PINSEL1 registe r ( Section 9–5.2 “ Pin Function Select Register 1 (PINSEL1 - 0xE002 C004 ) ” on page 179 ) control whether the [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 676 o f 792 1. How to read this chapter Remark: This chapter applies to part s LPC2458, LPC2468, an d LPC2478. 2. Flash boot loader The Boot Loader controls initial opera tion after rese t, and also provides the means to accomplish programming of the Flash me[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 677 o f 792 NXP Semiconductors UM10237 Chapter 30: LPC24XX Flas h memory programming firmware When ISP mode is entered after a power on reset, the IRC and PLL are used to ge nerate CCLK of 14.748 MHz. This may not be the case when ISP is invoked by the user a[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 678 o f 792 NXP Semiconductors UM10237 Chapter 30: LPC24XX Flas h memory programming firmware If the signature is not valid, the auto-b aud routin e synchronizes with the host via serial po rt 0. The host should send a ’?’ (0x3F) as a synchronization char[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 679 o f 792 NXP Semiconductors UM10237 Chapter 30: LPC24XX Flas h memory programming firmware A description of UU-encode is available at th e wotsit webpage. 5.2.4 ISP flow control A software XON/XO FF flow control scheme is used to prevent da ta loss due to [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 680 o f 792 NXP Semiconductors UM10237 Chapter 30: LPC24XX Flas h memory programming firmware 6. Boot process flowchart (1) F or details on handling the crystal frequency , see Section 30–10.8 “ Reinvoke ISP ” on page 695 (2) F or details on available I[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 681 o f 792 NXP Semiconductors UM10237 Chapter 30: LPC24XX Flas h memory programming firmware 7. Sector numbers Some IAP and ISP commands oper ate on "sectors" and specify sector numbers. The following tab le indicate the correspondence between sect[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 682 o f 792 NXP Semiconductors UM10237 Chapter 30: LPC24XX Flas h memory programming firmware 8. Code Read Protection (CRP) Code Read Protectio n is a mech an ism tha t allo ws us er to enab le different lev els of security in the system so that access to the[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 683 o f 792 NXP Semiconductors UM10237 Chapter 30: LPC24XX Flas h memory programming firmware In case a CR P mode is enab led and ac cess to the chip is allowed via the ISP , an unsupoorted or restrict ed ISP command will be te rminated with return code CODE_[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 684 o f 792 NXP Semiconductors UM10237 Chapter 30: LPC24XX Flas h memory programming firmware 9.1 Unlock <Unlock code> 9.2 Set Baud Rate <Baud Rate> <stop bit> [1] ISP entry after reset uses the on chip IRC and PLL to run the device at CCLK [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 685 o f 792 NXP Semiconductors UM10237 Chapter 30: LPC24XX Flas h memory programming firmware 9.3 Echo <setting> 9.4 Write to RAM <st art address> <number of bytes> The host should send t he data only after receiving th e CMD_SUCCESS return [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 686 o f 792 NXP Semiconductors UM10237 Chapter 30: LPC24XX Flas h memory programming firmware "OK<CR><LF>" to continue furthe r transmissi on. If the check-sum does not match then the host should respond with "RESEND< CR><L[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 687 o f 792 NXP Semiconductors UM10237 Chapter 30: LPC24XX Flas h memory programming firmware 9.7 Copy RAM to Flash <Flash addr ess> <RAM address> <n o of bytes> 9.8 Go <address> <mode> T able 612 . ISP Co py co mmand Command C I[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 688 o f 792 NXP Semiconductors UM10237 Chapter 30: LPC24XX Flas h memory programming firmware 9.9 Erase sector(s) <st a rt sector number> <end sector number> 9.10 Blank check sector(s) <sector number> <end sector number> 9.1 1 Read Par[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 689 o f 792 NXP Semiconductors UM10237 Chapter 30: LPC24XX Flas h memory programming firmware 9.12 Read Boot code version number 9.13 Comp are <address1> <address2> <no o f bytes> 9.14 ISP Return Codes T able 617 . LPC24xx part Identificatio[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 690 o f 792 NXP Semiconductors UM10237 Chapter 30: LPC24XX Flas h memory programming firmware 10. IAP commands For in application programming the IAP routine should be calle d with a word pointer in register r0 pointing to memory (R AM) contai ning command co[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 691 o f 792 NXP Semiconductors UM10237 Chapter 30: LPC24XX Flas h memory programming firmware Define the IAP location entry point. Since the 0t h bit of the IAP location is set there will be a change to Thumb instruction set wh en the program counter br anche[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 692 o f 792 NXP Semiconductors UM10237 Chapter 30: LPC24XX Flas h memory programming firmware The Flash memory is not accessible du ring a write or erase operatio n. IAP commands, which results in a Flash write/erase oper ation, use 32 bytes of spac e in the [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 693 o f 792 NXP Semiconductors UM10237 Chapter 30: LPC24XX Flas h memory programming firmware 10.2 Copy RAM to Flash T able 622 . IAP Prepare sector(s) for write operation command Command Prepare sector(s) for write operation Input Command cod e: 50 10 Param0[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 694 o f 792 NXP Semiconductors UM10237 Chapter 30: LPC24XX Flas h memory programming firmware 10.3 Erase Sector(s) 10.4 Blank check sector(s) 10.5 Read Part Identification number T able 624 . IAP Erase Sector(s) command Command Erase Sector(s ) Input Command [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 695 o f 792 NXP Semiconductors UM10237 Chapter 30: LPC24XX Flas h memory programming firmware 10.6 Read Boot code version number 10.7 Comp are <address1> <address2> <no of bytes> 10.8 Reinvoke ISP T able 627 . IAP Read Boot Co de version num[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 696 o f 792 NXP Semiconductors UM10237 Chapter 30: LPC24XX Flas h memory programming firmware 10.9 IAP St atus Codes 1 1. JT AG Flash programming int erface Debug tools can write p arts of the Flash imag e to the RAM and then execute the IAP call "Copy R[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 697 o f 792 1. How to read this chapter Remark: This chapter describes the boot proce ss fo r flashless part s LPC2420/60 and LPC2470. It does not apply to p arts LPC2458, LPC2468, and LPC2478. The on-chip bootloa der version 3.4 controls the boot process for[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 698 o f 792 NXP Semiconductors UM10237 Chapter 31: LPC24XX On-chip bootloa der for flashless part s Pin P2.10 that is used as hardwa re request fo r ISP requires special attention. Since P2.10 is in high impedance mode af ter reset, it is important th at the [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 699 o f 792 NXP Semiconductors UM10237 Chapter 31: LPC24XX On-chip bootloa der for flashless part s 4.2.1 ISP command format "Command Parameter_0 Param eter_1 ... Parameter_n<CR><LF>" "Dat a" (Data only for Write comman ds). 4.[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 700 o f 792 NXP Semiconductors UM10237 Chapter 31: LPC24XX On-chip bootloa der for flashless part s 4.2.9 RAM used by IAP command handler IAP program ming comman ds use the top 32 bytes of on-chip R AM. The maxim um stack usage in the user allocated st ack sp[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 701 o f 792 NXP Semiconductors UM10237 Chapter 31: LPC24XX On-chip bootloa der for flashless part s 6. ISP commands The following commands are acce pted by the ISP command handler . Detailed st atus codes are supported for each command . The command hand ler [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 702 o f 792 NXP Semiconductors UM10237 Chapter 31: LPC24XX On-chip bootloa der for flashless part s [1] ISP entry after reset uses the on chip IRC and PLL to run the device at CCLK = 14.748 MHz 6.3 Echo <setting> 6.4 Write to RAM <st art address> [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 703 o f 792 NXP Semiconductors UM10237 Chapter 31: LPC24XX On-chip bootloa der for flashless part s continue further transmission. If the check-sum doe s not match, the ISP command handler responds with "RESEND< CR><LF>". In response th [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 704 o f 792 NXP Semiconductors UM10237 Chapter 31: LPC24XX On-chip bootloa der for flashless part s 6.6 Go <address> <mode> 6.7 Read Part Identification number 6.8 Read Boot code version number T able 638 . ISP Go command Command G Input Address: [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 705 o f 792 NXP Semiconductors UM10237 Chapter 31: LPC24XX On-chip bootloa der for flashless part s 6.9 Comp are <address1> <address2> <no of bytes> 6.10 ISP Return Codes T able 642 . ISP Co mpare command Command M Input Address1 (DST): S ta[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 706 o f 792 NXP Semiconductors UM10237 Chapter 31: LPC24XX On-chip bootloa der for flashless part s 7. IAP commands For in application programming the IAP routine should be calle d with a word pointer in register r0 pointing to memory (R AM) contai ning comma[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 707 o f 792 NXP Semiconductors UM10237 Chapter 31: LPC24XX On-chip bootloa der for flashless part s Setting function pointer: iap_entry=(IAP) IAP_LOCATION; Whenever you wish to call IAP you could use the following st atement. iap_entry (comm and, result); The[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 708 o f 792 NXP Semiconductors UM10237 Chapter 31: LPC24XX On-chip bootloa der for flashless part s 7.1 Read Part Identification number 7.2 Read Boot code version number Fig 143. IAP parameter p assing COMMAND CODE PARAMETER 1 PARAMETER 2 PARAMETER n STATUS C[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 709 o f 792 NXP Semiconductors UM10237 Chapter 31: LPC24XX On-chip bootloa der for flashless part s 7.3 Comp are <address1> <address2> <no of bytes> 7.4 Reinvoke ISP 7.5 IAP St atus Codes T able 647 . IAP Compare command Command Compare Inpu[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 710 o f 792 NXP Semiconductors UM10237 Chapter 31: LPC24XX On-chip bootloa der for flashless part s 3 DST_ADDR_ERROR Desti nation address is not on a correct boundary . 4 SRC_ADDR_NOT_MAPPED Source address is not mapped in the memory map. Count value is taken[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 71 1 of 792 1. Basic configuration The GPDMA is configured us ing the following registers: 1. Power: In the PCONP register ( Ta b l e 4 – 6 3 ), set bit PC GPDMA. Remark: On reset, the GPDMA is disabled (PCGPDMA = 0). 2. Clock: see T able 4–53 . 3. Interr[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 712 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller • Supports 8, 16, and 32 bit wide tra ns ac tion s. • Big-endian and little-endian support. The GPDMA defaults to little-end ian mode on reset. • An inter[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 713 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller example, a bidirectional po rt requires one st ream for transmit and one for receive. The source and destination ar eas can each be either a memory region or a [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 714 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller 4.2.4 Channel Logic and Channel Register Bank The channel logic and channel re gister bank c ontains registe rs and logic required for each DMA channel. 4.2.5 I[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 715 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller T able 32–651 shows endian behavio r for dif f erent source and destination combination s. T able 65 1. Endian behavior Source Endian Destination Endian Sourc[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 716 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller 4.2.9 Error conditions An error during a DMA transfer is flagged directly by the periphe ra l by asserting an Error response on the AHB bus during the transfer [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 717 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller 4.2.10 Channel hardware Each stream is supported by a dedicated hardware ch annel, including source and destination controllers, and a FIFO. This enab les b ett[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 718 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller 5. Programming the GPDMA The GPDMA enables peripher al-to-memory , memory-to-per ipheral, peripheral- to -pe rip he ra l, an d m em o ry-to -m e mo ry tran sa c[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 719 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller 5.3 Enabling a DMA channel T o enable the DMA channel set the Channel Enab le bit in the relevant DMA channel Configuration Register ( Section 32 –6.2.6 “ C[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 720 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller 5.9 Programming a DMA channel T o program a DMA channel: 1. Choose a free DMA channel with th e priority required. DMA channel 0 has the highest priority and DM[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 721 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller [1] Reset V alue reflects the data stored in used bits only . It does not include reserved bits content. [2] Bit [17] is read-only . 6.1 General GPDMA registers[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 722 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller 6.1.2 Interrupt T erminal Count St atus Register (DMACIntTCSt atus - 0xFFE0 4004) The DMACIntTCS t atus Register is read -only and indicates the status of the t[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 723 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller 6.1.5 Interrupt Error Clear Register (DMACIntErrClr - 0xFFE0 4010) The DMACIntErrClr Register is write-only an d clears the error interrupt requests. When writi[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 724 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller 6.1.8 Enabled Channel Register (DMACEnbldChns - 0xFFE0 401C) The DMACEnbld Chns Register is read-only an d indicates which D MA channels ar e enabled, as indica[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 725 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller 6.1.10 Software Single Request Regi ster (DMACSof tSReq - 0xFFE0 4024) The DMACSoftSReq Registe r is read/write and enables DMA single request s to be generated[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 726 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller 6.1.13 Configuration Register (DMACConfiguration - 0xFFE0 4030) The DMACConfiguration Register is read/wri te an d co nfigures the operation of the GPDMA. The e[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 727 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller 6.2 Channel registers The channel registers are u s ed to program the two DMA cha nnels. These registers consist of: • T wo DMACCxSrcAdd r Re gist er s • T [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 728 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller 6.2.3 Channel Linked List Item Registers (DMACC0LLI - 0xFFE0 4108 and DMACC1LLI - 0xFFE0 4128) The two read/write DMACCxLLI Registers co nt ain a word -a lig ne[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 729 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller T able 32–672 shows the value of the 3 bit DBSize or SBSize fields and the corresponding burst sizes. T able 671 . Channel Control registers (D MACC0Control -[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 730 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller T able 32–673 shows the value of the 3 bit SWidth or DWidth fields an d the corres ponding transfer width. 6.2.5 Protection and Access Information AHB access [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 731 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller 6.2.6 Channel Configuration Registers (D MACC0Configuration - 0xFFE0 41 10 and DMACC1Configuration - 0xFFE0 4130) The two DM ACCxConfiguratio n Registers a re r[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 732 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller 6.2.7 Lock control Set the lock bit by programming bit 16 in the DMACCxConfiguration Reg ister . When a burst occurs, the AHB arbite r must not de- grant the ma[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 733 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller There are situations when the GPDMA asserts the lock for so urce transfe rs followed by destination tr an sfe rs . Th is is possible when internal cond itions i[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 734 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller 8.2 Programming the GPDMA for scatter/gather DMA T o program the GPDMA fo r sca tter/ga ther DMA: 1. Write the LLIs for th e complete DMA transfer to memory . E[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 735 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller • Source start ad dress 0x0A200. • Destination address set to the destination periphe ral address. • T ransfer width, word (32 bit). • T ransfer size, 3[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 736 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller 9.1 Hardware interrupt sequence flow When a DMA interrupt requ est occurs, the Interrupt Service Routine needs to: 1. Read the DMACIntS tatus Register to determ[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 737 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller 10.1 Peripheral-to-memory , or Memory-to-peripheral DMA flow For a peripheral-t o-memory or memory-to-pe ripheral DMA flow the followin g sequence occurs: 1. Pr[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 738 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller – The DMA stream h a s the highest pending priority . – The GPDMA is the bus master of the AHB bus. 4. If an error occurs while tran sferring the dat a an e[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 739 o f 792 NXP Semiconductors UM10237 Chapter 32: LPC24XX General Pu rpose DMA (GPDMA) controller 11 . F l o w c o n t r o l The peripheral that contro ls the length of t he p a cket is known as the flow controller . The flow controller is usually the GPDMA [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 740 o f 792 1. Features • No target resources are required by the sof tware debugger in order to start the debugging session. • Allows the softwar e debugger to t alk via a JT AG (Joint T es t Action Group) port directly to the core. • Inserts instructi[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 741 o f 792 NXP Semiconductors UM10237 Chapter 33: LPC24XX EmbeddedICE trigger on an access to a periph eral and the second to trigger on the code segment that performs the task switching. The r efore when the breakpoint s trigger the information regarding wh[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 742 o f 792 NXP Semiconductors UM10237 Chapter 33: LPC24XX EmbeddedICE 5. JT AG function select Remark: JT AG access to the LPC2400 is onl y possible if no code read protection is selected, see Section 3–5 . The JT AG port may be used either for debug or fo[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 743 o f 792 NXP Semiconductors UM10237 Chapter 33: LPC24XX EmbeddedICE Fig 147. Embedded ICE debug enviro nme nt block diagram ARM7TDMI-S TARGET BOARD EMBEDDED ICE INTERFACE PROTOCOL CONVERTER EMBEDDED ICE JTAG PORT 5 serial parallel interface host running de[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 744 o f 792 1. Features • Closely track the instructions t hat the ARM core is executing. • One external trigger input. • 10 pin interface. • All registers are program med through JT AG interface. • Does not consume power when tr ace is not being us[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 745 o f 792 NXP Semiconductors UM10237 Chapter 34: LPC24XX Embedded T race Module (ETM) [1] For details refer to ARM documentation "Embedded Trace Macrocell S pecification (ARM IHI 0014E)". 4. Pin description 5. Register description The ETM conta in[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 746 o f 792 NXP Semiconductors UM10237 Chapter 34: LPC24XX Embedded T race Module (ETM) 6. Reset st ate of multiplexed pins On the LPC2400, the ETM pin functions ar e multiplexed with GPIO, PWM, UART , and CAN functions. In order to use the trace feature , th[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 747 o f 792 NXP Semiconductors UM10237 Chapter 34: LPC24XX Embedded T race Module (ETM) 7. Block diagram The block diagram of the ETM deb ug environment is shown below in Figure 34–1 48 . Fig 148. ETM debu g environment bl ock diagram PERIPHERAL TRACE PORT [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 748 o f 792 1. Features Remark: RealMonitor is a configurab le software module which enables real time d ebug. RealMonitor is develope d by ARM Inc. Informati on presen ted in this chapte r is take n from the ARM docum ent RealMonit or T ar get Integration Gu[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 749 o f 792 NXP Semiconductors UM10237 Chapter 35: LPC24XX RealMonitor processor context saving and restori ng. Re alMonitor is pre-program med in the on-ch ip ROM memory (boot se ctor). When enabled It allows user to observe and deb ug while part s of applic[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 750 o f 792 NXP Semiconductors UM10237 Chapter 35: LPC24XX RealMonitor 3.2 How RealMonitor works In general terms, the RealMon itor operat es as a state ma chine, as shown in Figure 35–150 . Re alMonitor switches between running and stopp ed states, in resp[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 751 o f 792 NXP Semiconductors UM10237 Chapter 35: LPC24XX RealMonitor – Undef exception caused by the undefin ed instructio ns in user foreground application. This indicates an error in the application being debugg ed. RealMonitor stops the user applicatio[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 752 o f 792 NXP Semiconductors UM10237 Chapter 35: LPC24XX RealMonitor 4.5 Prefetch Abort mode RealMonitor uses four words on entry to it s Prefetch abort interrupt handler . 4.6 Dat a Abort mode RealMonitor uses four wo rds on entry to its dat a abort interr[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 753 o f 792 NXP Semiconductors UM10237 Chapter 35: LPC24XX RealMonitor 4.10 RMT arget initialization While the processor is in a privileged mode , and IRQs are disabled, user must include a line of code within the start- up sequence of application to call rm_[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 754 o f 792 NXP Semiconductors UM10237 Chapter 35: LPC24XX RealMonitor NOP ; Insert User code valid si gnature here. LDR pc, [pc, #-0x120] ;Load IRQ vector from VIC LDR PC, FIQ_A ddress Reset_Address DCD __init ;Reset Entry point Undefined_Addre ss DCD rm_und[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 755 o f 792 NXP Semiconductors UM10237 Chapter 35: LPC24XX RealMonitor ; /************ ****************** ****************** ******************* ** ; * Setup Vecto red Interrupt cont roller. DCC Rx and Tx interrupts ; * generate No n Vectored IRQ req uest. rm[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 756 o f 792 NXP Semiconductors UM10237 Chapter 35: LPC24XX RealMonitor ;is not aware of the VIC interr upt priority hardwa re so trick ;rm_irqhandle r2 to return here STMFD sp!, {i p,pc} LDR pc, rm_irqhandler2 ;rm_irqhandle r2 returns here MSR cpsr_c, #0x52 ;[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 757 o f 792 NXP Semiconductors UM10237 Chapter 35: LPC24XX RealMonitor RM_OPT_READBYTES=TRUE RM_OPT_WRITEBYTES=TRUE RM_OPT_READHALFWORDS=TRUE RM_OPT_WRITEHALFWORDS=TRUE RM_OPT_READWORDS=TRUE RM_OPT_WRITEWORDS=TRUE Enables/Disab les support for 8/16/32 bit rea[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 758 o f 792 NXP Semiconductors UM10237 Chapter 35: LPC24XX RealMonitor This option specifies the size, in word s, of the data logging FIFO buffer . CHAIN_VECTORS=F ALSE This option allows RMT arget to support vector ch aining through µHAL (ARM HW abstraction[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 759 o f 792 1. Abbreviations UM10237 Chapter 36: LPC24XX Suppl ement ary information Rev . 02 — 19 December 2 008 User manual T able 684 . Acron yms and abbreviations Acronym Descriptio n ADC Analog -to-Digital Converter AHB Advanced High-performance Bus AM[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 760 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information 2. Legal information 2.1 Definitions Draft — The document is a draf t versi on only . The content is still under internal review and subject to formal approval, which m ay[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 761 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information 3. T ables T able 1. LPC24XX ove rview . . . . . . . . . . . . . . . . . . . . . . . 3 T able 2. Differences between LPC240 0 parts . . . . . . . . . 4 T able 3. LPC2458 ord[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 762 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information 0xFFE0 8028) bit description . . . . . . . . . . . . . . 81 T able 74. Dynamic Memory Percentage Command Period register (EMCDynamictRP - address 0xFFE0 8030) bit descriptio[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 763 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information Interrupt C ontroller . . . . . . . . . . . . . . . . . . . . . 1 15 T able 1 17. Interrupt sources bit allocation table . . . . . . . . 1 17 T able 1 18. LPC2400 pin conf i[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 764 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information T able 175. GPIO overall Interrupt St atu s register (IOIntS tatus - address 0xE002 8080) b it description . . . . . 20 6 T able 176. GPIO Interrup t Enable for Rising edge [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 765 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information T able 228. Int errupt S tatus register (IntS tatus - address 0xFFE0 0FE0) bit description . . . . . . . . . . . . . 238 T able 229. Int errupt Enable register (intEnable - [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 766 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information (USBDevIntS t - address 0xFFE0 C200) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 T able 299. USB Device Interrupt S tatus register (USBDevIntS[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 767 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information description . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 T able 345. USB System Error Interrupt Clear register (USBSysErrIntClr - address 0xFFE0 C2BC) bit descr[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 768 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information T able 401: UART1 Interrupt Enable Register (U1IER - address 0xE001 0004 when DLAB = 0) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 T able 402:[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 769 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information T able 452. F ullCAN Interrupt and Capture regi ster 0 (FCANIC0 - address 0xE003 C024) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 T able 453. [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 770 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information T able 514. I 2 C Control Set Register (I2C[ 0/1/2]CONCLR - addresses 0xE001 C018, 0xE005 C018, 0xE008 0018) bit descrip tion . . . . . . . . . . . . . 584 T able 515. I 2 C[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 771 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information T able 573. Ala rm Mask Register (AMR - address 0xE002 4010) bit descrip tion . . . . . . . . . . . . . 653 T able 574. Consoli dated T i me regi ster 0 (CTIME0 - address 0x[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 772 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information T able 656. I nt errupt T erminal Count Clear register (DMACIntClear - addre ss 0xF FE0 4 008) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 722 T ab[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 773 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information 4. Figures Fig 1. LPC2458 block diagram . . . . . . . . . . . . . . . . . . . 1 1 Fig 2. LPC2460 block diagram . . . . . . . . . . . . . . . . . . . 12 Fig 3. LPC2468 block [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 774 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information Fig 88. Message overwritten indicate d by semaphore bits and message lost . . . . . . . . . . . . . . . . . . . . . . . . 516 Fig 89. Message overwritten indicate d by messa[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 775 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information 5. Content s Chapter 1: LPC24XX Introductory inform ation 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 How to read th is manual . . . . . . . .[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 776 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information 3.2.14 PLL setup sequence . . . . . . . . . . . . . . . . . . . . 56 3.3 Clock dividers . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.3.1 CPU Clock Configuration re[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 777 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information 10.26 S tatic Memory Write Delay registers (EMCS taticW ai twr0-3 - 0xFFE0 8214, 234, 254, 274) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 10.27 S ta[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 778 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information 5.9 Pin Function Select Re gister 8 (PINSEL8 - 0xE002 C020) . . . . . . . . . . . . . . . . . . . . . . . . 186 5.10 Pin Function Select Register 9 (PI NSEL9 - 0xE002 C024) [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 779 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information 7.1.8 T est Register (TEST - 0xFFE0 001C) . . . . . . 223 7.1.9 MII Mgmt Configuration Register (MCFG - 0xFFE0 0020) . . . . . . . . . . . . . . . . . . . . . . . . 224 7.1.[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 780 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information 4.1 Programmable p arameters . . . . . . . . . . . . . . 281 4.2 Hardware cursor sup port . . . . . . . . . . . . . . . 281 4.3 T ypes of LCD p anels supporte d . . . . . . [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 781 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information 7 Pin descriptio n . . . . . . . . . . . . . . . . . . . . . . . . 333 7.1 USB device usage note . . . . . . . . . . . . . . . . 333 8 Clocking and power management . . . . [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 782 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information 1 1.5 Read T est Register (Comma nd: 0xFD, Data: rea d 2 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 1 1.6 Set Device St atus (Co mmand: 0xFE, Data:[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 783 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information 7.3 OTG Interrupt Enable Register (OTGIntEn - 0xFFE0 C104) . . . . . . . . . . . . . . . . . . . . . . . 401 7.4 OTG Interrupt Set Register (OTG IntSet - 0xFFE0 C20C) . . . [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 784 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information 4.1 UART1 Receiver Buffer Register (U1RBR - 0xE001 0000, when DLAB = 0 Read Only) . 447 4.2 UART1 T ransmitter Holding Re gister (U1 THR - 0xE001 0000 when DLAB = 0 , Write [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 785 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information 9.3 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 9.4 Tra nsmit priorit y . . . . . . . . . . . . . . . . . . . . . . 495 10 Centralize d CAN re gist[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 786 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information 7.4 SPI Clock Counter Reg ister (S0SPCCR - 0xE002 000C) . . . . . . . . . . . . . . . . . . . . . . . . 533 7.5 SPI T est Cont rol Re gister (SPTCR - 0xE002 0010) . . . . . [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 787 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information 6.14 FIFO Counter Register (MCIF ifoCnt - 0xE008 C048) . . . . . . . . . . . . . . . . . . . . . . . . 571 6.15 Data FIFO Regist er (MCIFIFO - 0xE0 08 C08 0 to 0xE008 C0BC) [...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 788 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 1 4 Pin descriptio ns . . . . . . . . . . . . . . . . . . . . . . . 612 5 Register description . . . .[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 789 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information 5 Pin descriptio n . . . . . . . . . . . . . . . . . . . . . . . . 648 6 Register description . . . . . . . . . . . . . . . . . . . 649 6.1 RTC interru pts . . . . . . . . .[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 790 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information 5.2.4 ISP flow control . . . . . . . . . . . . . . . . . . . . . . . 679 5.2.5 ISP command abort . . . . . . . . . . . . . . . . . . . 679 5.2.6 Interrupts durin g ISP . . .[...]

UM10237_2 © NXP B.V. 2008. All rights reserved. User manual Rev . 02 — 19 December 2008 791 o f 792 NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information 5 Programming the GPDMA . . . . . . . . . . . . . . . 718 5.1 Enabling the GPD MA . . . . . . . . . . . . . . . . . . 718 5.2 Disabling the GPDMA. . . . . . . . . . . . . . [...]

NXP Semiconductors UM10237 Chapter 36: LPC24XX Supplement ary information © NXP B.V . 2008. All rights reserv ed. For more information, please visit: http://www.nxp.co m For sales office addresses, plea se se nd an email t o: salesaddresses@nxp .com Date of release : 19 December 2008 Document identi fier: UM10237 _2 Please be aware that impo rtant[...]