Omron C200HS инструкция обслуживания

Cat. No. W235-E1-5 Programmable Controllers SYSMAC C200HS[...]

C200HS Programmable Controllers Operation Manual Revised February 2002[...]

! ! ! ii Notice: OMRON products are manufactured for use according to proper procedures by a qualified operator and only for the purposes described in this manual. The following conventions are used to indicate and classify precautions in this manual. Always heed the information provided with them. Failure to heed precautions can result in injury t[...]

iii About this Manual: This manual describes the operation of the C200HS C-series Programmable Controllers, and it includes the sections described below . Installation information is provided in the C200HS Programmable Control- ler Installation Guide . A table of other manuals that can be used in conjunction with this manual is provided in Section [...]

v T ABLE OF CONTENTS PRECAUTIONS xiii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Intended Audience xiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 General Precautions xiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

T able of contents vi 3-4-10 I/O V erification Error Flag 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4-1 1 First Cycle Flag 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4-12 Clock Pulse Bits 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

T able of contents vii 4-5-1 The Keyboard 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5-2 PC Modes 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5-3 The Display Message Switch 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Pre[...]

T able of contents viii 5-15 Data Shifting 150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15-1 SHIFT REGISTER – SFT(10) 150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15-2 REVERSIBLE SHIFT REGISTER – SFTR(84) 152 . . . . . . . . . . . . . . . . . 5-15-3 ARITHM[...]

T able of contents ix 5-19-1 1 BCD DIVIDE – DIV(33) 212 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19-12 DOUBLE BCD DIVIDE – DIVL(57) 213 . . . . . . . . . . . . . . . . . . . . . . . . . 5-19-13 FLOA TING POINT DIVIDE – FDIV(79) 214 . . . . . . . . . . . . . . . . . . . . . . 5-19-14 SQUARE ROOT – ROOT(72) 217 [...]

T able of contents x 5-28 Advanced I/O Instructions 301 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28-1 7-SEGMENT DISPLA Y OUTPUT – 7SEG(––) 301 . . . . . . . . . . . . . . . . . 5-28-2 DIGIT AL SWITCH INPUT – DSW(––) 304 . . . . . . . . . . . . . . . . . . . . . . . 5-28-3 HEXADECIMAL KEY INPU[...]

T able of contents xi SECTION 10 – T roubleshooting 391 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Alarm Indicators 392 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 Programmed Alarms and Error Messages 392 . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

T able of contents xii Appendix 433 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A – Standard Models 433 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B – Programming Instructions 443 . . . . . . . . . . . . . . . . . . . . .[...]

xiii PRECAUTIONS This section provides general precautions for using the Programmable Controller (PC) and related devices. The information contained in this section is important for the safe and reliable application of the PC. Y ou must r ead this section and understand the information contained before attempting to set up or operate a PC system. 1[...]

! ! ! xiv 1 Intended Audience This manual is intended for the following personnel, who must also have knowl- edge of electrical systems (an electrical engineer or the equivalent). • Personnel in charge of installing F A systems. • Personnel in charge of designing F A systems. • Personnel in charge of managing F A systems and facilities. 2 Gen[...]

! ! ! ! xv Caution Th e operating environment of the PC System can have a large effect on the lon- gevity and reliability of the system. Improper operating environments can lead to malfunction, failure, and other unforeseeable problems with the PC System. Be sure that the operating environment is within the specified conditions at installa- tion an[...]

xvi 6 Conformance to EC Directives Observe the following precautions when installing the C200HS-CPU01-EC and C200HS-CPU21-EC that conform to the EC Directives. Provide reinforced insulation or double insulation for the DC power source con- nected to the DC I/O Unit and for the Power Supply Unit. Us e a separate power source for the DC I/O Unit from[...]

1 SECTION 1 Intr oduction This section gives a brief overview of the history of Programmable Controllers and explains terms commonly used in ladder - diagram programming. It also provides an overview of the process of programming and operating a PC and explains basic terminology used with OMRON PCs. Descriptions of peripheral devices used with the [...]

2 1-1 Overview A PC (Programmable Controller) is basically a CPU (Central Processing Unit) containing a program and connected to input and output (I/O) devices. The pro- gram controls the PC so that when an input signal from an input device turns ON, the appropriate response is made. The response normally involves turning ON an output signal to som[...]

3 1-3 PC T erminology Although also provided in the Glossary at the back of this manual, the following terms are crucial to understanding PC operation and are thus explained here. PC Because the C200HS is a Rack PC, there is no one product that is a C200HS PC. That is why we talk about the configuration of the PC, because a PC is a configuration of[...]

4 High-density I/O Units are designed to provide high-density I/O capability and include Group 2 High-density I/O Units and Special I/O High-density I/O Units. Special I/O Units are dedicated Units that are designed to meet specific needs. These include some of the High-density I/O Units, Position Control Units, High- speed Counter Units, and Analo[...]

5 Input/Output Requirements The first thing that must be assessed is the number of input and output points that the controlled system will require. This is done by identifying each device that is to send an input signal to the PC or which is to receive an output signal from the PC. Keep in mind that the number of I/O points available depends on the[...]

6 Name Contents Cat. No. SYSMAC Support Software Operation Manuals W247/W248 Programming procedures for using the SSS Data Access Console Operation Guide W173 Data area monitoring and data modification procedures for the Data Access Console Printer Interface Unit Operation Guide W107 Procedures for interfacing a PC to a printer PROM Writer Operatio[...]

7 1-8-1 Improved Memory Capabilities Internal Memory (UM) Th e C200HS CPUs come equipped with 16 KW of RAM in the PC itself, so a very large memory capacity is available without purchasing a separate Memory Unit. Furthermore, the Ladder Program Area has been increased to 15.2 KW . Memory Cassettes T wo types of Memory Cassettes are available for st[...]

8 I/O Refreshing Time Th e I/O refreshing time has been reduced for all units, as shown in the following table. I/O Unit Time Required for Refreshing Standard I/O Units ! @ 3 of the C200H I/O refreshing time Group-2 High-density I/O Units ! @ 3 of the C200H I/O refreshing time Special I/O Units $ @ 5 of the C200H I/O refreshing time 1-8-3 Larger In[...]

9 TRSM(45) TRACE MEMOR Y SAMPLE MCRO(99) MACRO MAX(--) FIND MAXIMUM MIN(--) FIND MINIMUM SUM(--) SUM SRCH(--) DA T A SEARCH FPD(--) F AILURE POINT DETECTION PID(--) PID CONTROL HEX(--) ASCII T O HEX XDMR(--) EXP ANSION DM READ DSW(--) DIGIT AL SWITCH INPUT TKY(--) TEN-KEY INPUT MTR(--) MA TRIX INPUT HKY(--) 16-KEY INPUT ADBL(--) DOUBLE BINAR Y ADD [...]

10 1-8-7 Built-in RS-232C Connector Host link communications are possible using the RS-232C connector built into the C200HS-CPU21-E/CPU23-E/CPU31-E/CPU33-E CPU. By using the TXD and RXD instructions, RS-232C communications is possible without using time- consuming procedures. A 1-to-1 link using the LR Area or an NT link with the Programmable T erm[...]

11 I/O Comments Stored in PC By allocating a part of UM as the I/O Comment area, it is no longer necessary to read I/O Comments from a Peripheral Device’ s floppy disk. If the Peripheral De- vice is connected to the C200HS online, the ladder diagram can be viewed with I/O comments. Online Editing A “CYCLE TIME OVER” error will no longer be ge[...]

12 7. T ransfer the program and and any other require data to the C200HS. Y ou will probably want to transfer DM data and the I/O table, if you have created an I/O table for the C200H. 8. T urn the C200HS off and then back on to reset it. 9. T est program execution before attempting actual operation. Using Memory Cassettes The following procedure o[...]

13 10. T urn the C200HS off and then back on to reset it and transfer data from the Memory Cassette to the CPU. 1 1. T est program execution before attempting actual operation. New C200HS Features Section 1-8[...]

15 SECTION 2 Hardware Considerations This section provides information on hardware aspects of the C200HS that are relevant to programming and software opera- tion. These include CPU Components, basic PC configuration, CPU capabilities, and Memory Cassettes. This information is covered in detail in the C200HS Installation Guide . 2-1 CPU Components [...]

! 16 2-1 CPU Components There are two groups of CPUs available, one that uses an AC power supply , and on e that uses a DC power supply . Select one of the models shown below accord- ing to requirements of your control system. CPU model Power supply voltage C200HS-CPU01-E/CPU21-E/CPU31-E 100 to 120 V AC or 200 to 240 V AC (voltage selector) C200HS-[...]

17 C200HS-CPU21-E/CPU23-E/CPU31-E/CPU33-E Memory Casette compartment Bus connector: Available only with the CPU31-E and CPU33-E. Use this connector when SYSMAC NET Link Unit or SYSMAC LINK Unit is used. RS-232C connector Cable connector for peripheral devices Battery/Switch compartment Power fuse (MF51NR, 5.2 dia. x 20 mm): C200HS-CPU21-E/CPU31-E: [...]

18 2-1-2 Peripheral Device Connection A Programming Console or IBM PC/A T running LSS can be used to program and monitor the C200HS PCs. Programming Console A C200H-PR027-E or CQM1-PRO01-E Programming Console can be con- nected as shown in the following diagram. The C200H-PR027-E is connected via the C200H-CN222 or C200H-CN422 Programming Console C[...]

19 Expansion I/O Racks An Expansion I/O Rack can be thought of as an extension of the PC because it provides additional slots to which other Units can be mounted. It is built onto an Expansion I/O Backplane to which a Power Supply and up to ten other Units are mounted. An Expansion I/O Rack is always connected to the CPU via the connectors on th e [...]

20 C200HS Function C200HS CPU01-E CPU21-E CPU31-E CPU03-E CPU23-E CPU33-E Built-in clock/calendar Ye s Error log Ye s 1 Data T race Ye s Differential Monitor Ye s Expansion DM 3K words max. 2 General-use DM 6K words Ladder Program capacity 15.2K words max 2 SR Area SR 236 to SR 255 and SR 256 to SR 299 New instructions: (See 1-8-3 Larger Instructio[...]

! 21 C200HS-MP j 16K (EPROM) The program is written using a PROM Writer . The ROM is mounted to the Memory Casette and then installed in the CPU. I/O data cannot be stored. Notch 2-5 Installing Memory Cassettes An optional Memory Cassette can be installed in the C200HS. (The C200H Memory Unit cannot be used with the C200HS.) The two types of Memory[...]

22 3. Remove the bracket from the Memory Cassette, as shown in the illustration below . Metal bracket 4. Check that the connector side goes in first and that the Cassette’s circuit components face right and then insert the Cassette into the CPU. The Cas- sette slides in along a track in the CPU. 5. Replace the Memory Cassette bracket over the Cas[...]

23 2 - 6 CPU DIP Switch The DIP switch on C200HS CPUs is located between the Memory Cassette compartment and battery . The 6 pins on the DIP switch control 6 of the CPU’s operating parameters. Pin no. Item Setting Function 1 Memory protect ON Program Memory and read-only DM (DM 6144 to DM 6655) data cannot be overwritten from a Peripheral Device.[...]

25 SECTION 3 Memory Ar eas V arious types of data are required to achieve effective and correct control. T o facilitate managing this data, the PC is provided with various memory areas for data, each of which performs a dif ferent function. The areas generally accessible by the user for use in programming are classified as data areas . The other me[...]

26 3-1 Introduction Details, including the name, size, and range of each area are summarized in the following table. Data and memory areas are normally referred to by their acro- nyms, e.g., the IR Area, the SR Area, etc. Area Size Range Comments I/O Area 480 bits IR 000 to IR 029 I/O words are allocated to the CPU Rack and Expansion I/O Racks by s[...]

27 Work Bits and W ords When some bits and words in certain data areas are not being used for their in - tended purpose, they can be used in programming as required to control other bits. Words and bits available for use in this fashion are called work words and work bits. Most, but not all, unused bits can be used as work bits. Those that can be u[...]

28 Th e same TC number can be used to designate either the present value (PV) of th e timer or counter , or a bit that functions as the Completion Flag for the timer or counter . This is explained in more detail in 3-8 TC Area . Area Word designation Bit designation IR 000 00015 (leftmost bit in word 000) SR 252 25200 (rightmost bit in word 252) DM[...]

29 Decimal Points Decimal points are used in timers only . The least significant digit represents tenths of a second. All arithmetic instructions operate on integers only . Signed and Unsigned Binary Data This section explains signed and unsigned binary data formats. Many instruc- tions can use either signed or unsigned data and a few (CPS(––),[...]

30 The following table shows the corresponding decimal, 16-bit hexadecimal, and 32-bit hexadecimal values. Decimal 16-bit Hex 32-bit Hex 2147483647 2147483646 . . . 32768 32767 32766 . . . 2 1 0 –1 –2 . . . –32767 –32768 –32769 . . . –2147483647 –2147483648 ––– ––– . . . ––– 7FFF 7FFE . . . 0002 0001 0000 FFFF FFFE .[...]

31 3-3 IR (Internal Relay) Area T he IR area is used both as data to control I/O points, and as work bits to manipu- late and store data internally . It is accessible both by bit and by word. In the C200HS PC, the IR area is comprised of words 000 to 235 and 298 to 51 1. Words i n the IR area that are used to control I/O points are called I/O words[...]

32 Up to ten Special I/O Units may be mounted in any slot of the CPU Rack or Ex- pansion I/O Racks. Up to five Slave Racks may be used, whether one or two Masters are used. IR area words are allocated to Special I/O Units and Slave Racks by the unit number on the Unit, as shown in the following tables. Special I/O Units Slave Racks Unit number IR a[...]

33 Group-2 High-density I/O Units and B7A Interface Units are allocated words be- tween IR 030 and IR 049 according to I/O number settings made on them and do no t use the words allocated to the slots in which they are mounted. For 32-point Units, each Unit is allocated two words; for 64-point Units, each Unit is allocated four words. The words all[...]

34 Note all SR words and bits are writeable by the user . Be sure to check the func- tion of a bit or word before attempting to use it in programming. Word(s) Bit(s) Function 236 00 to 07 Node loop status output area for operating level 0 of SYSMAC NET Link System 08 to 15 Node loop status output area for operating level 1 of SYSMAC NET Link System[...]

35 Word(s) Function Bit(s) 254 00 1-minute clock pulse bit 01 0.02-second clock pulse bit 02 and 03 Reserved for function expansion. Do not use. 04 Overflow Flag (for signed binary calculations) 05 Underflow Flag (for signed binary calculations) 06 Differential Monitor End Flag 07 Step Flag 08 MTR Execution Flag 09 7SEG Execution Flag 10 DSW Execut[...]

36 Word(s) Function Bit(s) 267 00 to 04 Reserved by system (not accessible by user) 05 Host Link Level 0 Send Ready Flag 06 to 12 Reserved by system (not accessible by user) 13 Host Link Level 1 Send Ready Flag 14 and 15 Reserved by system (not accessible by user) 268 00 to 15 Reserved by system (not accessible by user) 269 00 to 07 Memory Cassette[...]

37 Word(s) Function Bit(s) 273 00 Save IOM to Cassette Bit Data transferred to Memory Cassette when Bit is turned ON in PROGRAM mode. Bit will automaticall y turn OFF . 01 Load IOM from Cassette Bit ON in PROGRAM mode . Bit will automatically turn OFF . An error will be produced if turned ON in any other mode. 02 to 1 1 Reserved by system (not acce[...]

38 SYSMAC LINK Code Item Meaning 00 Normal end Processing ended normally . 01 Parameter error Parameters for network communication instruction is not within acceptable ranges. 02 Unable to send Unit reset during command processing or local node in not in network. 03 Destination not in network Destination node is not in network. 04 Busy error The de[...]

39 SYSMAC NET Operating ll 0 Operating ll 1 Bit (Node numbers below) pg level 0 pg level 1 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 S R 2 3 8 S R 2 4 2 8765432187654321 SR 239 SR 243 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 SR 240 SR 244 24 23 22 21 20 19 18 17 24 23 22 21 20 19 18 17 SR 241 SR 245 32 31 30 29 28 27 26 25 32 31 30 29 28[...]

40 Host Link Systems Both Error flags and Restart bits are provided for Host Link Systems. Error flags turn ON t o indicate errors in Host Link Units. Restart bits are turned ON and then OF F to restart a Host Link Unit. SR bits used with Host Link Systems are summa- rized in the following table. Rack-mounting Host Link Unit Restart bits are not ef[...]

41 Flag type Bit no. SR 247 SR 248 SR 249 SR 250 Run flags 00 Unit #8, level 1 Unit #0, level 1 Unit #8, level 0 Unit #0, level 0 01 Unit #9, level 1 Unit #1, level 1 Unit #9, level 0 Unit #1, level 0 02 Unit #10, level 1 Unit #2, level 1 Unit #10, level 0 Unit #2, level 0 03 Unit #1 1, level 1 Unit #3, level 1 Unit #1 1, level 0 Unit #3, level 0 0[...]

42 The status of SR 2521 1 and thus the status of force-set and force-reset bits can be maintained when power is turned off and on by enabling the Forced Status Hold Bit in the PC Setup. If the Forced Status Hold Bit is enabled, the status of SR 2521 1 will be preserved when power is turned off and on. If this is done and SR 2521 1 is ON, then the [...]

43 This bit can be programmed to activate an external warning for a low battery volt- age. The operation of the battery alarm can be disabled in the PC Setup if desired. Refer to 3-6-4 PC Setup for details. 3-4-9 Cycle Time Error Flag SR bit 25309 turns ON if the cycle time exceeds 100 ms. The ALM/ERR indicator on the front of the CPU will also fla[...]

! 44 3-4-13 Step Flag SR bit 25407 turns ON for one cycle when step execution is started with the STEP(08) instruction. 3-4-14 Group-2 Error Flag SR bit 25414 turns ON for any of the following errors for Group-2 High-density I/O Units and B7A Interface Units: the same I/O number set twice, the same words allocated to more than one Unit, refresh err[...]

45 Overflow Flag, OF SR bit 25404 turns ON when the result of a binary addition or subtraction ex- ceeds 7FFF or 7FFFFFFF . Underflow Flag, UF S R bit 25405 turns ON when the result of a signed binary addition or subtraction exceeds 8000 or 80000000. Carry Flag, CY S R bit 25504 turns ON when there is a carry in the result of an arithmetic opera- t[...]

46 3-4-20 Peripheral Port Communications Areas Peripheral Port Error Code SR bits 26408 to 2641 1 are set when there is a peripheral port error in the Gener- al I/O Mode. Setting Error type 0 No error 1 Parity error 2 Framing error 3 Overrun error F Connected in Peripheral Mode SR bit 26412 turns ON when there is a peripheral port communication err[...]

47 SR bit 27002 turns ON when data is verified between DM and a Memory Cas- sette. SR bit 27003 turns OFF when the contents of the verification coincide and turns ON when the contents of the verification do not coincide. 3-4-22 Data T ransfer Error Bits Data will not be transferred from UM to the Memory Cassette if an error occurs (except for Board[...]

48 Save IOM to Cassette Bit SR bit 27300 turns ON when IOM is saved to a Memory Cassette. Load IOM from Cassette Bit SR bit 27301 turns ON when loading to IOM from a Memory Cassette. 3-4-26 T ransfer Error Flags Data will not be transferred from IOM to the Memory Cassette if an error occurs (except for Read Only Error). SR bit 27312 turns ON when a[...]

49 Word(s) Function Bit(s) 01 00 to 09 Restart Bits for Special I/O Units 0 to 9 (also function as Restart Bits for PC Link Units) 10 Restart Bit for operating level 1 of SYSMAC LINK or SYSMAC NET Link System 11 Restart Bit for operating level 0 of SYSMAC LINK or SYSMAC NET Link System 12, 13 Not used. 14 Remote I/O Master Unit 1 Restart Flag. 15 R[...]

50 Word(s) Function Bit(s) 24 00 to 04 Reserved by system. 05 Cycle T ime Flag 06 SYSMAC LINK System Network Parameter Flag for operating level 1 07 SYSMAC LINK System Network Parameter Flag for operating level 0 08 SYSMAC/SYSMAC NET Link Unit Level 1 Mounted Flag 09 SYSMAC/SYSMAC NET Link Unit Level 0 Mounted Flag 10 Reserved by system. 1 1 and 12[...]

51 number , 0 through 31, and a letter , L or H. Bits are allocated as shown in the fol- lowing table. Bits AR03 allocation AR04 allocation AR05 allocation AR06 allocation 00 0 L 8 L 16 L 24 L 01 0 H 8 H 16 H 24 H 02 1 L 9 L 17 L 25 L 03 1 H 9 H 17 H 25 H 04 2 L 10 L 18 L 26 L 05 2 H 10 H 18 H 26 H 06 3 L 11 L 19 L 27 L 07 3 H 11 H 19 H 27 H 08 4 L[...]

52 AR 0714 (Error History Reset Bit) is turned ON and then OFF by the user to reset the Error Record Pointer (DM 0969) and thus restart recording error records at the beginning of the history area. AR 0715 (Error History Enable Bit) is turned ON by the user to enable error histo- ry storage and turned OFF to disable error history storage. Refer to [...]

53 30-second Compensation Bit AR 21 13 is turned ON to round the seconds of the Calendar/clock Area to zero, i.e., if the seconds is 29 or less, it is merely set to 00; if the seconds is 30 or great- er , the minutes is incremented by 1 and the seconds is set to 00. Clock Stop Bit AR 21 14 is turned OFF to enable the operation of the Calendar/clock[...]

54 3-5-1 1 Power OFF Counter AR 23 provides in 4-digit BCD the number of times that the PC power has been turned off. This counter can be reset as necessary using the PV Change 1 op- eration from the Programming Console. (Refer to 7-1-4 Hexadecimal/BCD Data Modification for details.) The Power OFF Counter is refreshed every time power is turned on.[...]

55 3-6 DM (Data Memory) Area The DM area is divided into various parts as described in the following table. A portion of U M (up to 3,000 words in 1,000-word increments) can be allocated as Expansion DM. Addresses User read/write Usage DM 0000 to DM 0999 Read/W rite Normal DM. DM 1000 to DM 1999 Special I/O Unit Area 1 DM 2000 to DM 5999 Normal DM.[...]

56 3-6-1 Expansion DM Area The expansion DM area is designed to provide memory space for storing oper- ating parameters and other operating data for Link Units and Special I/O Units. Up to 3,000 words of UM can be allocated as Expansion DM (in 1K-word incre- ments) using the UM ALLOCA TION operation in the Programming Console or LSS. Expansion DM a[...]

57 whether DM 1000 to DM 1999 or DM 7000 to 7999 will be used. Refer to 3-6-4 PC Setup for details. Unit Addresses 0 DM 1000 to DM 1099 or DM 7000 to DM 7099 1 DM 1 100 to DM 1 199 or DM 7100 to DM 7199 2 DM 1200 to DM 1299 or DM 7200 to DM 7299 3 DM 1300 to DM 1399 or DM 7300 to DM 7399 4 DM 1400 to DM 1499 or DM 7400 to DM 7499 5 DM 1500 to DM 15[...]

58 The following table lists the possible error codes and corresponding errors. Error severity Error code Error Fatal errors 00 Power Interruption 01 to 99 System error (F ALS) 9F Cycle time error C0 to C2 I/O bus error E0 Input-output I/O table error E1 T oo many Units F0 No END(01) instruction F1 Memory error Non-fatal errors 01 to 99 System erro[...]

59 The PC Setup is allocated to DM 6600 through DM 6655. Parameter Default Settings Remarks ST ARTUP MODE ST ARTUP MODE Programming Console mode selector Programming Console mode selector , previous mode (i.e., the mode in use last time power was interrupted), PROGRAM, MONITOR, or RUN Determines the operating mode the PC will start in when power is[...]

60 3-7 HR (Holding Relay) Area The HR area is used to store/manipulate various kinds of data and can be ac- cessed either by word or b y bit. W ord addresses range from HR 00 through HR 99; bit addresses, from HR 0000 through HR 9915. HR bits can be used in any order required and can be programmed as often as required. The HR area retains status wh[...]

61 3-9 LR (Link Relay) Area The LR area is used as a common data area to transfer information between PCs. This data transfer is achieved through a PC Link System. Certain words will be allocated as the write words of each PC. These words are written by the PC and automatically transferred to the same LR words in the other PCs in the System. The wr[...]

63 SECTION 4 W riting and Inputting the Pr ogram This section explains the basic steps and concepts involved in writing a basic ladder diagram program, inputting the program into memory , and executing it. It introduces the instructions that are used to build the basic structure of the ladder diagram and control its execution. The entire set of ins[...]

64 4-1 Basic Procedure There are several basic steps involved in writing a program. Sheets that can be copied to aid in programming are provided in Appendix F Word Assignment Re- cording Sheets and Appendix G Program Coding Sheet . 1, 2, 3... 1. Obtain a list of all I/O devices and the I/O points that have been assigned to them and prepare a table [...]

65 4-3 Program Capacity The maximum user program size varies with the amount of UM allocated to ex- pansion DM and the I/O Comment Area. Approximately 10.1 KW are available fo r the ladder program when 3 KW are allocated to expansion DM and 2 KW are allocated to I/O comments as shown below . Refer to the 3-10 UM Area for further information on UM a[...]

66 4-4-1 Basic T erms Each condition in a ladder diagram is either ON or OFF depending on the status of the operand bit that has been assigned to it. A normally open condition is ON if th e operand bit is ON; OFF if the operand bit is OFF . A normally closed condition is ON if the operand bit is OFF; OFF if the operand bit is ON. Generally speaking[...]

67 Program Memory addresses start at 00000 and run until the capacity of Program Memory has been exhausted. The first word at each address defines the instruc- tion. Any definers used by the instruction are also contained in the first word. Also, if an instruction requires only a single bit operand (with no definer), the bit operand is also program[...]

68 LOAD and LOAD NOT The first condition that starts any logic block within a ladder diagram corre- sponds to a LOAD or LOAD NOT instruction. Each of these instruction requires one line of mnemonic code. “Instruction” is used as a dummy instruction in the following examples and could be any of the right-hand instructions described lat- er in th[...]

69 OR and OR NOT When two or more conditions lie on separate instruction lines which run in paral- lel and then join together , the first condition corresponds to a LOAD or LOAD NO T instruction; the other conditions correspond to OR or OR NOT instructions. The following example shows three conditions which correspond (in order from the top) to a L[...]

70 4-4-4 OUTPUT and OUTPUT NOT The simplest way to output the results of combining execution conditions is to output it directly with the OUTPUT and OUTPUT NOT . These instructions are used to control the status of the designated operand bit according to the execu- tion condition. With the OUTPUT instruction, the operand bit will be turned ON as lo[...]

71 Now you have all of the instructions required to write simple input-output pro- grams. Before we finish with ladder diagram basic and go onto inputting the pro- gram into the PC, let’ s look at logic block instruction (AND LOAD and OR LOAD), which are sometimes necessary even with simple diagrams. 4-4-6 Logic Block Instructions Logic block ins[...]

72 Analyzing the above ladder diagram in terms of mnemonic instructions, the con- dition for IR 00000 is a LOAD instruction and the condition below it is an OR in- struction between the status of IR 00000 and that of IR 00001. The condition at IR 00002 is another LOAD instruction and the condition below is an OR NOT instruction, i.e., an OR between[...]

73 The following diagram requires AND LOAD to be converted to mnemonic code because three pairs of parallel conditions lie in series. The two options for coding the programs are also shown. 00000 00002 00004 00001 00003 00005 00500 Address Instruction Operands Address Instruction Operands 00000 LD 00000 00001 OR NOT 00001 00002 LD NOT 00002 00003 O[...]

74 The following diagram contains only two logic blocks as shown. It is not neces- sary to further separate block b components, because it can be coded directly using only AND and OR. 00000 00001 00002 00003 00201 00501 00004 Block a Block b Address Instruction Operands 00000 LD 00000 00001 AND NOT 00001 00002 LD 00002 00003 AND 00003 00004 OR 0020[...]

75 When working with complicated diagrams, blocks will ultimately be coded start- ing at the top left and moving down before moving across. This will generally mean that, when there might be a choice, OR LOAD will be coded before AND LOAD. The following diagram must be broken down into two blocks and each of these then broken into two blocks before[...]

76 Th e following diagram requires an OR LOAD followed by an AND LOAD to code th e top of the three blocks, and then two more OR LOADs to complete the mne- monic code. 00002 00003 LR 0000 00000 00001 00004 00005 00006 00007 Address Instruction Operands 00000 LD 00000 00001 LD 00001 00002 LD 00002 00003 AND NOT 00003 00004 OR LD –– 00005 AND LD [...]

77 Again, this diagram can be redrawn as follows to simplify program structure and coding and to save memory space. 00006 00007 LR 0000 00005 00001 00002 00003 00004 00000 Address Instruction Operands 00000 LD 00006 00001 AND 00007 00002 OR 00005 00003 AND 00003 00004 AND 00004 00005 LD 00001 00006 AND 00002 00007 OR LD –– 00008 AND 00000 00009[...]

78 4-4-7 Coding Multiple Right-hand Instructions If there is more than one right-hand instruction executed with the same execu- tion condition, they are coded consecutively following the last condition on the instruction line. In the following example, the last instruction line contains one more condition that corresponds to an AND with IR 00004. 0[...]

79 Except for the SHIFT key on the upper right, the gray keys are used to input in- structions and designate data area prefixes when inputting or changing a pro- gram. The SHIFT key is similar to the shift key of a typewriter , and is used to alter the function of the next key pressed. (It is not necessary to hold the SHIFT key down; just press it [...]

! ! 80 4-5-2 PC Modes T he Programming Console is equipped with a switch to control the PC mode. T o select one of the three operating modes—RUN, MONITOR, or PROGRAM— use the mode switch. The mode that you select will determine PC operation as well as the procedures that are possible from the Programming Console. RUN mode is the mode used for n[...]

81 4. Confirm that the CPU’ s POWER LED is lit and the following display appears on the Programming Console screen. (If the ALM/ERR LED is lit or flashing or an error message is displayed, clear the error that has occurred.) <PROGRAM> P ASSWORD! 5. Enter the password. See 4-6-1 Entering the Password for details. 6. Clear memory . Skip this [...]

82 4-6-3 Clearing Memory Using the Memory Clear operation it is possible to clear all or part of the UM area (RAM or EEPROM), and the IR, HR, AR, DM and TC areas. Unless otherwise specified, the clear operation will clear all of the above memory areas. The UM area will not be cleared if the write-protect switch (pin 1 of the CPU’ s DIP switch) is[...]

83 The following procedure is used to clear memory completely . Continue pressing the CLR key once for each error message until “00000” appears on the display All clear MEMOR Y ERR I/O VER ERR 00000 00000MEMOR Y CLR? HR CNT DM 00000MEM ALLCLR? 00000 00000MEM ALLCLR END Partial Clear It is possible to retain the data in specified areas or part o[...]

84 T o leave the TC area uncleared and retain Program Memory addresses 00000 through 00122, input as follows: 00000 00000 00000 00000MEMOR Y CLR? HR CNT DM 00000MEMOR Y CLR? HR DM 00123MEMOR Y CLR? HR DM 00000MEMOR Y CLR END HR DM Memory Clear The memory clear operation clears all memory areas except the I/O comments and UM Allocation information. [...]

85 It is necessary to register the I/O table if I/O Units are changed, otherwise an I/O verification error message, “I/O VER ERR” or “I/O SET ERROR”, will appear when starting programming operations. I/ O T able Registration can be performed only in PROGRAM mode with the write- protection switch (pin 1 of the CPU’s DIP switch) set to OFF [...]

86 4-6-6 V erifying the I/O T able The I/O T able V erification operation is used to check the I/O table registered in memory to see if it matches the actual sequence of I/O Units mounted. The first inconsistency discovered will be displayed as shown below . Every subsequent pressing of VER displays the next inconsistency . Note This operation can [...]

87 4-6-7 Reading the I/O T able The I/O T able Read operation is used to access the I/O table that is currently registered in the CPU memory . This operation can be performed in any PC mode. Key Sequence [0 to 2] [0 to 9] Rack number Unit number Press the EXT key to select Remote I/O Slave Racks or Optical I/O Units. 00000 00000 FUN (??) 00000IOTBL[...]

88 Meaning of Displays I/O Unit Designations for Displays (see I/O Units Mounted in Remote Slave Racks , page 89) No. of points 16 32 64 Input Unit Output Unit C500, 1000H/C2000H I/O Units No. of points 8 16 Input Unit Output Unit 0 0 0 0 0 0 * * 0 * * * I * * * I I * * I I I I i(*)* * i i * * o o * * o * * * C200H I/O Units Note: ( ∗ ) is i for [...]

89 I/O word number I/O type: I, O i, o (see tables on previous page) Unit number (0 to 9) Remote I/O Slave Unit number (0 to 4) Remote I/O Master Unit number (0 or 1) Indicates a Remote I/O Rack 00000IOTBL READ R**-*U=**** *** Unit number (0 to 9) Indicates Group-2 HIgh-density I/O Unit 00000IOTBL READ *-*U=#*** 2: 2 words (32 pts) 4: 4 words (64 p[...]

90 Key Sequence 00000 00000 FUN (??) 00000IOTBL ?-?U= 00000IOTBL CANC ???? 00000IOTBL CANC 9713 00000IOTBL CANC OK 00000IOTBL WRIT ???? 4-6-9 SYSMAC NET Link T able T ransfer (CPU31/33-E Only) The SYSMAC NET Link T able T ransfer operation transfers a copy of the SYS- MAC NET Link Data Link table to RAM or EEPROM program memory .This al- lows the u[...]

91 Key Sequence 00000LINK TBL~UM (SYSMAC-NET)???? 00000LINK TBL~UM OK 00000LINK TBL~UM (SYSMAC-NET)9713 00000LINK TBL~UM DISABLED The following indicates that the I/O table cannot be transferred. 00000 00000 FUN(??) Example Preparation for Operation Section 4-6[...]

92 4-7 Inputting, Modifying, and Checking the Program Once a program is written in mnemonic code, it can be input directly into the PC from a Programming Console. Mnemonic code is keyed into Program Memory addresses from the Programming Console. Checking the program involves a syntax check to see that the program has been written according to synta[...]

93 If the following mnemonic code has already been input into Program Memory , the key inputs below would produce the displays shown. 00000 00200 00200READ OFF LD 00000 00201READ ON AND 00001 00202READ OFF TIM 000 00202 TIM #0123 00203READ ON LD 00100 Address Instruction Operands 00200 LD 00000 00201 AND 00001 00202 TIM 000 # 0123 00203 LD 00100 4-[...]

! 94 The SV (set value) for a timer or counter is generally entered as a constant, al- though inputting the address of a word that holds the SV is also possible. When inputting an SV as a constant, CONT/# is not required; just input the numeric value and press WRITE. T o designate a word, press CLR and then input the word address as described above[...]

95 Example The following program can be entered using the key inputs shown below . Dis- plays will appear as indicated. 00000 00200 00200 LD 00002 00201READ NOP (00) 00201 TIM 000 00201 TIM DA T A #0000 00201 TIM #0123 00202READ NOP (00) 00202 FUN (??) 00202 TIMH (15) 001 00202 TIMH DA T A #0000 00202 TIMH #0500 00203READ NOP (00) Address Instructi[...]

96 Error Messages The following error messages may appear when inputting a program. Correct th e error as indicated and continue with the input operation. The asterisks in the displays shown below will be replaced with numeric data, normally an address, in the actual display . Message Cause and correction ****REPL ROM An attempt was made to write t[...]

97 Many of the following errors are for instructions that have not yet been described yet. Refer to 4-8 Controlling Bit Status or to Section 5 Instruction Set for details on these. T ype Message Meaning and appropriate response T ype A ????? The program has been lost. Re-enter the program. NO END INSTR There is no END(01) in the program. Write END([...]

98 Example Th e following example shows some of the displays that can appear as a result of a program check. Display #2 Display #3 Halts program check Check continues until END(01) When errors are found Display #1 00699CHK ABOR TD 02000PROG CHK END (01)(02.7KW) 00178CIRCUIT ERR OUT 00200 00200IL-ILC ERR ILC (03) 02000NO END INST END 00000 00000PROG[...]

99 4-7-5 Program Searches The program can be searched for occurrences of any designated instruction or data area address used in an instruction. Searches can be performed from any currently displayed address or from a cleared display . T o designate a bit address, press SHIFT , press CONT/#, then input the address, including any data area designati[...]

100 00000 00000 LD 00000 00200SRCH LD 00000 00202 LD 00000 02000SRCH END (01)(02.7KW) 00000 00100 00100 TIM 001 00203SRCH TIM 001 00203 TIM DA T A #0123 00000 00000CONT SRCH CONT 00005 00200CONT SRCH LD 00005 00203CONT SRCH AND 00005 02000 END (01)(02.7K) 4-7-6 Inserting and Deleting Instructions In PROGRAM mode, any instruction that is currently d[...]

! 101 T o delete an instruction, display the instruction word of the instruction to be de- leted and then press DEL and the up key . All the words for the designated in- struction will be deleted. Caution Be careful not to inadvertently delete instructions; there is no way to recover them without reinput- ting them completely . Key Sequences When a[...]

102 Find the address prior to the inser- tion point Insert the instruction Program After Insertion Inserting an Instruction 00000 00000 OUT 00000 00000 OUT 00201 00207SRCH OUT 00201 00206READ AND NOT 00104 00206 AND 00000 00206 AND 00105 00206INSER T? AND 00105 00207INSER T END AND NOT 00104 00206READ AND 00105 Address Instruction Operands 00000 LD[...]

103 4-7-7 Branching Instruction Lines When an instruction line branches into two or more lines, it is sometimes neces- sary to use either interlocks or TR bits to maintain the execution condition that existed at a branching point. This is because instruction lines are executed across to a right-hand instruction before returning to the branching poi[...]

104 Th e previous diagram B can be written as shown below to ensure correct execu- tion. In mnemonic code, the execution condition is stored at the branching point using the TR bit as the operand of the OUTPUT instruction. This execution con- dition is then restored after executing the right-hand instruction by using the same TR bit as the operand [...]

105 When drawing a ladder diagram, be careful not to use TR bits unless necessary . Often the number of instructions required for a program can be reduced and ease of understanding a program increased by redrawing a diagram that would otherwise required TR bits. In both of the following pairs of diagrams, the bottom versions require fewer instructi[...]

106 When an INTERLOCK instruction is placed before a section of a ladder pro- gram, th e execution condition for the INTERLOCK instruction will control the ex- ecution of all instruction up to the next INTERLOCK CLEAR instruction. If the execution condition for the INTERLOCK instruction is OFF , all right-hand in- structions through the next INTERL[...]

107 If IR 00000 in the above diagram is OFF (i.e., if the execution condition for the first INTERLOCK instruction is OFF), instructions 1 through 4 would be ex- ecuted with OFF execution conditions and execution would move to the instruc- tion following the INTERLOCK CLEAR instruction. If IR 00000 is ON, the status of IR 00001 would be loaded as th[...]

108 The other type of jump is created with a jump number of 00. As many jumps as desired can be created using jump number 00 and JUMP instructions using 00 can be used consecutively without a JUMP END using 00 between them. It is even possible for all JUMP 00 instructions to move program execution to the same JUMP END 00, i.e., only one JUMP END 00[...]

109 4-8-1 DIFFERENTIA TE UP and DIFFERENTIA TE DOWN DIFFERENTIA TE UP and DIFFERENTIA TE DOWN instructions are used to turn the operand bit ON for one cycle at a time. The DIFFERENTIA TE UP in- struction turns ON the operand bit for one cycle after the execution condition for it goes from OFF to ON; the DIFFERENTIA TE DOWN instruction turns ON the [...]

11 0 T o create a self-maintaining bit, the operand bit of an OUTPUT instruction is used a s a condition for the same OUTPUT instruction in an OR setup so that the operand bit of the OUTPUT instruction will remain ON or OFF until changes o c - cur in other bits. At least one other condition is used just before the OUTPUT instruction to function as [...]

111 Work bits can be used to simplify programming when a certain combination of conditions is repeatedly used in combination with other conditions. In the follow- ing example, IR 00000, IR 00001, IR 00002, and IR 00003 are combined in a logic block that stores the resulting execution condition as the status of IR 24600. IR 24600 is then combined wi[...]

11 2 This action is easily programmed by using IR 22500 as a work bit as the operand of the DIFFERENTIA TE UP instruction (DIFU(13)). When IR 00000 turns ON, IR 22500 will be turned ON for one cycle and then be turned OFF the next cycle by DIFU(13). Assuming the other conditions controlling IR 00100 are not keeping it ON, the work bit IR 22500 will[...]

11 3 Except for instructions for which conditions are not allowed (e.g., INTERLOCK CLEAR and JUMP END, see below), every instruction line must also have at least one condition on it to determine the execution condition for the instruction at the right. Again, diagram A , below , must be drawn as diagram B. If an instruc- tion must be continuously e[...]

11 4 4-1 1 Program Execution When program execution is started, the CPU cycles the program from top to bot- tom, checking all conditions and executing all instructions accordingly as it moves down the bus bar . It is important that instructions be placed in the proper order so that, for example, the desired data is moved to a word before that word [...]

11 5 SECTION 5 Instruction Set Th e C200HS PC has a large programming instruction set that allows for easy programming of complicated control processes. This section explains instructions individually and provides the ladder diagram symbol, data areas, and flags used with each. The C200HS can process more than 100 instructions that require function[...]

11 6 5-16-2 MOVE NOT – MVN(22) 159 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16-3 BLOCK SET – BSET(71) 160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16-4 BLOCK TRANSFER – XFER(70) 161 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16-5 DA T A EXCHANGE – XCHG(73) 162 . . [...]

11 7 5-20-9 SIGNED BINAR Y DIVIDE – DBS(––) 231 . . . . . . . . . . . . . . . . . . . . . . . . 5-20-10 DOUBLE SIGNED BINAR Y DIVIDE – DBSL(––) 232 . . . . . . . . . . . . . . 5-21 Special Math Instructions 233 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21-1 FIND MAXIMUM – MAX(––) 233[...]

11 8 5-1 Notation In the remainder of this manual, all instructions will be referred to by their mne- monics. For example, the Output instruction will be called OUT ; the AND Load instruction, AND LD. If you’re not sure of the instruction a mnemonic is used for , refer to Appendix B Programming Instructions . If an instruction is assigned a funct[...]

! 11 9 Caution The IR and SR areas are considered as separate data areas. If an operand has access to one area, it doesn’t necessarily mean that the same operand will have access to the other area. The border bet ween the IR and SR areas can, however , be crossed for a single operand, i.e., the last bi t in the IR area may be specified for an ope[...]

! 120 A non-differentiated instruction is executed each time it is cycled as long as its execution condition is ON. A dif ferentiated instruction is executed only once af- ter its execution condition goes from OFF to ON. If the execution condition has not changed or has changed from ON to OFF since the last time the instruction was cycled, the inst[...]

121 Code Mnemonic Name Page 17 (@)ASFT ASYNCHRONOUS SHIFT REGISTER 157 18 (@)SCAN CYCLE TIME 276 19 (@)MCMP MUL TI-WORD COMP ARE 169 47 (@)LMSG 32-CHARACTER MESSAGE 279 48 (@)TERM TERMINAL MODE 280 60 CMPL DOUBLE COMP ARE 172 61 (@)MPRF GROUP-2 HIGH-DENSITY I/O REFRESH 282 62 (@)XFRB TRANSFER BITS 168 63 (@)LINE COLUMN TO LINE 200 64 (@)COLM LINE T[...]

122 5-6 Coding Right-hand Instructions Writing mnemonic code for ladder instructions is described in Section 4 Writing and Inputting the Program . Converting the information in the ladder diagram symbol for all other instructions follows the same pattern, as described below , and is not specified for each instruction individually . The first word o[...]

123 The following diagram and corresponding mnemonic code illustrates the points described above. Address Instruction Data 00000 LD 00000 00001 AND 00001 00002 OR 00002 00003 DIFU(13) 22500 00004 LD 00100 00005 AND NOT 00200 00006 LD 01001 00007 AND NOT 01002 00008 AND NOT LR 6300 00009 OR LD –– 00010 AND 22500 0001 1 BCNT(67) –– # 0001 004[...]

124 Multiple Instruction Lines If a right-hand instruction requires multiple instruction lines (such as KEEP(1 1)), all of the lines for the instruction are entered before the right-hand instruction. Each of the lines for the instruction is coded, starting with LD or LD NOT , to form ‘logic blocks’ that are combined by the right-hand instructio[...]

Instruction Set Lists Section 5-7 125 5-7 Instruction Set Lists This section provides tables of the instructions available in the C200HS. The first table can be used to find instructions by function code. The second table can be used to find instruction by mnemonic. In both tables, the @ symbol indicates in- structions with differentiated variation[...]

Instruction Set Lists Section 5-7 126 Mnemonic Page Name Words Code ASL (@) 25 2 ARITHMETIC SHIFT LEFT 154 ASR (@) 26 2 ARITHMETIC SHIFT RIGHT 154 A VG (@) –– 4 A VERAGE V ALUE 235 BCD (@) 24 3 BINARY TO BCD 181 BCDL (@) 59 3 DOUBLE BINARY -TO-DOUBLE BCD 182 BCMP (@) 68 4 BLOCK COMP ARE 174 BCNT (@) 67 4 BIT COUNTER 283 BIN (@) 23 3 BCD-TO-BINA[...]

Instruction Set Lists Section 5-7 127 Mnemonic Page Name Words Code LD NOT None 1 LOAD NOT 129 LINE (@) 63 4 COLUMN TO LINE 200 LMSG (@) 47 4 32-CHARACTER MESSAGE 279 MAX (@) –– 4 FIND MAXIMUM 233 MBS (@) –– 4 SIGNED BINARY MUL TIPL Y 229 MBSL (@) –– 4 DOUBLE SIGNED BINARY MUL TIPL Y 230 MCMP (@) 19 4 MUL TI-WORD COMP ARE 169 MCRO (@) 9[...]

Instruction Set Lists Section 5-7 128 Mnemonic Page Name Words Code SLD (@) 74 3 ONE DIGIT SHIFT LEFT 156 SNXT 09 2 STEP ST ART 266 SRCH (@) –– 4 DA T A SEARCH 289 SRD (@) 75 3 ONE DIGIT SHIFT RIGHT 156 STC (@) 40 1 SET CARRY 205 STEP 08 2 STEP DEFINE 266 SUB (@) 31 4 BCD SUBTRACT 207 SUBL (@) 55 4 DOUBLE BCD SUBTRACT 209 SUM (@) –– 4 SUM C[...]

129 5-8 Ladder Diagram Instructions Ladder Diagram instructions include Ladder instructions and Logic Block instructions and correspond to the conditions on the ladder diagram. Logic block instructions are used to relate more complex parts. 5-8-1 LOAD, LOAD NOT , AND, AND NOT , OR, and OR NOT B : Bit IR, SR, AR, HR, TC, LR, TR Ladder Symbols Operan[...]

130 5-8-2 AND LOAD and OR LOAD Ladder Symbol AND LOAD – AND LD 00002 00003 00000 00001 Ladder Symbol OR LOAD – OR LD 00000 00001 00002 00003 Description When instructions are combined into blocks that cannot be logically combined using only OR and AND operations, AND LD and OR LD are used. Whereas AND and OR operations logically combine a bit s[...]

131 OUT turns ON the designated bit for an ON execution condition, and turns OFF th e designated bit for an OFF execution condition. With a TR bit, OUT appears at a branching point rather than at the end of an instruction line. Refer to 4-7-7 Branching Instruction Lines for details. OUT NOT turns ON the designated bit for a OFF execution condition,[...]

132 Precautions DIFU(13) and DIFD(14) operation can be uncertain when the instructions are programmed between IL and ILC, between JMP and JME, or in subroutines. Re- fer to 5-10 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03) , 5-1 1 JUMP and JUMP END – JMP(04) and JME(05) , and 5-23 Subroutines and Inter- rupt Control for details. In diagra[...]

133 5-9-3 SET and RESET – SET and RSET B : Bit IR, SR, AR, HR, LR Ladder Symbols Operand Data Areas SET B B : Bit IR, SR, AR, HR, LR RSET B Description SE T turns the operand bit ON when the execution condition is ON, and does not affect the status of the operand bit when the execution condition is OFF . RSET turns the operand bit OFF when the ex[...]

134 Description KEEP(1 1) is used to maintain the status of the designated bit based on two exe- cution conditions. These execution conditions are labeled S and R. S is the set input; R, the reset input. KEEP(1 1) operates like a latching relay that is set by S and reset by R. When S turns ON, the designated bit will go ON and stay ON until reset, [...]

135 Example If a HR bit or an AR bit is used, bit status will be retained even during a power interruption. KEEP(1 1) can thus be used to program bits that will maintain status after restarting the PC following a power interruption. An example of this that can be used to produce a warning display following a system shutdown for an emer- gency situa[...]

136 IL(02) and ILC(03) do not necessarily have to be used in pairs. IL(02) can be used several times in a row , with each IL(02) creating an interlocked section through the next ILC(03). ILC(03) cannot be used unless there is at least one IL(02) between it and any previous ILC(03). Changes in the execution condition for a DIFU(13) or DIFD(14) are n[...]

137 Example The following diagram shows IL(02) being used twice with one ILC(03). 00000 00001 ILC(03) IL(02) 00004 00005 00003 00002 IL(02) 00502 TIM 51 1 CP R CNT 001 IR 010 00100 001.5 s TIM 51 1 #0015 Address Instruction Operands 00000 LD 00000 00001 IL(02) 00002 LD 00001 00003 TIM 51 1 # 0015 00004 LD 00002 00005 IL(02) 00006 LD 00003 00007 AND[...]

138 If the jump number for JMP(04) is 00, the CPU will look for the next JME(05) with a jump number of 00. T o do so, it must search through the program, causing a longer cycle time (when the execution condition is OFF) than for other jumps. The status of timers, counters, bits used in OUT , bits used in OUT NOT , and all other status controlled by[...]

139 Any one TC number cannot be defined twice, i.e., once it has been used as the definer in any of the timer or counter instructions, it cannot be used again. Once defined, TC numbers can be used as many times as required as operands in instructions other than timer and counter instructions. TC numbers run from 000 through 51 1. No prefix is requi[...]

140 If the execution condition remains ON long enough for TIM to time down to zero, the Completion Flag for the TC number used will turn ON and will remain ON until TIM is reset (i.e., until its execution condition is goes OFF). The following figure illustrates the relationship between the execution condition for TIM and the Completion Flag assigne[...]

141 There are two ways to achieve timers that operate for longer than 999.9 sec- onds. One method is to program consecutive timers, with the Completion Flag of each timer used to activate the next timer . A simple example with two 900.0-sec- ond (15-minute) timers combined to functionally form a 30-minute timer . 00000 TIM 001 TIM 002 00200 900.0 s[...]

142 The length of time that a bit is kept ON or OFF can be controlled by combining TI M with OUT or OUT NO. The following diagram demonstrates how this is pos- sible. In this example, 00204 would remain ON for 1.5 seconds after 00000 goes ON regardless of the time 00000 stays ON. This is achieved by using 01000 as a self-maintaining bit activated b[...]

143 Bits can be programmed to turn ON and OFF at regular intervals while a desig- nated execution condition is ON by using TIM twice. One TIM functions to turn ON and OFF a specified bit, i.e., the Completion Flag of this TIM turns the speci- fied bit ON and OFF . The other TIM functions to control the operation of the first TIM, i.e., when the fir[...]

144 Each TC number can be used as the definer in only one TIMER or COUNTER instruction. If the cycle time is greater than 10 ms, use TC 000 through TC 015. Description TIMH(15) operates in the same way as TIM except that TIMH measures in units of 0.01 second. Th e cycle time affects TIMH(15) accuracy if TC 016 through TC 51 1 are used. I f the cycl[...]

145 Precautions The PVs of totalizing timers in interlocked program sections are maintained when the execution condition for IL(02) is OFF . Unlike timers and high-speed timers, totalizing timers in jumped program sections do not continue timing, but maintain the PV . Power interruptions will reset timers. T otalizing timers will not restart after [...]

146 Limitations Each TC number can be used as the definer in only one TIMER or COUNTER instruction. Description CNT is used to count down from SV when the execution condition on the count pulse, CP , goes from OFF to ON, i.e., the present value (PV) will be decre- mented by one whenever CNT is executed with an ON execution condition for CP and the [...]

147 Th e above CNT can be modified to restart from SV each time power is turned ON to the PC. This is done by using the First Cycle Flag in the SR area (25315) to reset CNT as shown below . 00000 CP R CNT 004 #0150 00002 00001 00205 CNT 004 25315 Address Instruction Operands 00000 LD 00000 00001 AND 00001 00002 LD 00002 00003 OR 25315 00004 CNT 004[...]

! 148 tween when the Completion Flag for TIM 001 goes ON and TIM 001 is reset by its Completion Flag). TIM 001 is also reset by the Completion Flag for CNT 002 so that the extended timer would not start again until CNT 002 was reset by 00001, which serves as the reset for the entire extended timer . Because in this example the SV for TIM 001 is 5.0[...]

149 Limitations Each TC number can be used as the definer in only one TIMER or COUNTER instruction. Description The CNTR(12) is a reversible, up/down circular counter , i.e., it is used to count between zero and SV according to changes in two execution conditions, those i n the increment input (II) and those in the decrement input (DI). The present[...]

150 5-15 Data Shifting Al l of the instructions described in this section are used to shift data, but in diffe r- ing amounts and directions. The first shift instruction, SFT(10), shifts an execu- tion condition into a shift register; the rest of the instructions shift data that is al- ready in memory . 5-15-1 SHIFT REGISTER – SFT(10) St : Starti[...]

151 The following example uses the 1-second clock pulse bit (25502) so that the execution condition produced by 00005 is shifted into a 3-word register between IR 010 and IR 012 every second. I P SFT(10) 010 012 R 00005 25502 00006 Address Instruction Operands 00000 LD 00005 00001 LD 25502 00002 LD 00006 00003 SFT(10) 010 012 Th e following program[...]

152 The program is set up so that a rotary encoder (00000) controls execution of SFT(10) through a DIFU(13), the rotary encoder is set up to turn ON and OFF each time a product passes the first sensor . Another sensor (00002) is used to detect faulty products in the shoot so that the pusher output and HR 0003 of the shift register can be reset as r[...]

153 Description SFTR(84) is used to create a single- or multiple-word shift register that can shift data to either the right or the left. T o create a single-word register , designate the same word for St and E. The control word provides the shift direction, the status to be put into the register , the shift pulse, and the reset input. The control [...]

154 5-15-3 ARITHMETIC SHIFT LEFT – ASL(25) Wd : Shift word IR, SR, AR, DM, HR, LR Ladder Symbols Operand Data Areas ASL(25) Wd @ASL(25) Wd Description When the execution condition is OFF , ASL(25) is not executed. When the execu- tion condition is ON, ASL(25) shifts a 0 into bit 00 of Wd, shifts the bits of Wd one bit to the left, and shifts the [...]

155 5-15-5 ROT A TE LEFT – ROL(27) Wd : Rotate word IR, SR, AR, DM, HR, LR Ladder Symbols Operand Data Areas ROL(27) Wd @ROL(27) Wd Description When the execution condition is OFF , ROL(27) is not executed. When the exe- cution condition is ON, ROL(27) shifts all Wd bits one bit to the left, shifting CY into bit 00 of Wd and shifting bit 15 of Wd[...]

156 5-15-7 ONE DIGIT SHIFT LEFT – SLD(74) Ladder Symbols Operand Data Areas SLD(74) St E @SLD(74) St E St : Starting word IR, SR, AR, DM, HR, LR E : End word IR, SR, AR, DM, HR, LR Limitations St and E must be in the same data area, and St must be less than or equal to E. Description When the execution condition is OFF , SLD(74) is not executed. [...]

157 Precautions If a power failure occurs during a shift operation across more than 50 words, the shift operation might not be completed. Set the range between E and St to a maximum of 50 words. Flags ER: The St and E words are in different areas, or St is less than E. Indirectly addressed DM word is non-existent. (Content of ∗ DM word is not BCD[...]

158 Description When the execution condition is OFF , ASFT(17) does nothing and the program moves to the next instruction. When the execution condition is ON, ASFT(17) is used to create and control a reversible asynchronous word shift register be- tween St and E. This register only shifts w ords when the next word in the register is zero, e.g., if [...]

159 5-16-1 MOVE – MOV(21) S : Source word IR, SR, AR, DM, HR, TC, LR, # D : Destination word IR, SR, AR, DM, HR, LR Ladder Symbols Operand Data Areas MOV(21) S D @MOV(21) S D Description When the execution condition is OFF , MOV(21) is not executed. When the exe- cution condition is ON, MOV(21) copies the content of S to D. Source word Destinatio[...]

160 5-16-3 BLOCK SET – BSET(71) S : Source data IR, SR, AR, DM, HR, TC, LR, # St : Starting word IR, SR, AR, DM, HR, TC, LR Ladder Symbols Operand Data Areas E : End Word IR, SR, AR, DM, HR, TC, LR BSET(71) S St E @BSET(71) S St E Limitations St must be less than or equal to E, and St and E must be in the same data area. Description When the exec[...]

161 Example Th e following example shows how to use BSET(71) to change the PV of a timer depending on the status of IR 00003 and IR 00004. When IR 00003 is ON, TIM 01 0 will operate as a 50-second timer; when IR 00004 is ON, TIM 010 will oper- ate as a 30-second timer . TIM 010 #9999 @BSET(71) #0500 TIM 010 TIM 010 @BSET(71) #0300 TIM 010 TIM 010 0[...]

162 Flags ER: N is not BCD between 0000 and 2000. S and S+N or D and D+N are not in the same data area. Indirectly addressed DM word is non-existent. (Content of ∗ DM word is not BCD, or the DM area boundary has been exceeded.) 5-16-5 DA T A EXCHANGE – XCHG(73) E1 : Exchange word 1 IR, SR, AR, DM, HR, TC, LR E2 : Exchange word 2 IR, SR, AR, DM,[...]

163 When the execution condition is OFF , DIST(80) is not executed. When the exe- cution condition is ON, DIST(80) operates a stack from DBs to DBs+C–9000. DB s is the stack pointer , so S is copied to the word indicated by DBs and DBs is incremented by 1. Specifies the stack length (000 to 999). A value of 9 indicates stack operation. Digits of [...]

164 5-16-7 DA T A COLLECT – COLL(81) SBs : Source base word IR, SR, AR, DM, HR, TC, LR C : Offset data (BCD) IR, SR, AR, DM, HR, TC, LR, # Ladder Symbols Operand Data Areas D : Destination word IR, SR, AR, DM, HR, TC, LR COLL(81) SBs C D @COLL(81) SBs C D Limitations C must be a BCD. If C ≤ 6655, SBs must be in the same data area as SBs+C. If t[...]

165 Example In the following example, the content of C (HR 00) is 9010, and COLL(81) is used to copy the oldest entries from a10-word stack (IR 001 to IR 010) to LR 20. Stack pointer decremented After one execution After two executions DIST(80) 001 HR 00 LR 20 00001 Address Instruction Operands 00000 LD 00001 00001 COLL(81) 001 HR 00 LR 20 IR 001 B[...]

166 Example In the following example, the content of C (HR 00) is 8010, and COLL(81) is used to copy the most recent entries from a 10-word stack (IR 001 to IR 010) to LR 20. Stack pointer decremented After one execution After two executions COLL(81) 001 HR 00 LR 20 00001 Address Instruction Operands 00000 LD 00001 00001 COLL(81) 001 HR 00 LR 20 IR[...]

167 Description When the execution condition is OFF , MOVB(82) is not executed. When the exe- cution condition is ON, MOVB(82) copies the specified bit of S to the specified bit in D. The bits in S and D are specified by Bi. The rightmost two digits of Bi desig- nate the source bit; the leftmost two bits designate the destination bit. 1 Bi 120 Sour[...]

168 Digit Designator The following show examples of the data movements for various values of Di. 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 S Di: 0031 Di: 0023 Di: 0030 Di: 0010 S S S 0 1 2 3 D 0 1 2 3 D 0 1 2 3 D 0 1 2 3 D Flags ER: At least one of the rightmost three digits of Di is not between 0 and 3. Indirectly addressed DM word is non-existent. (Content[...]

169 Example In the following example, XFRB(62) is used to transfer 5 bits from IR 020 to LR 2 1 when IR 00001 is ON. The starting bit in IR 020 is 0, and the starting bit in LR 21 is 4, so IR 02000 to IR 02004 are copied to LR 2104 to LR 2108. XFRB(62) #0540 IR 020 LR 21 00001 Address Instruction Operands 00000 LD 00001 00001 XFRB(62) # 0540 020 LR[...]

170 Example The following example shows the comparisons made and the results provided for MCMP(19). Here, the comparison is made during each cycle when 00000 is ON. IR 100 0100 DM 0200 0100 DM 030000 0 IR 101 0200 DM 0201 0200 DM 030001 0 IR 102 0210 DM 0202 0210 DM 030002 0 IR 103 ABCD DM 0203 0400 DM 030003 1 IR 104 ABCD DM 0204 0500 DM 030004 1 [...]

171 Flags ER: Indirectly addressed DM word is non-existent. (Content of ∗ DM word is not BCD, or the DM area boundary has been exceeded.) EQ : ON if Cp1 equals Cp2. LE : ON if Cp1 is less than Cp2. GR : ON if Cp1 is greater than Cp2. Flag Address C1 < C2 C1 = C2 C1 > C2 GR 25505 OFF OFF ON EQ 25506 OFF ON OFF LE 25507 ON OFF OFF The followi[...]

172 The branching structure of this diagram is important in order to ensure that 00200, 00201, and 00202 are controlled properly as the timer counts down. Be- cause all of the comparisons here use to the timer ’s PV a s reference, the other operand for each CMP(20) must be in 4-digit BCD. #2000 CMP(20) TIM 010 #3000 CMP(20) TIM 010 CMP(20) TIM 01[...]

173 Limitations Cp1 and Cp1+1 must be in the same data area, as must Cp2 and Cp2+1. Description When the execution condition is OFF , CMPL(60) is not executed. When the exe- cution condition is ON, CMPL(60) joins the 4-digit hexadecimal content of Cp1+1 with that of Cp1, and that of Cp2+1 with that of Cp2 to create two 8-digit hexadecimal numbers, [...]

174 5-17-4 BLOCK COMP ARE – BCMP(68) CD : Compare data IR, SR, AR, DM, HR, TC, LR, # CB : First comparison block word IR, DM, HR, TC, LR Ladder Symbols Operand Data Areas R : Result word IR, SR, AR, DM, HR, TC, LR BCMP(68) CD CB R @BCMP(68) CD CB R Limitations Each l ower limit word in the comparison block must be less than or equal to the upper [...]

175 Example The following example shows the comparisons made and the results provided for BCMP(68). Here, the comparison is made during each cycle when 00000 is ON. CD 001 Lower limits Upper limits R: HR 05 001 0210 HR 10 0000 HR 1 1 0100 HR 0500 0 HR 12 0101 HR 13 0200 HR 0501 0 HR 14 0201 HR 15 0300 HR 0502 1 HR 16 0301 HR 17 0400 HR 0503 0 HR 18[...]

176 Example The following example shows the comparisons made and the results provided for TCMP(85). Here, the comparison is made during each cycle when 00000 is ON. CD: 001 Upper limits R: HR 05 001 0210 HR 10 0100 HR 0500 0 HR 1 1 0200 HR 0501 0 HR 12 0210 HR 0502 1 HR 13 0400 HR 0503 0 HR 14 0500 HR 0504 0 HR 15 0600 HR 0505 0 HR 16 0210 HR 0506 [...]

177 Precautions Placing other instructions between ZCP(88) and the operation which accesses the EQ, LE, and GR flags may change the status of these flags. Be sure to ac- cess them before the desired status is changed. Flags ER: Indirectly addressed DM word is non-existent. (Content of ∗ DM word is not BCD, or the DM area boundary has been exceede[...]

178 Description When the execution condition i s OF F , ZCPL(––) is not executed. When the exe- cution condition is ON, ZCPL(––) compares the 8-digit value in CD, CD+1 to the range defined by lower limit LL+1,LL and upper limit UL+1,UL and outputs the result to the GR, EQ, and LE flags in the SR area. The resulting flag status is shown in t[...]

179 Flags ER: Indirectly addressed DM word is non-existent. (Content of ∗ DM word is not BCD, or the DM area boundary has been exceeded.) EQ : ON if Cp1 equals Cp2. LE : ON if Cp1 is less than Cp2. GR : ON if Cp1 is greater than Cp2. Comparison result Flag status p GR (SR 25505) EQ (SR 25506) LE (SR 25505) Cp1 < Cp2 0 0 1 Cp1 = Cp2 0 1 0 Cp1 &[...]

180 5-18 Data Conversion The conversion instructions convert word data that is in one format into another format and output the converted data to specified result word(s). Conversions are available to convert between binary (hexadecimal) and BCD, to 7-segment display data, to ASCII, and between multiplexed and non-multiplexed data. All o f these in[...]

181 5-18-2 DOUBLE BCD-T O-DOUBLE BINAR Y – BINL(58) S : First source word (BCD) IR, SR, AR, DM, HR, TC, LR R : First result word IR, SR, AR, DM, HR, LR Ladder Symbols Operand Data Areas BINL(58) S R @BINL(58) S R Description When the execution condition is OFF , BINL(58) is not executed. When the exe- cution condition is ON, BINL(58) converts an [...]

182 Signed Binary Data BCD(24) cannot be used to convert signed binary data directly to BCD. T o con- vert signed binary data, first determine whether the data is positive or negative. If it is positive, BCD(24) can be used to convert the data to BCD. If it is negative, use the 2’s COMPLEMENT – NEG(––) instruction to convert the data to un-[...]

183 5-18-5 HOURS-T O-SECONDS – SEC(65) S : Beginning source word (BCD) IR, SR, AR, DM, HR, TC, LR R : Beginning result word (BCD) IR, SR, AR, DM, HR, TC, LR Ladder Symbols Operand Data Areas --- : Not used. SEC(65) S R --- @SEC(65) S R --- Limitations S and S+1 must be within the same data area. R and R+1 must be within the same data area. S and [...]

184 5-18-6 SECONDS-T O-HOURS – HMS(66) S : Beginning source word (BCD) IR, SR, AR, DM, HR, TC, LR R : Beginning result word (BCD) IR, SR, AR, DM, HR, TC, LR Ladder Symbols Operand Data Areas --- : Not used. HMS(66) S R --- @HMS(66) S R --- Limitations S and S+1 must be within the same data area. R and R+1 must be within the same data area. S and [...]

185 5-18-7 4-T O-16 DECODER – MLPX(76) S : Source word IR, SR, AR, DM, HR, TC, LR C : Control word IR, SR, AR, DM, HR, TC, LR, # Ladder Symbols Operand Data Areas R : First result word IR, SR, AR, DM, HR, LR MLPX(76) S C R @MLPX(76) S C R Limitations When the leftmost digit of C is 0, the rightmost two digits of C must each be be- tween 0 and 3. [...]

186 Some example C values and the digit-to-word conversions that they produce are shown below . 0 1 2 3 R R + 1 R R + 1 R + 2 0 1 2 3 0 1 2 3 0 1 2 3 R R + 1 R + 2 R + 3 R R + 1 R + 2 R + 3 S C: 0031 C: 0023 C: 0030 C: 0010 S S S Th e following is an example of a one-digit decode operation from digit number 1 of S, i.e., here C would be 0001. Sourc[...]

187 The 4 possible C values and the conversions that they produce are shown be- low . (In S, 0 indicates the rightmost byte and 1 indicates the leftmost byte.) 0 1 R to R+15 R+16 to R+31 S C: 1000 0 1 R to R+15 R+16 to R+31 S C: 1010 0 1 R to R+15 R+16 to R+31 S C: 101 1 0 1 R to R+15 R+16 to R+31 S C: 1001 The following is an example of a one-byte[...]

188 The following program converts three digits of data from LR 20 to bit positions and turns ON the corresponding bits in three consecutive words starting with HR 10. 00000 MLPX(76) DM 0020 #0021 HR 10 Address Instruction Operands 00000 LD 00000 00001 MLPX(76) LR 20 # 0021 HR 10 S: LR 20 R: HR 10 R+1: HR 1 1 R+2: HR 12 DM 00 2 0 HR 1000 0 HR 1 100[...]

189 16-bit to 4-bit encoder DMPX(77) operates as a 16-bit to 4-bit encoder when the leftmost digit of C is 0. When the execution condition is OFF , DMPX(77) is not executed. When the exe- cution condition is ON, DMPX(77) determines the position of the highest ON bit in S, encodes it into single-digit hexadecimal value corresponding to the bit num- [...]

190 256-bit to 8-bit Encoder DMPX(77) operates as a 256-bit to 8-bit encoder when the leftmost digit of C is set to 1. When the execution condition is OFF , DMPX(77) is not executed. When the exe- cution condition is ON, DMPX(77) determines the position of the highest (left- most) ON bit in the group of 16 source words from S to S+15 or S+16 to S+3[...]

191 When 00000 is ON, the following diagram encodes IR words 010 and 01 1 to the first two digits of HR 20 and then encodes LR 10 and 1 1 to the last two digits of HR 20. Although the status of each source word bit is not shown, it is assumed that the bit with status 1 (ON) shown is the highest bit that is ON in the word. 00000 DMPX(77) 010 HR 20 #[...]

192 Any or all of the digits in S may be converted in sequence from the designated first digit. The first digit, the number of digits to be converted, and the half of D to receive the first 7-segment display code (rightmost or leftmost 8 bits) are desig- nated in Di. If multiple digits are designated, they will be placed in order starting from the [...]

193 Example The following example shows the data to produce an 8. The lower case letters show which bits correspond to which segments of the 7-segment display . The table underneath shows the original data and converted code for all hexadeci- mal digits. 2 0 2 1 2 2 2 3 2 0 2 1 2 2 2 3 2 0 2 1 2 2 2 3 2 0 2 1 2 2 2 3 0 1 0 0 0 0 0 1 0 1 1 1 1 0 1 1[...]

194 5-18-10 ASCII CONVERT – ASC(86) S : Source word IR, SR, AR, DM, HR, TC, LR Di : Digit designator IR, SR, AR, DM, HR, TC, LR, # Ladder Symbols Operand Data Areas D : First destination word IR, SR, AR, DM, HR, LR ASC(86) S Di D @ASC(86) S Di D Limitations Di must be within the values given below All destination words must be in the same data ar[...]

195 Some examples of Di values and the 4-bit binary to 8-bit ASCII conversions that they produce are shown below . 0 1 2 3 S Di: 001 1 D 0 1 2 3 Di: 0030 S 0 1 2 3 Di: 0130 S Di: 01 12 0 1 2 3 S 1st half 2nd half D 1st half 2nd half D+1 1st half 2nd half D 1st half 2nd half D+1 1st half 2nd half D 1st half 2nd half D+1 1st half 2nd half D+2 1st hal[...]

196 Limitations Di must be within the values given below . All source words must be in the same data area. Bytes in the source words must contain the ASCII code equivalent of hexadeci- mal values, i.e., 30 to 39 (0 to 9), 41 to 46 (A to F), or 61 to 66 (a to f). Description When the execution condition is OFF , HEX(––) is not executed. When the[...]

197 Some examples of Di values and the 8-bit ASCII to 4-bit hexadecimal conver- sions that they produce are shown below . 0 1 2 3 D Di: 001 1 S Di: 0030 Di: 0133 Di: 0023 1 st byte 2 nd byte S 1 st byte 2 nd byte S+1 1 st byte 2 nd byte 0 1 2 3 D S 1 st byte 2 nd byte S+1 1 st byte 2 nd byte 0 1 2 3 D S 1 st byte 2 nd byte S+1 1 st byte 2 nd byte 0[...]

198 Flags ER: Incorrect digit designator , or data area for destination exceeded. Indirectly addressed DM word is non-existent. (Content of ∗ DM word is not BCD, or the DM area boundary has been exceeded.) Example In the following example, the 2 nd byte of LR 10 and the 1 st byte of LR 1 1 are con- verted to hexadecimal values and those values ar[...]

199 The following table shows the functions and ranges of the parameter words: Parameter Function Range Comments P1 BCD point #1 (A Y ) 0000 to 9999 --- P1+1 Hex. point #1 (A X ) 0000 to FFFF Do not set P1+1=P1+3. P1+2 BCD point #2 (B Y ) 0000 to 9999 --- P1+3 Hex. point #2 (B X ) 0000 to FFFF Do not set P1+3=P1+1. The following diagram shows the s[...]

200 5-18-13 COLUMN TO LINE – LINE(63) S : First word of 16 word source set IR, SR, AR, DM, HR, TC, LR C: Column bit designator (BCD) IR, SR, AR, DM, HR, TC, LR, # Ladder Symbols Operand Data Areas D : Destination word IR, SR, AR, DM, HR, TC, LR LINE(63) S C D @LINE(63) S C D Limitations S and S+15 must be in the same data area. C must be between [...]

201 5-18-14 LINE TO COLUMN – COLM(64) S : Source word IR, SR, AR, DM, HR, TC, LR C: Column bit designator (BCD) IR, SR, AR, DM, HR, TC, LR, # Ladder Symbols Operand Data Areas D : First word of the destination set IR, AR, DM, HR, TC, LR COLM(64) S D C @COLM(64) S D C Limitations D and D+15 must be in the same data area. C must be between #0000 an[...]

202 5-18-15 2’S COMPLEMENT – NEG(––) S : Source word IR, SR, AR, DM, HR, TC, LR, # Ladder Symbols Operand Data Areas R : Result word IR, SR, AR, DM, HR, LR NEG(––) S R --- @NEG(––) S R --- Description Converts the four-digit hexadecimal content of the source word (S) to its 2’s complement and outputs the result to the result word [...]

203 5-18-16 DOUBLE 2’S COMPLEMENT – NEGL(––) S : First source word IR, SR, AR, DM, HR, TC, LR Ladder Symbols Operand Data Areas R : First result word IR, SR, AR, DM, HR, LR NEGL(––) S R --- @NEGL(––) S R --- Limitations S and S+1 must be in the same data area, as must R and R+1. Description Converts the eight-digit hexadecimal conte[...]

204 5-19 BCD Calculations The BCD calculation instructions – INC(38), DEC(39), ADD(30), ADDL(54), SUB(31), SUBL(55), MUL(32), MULL(56), DIV(33), DIVL(57), FDIV(79), and ROOT(72) – all perform arithmetic operations on BCD data. Fo r INC(38) and DEC(39) the source and result words are the same. That is, the content of the source word is overwritt[...]

205 5-19-3 SET CARR Y – STC(40) Ladder Symbols STC(40) @STC(40) When the execution condition is OFF , STC(40) is not executed.When the execu- tion condition is ON, STC(40) turns ON CY (SR 25504). Note Refer to Appendix C Error and Arithmetic Flag Operation for a table listing the instructions that affect CY . 5-19-4 CLEAR CARR Y – CLC(41) Ladde[...]

206 Example If 00002 is ON, the program represented by the following diagram clears CY with CLC(41), adds the content of LR 25 to a constant (6103), places the result in DM 0100, and then moves either all zeros or 0001 into DM 0101 depending on the status of C Y (25504). This ensures that any carry from the last digit is preserved in R+1 so that th[...]

207 Flags ER: Au and/or Ad is not BCD. Indirectly addressed DM word is non-existent. (Content of ∗ DM word is not BCD, or the DM area boundary has been exceeded.) CY : ON when there is a carry in the result. EQ : ON when the result is 0. Example When 00000 is ON, the following program adds two 12-digit numbers, the first contained in LR 20 throug[...]

! 208 Flags ER: Mi and/or Su is not BCD. Indirectly addressed DM word is non-existent. (Content of ∗ DM word is not BCD, or the DM area boundary has been exceeded.) CY : ON when the result is negative, i.e., when Mi is less than Su plus CY . EQ : ON when the result is 0. Caution Be sure to clear the carry flag with CLC(41) before executing SUB(31[...]

209 Note The actual SUB(31) operation involves subtracting Su and CY from 10,000 plus Mi. For positive results the leftmost digit is truncated. For negative results the 10s complement is obtained. The procedure for establishing the correct answer is given below . First Subtraction IR 010 1029 DM 0100 – 3452 CY – 0 HR 20 7577 (1029 + (10000 – [...]

210 Flags ER: Mi, M+1,Su, or Su+1 are not BCD. Indirectly addressed DM word is non-existent. (Content of ∗ DM word is not BCD, or the DM area boundary has been exceeded.) CY : ON when the result is negative, i.e., when Mi is less than Su. EQ : ON when the result is 0. The following example works much like that for single-word subtraction. In this[...]

21 1 5-19-9 BCD MUL TIPL Y – MUL(32) Md : Multiplicand (BCD) IR, SR, AR, DM, HR, TC, LR, # Mr : Multiplier (BCD) IR, SR, AR, DM, HR, TC, LR, # Ladder Symbols Operand Data Areas R : First result word IR, SR, AR, DM, HR LR MUL(32) Md Mr R @MUL(32) Md Mr R Limitations R and R+1 must be in the same data area. Description When the execution condition [...]

212 5-19-10 DOUBLE BCD MUL TIPL Y – MULL(56) Md : First multiplicand word (BCD) IR, SR, AR, DM, HR, TC, LR Mr : First multiplier word (BCD) IR, SR, AR, DM, HR, TC, LR Ladder Symbols Operand Data Areas R : First result word IR, SR, AR, DM, HR LR MULL(56) Md Mr R @MULL(56) Md Mr R Limitations Md and Md+1 must be in the same data area, as must Mr an[...]

213 Description When the execution condition is OFF , DIV(33) is not executed and the program moves to the next instruction. When the execution condition is ON, Dd is divided by Dr and the result is placed in R and R + 1: the quotient in R and the remainder in R + 1. R+1 R Dd Dr Quotient Remainder Flags ER: Dd or Dr is not in BCD. Indirectly addres[...]

214 Description When the execution condition is OFF , DIVL(57) is not executed. When the exe- cution condition is ON, DIVL(57) the eight-digit content of Dd and D+1 is divided by the content of Dr and Dr+1 and the result is placed in R to R+3: the quotient in R and R+1, the remainder in R+2 and R+3. R+1 R Quotient Remainder Dd+1 Dd Dr+1 Dr R+3 R+2 [...]

215 T o represent the floating point values, the rightmost seven digits are used for the mantissa and the leftmost digit is used for the exponent, as shown below . The mantissa is expressed as a value less than one, i.e., to seven decimal places. 15 14 13 12 1 1 10 09 08 07 06 05 04 03 02 01 00 First word exponent (0 to 7) sign of exponent 0: + 1: [...]

216 DM 0000 3 452 @MOV(21) #0000 HR 00 00000 @MOV(21) #0000 HR 02 @MOV(21) #4000 HR 01 @MOV(21) #4000 HR 03 @MOVD(83) DM 0000 #0021 HR 01 @MOVD(83) DM 0000 #0300 HR 00 @MOVD(83) DM 0001 #0021 HR 03 @MOVD(83) DM 0001 #0300 HR 02 @FDIV(79) HR 00 HR 02 DM 0002 HR 01 HR 00 0000 0000 HR 01 HR 00 4 0000000 4000 HR 01 HR 00 4 3450000 DM 0000 3 452 HR 01 H[...]

217 5-19-14 SQUARE ROOT – ROOT(72) Sq : First source word (BCD) IR, SR, AR, DM, HR, TC, LR R : Result word IR, SR, AR, DM, HR, LR, Ladder Symbols Operand Data Areas ROOT(72) Sq R @ROOT(72) Sq R Limitations Sq and Sq+1 must be in the same data area. Description When the execution condition is OFF , ROOT(72) is not executed. When the exe- cution co[...]

218 In this example, √ 6017 = 77.56, and 77.56 is rounded off to 78. 010 6 017 00000 @MOV(21) 010 DM 0101 @ROOT(72) DM 0100 DM 0102 @MOV(21) #0000 01 1 @MOVD(83) DM 0102 #0012 01 1 @MOVD(83) DM 0102 #0210 DM 0103 @CMP(20) DM 0103 #4900 @INC(38) 01 1 DM 0101 DM 0100 0 0000000 0000 DM 0101 DM 0100 6 0170000 DM 0102 7 756 IR 01 1 DM 0103 0 0775600 @[...]

219 5-20 Binary Calculations Binary calculation instructions — ADB(50), SBB(51), MLB(52), DVB(53), ADBL(––), SBBL(––), MBS(––), MBSL(––), DBS(––), and DBSL(––) — perform arithmetic operations on hexadecimal data. Four of these instructions (ADB(50), SBB(51), ADBL(––), and SBBL(––)) can ac t o n both normal and si[...]

220 The following example shows a four-digit addition with CY used to place either #0000 or #0001 into R+1 to ensure that any carry is preserved. CLC(41) 00000 ADB(50) 010 DM 0100 HR 10 MOV(21) #0000 HR 1 1 MOV(21) #0001 HR 1 1 TR 0 25504 25504 = R = R+1 = R+1 Address Instruction Operands 00000 LD 00000 00001 OUT TR 0 00002 CLC(41) 00003 ADB(50) 01[...]

221 In the case below , 25,321 +(–13,253) = 12,068 (62E9 + CC3B = 2F24). Neither OF nor UF are turned ON. Au: LR 20 62E 9 Ad: DM 0010 CC3 B + Ad: DM 0010 2F 24 Note Th e status of the CY flag can be ignored when adding signed binary data since it is relevant only in the addition of normal hexadecimal values. 5-20-2 BINAR Y SUBTRACT – SBB(51) Mi[...]

222 Example 1: Normal Data The following example shows a four-digit subtraction with CY used to place ei- ther #0000 or #0001 into R+1 to ensure that any carry is preserved. CLC(41) 00001 SBB(51) 001 LR20 HR 21 MOV(21) #0000 HR 22 MOV(21) #0001 HR 22 TR 1 25504 25504 = R = R+1 = R+1 Address Instruction Operands 00000 LD 00001 00001 OUT TR 1 00002 C[...]

223 In the following example, SBB(51) is used to subtract one 16-bit signed binary value from another . (The 2’s complement is used to express negative values). Th e ef fective range for 16-bit signed binary values is –32,768 (8000) to +32,767 (7FFF). The overflow flag (OF: SR 25404) is turned ON if the result exceeds +32,767 (7FFF) and the und[...]

224 5-20-3 BINAR Y MUL TIPL Y – MLB(52) Md : Multiplicand word (binary) IR, SR, AR, DM, HR, TC, LR, # Mr : Multiplier word (binary) IR, SR, AR, DM, HR, TC, LR, # Ladder Symbols Operand Data Areas R : First result word IR, SR, AR, DM, HR LR MLB(52) Md Mr R @MLB(52) Md Mr R Limitations R and R+1 must be in the same data area. Description When the e[...]

225 Precautions DVB(53) cannot be used to divide signed binary data. Use DBS(––) instead. Re- fer to 5-20-9 SIGNED BINAR Y DIVIDE – DBS(––) for details. Flags ER: Dr contains 0. Indirectly addressed DM word is non-existent. (Content of : DM word is not BCD, or the DM area boundary has been exceeded.) EQ : ON when the result is 0. Example [...]

226 ADBL(––) can also be used to add signed binary data. The underflow and over- flow flags (SR 25404 and SR 25405) indicate whether the result has exceeded th e lower or upper limits of the 32-bit signed binary data range. Refer to page 2 9 for details on signed binary data. Flags ER: Indirectly addressed DM word is non-existent. (Content of :[...]

227 In the case below , 1,799,100,099 + (–282,751,929) = 1,516,348,100 (6B3C167D + EF258C47 = 5A61A2C4). Neither OF nor UF are turned ON. Au + 1 : LR 21 Au : LR 20 Ad + 1 : DM 001 1 Ad : DM 0010 6 B 3 C 167 D EF 2 5 8C4 7 0 + R + 1 : DM 0021 R : DM 0020 A2C 4 5A6 1 0 CY (Cleared with CLC(41)) UF (SR 25405) 0 OF (SR 25404) Note Th e status of the [...]

228 Flags ER: Indirectly addressed DM word is non-existent. (Content of : DM word is not BCD, or the DM area boundary has been exceeded.) CY : ON when the result is negative, i.e., when Mi is less than Su plus CY . EQ : ON when the result is 0. OF : ON when the result exceeds +2,147,483,647 (7FFF FFFF). UF : ON when the result is below –2,147,483[...]

229 In the case below , 1,799,100,099 – (–282,751,929) = 2,081,851,958 (6B3C 167D – {EF25 8C47 – 1 0000 0000} = 7C16 8A36). Neither OF nor UF are turned ON. Au + 1 : 001 Au : 000 Ad + 1 : DM 0021 Ad : DM 0020 6 B 3 C 167 D EF 2 5 8C4 7 0 – R + 1 : LR 22 R : LR 21 8A 36 7C1 6 0 CY (Cleared with CLC(41)) UF (SR 25405) 0 OF (SR 25404) – No[...]

230 Example In the following example, MBS(––) is used to multiply the signed binary contents of IR 001 with the signed binary contents of DM 0020 and output the result to LR 21 and LR 22. MBS(––) 001 DM 0020 LR 21 Address Instruction Operands 00000 LD 00000 00001 MBS(––) 001 DM 0020 LR 21 00000 Md: IR 100 15B 1 Mr: DM 0020 FC 1 3 R: LR [...]

231 Example In the following example, MBSL(––) is used to multiply the signed binary con- tents of IR 101 and IR 100 with the signed binary contents of DM 0021 and DM 0020 and output the result to LR 24 through LR 21. MBSL(––) 100 DM 0020 LR 21 Address Instruction Operands 00000 LD 00000 00001 MBSL(––) 100 DM 0020 LR 21 00000 Md: IR 100[...]

232 Example In the following example, DBS(––) is used to divide the signed binary contents of IR 001 with the signed binary contents of DM 0020 and output the result to LR 21 and LR 22. DBS(––) 001 DM 0020 LR 21 Address Instruction Operands 00000 LD 00000 00001 DBS(––) 001 DM 0020 LR 21 00000 Dd: IR 001 DDDA Dr: DM 0020 001A R: LR 21 FE[...]

233 Example In the following example, DBSL(––) is used to divide the signed binary contents of IR 002 and IR 001 with the signed binary contents of DM 0021 and DM 0020 and output the result to LR 24 through LR 21. DBSL(––) 001 DM 0020 LR 21 Address Instruction Operands 00000 LD 00000 00001 DBSL(––) 001 DM 0020 LR 21 00000 Dd: IR 001 B1 [...]

! 234 If bit 15 of C is ON and more than one address contains the same maximum val- ue, the position of the lowest of the addresses will be output to D+1. Th e number of words within the range (N) is contained in the 3 rightmost digits of C, which must be BCD between 001 and 999. When bit 15 of C is OFF , data within the range is treated as normal [...]

! 235 If bit 14 of C is ON and more than one address contains the same minimum val- ue, the position of the lowest of the addresses will be output to D+1. Th e number of words within the range (N) is contained in the 3 rightmost digits of C, which must be BCD between 001 and 999. When bit 15 of C is OFF , data within the range is treated as unsigne[...]

236 O n the N th cycle, the previous value of S is written to last word in the range D+2 to D+N+1. The average value of the previous values stored in D+2 to D+N+1 is cal- culated and written to D, bit 15 of D+1 is turned ON, and the previous value point- er (the first 2 digits of D+1) is reset to zero. Each time that A VG(––) is executed, th e [...]

237 Example In the following example, the content of IR 040 is set to #0000 and then increm- ented by 1 each cycle. For the first two cycles, A VG(––) moves the content of IR 040 to DM 1002 and DM 1003. The contents of DM 1001 will also change (which can be used to confirm that the results of A VG(––) has changed). On the third and later cy[...]

238 Description When the execution condition is OFF , SUM(––) is not executed. When the ex- ecution condition is ON, SUM(––) adds either the contents of words R 1 to R 1 +N–1 o r the bytes in words R 1 to R 1 +N/2–1 and outputs that value to the desti- nation words (D and D+1). The data can be summed as binary or BCD and will be output [...]

239 Example In the following example, the BCD contents of the 8 words from DM 0000 to DM 0007 are added when IR 00001 is ON and the result is written to DM 0010 and DM 001 1. @SUM(––) DM 0000 #4008 00001 DM 0010 Address Instruction Operands 00000 LD 00001 00001 @SUM(––) # 4008 DM 0000 DM 0010 DM 0000 0001 DM 0001 0002 DM 0002 0003 DM 0003 0[...]

240 Examples Sine Function T h e following example demonstrates the use of the APR(69) sine function to cal- culate the sine of 30 ° . The sine function is specified when C is #0000. Input data, x Result data S: DM 0000 D: DM 0100 01 0 1 10 0 10 –1 10 –1 10 –2 10 –3 10 –4 0300 5000 APR(69) #0000 DM 0000 DM 0100 00000 Enter input data not[...]

Y 0 X 0 X 1 X 2 X 3 X 4 X m X Y Y m Y 4 Y 3 Y 1 Y 2 241 Enter the coordinates of the m+1 end-points, which define the m line segments, as shown in the following table. Enter all coordinates in BIN form. Always enter th e coordinates from the lowest X value (X 1 ) to the highest (X m ). X 0 is 0000, and does not have to be entered. Word Coordinate C[...]

! 242 In this case, the input data word, IR 010, contains #0014, and f(0014) = #0726 is output to R, IR 01 1. X Y $1F20 $0F00 $0726 $0402 (0,0) $0005 $0014 $001A $05F0 (x,y) 5-21-6 PID CONTROL – PID(––) S : Input word IR, SR, AR, DM, HR, LR, C : First parameter word IR, SR, DM, HR, LR Operand Data Areas D : Output word IR, SR, AR, DM, HR, LR [...]

243 Parameter Settings Item Contents Setting range Set value (SV) This is the target value of the process being controlled. Binary data (of the same number of bits as specified for the input range) Proportional band This is the parameter for P control expressing the proportional control range/total control range. 0001 to 9999 (4 digits BCD); (0.1% [...]

244 When overshooting is prevented with simple PID control, stabilization of distur- bances is slowed (1). If stabilization of disturbances is speeded up, on the other hand, overshooting occurs and response toward the target value is slowed (2). With feed-forward PID control, there is no overshooting, and response toward the target value and stabil[...]

245 integral time is too short, the correction will be too strong and will cause hunting to occur . Integral Operation PI Operation and Integral Time Deviation Operation amount Step response PI operation P operation T i: Integral time 0 0 0 0 Deviation Operation amount Step response I operation Derivative Operation (D) Proportional operation and in[...]

246 without hunting, integral operation to automatically correct any o f fset, and deriv- ative operation to speed up the response to disturbances. PID Operation Output Step Response PID Operation Output Lamp Response PID operation I operation P operation D operation Ramp response 0 0 Deviation Operation amount PID operation I operation P operation[...]

247 hunting will be reduced if the integral time is increased or the proportional band is enlarged. Control by measured PID (when loose hunting occurs) Enlarge I or P . SV • If the period is short and hunting occurs, it may be that the control system re- sponse is quick and the derivative operation is too strong. In that case, set the derivative [...]

248 Creating the Program Follow the procedure outlined below in creating the program. 1, 2, 3... 1. Set the target value (binary 0000 to 0FFF) in DM 0000. 2. Input the PV of the temperature sensing element (binary 000 to 0FFF) in bits 0 to 1 1 of word 101. 3. Output the operation amount of the heater to bits 0 to 1 1 of word 1 10 by means of the fi[...]

249 Note When using PID(––) or SCL(––), make the data settings in advance with a Pe- ripheral Device such as the Programming Console or LSS. T arget value HR Proportional band Integral time/sampling period Derivative time/sampling period Sampling period Forward/reverse designation/ PID parameters I/O range Heater (DM0000) 0080 0200 0100 000[...]

250 5-22-2 LOGICAL AND – ANDW(34) I1 : Input 1 IR, SR, AR, DM, HR, TC, LR, # I2 : Input 2 IR, SR, AR, DM, HR, TC, LR, # Ladder Symbols Operand Data Areas R : Result word IR, SR, AR, DM, HR, LR ANDW(34) I1 I2 R @ANDW(34) I1 I2 R Description When the execution condition is OFF , ANDW(34) is not executed. When the ex- ecution condition is ON, ANDW(3[...]

251 5-22-3 LOGICAL OR – ORW(35) I1 : Input 1 IR, SR, AR, DM, HR, TC, LR, # I2 : Input 2 IR, SR, AR, DM, HR, TC, LR, # Ladder Symbols Operand Data Areas R : Result word IR, SR, AR, DM, HR, LR ORW(35) I1 I2 R @ORW(35) I1 I2 R Description When the execution condition is OFF , ORW(35) is not executed. When the ex- ecution condition is ON, ORW(35) log[...]

252 5-22-4 EXCLUSIVE OR – XORW(36) I1 : Input 1 IR, SR, AR, DM, HR, TC, LR, # I2 : Input 2 IR, SR, AR, DM, HR, TC, LR, # Ladder Symbols Operand Data Areas R : Result word IR, SR, AR, DM, HR, LR XORW(36) I1 I2 R @XORW(36) I1 I2 R Description When the execution condition is OFF , XORW(36) is not executed. When the e x - ecution condition is ON, XOR[...]

253 5-22-5 EXCLUSIVE NOR – XNRW(37) I1 : Input 1 IR, SR, AR, DM, HR, TC, LR, # I2 : Input 2 IR, SR, AR, DM, HR, TC, LR, # Ladder Symbols Operand Data Areas R : Result word IR, SR, AR, DM, HR, LR XNRW(37) I1 I2 R @XNRW(37) I1 I2 R Description When the execution condition is OFF , XNRW(37) is not executed. When the ex- ecution condition is ON, XNR [...]

254 INT(89) is used to control the interrupt signals received from the Interrupt Input Unit, and also to control the scheduling of the scheduled interrupt. INT(89) pro- vides such functions as masking of interrupts (so that they are recorded but ig- nored) and clearing of interrupts. Refer to 5-23-2 Interrupts for more details on interrupts. MCRO(9[...]

255 The following setting is used for normal interrupt mode. DM 6620 0000 In normal interrupt mode, the following processing will be completed once started even if an interrupt occurs The interrupt will be processed as soon as the current process is completed. • Host Link servicing • Remote I/O servicing • Special I/O Unit servicing • Indiv[...]

256 Th e PC Setup for the C200HS contains settings in DM 6620 that disable refresh- ing in the normal cycle for specific Special I/O Units. This settings are as shown below . Interrupt mode (1 = high-speed) Bit 15 00 1 0 0 ********** Unit #0 Unit #1 . . . Unit #9 DM6620 12 Note Disabling special I/O refreshing in the normal cycle to refresh special[...]

257 If you must handle the same data both in the main program and in an interrupt subroutine, use programming such as that shown below to be sure that data concurrence is preserved, i.e., mask interrupts while read/writing data that is also handled in an interrupt subroutine. (@)INT(89) 100 000 000 (@)INT(89) 200 000 000 Reading and writing common [...]

258 Description A subroutine can be executed by placing SBS(91) in the main program at the point where the subroutine is desired. The subroutine number used in SBS(91) indicates the desired subroutine. When SBS(91) is executed (i.e., when the ex- ecution condition for it is ON), the instructions between the SBN(92) with the same subroutine number a[...]

! 259 The following diagram illustrates program execution flow for various execution conditions for two SBS(91). SBS(91) 00 SBS(91) 01 SBN(92) 00 RET(93) SBN(92) 01 RET(93) END(01) Main program Subroutines A B C D E A A A A B B B B C C C C D D E E OFF execution conditions for subroutines 00 and 01 ON execution condition for subroutine 00 only ON ex[...]

260 Al l subroutines must be programmed at the end of the main program. When one or more subroutines have been programmed, the main program will be ex- ecuted up to the first SBN(92) before returning to address 00000 for the next cycle. Subroutines will not be executed unless called by SBS(91). END(01) must be placed at the end of the last subrouti[...]

261 In the following example, the contents of DM 0010 through DM 0013 are copied to SR 290 through SR 293, the contents of DM 0020 through DM 0023 are co- pied to SR 294 through SR 297, and subroutine 10 is called and executed. When the subroutine is completed, the contents of SR 294 through SR 297 are copied back to DM 0020 to DM 0023. MCRO(99) 10[...]

262 Example The following examples shows the use of four MCRO(99) instructions that ac- cess the same subroutine. The program section on the left shows the same pro- gram without the use of MCRO(99). 10000 00000 10001 10000 10001 00001 00002 10500 00200 10501 10500 10501 00201 00202 12000 00500 12001 12000 12001 00501 00502 15000 01000 15001 15000 [...]

263 Description INT(89) is used to control interrupts and performs one of 8 functions depending on the values of C and N. As shown in the following tables, three of the functions act on input interrupts, three act on the scheduled interrupt, and the other two mask or unmask all interrupts. Interrupt V alue of C INT(89) Function Comments Input (N 00[...]

264 Flags ER: Indirectly addressed DM word is non-existent. (Content of : DM word is not BCD, or the DM area boundary has been exceeded.) C, and/or N are not within specified values. Example 1: Input Interrupt This example shows how to unmask a particular interrupt input. Input interrupt subroutines will be executed when the CPU receives the corres[...]

265 Th e scheduled interrupt is disabled at the start of operation (the scheduled inter- rupt interval is 0), so the time to the first interrupt and scheduled interrupt interval must be set using INT(89) with N=004 and C=001/000. In the following diagram, the subroutine would be executed every 20 ms if the scheduled interrupt time unit is set to 10[...]

266 5-24 Step Instructions Th e step instructions STEP(08) and SNXT(09) are used in conjunction to set up breakpoints between sections in a large program so that the sections can be ex- ecuted as units and reset upon completion. A section of program will usually be defined to correspond to an actual process in the application. (Refer to the appli- [...]

267 Execution of a step is completed either by execution of the next SNXT(09) or by turning OFF the control bit for the step (see example 3 below). When the step is completed, all of the IR and HR bits in the step are turned OFF . All timers in the step except TTIM(––) are reset to their SVs. TTIM(––), counters, shift registers, bits set or[...]

268 Flags 25407: Step Start Flag; turns ON for one cycle when STEP(08) is executed and can be used to reset counters in steps as shown below if necessary . SNXT(09) 01000 CP R CNT 01 #0003 00000 00100 25407 STEP(08) 01000 1 cycle 25407 01000 Start Address Instruction Operands Address Instruction Operands 00000 LD 00000 00001 SNXT(09) 01000 00002 ST[...]

269 The following diagram demonstrates the flow of processing and the switches that are used for execution control. Process A Process B Process C Loading Part Installation Inspection/discharge SW1 SW2 SW3 SW4 Step Instructions Section 5-24[...]

270 The program for this process, shown below , utilizes the most basic type of step programming: each step is completed by a unique SNXT(09) that starts the next step. Each step starts when the switch that indicates the previous step has been completed turns ON. SNXT(09) 12800 00001 (SW1) STEP(08) 12800 SNXT(09) 12801 STEP(08) 12801 SNXT(09) 12802[...]

271 The following process requires that a product is processed in one of two ways, depending on its weight, before it is printed. The printing process is the same regardless of which of the first processes is used. V arious sensors are posi- tioned to signal when processes are to start and end. SW A1 SW A2 SW B1 SW B2 Process C Weight scale Process[...]

272 The program for this process, shown below , starts with two SNXT(09) instruc- tions that start processes A and B. Because of the way 00001 (SW A1) and 00002 (SB B1) are programmed, only one of these will be executed to start either process A or process B. Both of the steps for these processes end with a SNXT(09) that starts the step for process[...]

273 The following process requires that two parts of a product pass simultaneously through two processes each before they are joined together in a fifth process. V arious sensors are positioned to signal when processes are to start and end. Process C SW1 SW2 Process A SW3 SW4 Process D Process B Process E SW6 SW5 SW7 The following diagram demonstra[...]

274 STEP(08) LR 0000 SNXT(09) LR 0001 STEP(08) LR 0001 STEP(08) LR 0004 SNXT(09) LR 0005 STEP(08) Process A Process B Process C 00002 (SW3) 00005 (SW7) Process A started. Process A reset. Process B started. Process E reset. 00001 (SW1 and SW2)) SNXT(09) LR 0000 SNXT(09) LR 0002 Process C started. 01 101 SNXT(09) LR 0004 00004 (SW5 and SW6) LR 0003 [...]

275 Address Instruction Operands Address Instruction Operands 00000 LD 00001 00001 SNXT(09) LR 0000 00002 SNXT(09) LR 0002 00003 STEP(08) LR 0000 Process A 00100 LD 00002 00101 SNXT(09) LR 0001 00102 STEP(08) LR 0001 Process B 00100 LD 01 101 00101 OUT LR 0003 00101 AND 00004 00101 SNXT(09) LR 0004 00102 STEP(08) LR 0002 Process C 00200 LD 00003 00[...]

276 F AL(06) produces a non-fatal error and F AL(07) produces a fatal error . When F AL(06) is executed with an ON execution condition, the ALARM/ERROR indi- cator on the front of the CPU will flash, but PC operation will continue. When F ALS(07) is executed with an ON execution condition, the ALARM/ERROR indi- cator will light and PC operation wil[...]

277 5-25-3 TRACE MEMOR Y SAMPLING – TRSM(45) Data tracing can be used to facilitate debugging programs. T o set up and use data tracing it is necessary to have a host computer running LSS; no data tracing is possible from a Programming Console. Data tracing is described in detail in the LSS Operation Manual . This section shows the ladder symbol [...]

278 The sampled data is written to trace memory , jumping to the beginning of the memory area once the end has been reached and continuing up to the start marker . This might mean that previously recorded data (i.e., data from this sam- ple that falls before the start marker) is overwritten (this is especially true if the delay is positive). The ne[...]

MSG ABCDEFGHIJKLMNOP 279 In handling indirectly addressed messages (i.e. : DM), those with the lowest DM address values have higher priority . Clearing Messages T o clear a message, execute F AL(06) 00 or clear it via a Programming Console using the procedure in 4-6-5 Clearing Error Messages . If the message data changes while the message is being [...]

280 Description LMSG(47) is used to output a 32-character message to a Programming Con- sole. The message to be output must be in ASCII beginning in word S and end- in g i n S+15, unless a shorter message is desired. A shorter message can be pro- duced by placing a null character (00) into the string; no characters from the null character on will b[...]

281 Example In the following example, TERM(48) is used to switch the Programming Console to TERMINAL mode when 00000 is ON. Be sure that pin 6 of the CPU’s DIP switch is OFF . TERM(48) 000 000 000 00000 Address Instruction Operands 00000 LD 00000 00001 TERM(48) 000 000 000 5-25-7 W A TCHDOG TIMER REFRESH – WDT(94) T : W atchdog timer value # (0[...]

282 T o refresh I/O words allocated to Special I/O Units (IR 100 to IR 199), indicate the unit numbers of the Units by designating IR 040 to IR 049 (see note). IR 040 to IR 049 correspond to Special I/O Units 0 to 9. For example, set St to IR 043 and E to IR 045 to refresh the I/O words allocated to Special I/O Units 3, 4, and 5. The I/O words allo[...]

283 Refer to 6-1 Cycle Time for a table showing I/O refresh times for Group-2 High-density I/O Units. Flags ER : St or E is not BCD between #0000 and #0009. St is greater than E. 5-25-10 BIT COUNTER – BCNT(67) N : Number of words (BCD) IR, SR, AR, DM, HR, TC, LR, # SB : Source beginning word IR, SR, AR, DM, HR, TC, LR Operand Data Areas D : Desti[...]

284 The function of bits in C are shown in the following diagram and explained in more detail below . 15 14 13 12 1 1 00 Number of items in range (N, BCD) 001 to 999 words or bytes First byte (when bit 13 is ON) 1 (ON): Rightmost 0 (OFF): Leftmost Calculation units 1 (ON): Bytes 0 (OFF): Words C: Not used. Set to zero. Number of Items in Range Th e[...]

285 Example When IR 00000 is ON in the following example, the frame checksum (0008) is calculated for the 8 words from DM 0000 to DM 0007 and the ASCII equivalent (30 30 30 38) is written to DM 001 1 and DM 0010. @FCS(––) DM 0000 #0008 00000 DM 0010 Address Instruction Operands 00000 LD 00000 00001 @FCS(––) # 0008 DM 0000 DM 0010 DM 0000 00[...]

286 When the execution condition is OFF , FPD(––) is not executed. When the exe- cution condition is ON, FPD(––) monitors the time until the logic diagnostics condition goes ON, turning ON the diagnostic output. If this time exceeds T , the following will occur: 1, 2, 3... 1. A n F AL(06) error is generated with the F AL number specified in[...]

287 D+1 contains the bit address code of the input condition, as shown below . The word addresses, bit numbers, and TC numbers are in binary . Data A D+1 bit status aa Area 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 IR, SR (see 1 0 0 0 Word address Bit number ( see note c) 1 0 1 0 Word address Bit number HR 1 0 0 1 1 Word address Bit number LR[...]

288 Example In the following example, the FPD(––) is set to display the bit address and mes- sage (“ABC”) when a monitoring time of 123.4 s is exceeded. MOV(21) HR 15 #4142 SR 25315 Address Instruction Operands 00000 LD 25315 00001 MOV(21) # 4142 HR 15 00002 LD 25315 00003 MOV(21) # 430D HR 16 00004 LD LR 0000 00005 FPD(––) # 8010 # 123[...]

289 5-25-13 DA T A SEARCH – SRCH(––) R 1 : First word in range IR, SR, AR, DM, HR, TC, LR N : Number of words IR, SR, AR, DM, HR, TC, LR, # Ladder Symbols Operand Data Areas @SRCH(––) N R 1 C C : Comparison data, result word IR, SR, AR, DM, HR, LR SRCH(––) N R 1 C Limitations N must be BCD between 0001 to 6656. R 1 and R 1 +N–1 must[...]

290 Example In the following example, the 10 word range from DM 0010 to DM 0019 is searched for addresses that contain the same data as DM 0000 (#FFFF). Since DM 0012 contains the same data, the EQ Flag (SR 25506) is turned ON and #0012 is written to DM 0001. @SRCH(––) DM 0010 #0010 00001 DM 0000 Address Instruction Operands 00000 LD 00001 0000[...]

291 Example In the following example, the 100 word range from DM 7000 through DM 7099 is copied to DM 0010 through DM 0109 when IR 00001 is ON. @XDMR(––) #7000 #0100 00001 DM 0010 Address Instruction Operands 00000 LD 00001 00001 @XDMR(––) # 0100 # 7000 DM 0010 DM 7000 DM 9999 DM 7000 to DM 7099 DM 0000 DM 6143 DM 0010 to DM 0109 5-26 Netwo[...]

292 The status of bit 15 of C+1 determines whether the instruction is for a SYSMAC NET Link System or a SYSMAC LINK System. Control Data SYSMAC NET Link Systems T he destination port number is always set to 0. Set the destination node number to 0 to send the data to all nodes. Set the network number to 0 to send data to a node on the same Subsystem[...]

293 Flags ER : T he specified node number is greater than 126 in a SYSMAC NET Link System or greater than 62 in a SYSMAC LINK System. The sent data overruns the data area boundaries. Indirectly addressed DM word is non-existent. (Content of : DM word is not BCD, or the DM area boundary has been exceeded.) There is no SYSMAC NET Link/SYSMAC LINK Uni[...]

294 SYSMAC LINK Systems Refer to the SYSMAC LINK System Manual for details. Word Bits 00 to 07 Bits 08 to 15 C Number of words (0 to 256 in 4-digit hexadecimal, i.e., 0000 hex to 0100 hex ) C+1 Response time limit (0.1 and 25.4 seconds in 2-digit hexadecimal without decimal point, i.e., 00 hex to FF hex ) Note: The response time will be 2 seconds i[...]

295 5-26-3 About Network Communications SEND(90) and RECV(98) are based on command/response processing. That is, the transmission is not complete until the sending node receives and ac- knowledges a response from the destination node. Note that the SEND(90)/RECV(98) Enable Flag is not turned ON until the first END(01) after the transmission is comp[...]

296 S R KEEP(1 1) 12802 DIFU(13) 12801 @MOV(21) #000A DM 0000 12800 00000 25204 12802 12801 @MOV(21) #0000 DM 0001 @MOV(21) #0003 DM 0002 XFER(70) #0010 000 DM 0010 @SEND(90) DM 0010 DM 0020 DM 0000 00200 XFER(70) #0016 000 DM 0030 00001 25204 12800 12803 @MOV(21) #0010 DM 0003 12802 @MOV(21) #0000 DM 0004 @MOV(21) #007E DM 0005 @RECV(98) HR 10 LR [...]

297 Address Instruction Operands Address Instruction Operands 00000 LD 00000 00001 AND 25204 00002 AND NOT 12802 00003 LD 12801 00004 KEEP(1 1) 12800 00005 LD 12800 00006 @MOV(21) # 000A DM 0000 00007 @MOV(21) # 0000 DM 0001 00008 @MOV(21) # 0003 DM 00002 00009 @XFER(70) # 0010 000 DM 0002 00010 @SEND(90) DM 0010 DM 0020 DM 0000 0001 1 LD 12800 000[...]

! 298 Note RXD(––) is required to receive data via the peripheral port or RS-232C port only . Transmission sent from a host computer to a Host Link Unit are processed auto- matically and do not need to be programmed. Caution The PC will be incapable of receiving more data once 256 bytes have been received if received data is not read using RXD([...]

299 5-27-2 TRANSMIT – TXD(––) S: First source word IR, SR, AR, DM, HR, TC, LR C : Control word IR, SR, AR, DM, HR, TC, LR, # Ladder Symbols Operand Data Areas N: Number of bytes IR, SR, AR, DM, HR, TC, LR, # TXD(––) S C N @TXD(––) S C N Limitations S and S+(N ÷ 2)–1 must be in the same data area. N must be BCD from #0000 to #0256. [...]

300 The following diagram shows the format for host link command (TXD) sent from the C200HS. The C200HS automatically attaches the prefixes and suffixes, such as the node number , header , and FCS. @ X X X X X X ......... X X X ∗ CR Header code (EX) Data (122 ASCII characters max.) FCS Node number T erminator RS-232C Mode N must be BCD from #0000[...]

301 5-28 Advanced I/O Instructions Advanced I/O instructions enable control, with a single instruction, of previously complex operations involving external I/O devices (digital switches, 7-segment displays, etc.). There are five advanced I/O instructions, as shown in the following table. All of these are expansion instructions and must be assigned [...]

302 If there are 8 digits of source data, they are placed in S and S+1, with the most significant digits placed in S+1. If there are 4 digits of source data, they are placed in S. 7SEG(––) displays the 4 or 8-digit data in 12 cycles, and then starts over and continues displaying the data. The 7-segment display must provide four data lines and o[...]

303 2. The 7-segment display may require either positive or negative logic, de- pending on the model. 3. T he 7-segment display must have 4 data signal lines and 1 latch signal line for each digit. Using the Instruction If the first word holding the data to be displayed is specified at S, and the output word is specified at O, and the SV taken from[...]

304 5-28-2 DIGIT AL SWITCH INPUT – DSW(––) IW: Input word IR, SR, AR, HR, LR Ladder Symbols Operand Data Areas DSW(––) IW OW R R: First result word IR, SR, AR, DM, HR, LR OW: Output word IR, SR, AR, HR, LR Overview DSW(––) is used to read the value set on a digital switch connected to I/O Units. When the execution condition is OFF , D[...]

305 Hardware With this instruction, 8-digit BCD set values are read from a digital switch. DSW(––) utilizes 5 output bits and 8 input bits. Connect the digital switch and the Input and Output Units as shown in the diagram below . Output point 5 will be turned ON when one round of data is read, but there is no need to connect output point 5 unle[...]

306 The following example illustrates connections for an A7B Thumbwheel Switch. 1 3 5 7 9 11 13 15 COM 0 2 4 6 8 10 12 14 COM ID212 Input Unit Switch no. 8 1 3 5 7 9 11 13 15 COM 0 2 4 6 8 10 12 14 DC OD212 1 2 4 8 76 5 4 3 2 1 C Output Unit A7B Thumbwheel Switch Note The data read signal is not required in the example. Th e inputs must be connecte[...]

307 Using the Instruction If the input word for connecting the digital switch is specified at for word A, and the output word is specified for word B, then operation will proceed as shown below when the program is executed. 00 01 02 03 04 05 Wd 0 10 0 10 1 10 2 10 3 D+1 D Four digits: 00 to 03 Eight digits: 00 to 03, 04 to 07 0 1 2 3 4 5 6 7 8 9 10[...]

308 5-28-3 HEXADECIMAL KEY INPUT – HKY(––) OW : Control signal output word IR, SR, AR, HR, LR IW : Input word IR, SR, AR, HR, LR Ladder Symbols Operand Data Areas HKY(––) IW OW D D : First register word IR, SR, AR, DM, HR, LR Limitations D and D+2 must be in the same data area. Overview When the execution condition is OFF , HKY(––) is[...]

309 Hardware This instruction inputs 8 digits in hexadecimal from a hexadecimal keyboard. I t utilizes 5 output bits and 4 input bits. Prepare the hexadecimal keyboard, and connect the 0 to F numeric key switches, as shown below , to input points 0 through 3 and output points 0 through 3. Output point 4 will be turned ON while any key is being pres[...]

310 Using the Instruction If the input word for connecting the hexadecimal keyboard is specified at word A, an d the output word is specified at word B, then operation will proceed as shown below when the program is executed. 0000 123 456 7 8 0000 D+1 D 0000 D+1 000F D 91 0 1 1 1 2 0000 D+1 00F9 D IW 16-key 0 to 9 to D+2 00 to 09 to 15 OW 04 F 00 0[...]

31 1 5-28-4 TEN KEY INPUT – TKY(––) D 1 : First register word IR, SR, AR, DM, HR, LR IW : Input word IR, SR, AR, HR, LR Ladder Symbols Operand Data Areas TKY(––) IW D 1 D 2 D 2 : Key input word IR, SR, AR, DM, HR, LR Limitations D 1 and D 1 +1 must be in the same data area. Overview When the execution condition is OFF , TKY(––) is not[...]

312 Using the Instruction If the input word for connecting the 10-key keypad is specified for IW , then opera- tion will proceed as shown below when the program is executed. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 2 0 0 0 0 1 0 2 9 D 1 +1 D 1 (1) (2) (3) (4) (1) (2) (3) (4) 00 01 02 09 00 01 02 09 10 to IW to Input from 10-key[...]

313 5-28-5 MA TRIX INPUT – MTR(––) OW : Output word IR, SR, AR, HR, LR IW : Input word IR, SR, AR, HR, LR Ladder Symbols Operand Data Areas MTR(––) IW OW D D : First destination word IR, SR, AR, DM, HR, LR Limitations D and D+3 must be in the same data area. Overview When the execution condition is OFF , MTR(––) is not executed. When [...]

314 Hardware This instruction inputs up to 64 signals from an 8 x 8 matrix using 8 input points an d 8 output points. Any 8 x 8 matrix can be used. The inputs must be connected through a D C Input Unit with 8 or more points and the outputs must be connected through a T ransistor Output Unit with 8 or more points. The basic wiring and tim- ing diagr[...]

315 Example The following examples shows programming MTR(––) in a scheduled subrou- tine, where IORF(97) is programmed to ensure that the I/O words used by MTR(––) are refreshed each time MTR(––) is executed. INT(89) 001 004 # 0002 INT(89) 000 004 # 0002 SBN(92) 99 MTR(––) S D1 D2 IORF(97) D1 D2 RET(93) END(01) Flags ER: Indirectly [...]

317 SECTION 6 Pr ogram Execution T iming The timing of various operations must be considered both when writing and debugging a program. The time required to ex- ecute the program and perform other CPU operations is important, as is the timing of each signal coming into and leaving the PC in order to achieve the desired control action at the right t[...]

318 6-1 Cycle Time T o aid in PC operation, the average, maximum, and minimum cycle times can be displayed on the Programming Console or any other Programming Device and the maximum cycle time and current cycle time values are held in AR 26 and AR 27. Understanding the operations that occur during the cycle and the ele- ments that af fect cycle tim[...]

319 Flowchart of CPU Operation YES NO NO Power application Clears IR area and resets all timers Checks I/O Unit connections Resets watchdog timer Checks hardware and Program Memory Check OK? Services Host Link ALARM/ERROR Sets error flags and turns ON or flashes indicator Executes user program Resets watchdog timer Refreshes input bits and output s[...]

320 The first three operations immediately after power application are performed only once each time the PC is turned on. The rest of the operations are per- formed in cyclic fashion. The cycle time is the time that is required for the CPU to complete one of these cycles. This cycle includes basically eight types of opera- tion. 1, 2, 3... 1. Overs[...]

321 I/O pts to refresh Time required (ms) 512 7.4 256 4.1 128 2.7 64 1.7 Unit Time required per Unit C200H-ID501/215 0.6 ms C200H-OD501/215 0.6 ms when set for 32 I/O pts. C200H-MD501/215 1.6 ms when set for dynamic I/O C200H-CT001-V1/CT002 2.6 ms C200H-NC1 1 1/NC1 12 2.5 ms C200H-NC21 1 5.0 ms C200H-AD001 1.3 ms C200H-DA001 1.0 ms C200H-TS001/TS10[...]

! 322 Even i f the cycle time does not exceed the set value of the watchdog timer , a long cycle time can adversely affect the accuracy of system operations as shown in the following table. Cycle time (ms) Possible adverse affects 10 or greater TIMH(15) inaccurate when TC 016 through TC 51 1 are used. (Accuracy when using TC 000 through TC 0015 not[...]

323 Calculations The equation for the cycle time from above is as follows: Cycle time = Overseeing time + Program execution time + I/O refresh time + Peripheral device servicing time Process Calculation With Peripheral Device Without Peripheral Device Overseeing Fixed 0.7 ms 0.7 ms Program execution 0.47 µ s/instruction × 5,000 instructions 2.35 [...]

324 Calculations The equation for the cycle time is as follows: Cycle time = Overseeing time + Program execution time + I/O refreshing time + Host Link Unit servicing time + Peripheral device servicing time Process Calculation With Peripheral Device Without Peripheral Device Overseeing Fixed 0.7 ms 0.7 ms Program execution 0.47 µ s/instruction × [...]

325 Instruction OFF execution time ( µ s) ON execution time ( µ s) Conditions AND LD --- 0.375 0.375 OR LD --- 0.375 0.375 OUT For IR and SR 23600 to SR 25515 0.563 0.563 For SR 25600 to SR 51 1 15 0.938 0.563 OUT NOT For IR and SR 23600 to SR 25515 0.563 0.563 For SR 25600 to SR 51 1 15 0.938 0.563 TIM Constant for SV 1.125 R: 1.125 IL: 1.125 JM[...]

326 Instruction OFF execution time ( µ s) ON execution time ( µ s) Conditions SFT(10) With 1-word shift register 47.06 R: 35.80 IL: 15.70 JMP: 15.60 With 100-word shift register 340.00 R: 256.80 IL: 15.72 JMP: 15.68 With 250-word shift register 800.00 R: 590.80 IL: 15.60 JMP: 15.66 KEEP(1 1) For IR and SR 23600 to SR 25515 0.563 0.563 For SR 2560[...]

327 Instruction OFF execution time ( µ s) ON execution time ( µ s) Conditions BIN(23) When converting a word to a word 40.40 1.125 When converting : DM to : DM 74.80 BCD(24) When converting a word to a word 38.40 1.125 When converting : DM to : DM 72.80 ASL(25) When shifting a word 21.20 0.75 When shifting : DM 38.20 ASR(26) When shifting a word [...]

328 Instruction OFF execution time ( µ s) ON execution time ( µ s) Conditions ADB(50) Constant + word → word 43.20 1.5 Word + word → word 45.80 : DM + : DM → : DM 97.40 SBB(51) Constant – word → word 43.20 1.5 Word – word → word 45.80 : DM – : DM → : DM 97.40 MLB(52) Constant x word → word 36.00 1.5 Word x word → word 38.50 [...]

329 Instruction OFF execution time ( µ s) ON execution time ( µ s) Conditions DMPX(77) When encoding a word to a word 48.90 1.5 When encoding : DM to : DM 185.90 SDEC(78) When decoding a word to a word 53.20 1.5 When decoding 2 digits : DM to : DM 1 13.60 When decoding 4 digits : DM to : DM 126.00 FDIV(79) Word ÷ word → word (equals 0) 1 18.20[...]

330 Instruction OFF execution time ( µ s) ON execution time ( µ s) Conditions TERM(––) Default code: (48) --- 16.40 1.5 CMPL(––) When comparing words to words 51.40 1.5 Default code: (60) When comparing : DM to : DM 85.90 MPRF(––) 1 Unit 33.70 1.5 Default code: (61) 10 Units 74.20 XFRB(––) Sending 1 bit from word to word 45.50 1.5[...]

331 Instruction OFF execution time ( µ s) ON execution time ( µ s) Conditions : DM-designated 4 digits 66.60 to 72.80 Word-designated 8 digits 56.70 to 64.80 : DM-designated 8 digits 74.20 to 82.30 FPD(––) Word designation, code output 121.00 to 147.50 17.30 : DM designation, message output 170.50 to 228.80 SRCH(––) Constant for SV 78.50 [...]

332 Instruction OFF execution time ( µ s) ON execution time ( µ s) Conditions NEG(––) When converting a constant to a word 34.90 1.5 When converting a word to a word 37.50 When converting : DM to : DM 72.10 NEGL(––) When converting a word to a word 47.00 1.5 When converting : DM to : DM 81.90 ZCPL(––) When comparing two words 71.90 1.[...]

333 6-4 I/O Response T ime The I/O response time is the time it takes for the PC to output a control signal after it has received an input signal. The time it takes to respond depends on the cycle time and when the CPU receives the input signal relative to the input re- fresh period. The minimum and maximum I/O response time calculations described [...]

334 The PC takes longest to respond when it receives the input signal just after the I/ O refresh phase of the cycle. In this case the CPU does not recognize the input signal until the end of the next cycle. The maximum response time is thus one cycle longer than the minimum I/O response time, except that the I/O refresh time would not need to be a[...]

! 335 In looking at the following timing charts, it is important to remember the se- quence in which processing occurs during the PC scan, particular that inputs will not produce programmed actions until the program has been executed. When calculating the response times involving inputs and outputs from another CP U connected by an I/O Link Unit, t[...]

336 Example Calculations Calculations would be as shown below for an input ON delay of 1.5 ms, an out- put ON delay of 15 ms, and a cycle time of 20 ms. Minimum I/O Response Time T ime = 1.5 ms + (20 ms x 3) + 15 ms = 76.5 ms Maximum I/O Response Time T ime = 1.5 ms + (20 ms x 4) + 15 ms = 96.5 ms Note 1. T he cycle time may be less than or equal t[...]

! 337 6-4-4 PC Link Systems The processing that determines and the methods for calculating maximum and minimum response times from input to output are provided in this subsection. Th e following System and I/O program steps will be used in all examples below . This System contains eight PC Link Units. In looking at the following timing charts, it i[...]

338 Inserting the following values into this equation produces a minimum I/O re- sponse time of 149.3 ms. Input ON delay: 1.5 ms Output ON delay: 15 ms Cycle time for PC of Unit 0: 20 ms Cycle time for PC of Unit 7: 50 ms The following diagram illustrates the data flow that will produce the maximum response time. Delays occur because signals or dat[...]

339 Induction sequence processing: 15 ms x (8 PCs – 8 PCs) = 0 ms I/O refresh bits for Unit 0 256 I/O refresh bits for Unit 7 256 Reducing Response Time IORF(97) can be used in programming to shorten the I/O response time greater than is possible by setting a high number of refresh bits. (Remember , increasing the number of refresh bits set on th[...]

340 The minimum and maximum I/O response times are shown here, using as an example the following instructions executed at the master and the slave. In this example, communications proceed from the master to the slave. Input Output (LR) Input (LR) Output The following conditions are taken as examples for calculating the I/O response times. Input ON [...]

341 3. Communications are completed just after the slave executes communica- tions servicing. I/O refresh Overseeing, communica- tions, etc. Input ON delay Master Input point Input bit CPU processing Cycle time Instruction execution Instruction execution Instruction execution Instruction execution Instruction execution Slave Master to Slave Slave t[...]

342 Scheduled Interrupts Hardware time clock Scheduled interrupt subroutine execution t3 Scheduled in- terrupt interval t3 t3 t3 t3 = Software interrupt response time T otal interrupt response time = t3 (software interrupt response time) Th e software interrupt response time depends on the interrupt response param- eter setting in DM 6620 of the PC[...]

343 Note 1. If there are several elements that can cause interrupts or if the interrupt peri- od is shorted than the average interrupt processing time, the interrupt sub- routine will be executed and the main program will not be executed. This will cause the cycle monitoring time to be exceeded and an F ALS 9F error will be generated, stopping PC o[...]

345 SECTION 7 Pr ogram Monitoring and Execution This section provides the procedures for monitoring and controlling the PC through a Programming Console. Refer to the LSS Operation Manual for LSS procedures if you are using a computer running LSS. 7-1 Monitoring Operation and Modifying Data 346 . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

346 7-1 Monitoring Operation and Modifying Data Th e simplest form of operation monitoring is to display the address whose oper- and bit status is to be monitored using the Program Read or one of the search operations. As long as the operation is performed in RUN or MONITOR mode, the status of any bit displayed will be indicated. This section provi[...]

347 Key Sequence Cancels monitor operation Clears leftmost address Examples The following examples show various applications of this monitor operation. Program Read then Monitor Indicates Completion flag is ON Monitor operation is cancelled 00100 00100READ TIM 000 T000 1234 T001 o 0000 00100 TIM 001 Monitoring Operation and Modifying Data Section 7[...]

348 Bit Monitor 00000 00000 LD 00001 00001 ^ ON 00000 CONT 00001 Note The status of TR bits SR flags SR 25503 to 25507 (e.g., the arithmetic flags), cleared when END(01) is executed, cannot be monitored. Word Monitor 00000 00000 CHANNEL 000 00000 CHANNEL LR 01 cL01 FFFF cL00 0000 Monitoring Operation and Modifying Data Section 7-1[...]

349 +Multiple Address Monitoring 00000 00000 TIM 000 T000 0100 00000 T000 0100 00001 T000 0100 00001 T000 OFF 0100 D000000001 T000 ^OFF 0100 D000000001 T000 10FF^ OFF 0100 T000D000000001 0100 10FF^ OFF D000000001 10FF^ OFF 00001 ^ OFF 00000 CONT 00001 00000 CHANNEL DM 0000 0000000001 S ONR OFF Indicates Force Reset in operation. Indicates Force Set[...]

350 Bi t status will remain ON or OFF only as long as the key is held down; the original status will return as soon as the key is released. If a timer is started, the comple- tion flag for it will be turned ON when SV has been reached. SHIFT and PLA Y/SET or SHIFT and REC/RESET can be pressed to maintain the status of the bit after the key is relea[...]

351 Th e following displays show what happens when TIM 000 is set with 00100 OFF (i.e., 00500 is turned ON) and what happens when TIM 000 is reset with 00100 ON (i.e., timer starts operation, turning OFF 00500, which is turned back ON when the timer has finished counting down the SV). (This example is performed in MONITOR mode.) Indicates that forc[...]

352 Example The following example shows the displays that appear when Restore Status is carried out normally . 00000 00000 00000FORCE RELE? 00000FORCE RELE END 7-1-4 Hexadecimal/BCD Data Modification When the Bit/Digit Monitor operation is being performed and a BCD or hexadeci- mal value is leftmost on the display , CHG can be input to change the v[...]

353 Example The following example shows the effects of changing the PV of a timer . This example is in MONITOR mode Timing Timing PV decrementing Timing Timing 00000 00000 TIM 000 T000 0122 PRES V AL? T000 01 19 ???? PRES V AL? T000 0100 0200 T000 0199 Monitor status of timer PV that will be changed. PV changed. T imer/counter PVs can be changed ev[...]

354 7-1-5 Hex/ASCII Display Change This operation converts DM data displays from 4-digit hexadecimal data to AS- CII and vice versa. Key Sequence Word currently displayed. 00000 00000 CH DM 0000 D0000 4412 D0000 ”AB” D0000 4142 Press TR to change the display to ASCII code. Press TR again to return the display to hexadecimal. Monitor the desired[...]

355 7-1-6 4-digit Hex/Decimal Display Change This operation converts data displays from normal or signed 4-digit hexadecimal data to decimal and vice versa. Decimal values from 0 to 65,535 are valid when inputting normal 4-digit hexade- cimal data, and decimal values from –32,768 to +32,767 are valid when inputting signed 4-digit hexadecimal data[...]

356 7-1-7 8-digit Hex/Decimal Display Change This operation converts data displays from normal or signed, 4 or 8-digit hexa- decimal data to decimal and vice versa. Decimal values from 0 to 4,294,967,295 are valid when inputting normal 8-digit hexadecimal data, and decimal values from –2,147,483,648 to +2,147,483,647 are valid when inputting sign[...]

357 7-1-8 Differentiation Monitor This operation can be used to monitor the up or down dif ferentiation status of bits in the IR, SR, AR, LR, HR, and TC areas. T o monitor up or down dif ferentiation status, display the desired bit leftmost on the bit monitor display , and then press SHIFT and the Up or Down Arrow Key . A CLR entry changes the Dif [...]

358 7-1-9 3-word Monitor T o monitor three consecutive words together , specify the lowest numbered word, press MONTR, and then press EXT to display the data contents of the specified word and the two words that follow it. A CLR entry changes the Three-word Monitor operation to a single-word display . Key Sequence Single-word monitor in progress 00[...]

359 Example 3-word Monitor in progress. Stops in the middle of monitoring. Resumes previous monitoring. D0002D0001D0000 0123 4567 89AB D0002 3CH CHG? = 0123 4567 89AB D0002 3CH CHG? 0001 4567 89AB D0002 3CH CHG? 0001 = 4567 89AB D0002 3CH CHG? 0001 = 2345 89AB D0002D0001D0000 0001 2345 89AB D0002D0001D0000 0001 4567 89AB Input new data. 7-1-1 1 Bin[...]

360 00000 00000 CHANNEL 000 c000 MONTR 0000000000001 11 1 c001 MONTR 0000010101010100 00000 CHANNEL 001 00000 00000 CHANNEL DM 0000 D0000 FFFF D0000 MONTR 1111111111111111 D0000 FFFF 00000 CHANNEL DM 0000 0000S0100R01 10SR Indicates Force Reset in effect Indicates Force Set in effect Example Monitoring Operation and Modifying Data Section 7-1[...]

361 7-1-12 Binary Data Modification This operation assigns a new 16-digit binary value to an IR, HR, AR, LR, or DM word. Th e cursor , which can be shifted to the left w ith the up key and to the right with the down ke y , indicates the position of the bit that can be changed. After positioning to the desired bit, a 0 or a 1 can then be entered as [...]

362 IR bit 001 15 IR bit 00100 00000 00000 CHANNEL 000 00000 CHANNEL 001 c001 MONTR 0000010101010101 c001 CHG? = 000010101010101 c001 CHG? 1 = 00010101010101 c001 CHG? 10 = 0010101010101 c001 CHG? 100 = 010101010101 c001 CHG? 100S = 10101010101 c001 CHG? 100 = 010101010101 c001 CHG? 10 = S010101010101 c001 MONTR 10RS010101010101 c001 CHG? 1 = RS010[...]

363 Key Sequence The following examples show inputting a new constant, changing from a con- stant to an address, and incrementing to a new constant. 00000 00000 TIM 000 00201SRCH TIM 000 00201 TIM DA T A #0123 00201 TIM DA T A T000 #0123 #???? 00201 TIM DA T A T000 #0123 #0124 00201 TIM DA T A #0124 00201 DA T A? T000 #0123 c??? 00201 DA T A? T000 [...]

364 Returns to original display with new SV Current SV (during change operation) SV before the change 00000 00000 TIM 000 00201SRCH TIM 000 00201 TIM DA T A #0123 00201 TIM DA T A T000 #0123 #???? 00201DA T A ? U/D T000 #0123 #0123 00201DA T A ? T000 #0123 #0122 00201DA T A ? T000 #0123 #0123 00201DA T A ? T000 #0123 #0124 00201DA T A ? T000 #0124 [...]

365 7-1-14 Expansion Instruction Function Code Assignments This operation is used to read or change the function codes assigned to expan- sion instructions. There are 18 function codes that can be assigned to expansion instructions: 17, 18, 19, 47, 48, 60 to 69, and 87 to 89. More than one function code can be assigned to an expansion instruction. [...]

366 7-1-15 UM Area Allocation This operation is used to allocate part of the UM Area for use as expansion DM. I t ca n be performed in PROGRAM mode only . Memory allocated to expansion DM is deducted from the ladder program area. The amount of memory available for the ladder program depends on the amount of RAM in the CPU. About 15.2 KW of memory i[...]

367 7-1-16 Reading and Setting the Clock This operation is used to read or set the CPU’s clock. The clock can be read in any mode, but it can be set in MONITOR or PROGRAM mode only . The CPU will reject entries outside of the acceptable range, i.e., 01 to 12 for the month, 0 1 t o 3 1 for the day of the month, 00 to 06 for the day of the week, or[...]

368 Expansion TERMINAL Mode T he Programming Console can be put into Expansion TERMINAL mode by turn- ing ON AR 0709. Pin 6 of the CPU’s DIP switch must be ON. Switch the Programming Console to Expansion TERMINAL mode by turning AR 0709 ON. PROGRAM BZ <MESSAGE> NO MESSAGE PROGRAM BZ CONSOLE mode T urn AR 0709 OFF to return to CONSOLE mode. [...]

369 All bits from SR 27700 through SR 27909 will be turned OFF when AR 0708 is turned ON. Expansion keyboard mapping inputs are disabled when AR 0708 is ON. In addition to the keyboard mapping function, expansion TERMINAL mode al- lows messages output by MSG(46) and LMSG(47) to be displayed on the Pro- gramming Console. These messages will be erase[...]

370 SR word Corresponding key(s) Bit 277 12 13 14 15 278 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 279 00 01 02 Monitoring Operation and Modifying Data Section 7-1[...]

371 SR word Corresponding key(s) Bit 279 03 04 05 *3 06 07 VER 08 09 Monitoring Operation and Modifying Data Section 7-1[...]

373 SECTION 8 Communications This section provides an overview of the communications features provided by the C200HS. 8-1 Introduction 374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 Parameters for Host Link and RS-232C Communications 374 . . . . . . . . . . . . . . . . . . 8-2-1 S[...]

374 8-1 Introduction The C200HS supports the following types of communications. • Communications with Programming Devices (e.g., Programming Console, LSS, or SSS.) • Host Link communications with personal computers and other external de- vices. • RS-232C (no-protocol) communications with personal computers and other external devices. • One-[...]

375 8-2-1 Standard Communications Parameters Th e settings in DM 6645 and DM 6650 determine the main communications pa- rameters, as shown in the following diagram. Th e settings in bits 00 through 07 and bits 12 through 15 are valid only when pin 5 on the CPU’s DIP switch is OFF . Bits 08 though 1 1 are valid only in a PC set as the master for a[...]

376 8-2-2 Specific Communications Parameters The following settings are valid only when pin 5 on the CPU’s DIP switch is turned OFF and DM 6645 and DM 6655 are set to specify using the settings in words DM 6646 and DM 6656. Be sure to set the communications parameters to the same settings for both ends of the communications. T ransmission Frame F[...]

377 8-2-3 Wiring Ports U se the wiring diagram shown below as a guide in wiring the port to the external device. Refer to documentation provided with the computer or other external de- vice for wire details for it. The connections between the C200HS and a personal computer are illustrated below as an example. 1 2 3 4 5 6 FG SD RD RS CS – – – [...]

378 PC Setup The following parameter in the PC Setup is used only when the Host Link com- munications mode is being used. Host Link Node Number A node number must be set for host link communications to differentiate be- tween nodes when multiple nodes are participating in communications. Set the node number to 00 unless multiple nodes are connected[...]

379 TXD(––) instruction. In all other cases, data transmission based on a TXD(––) instruction will be given first priority . Application Example This example shows a program for using the RS-232C port in the Host Link mode to transmit 10 bytes of data (DM 0000 to DM 0004) to a computer . From DM 0000 to DM 0004, “1234” is stored in ever[...]

380 PC Setup Start and end codes or the amount of data to be received can be set as shown in the following diagrams if required for RS-232C communications. This setting is required only for RS-232C communications. Th e following settings are valid only with pin 5 on the CPU’s DIP switch is turned OFF . Enabling Start and End Codes 15 0 Bit 00 End[...]

381 Start and end codes are not included when the number of bytes to be transmitted is specified. The largest transmission that can be sent with or without start and end codes in 256 bytes, i.e., N will be between 254 and 256 depending on the designations for start and end codes. If the number of bytes to be sent is set to 0000, only the start and [...]

382 Application Example This example shows a program for using the RS-232C port in the RS-232C mode to transmit 10 bytes of data (DM 0100 to DM 0104) to the com puter , and to store the data received from the computer in the DM area beginning with DM 0200. Before executing the program, the following PC Setup setting must be made. DM 6645: 1000 (RS-[...]

383 Plug: XM2A-0901 (OMRON) or equivalent Hood: XM2S-0901 (OMRON) or equivalent 1 2 3 4 5 6 FG SD RD RS CS – – – SG 7 8 9 1 2 3 4 5 6 7 8 9 FG SD RD RS CS – – SG 9 C200HS C200HS Signal Abb. Pin No. Signal Abb. Pin No. – Note Ground the FG terminals the C200HS to a resistance of 100 Ω or less. PC Setup T o use a 1:1 link, the only sett[...]

384 When the program is executed at both the master and the slave, the status of IR 001 o f each Unit will be reflected in IR 100 of the other Unit. IR 001 is an input word and IR 100 is an output word. In the Master 25313 (Always ON) MOV(21) 001 LR00 MOV(21) LR08 100 In the Slave MOV(21) 001 LR08 MOV(21) LR00 100 25313 (Always ON) 8-2-7 NT Links N[...]

385 SECTION 9 Memory Cassette Operations This section describes how to manage both UM Area and IOM data via Memory Cassettes. mounted in the CPU. 9-1 Memory Cassettes 386 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Memory Cassette Settings and Flags 386 . . . . . . . . . . . . . . . . . . . [...]

! ! 386 9-1 Memory Cassettes Th e C200HS comes equipped with a built-in RAM for the user ’s program so pro- grams can be created even without installing a Memory Cassette. An optional Memory Cassette, however , can provide flexibility in handling program data, PC Setup data, DM data, I/O comment data, and other IOM Area data. Memory Cas- settes c[...]

387 Word Function Bit(s) SR 270 00 Save UM to Cassette Bit Data transferred to Memory Cassette when Bit is turned ON in PROGRAM mode. Bit will automaticall y turn OFF . 01 Load UM from Cassette Bit ON in PROGRAM mode . Bit will automatically turn OFF . An error will be produced if turned ON in any other mode. 02 Collation Execution Flag 03 Collatio[...]

388 4. T urn on the CPU. 5. I f the desired program or UM Area data is not already in the CPU, write the data or transfer it to the CPU. 6. Switch the C200HS to PROGRAM mode. 7. T urn ON SR 27000 from the LSS or a Programming Console. The UM Area data will be written to the Memory Card and SR 27000 will be turned OFF automatically . Reading Data Th[...]

389 Note The data inside the Memory Cassette should be protected by turning on the write-protect switch whenever you are not planning to write to the Cassette. Writing Data The following procedure is used to write IOM data from the C200HS CPU to a Memory Cassette mounted in the CPU. 1, 2, 3... 1. Turn of f the write-protect switch on the Memory Cas[...]

391 SECTION 10 T r oubleshooting The C200HS provides self-diagnostic functions to identify many types of abnormal system conditions. These functions mini- mize downtime and enable quick, smooth error correction. This section provides information on hardware and software errors that occur during PC operation. Program input errors are described i n 4[...]

! 392 10-1 Alarm Indicators The ALM/ERR indicator on the front of the CPU provides visual indication of an abnormality in the PC. When the indicator is ON (ERROR), a fatal error (i.e., ones that will stop PC operation) has occurred; when the indicator is flashing (ALARM), a nonfatal error has occurred. This indicator is shown in 2-1-1 CPU Indicator[...]

393 The type of error can be quickly determined from the indicators on the CPU, as described below for the three types of errors. If the status of an indicator is not mentioned in the description, it makes no difference whether it is lit or not. After eliminating the cause of an error , clear the error message from memory before resuming operation.[...]

394 Error and message Possible correction Probable cause FA L no. High-density I/O Unit error SYS F AIL F AL9A 9A An error occurred in data transfer between a High-density I/O Unit and the CPU. Check AR 0205 to AR 0214 to identify the Unit with a problem, replace the Unit, and restart the PC. PC Setup error SYS F AIL F AL9B 9B An error has been det[...]

395 Fatal Operating Errors T he following error messages appear for errors that occur after program execu- tion has been started. PC operation and program execution will stop and all out- puts from the PC will be turned OFF when any of the following errors occur . No CPU indicators will be lit for the power interruption error . For all other fatal [...]

396 Error and message Possible correction Probable cause FA L no. T oo many Units I/O UNIT OVER E1 T wo or more Special I/O Units are set to the same unit number T wo or more Group-2 High-density I/O Units are set to the same I/O number or I/O word. The I/O number of a 64-pt Group-2 High-density I/O Unit is set to 9. T wo SYSMAC NET Link or SYSMAC [...]

397 10-5 Error Flags The following table lists the flags and other information provided in the SR and AR areas that can be used in troubleshooting. Details are provided in 3-4 SR Area and 3-5 AR Area . SR Area Address(es) Function 23600 to 23615 Node loop status for SYSMAC NET Link system 23700 to 23715 Completion/error code output area for SEND(90[...]

398 AR Area Address(es) Function 0000 to 0009 Special I/O or PC Link Unit Error Flags 0010 SYSMAC LINK/SYSMAC NET Link Level 1 System Error Flags 001 1 SYSMAC LINK/SYSMAC NET Link Level 0 System Error Flags 0012 Rack-mounting Host Link Unit Level 1 Error Flag 0013 Rack-mounting Host Link Unit Level 0 Error Flag 0014 Remote I/O Master Unit 1 Error F[...]

399 10-6 Host Link Errors These error codes are received as the response code (end code) when a com- mand received by the C200HS from a host computer cannot be processed. The error code format is as shown below . @ XX ↵ : XX XXXX Node no. Header code T erminator FCS End code Th e header code will vary according to the command and can contain a su[...]

401 SECTION 1 1 Host Link Commands This section explains the methods and procedures for using host link commands, which can be used for host link communica- tions via the C200HS ports. 1 1-1 Communications Procedure 402 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1-2 Command and Response Formats 404 . . . .[...]

402 1 1-1 Communications Procedure Command Chart The commands listed in the chart below can be used for host link communica- tions w ith the C200HS. These commands are all sent from the host computer to the PC. Header code PC mode Name Page RUN MON PRG g RR V alid V alid V alid IR/SR AREA READ 407 RL V alid V alid V alid LR AREA READ 407 RH V alid [...]

403 Host link communications are executed by means an exchange of commands an d responses between the host computer and the PC. With the C200HS, there are two communications methods that can be used. One is the normal method, in which commands are issued from the host computer to the PC. The other method allows commands to be issued from the PC to [...]

404 When commands are issued to the host computer , the data is transmitted in one direction from the PC to the host computer . If a response to a command is re- quired use a host link communications command to write the response from the host computer to the PC. 1 1-2 Command and Response Formats This section explains the formats for the commands [...]

405 Long T ransmissions T h e largest block of data that can be transmitted as a single frame is 131 charac- ters. A command or response of 132 characters or more must therefore be di- vided into more than one frame before transmission. When a transmission is split, the ends of the first and intermediate frames are marked by a delimiter instead of [...]

406 time a frame is received and checking the result against the FCS that is included in the frame makes it possible to check for data errors in the frame. FCS : ↵ 0 1R R 0 @0 014 2 T ext Node no. Header code FCS calculation range T erminator @ 40 0100 0000 EOR 1 31 001 1 0001 EOR 0 30 001 1 0000 EOR R 52 0101 0010 1 31 001 1 0001 0100 0010 ↓?[...]

407 Reception Format When TXD(––) is executed, the data stored in the words beginning with the first send word is converted to ASCII and output to the host computer as a host link command in the format shown below . The “@” symbol, node number , header code, FCS, and delimiter are all added automatically when the transmission is sent. At th[...]

408 Response Format @ RL x 10 1 x 10 0 x 16 1 x 16 0 : ↵ x 16 3 x 16 2 x 16 1 x 16 0 FCS Node no. Header code End code Read data (1 word) Read data (for number of words read) T erminator Parameters Read Data (Response) The contents of the number of words specified by the command are returned in hexadecimal as a response. The words are returned in[...]

409 cimal as a response. The PVs are returned in order , starting with the specified beginning timer/counter . 1 1-3-5 TC ST A TUS READ –– RG Reads the status of the Completion Flags of the specified number of timers/ counters, starting from the specified timer/counter . Command Format @ RG FCS x 10 1 x 10 0 x 10 3 x 10 2 : ↵ x 10 1 x 10 0 x [...]

410 1 1-3-7 AR AREA READ –– RJ Reads the contents of the specified number of AR words, starting from the speci- fied word. Command Format @ RJ FCS x 10 1 x 10 0 x 10 3 x 10 2 : ↵ x 10 1 x 10 0 x 10 3 x 10 2 x 10 1 x 10 0 T erminator Beginning word (0000 to 0027) Node no. Header code No. of words (0001 to 0028) Response Format @ RJ FCS x 10 1 [...]

41 1 1 1-3-9 LR AREA WRITE –– WL Writes data to the LR area, starting from the specified word. W riting is done word by word. Command Format @ WL FCS x 10 1 x 10 0 x 10 3 x 10 2 : ↵ x 10 1 x 10 0 x 16 3 x 16 2 x 16 1 x 16 0 Node no. Header code T erminator Write data (1 word) Write data (for number of words to write ) Beginning word (0000 to [...]

412 1 1-3-1 1 PV WRITE –– WC Writes the PVs (present values) of timers/counters starting from the specified timer/counter . Command Format @ WC FCS x 10 1 x 10 0 x 10 3 x 10 2 : ↵ x 10 1 x 10 0 x 16 3 x 16 2 x 16 1 x 16 0 Node no. Header code T erminator Beginning timer/counter (0000 to 051 1) Write data (1 timer/counter) Write data (for no. [...]

413 Note If data is specified for writing which exceeds the allowable range, an error will be generated and the writing operation will not be executed. If, for example, 510 is specified as the beginning word for writing, and three words of data are speci- fied, then 512 will become the last word for writing data, and the command will not be execute[...]

414 Parameters Write Data (Command) Specify i n order the contents of the number of words to be written to the AR area in hexadecimal, starting with the specified beginning word. Note If data is specified for writing which exceeds the allowable range, an error will be generated and the writing operation will not be executed. If, for example, 26 is [...]

415 1 1-3-16 SV READ 2 –– R$ Reads the constant SV or the word address where the SV is stored. The SV that is read is a 4-digit decimal number (BCD) written as the second operand for the TIM, TIMH(15), CNT , CNTR(12), or TTIM(87) instruction at the specified pro- gram address in the user ’s program. This can only be done with a program of les[...]

416 1 1-3-17 SV READ 3 –– R% Reads the constant SV or the word address where the SV is stored. The SV that is read is a 4-digit decimal number (BCD) written in the second word of the TIM, TIMH(15), C N T , CNTR(12), or TTIM(87) instruction at the specified program ad- dress in the user ’ s program. With this command, program addresses can be [...]

417 1 1-3-18 SV CHANGE 1 –– W# Searches for the first instance of the specified TIM, TIMH(15), CNT , CNTR(12), or TTIM(87) instruction in the user ’s program and changes the SV to new constant SV specified in the second word of the instruction. The program is searched from the beginning, and it may therefore take approximately 10 se- conds to[...]

418 Parameters Name, TC Number (Command) In “Name”, specify the name of the instruction, in four characters, for changing the SV . In “TC number”, specify the timer/counter number used for the instruc- tion. Instruction name Classification TC number OP1 OP2 OP3 OP4 range T I M (S) TIMER 0000 to 051 1 T I M H HIGH-SPEED TIMER C N T (S) COUNT[...]

419 Parameters Name, TC Number (Command) In “Name”, specify the name of the instruction, in four characters, for changing the SV . In “TC number”, specify the timer/counter number used for the instruc- tion. Instruction name Classification TC number OP1 OP2 OP3 OP4 range T I M (S) TIMER 0000 to 051 1 T I M H HIGH-SPEED TIMER C N T (S) COUNT[...]

420 Parameters Status Data, Message (Response) “Status data” consists of four digits (two bytes) hexadecimal. The leftmost byte indicates CPU operation mode, and the rightmost byte indicates the size of the program area. 15 14 13 12 1 1 10 9 8 00 0 98 00 10 1 1 x 16 3 x 16 2 This area is different from that of ST A TUS WRITE. Bit Bit 1: F ALS g[...]

421 Parameters Mode Data (Command) “Mode data” consists of two digits (one byte) hexadecimal. With the leftmost tw o bits, specify the PC operating mode. Set all of the remaining bits to “0”. RUN mode 7 6543210 000000 10 00 10 1 1 x 16 1 PROGRAM mode MONITOR mode Bit Bit Operation mode This area is different from that of ST A TUS READ. x 16[...]

422 Error Information (Response) The error information comes in two words. 15 14 13 12 1 1 10 9 8 00 x 16 3 x 16 2 7654 x 16 1 3210 x 16 0 ON: Battery error (Error code F7) ON: Special I/O Unit error ON: System error (F AL) ON: Memory error (Error code F1) ON: I/O bus error (Error code C0) ON: PC link error ON: Host Link Unit transmission error ON:[...]

423 Parameters Name, W ord address, Bit (Command) In “Name”, specify the area (i.e., IR, SR, LR, HR, AR, or TC) that is to be forced set. Specify the name in four characters. In “W ord address”, specify the address of the word, and in “Bit” the number of the bit that is to be forced set. Name Classification Word address setting Bit OP1 [...]

424 Note 1. The area specified under “Name” must be in four characters. Fill any gaps with spaces to make a total of four characters. 2. Words 253 to 255 cannot be set when the CIO Area is specified. 1 1-3-26 MUL TIPLE FORCED SET/RESET –– FK Force sets, force resets, or cancels the status of the bits in one word in the IR, SR, LR, HR, AR, o[...]

425 Forced set/reset/cancel Data (Command) A separate hexadecimal digit is used to specify the desired process for each bit in the specified word, bits 00 to bit 5. The bits that are merely set or reset may change status the next time the program is executed, but bits that are force-set or force-reset will maintain the forced status until it is cle[...]

426 Parameters Model Code “Model code” indicates the PC model in two digits hexadecimal. Model code Model 01 C250 02 C500 03 C120 0E C2000 10 C1000H 11 C2000H/CQM1 12 C20H/C28H/C40H/C200H/C200HS 20 CV500 21 CV1000 22 CV2000 40 CVM1-CPU01-E 41 CVM1-CPU1 1-E 1 1-3-29 TEST–– TS Returns, unaltered, one block of data transmitted from the host co[...]

427 Parameters Program (Response) The program is read from the entire program area. Note T o stop this operation in progress, execute the ABORT (XZ) command. 1 1-3-31 PROGRAM WRITE –– WP Writes t o the PC user’s program area the machine language (object code) pro- gram transmitted from the host computer . The contents are written as a block, [...]

428 Command Format @ QQ x 10 0 x 10 1 x 10 3 x 10 2 x 10 1 x 10 0 OP1 OP2 OP3 OP4 M OP1 OP2 x 10 3 x 10 2 x 10 1 x 10 0 OP1 OP2 OP3 OP4 OP1 OP2 ↵ : Node no. Header code T erminator FCS Sub-header code Read area Read word address Data format Data break Single read information T otal read information (128 max.) Single read information T otal read i[...]

429 Data Break (Command) The read information is specified one item at a time separated by a break code (,). The maximum number of items that can be specified is 128. (When the PV of a timer/counter is specified, however , the status of the Completion Flag is also returned, and must therefore be counted as two items.) Batch Reading T he bit, word, [...]

430 1 1-3-35 INITIALIZE –– :: Initializes the transmission control procedure of all the PCs connected to the host computer . The INITIALIZE command does not use node numbers or FCS, and does not receive a response. Command Format ↵ @ : : 1 1-3-36 Undefined Command –– IC This response is returned if the header code of a command cannot be d[...]

431 1 1-4 Host Link Errors These error codes are received as the response code (end code) when a com- mand received by the C200HS from a host computer cannot be processed. The error code format is as shown below . @ XX ↵ : XX XXXX Node no. Header code T erminator FCS End code Th e header code will vary according to the command and can contain a s[...]

433 Appendix A Standard Models C200HS Racks Name Specifications Model number Backplane (same for all Racks) 10 slots C200H-BC101-V2 () 8 slots C200H-BC081-V2 5 slots C200H-BC051-V2 3 slots C200H-BC031-V2 CPU Rack CPU 100 to 120/200 to 240 V AC w/built-in ––– C200HS-CPU01-E power supply Conforms to EC directives (see note) C200HS-CPU01-EC RS-2[...]

Standard Models Appendix A 434 C200H Standard I/O Units Name Specifications Model number Input Units AC Input Unit 8 pts 100 to 120 V AC C200H-IA121 16 pts 100 to 120 V AC C200H-IA122/122V 8 pts 200 to 240 V AC C200H-IA221 16 pts 200 to 240 V AC C200H-IA222/222V DC Input Unit 8 pts No-voltage contact; NPN C200H-ID001 8 pts No-voltage contact; PNP C[...]

Appendix A Standard Models 435 C200H Group-2 High-density I/O Units Name Specifications Model number DC Input Unit 32 pts. 24 VDC C200H-ID216 C200H-ID218 64 pts. 24 VDC C200H-ID217 C200H-ID219 T ransistor Output Unit 32 pts. 16 mA 4.5 VDC to 100 mA 26.4 VDC C200H-OD218 0.5 A (5A/Unit) 24 VDC C200H-OD21B 64 pts. 16 mA 4.5 VDC to 100 mA 26.4 VDC C200[...]

Standard Models Appendix A 436 Name Model number Specifications Heat/Cool T emperature Control Unit Thermocou- ple T ransistor output C200H-TV001 V oltage output C200H-TV002 Current output C200H-TV003 Pt resis- tance ther- T ransistor output C200H-TV101 t ance th er- mometer V oltage output C200H-TV102 Current output C200H-TV103 PID Control Unit Tr[...]

Appendix A Standard Models 437 SYSMAC LINK Unit/SYSMAC NET Link Unit Th e SYSMAC LINK Units and SYSMAC NET Link Unit can only be used with the C200HS-CPU31-E and C200HS- CPU33-E CPUs. Name Specifications Model number SYSMAC LINK Unit Wired via coaxial cable. Bus Connection Unit required separately . One C1000H-CE001 F Adapter included. C200HS-SLK22[...]

Standard Models Appendix A 438 Mounting Rails and Accessories Name Specification s Model number DIN T rack Mounting Bracket 1 set (2 included) C200H-DIN01 DIN T rack Length: 50 cm; height: 7.3 mm PFP-50N Length: 1 m; height: 7.3 mm PFP-100N Length: 1 m; height: 16 mm PFP-100N2 End Plate --- PFP-M Spacer --- PFP-S Link Adapters Name Specifications M[...]

Appendix A Standard Models 439 Name Model number Specifications All Plastic Optical Fiber Cable Set 1-m cable with an Optical Connector A connected to each end 3G5A2-PF101 Optical Fiber Processing Kit Accessory: 125-mm nipper (Muromoto T ekko’s 550M) for APF 3G2A9-TL101 H-PCF Name Specifications Model number Optical Fiber Cable SYSMAC BUS SYSMAC [...]

Standard Models Appendix A 440 Optical Power T ester Name Specifications Head Unit Model number Optical Power T ester (see note) (provided with a connector adapter , light source unit, small single-head plug, hard case, and AC adapter) SYSMAC BUS: C200H-RM001-PV1 C200H-RT001/R T002-P C500-RM001-(P)V1 C500-RT001/R T002-(P)V1 S3200-CA T2822 (provided[...]

Appendix A Standard Models 441 An Optical Fiber Cable Bracket must be used to support an optical fiber cable connected to the C200HS-SNT32 SYSMAC NET Link Unit or C200HS-SLK12 SYSMAC LINK Unit. User optical fiber cables with both tension members and power supply lines. The following half-lock connector is used and connects to the C200HS SYSMAC LINK[...]

443 Appendix B Programming Instructions A PC instruction is input either by pressing the corresponding Programming Console key(s) (e.g., LD, AND, OR, NOT) or b y using function codes. T o input an instruction with its function code, press FUN, the function code, and then WRITE. Refer to the pages listed programming and instruction details. Code Mne[...]

Appendix B Programming Instructions 444 Code Page Function Name Mnemonic 13 DIFU DIFFERENTIA TE UP T urns ON the designated bit for one cycle on the rising edge of the input signal. 131 14 DIFD DIFFERENTIA TE DOWN T urns ON the bit for one cycle on the trailing edge. 131 15 TIMH HIGH-SPEED TIMER A high-speed, ON-delay (decrementing) timer . 143 (@)[...]

Appendix B Programming Instructions 445 Code Page Function Name Mnemonic (@)52 MLB BINARY MUL TIPL Y Multiplies two four-digit hexadecimal values and outputs result to specified result words. 224 (@)53 DVB BINARY DIVIDE Divides four-digit hexadecimal dividend by four-digit hexa- decimal divisor and outputs result to specified result words. 224 (@)5[...]

Appendix B Programming Instructions 446 Code Page Function Name Mnemonic (@)86 ASC ASCII CONVERT Converts hexadecimal values from the source word to eight-bit ASCII code starting at leftmost or rightmost half of starting destination word. 194 87 to 89 For expansion instructions. (@)90 SEND NETWORK SEND Used for communications with other PCs linked [...]

Appendix B Programming Instructions 447 Code Page Function Name Mnemonic 89 (@)INT INTERRUPT CONTROL Performs interrupt control, such as masking and un- masking the interrupt bits for I/O interrupts. 262 --- 7SEG 7-SEGMENT DISPLA Y OUTPUT Converts 4- or 8-digit BCD data to 7-segment display format and then outputs the converted data. 301 --- (@)ADB[...]

Appendix B Programming Instructions 448 Code Page Function Name Mnemonic --- (@)XDMR EXP ANSION DM READ The contents of the designated number of words of the fixed expansion DM data are read and output to the destination word on the PC side. 290 --- ZCPL DOUBLE AREA RANGE COMP ARE Compares an 8-digit value to a range defined by lower and upper limi[...]

449 Appendix C Error and Arithmetic Flag Operation The following table shows the instructions that affect the ER, CY , GR, LE and EQ flags. In general, ER indicates that operand data is not within requirements. CY indicates arithmetic or data shift results. GT indicates that a com- pared value is larger than some standard, L T that it is smaller , [...]

Appendix C Error and Arithmetic Flag Operation 450 Instructions Page 25507 (LE) 25506 (EQ) 25505 (GR) 25504 (CY) 25503 (ER) MLB(52) Unaffected Unaf fected Unaffected 224 DVB(53) Unaf fected Unaffected Unaffected 224 ADDL(54) Unaffected Unaffected 206 SUBL(55) 209 MULL(56) Unaf fected Unaffected Unaffected 212 DIVL(57) 213 BINL(58) 181 BCDL(59) 182 [...]

Appendix C Error and Arithmetic Flag Operation 451 Instructions Page 25507 (LE) 25506 (EQ) 25505 (GR) 25504 (CY) 25503 (ER) FPD(––) Unaf fected Unaffected Unaf fected 285 HEX(––) Unaf fected Unaffected Unaf fected Unaffected 195 HMS(66) Unaffected Unaf fected Unaffected 184 INT(89) Unaffected Unaf fected Unaffected Unaf fected 262 LINE(63) [...]

Appendix C Error and Arithmetic Flag Operation 452 Instructions SR 25404 (OF ) SR 25405 (UF) Page END(01) OFF OFF 138 ADB(50) 219 SBB(51) 221 ADBL(––) 225 SBBL(––) 227 NEG(––) Unaffected 202 NEGL(––) 203 These instructions also af fect the ER, CY , and EQ Flags. Refer to the previous tables in this appendix for details.[...]

453 Appendix D Memory Areas Overview The following table shows the data areas in PC memory . Area Size Range Comments I/O Area 480 bits IR 000 to IR 029 Group-2 High-density I/O Unit Area 320 bits IR 030 to IR 049 Can be used as ordinary I/O or , if not used for real I/O, can be used as work bits. SYSMAC BUS Area 800 bits IR 050 to IR 099 Can be us[...]

Appendix D Memory Areas 454 SR Area Word(s) Bit(s) Function 236 00 to 07 Node loop status output area for operating level 0 of SYSMAC NET Link System 08 to 15 Node loop status output area for operating level 1 of SYSMAC NET Link System 237 00 to 07 Completion code output area for operating level 0 following execution of SEND(90)/RECV(98) SYSMAC LIN[...]

Appendix D Memory Areas 455 Word(s) Function Bit(s) 254 00 1-minute clock pulse bit 01 0.02-second clock pulse bit 02 and 03 Reserved for function expansion. Do not use. 04 Overflow Flag (for signed binary calculations) 05 Underflow Flag (for signed binary calculations) 06 Differential Monitor End Flag 07 Step Flag 08 MTR Execution Flag 09 7SEG Exe[...]

Appendix D Memory Areas 456 Word(s) Function Bit(s) 267 00 to 04 Reserved by system (not accessible by user) 05 Host Link Level 0 Send Ready Flag 06 to 12 Reserved by system (not accessible by user) 13 Host Link Level 1 Send Ready Flag 14 and 15 Reserved by system (not accessible by user) 268 00 to 15 Reserved by system (not accessible by user) 269[...]

Appendix D Memory Areas 457 Word(s) Function Bit(s) 273 00 Save IOM to Cassette Bit Data transferred to Memory Cassette when Bit is turned ON in PROGRAM mode. Bit will automaticall y turn OFF . 01 Load IOM from Cassette Bit ON in PROGRAM mode . Bit will automatically turn OFF . An error will be produced if turned ON in any other mode. 02 to 1 1 Res[...]

Appendix D Memory Areas 458 AR Area Word(s) Bit(s) Function 00 00 to 09 Error Flags for Special I/O Units 0 to 9 (also function as Error Flags for PC Link Units) 10 Error Flag for operating level 1 of SYSMAC LINK or SYSMAC NET Link System 11 Error Flag for operating level 0 of SYSMAC LINK or SYSMAC NET Link System 12 Host Computer to Rack-mounting [...]

Appendix D Memory Areas 459 Word(s) Function Bit(s) 23 00 to 15 Power Off Counter (BCD) 24 00 to 04 Reserved by system. 05 Cycle T ime Flag 06 SYSMAC LINK System Network Parameter Flag for operating level 1 07 SYSMAC LINK System Network Parameter Flag for operating level 0 08 SYSMAC/SYSMAC NET Link Unit Level 1 Mounted Flag 09 SYSMAC/SYSMAC NET Lin[...]

461 Appendix E PC Setup Word(s) Bit(s) Function Default Startup Processing (DM 6600 to DM 6614) The following settings are effective after transfer to the PC only after the PC is restarted. DM 6600 00 to 07 Startup mode (ef fective when bits 08 to 15 are set to 02). 00: PROGRAM; 01: MONITOR 02: RUN PROGRAM 08 to 15 Startup mode designation 00: Prog[...]

Appendix E PC Setup 462 Word(s) Bit(s) Function Default Interrupt/Refresh Processing (DM 6620 to DM 6622) The following settings are effective after transfer to the PC the next time operation is started. DM 6620 00 to 09 Special I/O Unit cyclic refresh (Bit number corresponds to unit number , PC Link Units included) 0: Enable cyclic refresh and I/O[...]

Appendix E PC Setup 463 Word(s) Default Function Bit(s) DM 6648 00 to 07 Node number (Host link) 00 to 31 (BCD) 0 08 to 1 1 Start code enable (RS-232C) 0: Disable; 1: Set Disabled 12 to 15 End code enable (RS-232C) 0: Disable (number of bytes received) 1: Set (specified end code) 2: CR, LF Disabled DM 6649 00 to 07 Start code (RS-232C) 00 to FF (bi[...]

Appendix E PC Setup 464 Word(s) Default Function Bit(s) DM 6654 00 to 07 Start code (RS-232C) 00 to FF (binary) 0000 08 to 15 12 to 15 of DM 6653 set to 0: Number of bytes received 00: Default setting (256 bytes) 01 to FF: 1 to 255 bytes 12 to 15 of DM 6653 set to 1: End code (RS-232C) 00 to FF (binary) Error Settings (DM 6655) The following settin[...]

465 Appendix F W ord Assignment Recording Sheets This appendix contains sheets that can be copied by the programmer to record I/O bit allocations and terminal assignments, as well as details of work bits, data storage areas, timers, and counters.[...]

466 Programmer: Program: Date: Page: Word: Unit: Bit Field device Notes 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 Word: Unit: Bit Field device Notes 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 Word: Unit: Bit Field device Notes 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 Word: Unit: Bit Field device Notes 00 01 02 03 04 05 06 07 08 09[...]

467 Programmer: Program: Date: Page: Area: Word: Bit Usage Notes 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 Area: Word: Bit Usage Notes 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 Area: Word: Bit Usage Notes 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 Area: Word: Bit Usage Notes 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 Work Bits[...]

468 Programmer: Program: Date: Page: Word Contents Notes W ord Contents Notes Data Storage[...]

469 Programmer: Program: Date: Page: TC address T or C Set value Notes TC address T or C Set value Notes Timers and Counters[...]

471 Appendix G Program Coding Sheet Th e following page can be copied for use in coding ladder diagram programs. It is designed for flexibility , allowing the user to input all required addresses and instructions. When coding programs, be sure to specify all function codes for instructions and data areas (or # for constant) for operands. These will[...]

472 Programmer: Program: Date: Page: Address Instruction Operand(s) Address Instruction Operand(s) Address Instruction Operand(s) Program Coding Sheet[...]

473 Appendix H Data Conversion T ables Normal Data Decimal BCD Hex Binary 00 00000000 00 00000000 01 00000001 01 00000001 02 00000010 02 00000010 03 0000001 1 03 0000001 1 04 00000100 04 00000100 05 00000101 05 00000101 06 000001 10 06 000001 10 07 000001 1 1 07 000001 1 1 08 00001000 08 00001000 09 00001001 09 00001001 10 00010000 0A 00001010 11 0[...]

Data Conversion T ables Appendix H 474 Signed Binary Data Decimal 16-bit Hex 32-bit Hex 2147483647 2147483646 . . . 32768 32767 32766 . . . 5 4 3 2 1 0 –1 –2 –3 –4 –5 . . . –32767 –32768 –32769 . . . –2147483647 –2147483648 ––– ––– . . . ––– 7FFF 7FFE . . . 0005 0004 0003 0002 0001 0000 FFFF FFFE FFFD FFFC FFFB[...]

475 Appendix I Extended ASCII Programming Console Displays Bits 0 to 3 Bits 4 to 7 BIN 0000 0001 0010 001 1 0100 0101 01 10 01 1 1 1010 101 1 1 100 1 101 111 0 1111 HEX 0 1 2 3 4 5 6 7 A B C D E F 0000 0 NUL DLE Space 0 @ P ‘ p 0 @ P ‘ p 0001 1 SOH DC 1 ! 1 A Q a q ! 1 A Q a q 0010 2 STX DC 2 ” 2 B R b r ” 2 B R b r 001 1 3 ETX DC 3 # 3 C S[...]

477 Glossary address The location in memory where data is stored. For data areas, an address con- sists of a two-letter data area designation and a number that designates the word and/or bit location. For the UM area, an address designates the instruction location (UM area). In the FM area, the address designates the block location, etc. allocation[...]

Glossary 478 bit designator An operand that is used to designate the bit or bits of a word to be used by an instruction. bit number A number that indicates the location of a bit within a word. Bit 00 is the rightmost (least-significant) bit; bit 15 is the leftmost (most-significant) bit. buffer A temporary storage space for data in a computerized d[...]

Glossary 479 through a TC bit and used to count the number of times the status of a bit or an execution condition has changed from OFF to ON. CPU An acronym for central processing unit. In a PC System, the CPU executes the program, processes I/O signals, communicates with external devices, etc. CPU Backplane A Backplane which is used to create a CP[...]

Glossary 480 differentiated instruction An instruction that is executed only once each time its execution condition goes from OFF to ON. Nondif ferentiated instructions are executed each cycle as long as the execution condition stays ON. differentiation instruction An instruction used to ensure that the operand bit is never turned ON for more than [...]

Glossary 481 extended timer A timer created in a program by using two or more timers in succession. Such a timer is capable of timing longer than any of the standard timers provided by the individual instructions. Factory Intelligent T erminal A programming device provided with advanced programming and debugging capabilities to facilitate PC operat[...]

Glossary 482 initialization error An error that occurs either in hardware or software during the PC System star- tup, i.e., during initialization. initialize Part of the startup process whereby some memory areas are cleared, system setup is checked, and default values are set. input The signal coming from an external device into the PC. The term in[...]

Glossary 483 I/O Control Unit A Unit mounted to the CPU Rack in certain PCs to monitor and control I/O points on Expansion I/O Units. I/O devices The devices to which terminals on I/O Units, Special I/O Units, or Intelligent I/O Units are connected. I/O devices may be either part of the Control System, if they function to help control other devices[...]

Glossary 484 Ladder Support Software A software package that provides most of the functions of the Factory Intelligent T erminal on an IBM A T , IBM XT , or compatible computer . LAN An acronym for local area network. leftmost (bit/word) T he highest numbered bits of a group of bits, generally of an entire word, or the highest numbered words of a g[...]

Glossary 485 main program All of a program except for the subroutines. masking ‘Covering’ a n interrupt signal so that the interrupt is not effective until the mask is removed. Master Short for Remote I/O Master Unit. memory area Any of the areas in the PC used to hold data or programs. mnemonic code A form of a ladder-diagram program that cons[...]

Glossary 486 NOT A logic operation which inverts the status of the operand. For example, AND NO T indicates an AND operation with the opposite of the actual status of the op- erand bit. NSB An acronym for Network Service Board. NSU An acronym for Network Service Unit. OFF Th e status of an input or output when a signal is said not to be present. Th[...]

Glossary 487 output point The point at which an output leaves the PC System. Output points correspond physically to terminals or connector pins. output signal A signal being sent to an external device. Generally an output signal is said to exist when, for example, a connection point goes from low to high voltage or from a nonconductive to a conduct[...]

Glossary 488 grammable Controllers are used to automate control of external devices. Al- though single-component Programmable Controllers are available, build- ing-block Programmable Controllers are constructed from separate compo- nents. Such building-block Programmable Controllers are formed only when enough of these separate components are assem[...]

Glossary 489 Remote I/O Unit Any of the Units in a Remote I/O System. Remote I/O Units include Masters, Slaves, Optical I/O Units, I/O Link Units, and Remote T erminals. remote I/O word An I/O word allocated to a Unit in a Remote I/O System. reset The process of turning a bit or signal OFF or of changing the present value of a timer or counter to i[...]

Glossary 490 slot A position on a Rack (Backplane) to which a Unit can be mounted. software error An error that originates in a software program. software protect A means of protecting data from being changed that uses software as opposed to a physical switch or other hardware setting. source Th e location from which data is taken for use in an ins[...]

Glossary 491 timer A location in memory accessed through a TC bit and used to time down from the timer ’s set value. T imers are turned ON and reset according to their execution conditions. TM area A memory area used to store the results of a trace. transmission distance The distance that a signal can be transmitted. TR area A data area used to s[...]

Glossary 492 served for work words. Parts of other areas not required for special purposes m a y also be used as work words, e.g., LR words not used in a PC Link or Net Link System.[...]

493 Revision History A manual revision code appears as a suffix to the catalog number on the front cover of the manual. Cat. No. W235-E1-05 Revision code The following table outlines the changes made to the manual during each revision. Page numbers refer to the previous version. Revision code Date Revised content 1 January 1994 Original production [...]

Revision History 494 Revision code Revised content Date 2A April 1995 The following instructions have been corrected: ASFT(––) to ASFT(17), XFRB(––) to XFRB(62), MCMP(––) t o MCMP(19), CMPL(––) to CMPL(60), BCMP(––) to BCMP(68), ZCP(––) to ZCP(88), SEC(––) to SEC(65), HMS(––) to HMS(66), LINE(––) to LINE(63), COL[...]

Revision History 495 Revision code Revised content Date 2B July 1995 The following corrections and additions were made. Page 6: SYSMAC Support Software added and LSS removed. Pages 23 and 374: Default communications parameters changed. Page 26: I/O T erminals and B7A Interface Unit added and macro bits corrected. Page 31: List of Units that don’t[...]

497 Index A address tracing. See tracing, data tracing. addresses, in data area: sec3 27 advanced I/O instructions 7-SEGMENT DISPLA Y OUTPUT : 5–24 on 305 DIGIT AL SWITCH INPUT : 5–24 on 308 functions: 5–24 on 304 HEXADECIMAL KEY INPUT : 5–24 on 312 MA TRIX INPUT : 5–24 on 317 TEN-KEY INPUT : 5–24 on 314 application examples: 6–4 on 3[...]

Index 498 converting between hex and ASCII: sec7 354 I/O Unit designations: 4–1 to 4–6 88 Programming Console, English/Japanese switch: 4–1 to 4–6 80 DM area, allocating UM to expansion DM: sec7 366 E ER. See flag, Instruction Execution Error error codes, programming: 5–24 on 278 error history , dedicated bits: sec3 51 error messages, pro[...]

Index 499 WC: sec1 1 412 WD: sec1 1 413 WG: sec1 1 412 WH: sec1 1 41 1 WJ: sec1 1 413 WL: sec1 1 41 1 WP: sec1 1 427 WR: sec1 1 410 XZ: sec1 1 429 host link errors: sec1 1 431 Host Link Systems, error bits and flags: sec3 40 HR area: sec3 60 I I/O bit definition: sec3 31 limits: sec3 31 I/O numbers: sec3 33 I/O points, refreshing: 5–24 on 284 , 2[...]

Index 500 OR: 4–1 to 4–6 69 ; 5–1 to 5–14 129 combining with AND: 4−1 to 4−6 69 OR LD: 4–1 to 4–6 72 ; 5–1 to 5–14 130 combining with AND LD: 4−1 to 4−6 73 use in logic blocks: 4−1 to 4−6 73 OR NOT : 4–1 to 4–6 69 ; 5–1 to 5–14 129 ORW(35): 5–20 to 5–23 251 OUT : 4–1 to 4–6 70 ; 5–1 to 5–14 130 OUT NO[...]

Index 501 memory areas: appD 453 clearing: 4–1 to 4–6 82 definition: sec3 25 Memory Cassette, installing: sec2 21 Memory Cassettes transferring C200H programs: sec1 11 UM Area/IOM data: sec9 386 memory clear: 4–1 to 4–6 84 memory partial clear: 4–1 to 4–6 83 messages, programming: 5–24 on 281 , 282 mnemonic code, converting: 4–1 to [...]

Index 502 Special I/O Units. See Units SR area: sec3 33–48 stack operation COLL(81): 5–15 to 5–17 164 DIST(80): 5–15 to 5–17 162 ST ARTUP MODE, PC Setup: sec3 59 ST ARTUP SETTINGS, PC Setup: sec3 59 status indicators. See CPU indicators step execution, Step flag: sec3 44 step instructions: 5–24 on 269–278 subroutine number: 5–20 to [...]