Renesas 4514 инструкция обслуживания

Regar ding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas T echnology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas T echnology Corporation on April 1st 2003. These operations include microcomputer , logic, analog and discrete de vices, and[...]

MITSUBISHI 4-BIT SINGLE-CHIP MICROCOMPUTER 4500 SERIES 4513/4514 Group User’ s Man ual[...]

keep safety first in your circuit designs ! ● Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideratio[...]

Preface This user’s manual describes the hardware and instructions of Mitsubishi’s 4513/4514 Group CMOS 4-bit microcomputer. After reading this manual, the user should have a through knowledge of the functions and features of the 4513/4514 Group and should be able to fully utilize the product. The manual starts with specifications and ends with[...]

This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. 1. Organization CHAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function. CHAPTER 2 APPL IC ATION Th is ch apt e r d escr ibe s [...]

4513/4514 Group User’s Manual i T ab le of contents CHAPTER 1 HARDWARE DESCRIPTION ............................................................................................................................... . 1-3 FEATURES ..........................................................................................................................[...]

ii 4513/4514 Group User’s Manual CHAPTER 2 APPLICATION 2.1 I/O pins .................................................................................................................................... 2- 2 2.1.1 I/O ports .......................................................................................................................... 2- [...]

4513/4514 Group User’s Manual iii CHAPTER 3 APPENDIX 3.1 Electrical characteristics ..................................................................................................... 3- 2 3.1.1 Absolute maximum ratings ............................................................................................ 3- 2 3.1.2 Recommended operating [...]

iv 4513/4514 Group User’s Manual List of figures CHAPTER 1 HARDWARE PIN CONFIGURATION (TOP VIEW) 4513 Group ..................................................................... 1 -4 PIN CONFIGURATION (TOP VIEW) 4514 Group ............................................................ ......... 1- 5 BLOCK DIAGRAM (4513 Group) ......................[...]

4513/4514 Group User’s Manual v List of figures Fig. 42 Ceramic resonator external circuit ............................................................................... 1-58 Fig. 43 External clock input circuit ............................................................................................ 1-58 Fig. 44 External 0 interrupt program [...]

vi 4513/4514 Group User’s Manual CHAPTER 3 APPENDIX Fig. 3.2.1 A-D conversion characteristics data ........................................................................ 3-14 Fig. 44 External 0 interrupt program example ......................................................................... 3-21 Fig. 45 External 1 interrupt program example ..[...]

4513/4514 Group User’s Manual vii List of tables CHAPTER 1 HARDWARE Table Selection of system clock ................................................................................................ 1-11 Table 1 ROM size and pages .................................................................................................... 1-20 Table 2 RAM s[...]

viii 4513/4514 Group User’s Manual List of tables Table 2.5.1 A-D control register Q1 .......................................................................................... 2-50 Table 2.5.2 A-D control register Q2 .......................................................................................... 2-50 Table 2.5.3 Recommended operating [...]

CHAPTER 1 CHAPTER 1 HARD W ARE DESCRIPTION FEATURES APPLICATION PIN CONFIGURATION BLOCK DIAGRAM PERFORMANCE OVERVIEW PIN DESCRIPTION FUNCTION BLOCK OPERATIONS ROM ORDERING METHOD LIST OF PRECAUTIONS SYMBOL LIST OF INSTRUCTION FUNCTION INSTRUCTION CODE TABLE MACHINE INSTRUCTIONS CONTROL REGISTERS BUILT-IN PROM VERSION[...]

1-2 HARD W ARE 4513/4514 Group User’s Manual[...]

4513/4514 Group User’s Manual HARD W ARE 1-3 DESCRIPTION The 4513/4514 Group is a 4-bit single-chip microcomputer de- signed with CMOS technology . Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with serial I/O, four 8-bit timers (each timer has a reload register), and 10-bit A-D conv er te[...]

1-4 HARD W ARE 4513/4514 Group User’s Manual PIN CONFIGURA TION (T OP VIEW) 4513 Gr oup M34513Mx-XXXSP M34513E4SP 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P1 3 P1 2 P1 1 P1 0 P0 3 P0 2 P0 1 P0 0 A IN3 /CMP1+ A IN2 /CMP1- A IN1 /CMP0+ A IN0 /CMP0- P3 1 /INT1 P3 0 /INT0 VDCE V DD D 0 D 1 D 2 D 3 D 4 D 5[...]

4513/4514 Group User’s Manual HARD W ARE 1-5 PIN CONFIGURA TION (T OP VIEW) 4514 Gr oup P1 2 P1 1 P1 0 P0 3 P0 2 P0 1 P0 0 A IN3 /CMP1+ A IN2 /CMP1- A IN1 /CMP0+ A IN0 /CMP0- P3 1 /INT1 P3 0 /INT0 VDCE V DD M34514M x- XXXFP M34514E8FP Outl ine 42P2R- A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P1 3 D 1 D 2 D 3 D 4 D 5 D 6 /CNTR0 D 7 /CNTR1 P2 1 /S O[...]

1-6 HARD W ARE 4513/4514 Group User’s Manual BLOCK DIAGRAM (4513 Group) |[go 1 Voltage drop detection circuit 4 S e ria l I/O (8 b i ts ✕ 1) Voltage comparator (2 circuits) X IN –X OUT I/O port Internal peripheral functions Timer System clock generating circuit Watchdog timer (16 bits) Memory ROM 2048, 4096,6144, 8192 words × 10 bits RAM 128[...]

4513/4514 Group User’s Manual HARD W ARE 1-7 BLOCK DIAGRAM (4514 Group) Voltage drop detection circuit S e ria l I/O (8 b i ts ✕ 1) Voltage comparator (2 circuits) X IN —X OUT I/O port Internal peripheral functions Timer System clock generating circuit Watchdog timer (16 bits) Memory ROM 6144, 8192 words × 10 bits RAM 384 words × 4 bits 450[...]

1-8 HARD W ARE 4513/4514 Group User’s Manual PERFORMANCE O VERVIEW Function 123 128 0.75 µ s (at 4.0 MHz oscillation frequency , in high-speed mode) 2048 words ✕ 10 bits 4096 words ✕ 10 bits 6144 words ✕ 10 bits 8192 words ✕ 10 bits 6144 words ✕ 10 bits 8192 words ✕ 10 bits 128 words ✕ 4 bits 256 words ✕ 4 bits 384 words ✕ 4 bi[...]

4513/4514 Group User’s Manual HARD W ARE 1-9 PIN DESCRIPTION Name Power supply Ground V oltage drop detec- tion circuit enable CNV SS Reset input System clock input System clock output I/O port D (Input is examined by skip decision.) I/O port P0 I/O port P1 Input port P2 I/O port P3 I/O port P4 I/O port P5 Analog input Timer input/output Timer in[...]

1-10 HARD W ARE 4513/4514 Group User’s Manual Notes 1: Pins except above have just single function. 2: The input of D 6 , D 7 , P2 0 –P2 2 , CMP0-, CMP0+, CMP1-, CMP1+ and the input/output of P3 0 , P3 1 , P4 0 –P4 3 can be used even when CNTR0, CNTR1, S CK , S OUT , S IN , INT0, INT1, and A IN0 –A IN7 are selected. 3: The 4513 Group does n[...]

4513/4514 Group User’s Manual HARD W ARE 1-11 Notes 1: The 4513 Group does not have P3 2 and P3 3 . 2: The 4513 Group does not have these ports. DEFINITION OF CLOCK AND CYCLE ● System clock The system clock is the basic clock for controlling this product. The system clock is selected by the bit 3 of the clock control reg- ister MR. PORT FUNCTIO[...]

1-12 HARD W ARE 4513/4514 Group User’s Manual PORT BLOCK DIAGRAMS PIN DESCRIPTION D T Q Ai P0 0 ,P0 1 K0 0 PU 0 0 D T Ai P0 2 ,P0 3 K0 1 PU 0 1 D T Ai P1 0 ,P1 1 K0 2 PU 0 2 D T Ai P1 2 ,P 1 3 K0 3 PU 0 3 Key-on wakeup input Pull-up transistor OP0A instruction IAP0 instruction Key-on wakeup input Pull-up transistor OP0A instruction IAP0 instructi[...]

4513/4514 Group User’s Manual HARD W ARE 1-13 PORT BLOCK DIAGRAMS (continued) PIN DESCRIPTION Synchronous clock input for serial transfer Register A IAP2 instruction P2 0 /S CK J1 0 Synchronous clock output for serial transfer P3 0 /INT0,P3 1 /INT1 D T Q External interrupt circuit Register A Ai IAP3 instruction OP3A instruction J1 1 1 0 P2 1 /S O[...]

1-14 HARD W ARE 4513/4514 Group User’s Manual PORT BLOCK DIAGRAMS (continued) PIN DESCRIPTION A IN0 /CMP0- Q1 Q3 0 A IN1 /CMP0+ + - Q3 2 A IN2 /CMP1- Q3 1 A IN3 /CMP1+ + - Q3 3 OP4A instruction IAP4 instruction P4 0 /A IN4 –P4 3 /A IN7 D Q T Register A Ai Q1 Q1 Q1 Q1 Decoder Analog input Decoder Analog input Analog input Analog input Analog inp[...]

4513/4514 Group User’s Manual HARD W ARE 1-15 PORT BLOCK DIAGRAMS (continued) PIN DESCRIPTION P5 0 –P5 3 D T Q OP5A instruction Ai Register A IAP5 instruction D 0 –D 5 SD instruction S R Q Decoder Skip decision (SZD instruction) Register Y RD instruction D 6 /CNTR0 S R Q Skip decision (SZD instruction) SD instruction Decoder Register Y RD ins[...]

1-16 HARD W ARE 4513/4514 Group User’s Manual External interrupt circuit structure PIN DESCRIPTION 0 1 I2 2 0 1 EXF1 I2 1 SNZI1 P3 1 /INT1 0 1 I1 2 Wakeup Skip 0 1 EXF0 I1 1 SNZI0 P3 0 /INT0 Rising Falling One-sided edge detection circuit Both edges detection circuit External 0 interrupt External 1 interrupt Wakeup Skip Rising Falling One-sided e[...]

4513/4514 Group User’s Manual HARD W ARE 1-17 FUNCTION BLOCK OPERATIONS FUNCTION BLOCK OPERA TIONS CPU (1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit ar ithmetic such as 4- bit data addition, compar ison, AND oper ation, OR operation, and bit manipulation. (2) Register A and carry flag Register A is a 4-bit register [...]

1-18 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS (5) Stack registers (SK S ) and stack pointer (SP) Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when; • branching to an interrupt service routine (referred to as an int[...]

4513/4514 Group User’s Manual HARD W ARE 1-19 FUNCTION BLOCK OPERATIONS (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instr uction b ytes each time an instruction is ex ec[...]

1-20 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS PROGRAM MEMOY (ROM) The program memory is a mask ROM. 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). T able 1 shows the R OM size and pages . Fig- ure 10 shows the ROM map of M34514M8/E8. T ab le 1 ROM siz e an[...]

4513/4514 Group User’s Manual HARD W ARE 1-21 FUNCTION BLOCK OPERATIONS D A T A MEMOR Y (RAM) 1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memor y area. A RAM address is specified b y a data pointer . The data pointer consists of registers Z, X, and Y . Set a v[...]

1-22 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS INTERRUPT FUNCTION The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interr upt source. An interrupt occurs when the following 3 conditions are satisfied. • An interr upt activ ated condition is satisfied (re[...]

4513/4514 Group User’s Manual HARD W ARE 1-23 FUNCTION BLOCK OPERATIONS (4) Internal state during an interrupt The internal state of the microcomputer during an interrupt is as follows (Figure 14). • Program counter (PC) An interrupt address is set in program counter. The address to be executed when returning to the main routine is automaticall[...]

1-24 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS (6) Interrupt control registers • Interrupt control register V1 Interrupt enable bits of external 0, external 1, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The T A V1 instr uction can be u[...]

4513/4514 Group User’s Manual HARD W ARE 1-25 FUNCTION BLOCK OPERATIONS (7) Interrupt sequence Interrupts only occur when the respective INTE flag, interrupt en- able bits (V1 0 –V1 3 and V2 0 –V2 3 ), and interrupt request flag are “1. ” The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are[...]

1-26 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS T able 7 External interrupt activated conditions Name External 0 interrupt External 1 interrupt Input pin P3 0 /INT0 P3 1 /INT1 Activated condition When the next waveform is input to P3 0 /INT0 pin • Falling waveform (“H” → “L”) • Rising waveform (“L” → ?[...]

4513/4514 Group User’s Manual HARD W ARE 1-27 FUNCTION BLOCK OPERATIONS (1) External 0 interrupt request flag (EXF0) External 0 interrupt request flag (EXF0) is set to “1” when a valid waveform is input to P3 0 /INT0 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock ([...]

1-28 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS (3) External interrupt control registers • Interrupt control register I1 Register I1 controls the valid waveform for the external 0 inter- rupt. Set the contents of this register through register A with the TI1A instruction. The T AI1 instruction can be used to tr ansfer th[...]

4513/4514 Group User’s Manual HARD W ARE 1-29 FUNCTION BLOCK OPERATIONS TIMERS The 4513/4514 Group has the programmable timers. • Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt re-[...]

1-30 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS Count source • Instruction clock • Prescaler output (ORCLK) • Timer 1 underflow • Prescaler output (ORCLK) • CNTR0 input • 16-bit timer underflow • Timer 2 underflow • Prescaler output (ORCLK) • Timer 3 underflow • Prescaler output (ORCLK) • CNTR1 input [...]

4513/4514 Group User’s Manual HARD W ARE 1-31 FUNCTION BLOCK OPERATIONS Fig. 19 Timers structure T4F T3F 10 01 00 W3 1 ,W3 0 0 1 W3 3 (Note 3) 0 1 W4 3 (Note 3) 11 T1F (T2AB) T2F (TAB2) 0 1 W2 3 (Note 3) 0 1 (Note 3) W1 1 (TR1AB) T1AB T1AB (TAB1) (T4AB) (TAB4) (TR3AB) T3AB T3AB (TAB3) Q R S 1 - - - - - - - - - - - 15 16 WDF1 WDF2 WEF 10 01 00 W2 [...]

1-32 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS T able 10 Timer control register s 0 1 0 1 0 1 0 1 W2 1 0 0 1 1 Stop (state initialized) Operating Instruction clock divided by 4 Instruction clock divided by 16 Stop (state retained) Operating Count start synchronous circuit not selected Count start synchronous circuit selec[...]

4513/4514 Group User’s Manual HARD W ARE 1-33 FUNCTION BLOCK OPERATIONS (1) Timer control register s • Timer control register W1 Register W1 controls the count operation of timer 1, the selection of count start synchronous circuit, and the frequency dividing ra- tio and count operation of prescaler . Set the contents of this register through re[...]

1-34 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS (6) Timer 3 (interrupt function) Timer 3 is an 8-bit binar y down counter with the timer 3 reload reg- ister (R3). Data can be set simultaneously in timer 3 and the reload register (R3) with the T3AB instr uction. Data can be written to re- load register (R3) with the TR3AB i[...]

4513/4514 Group User’s Manual HARD W ARE 1-35 FUNCTION BLOCK OPERATIONS W A TCHDOG TIMER Watchdog timer pro vides a method to reset the system when a pro- gram runs wild. W atchdog timer consists of a 16-bit timer (WDT), watchdog timer enable flag (WEF), and watchdog timer flags (WDF1, WDF2). The timer WDT downcounts the instruction clocks as the[...]

1-36 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS SERIAL I/O The 4513/4514 Group has a built-in clock synchronous serial I/O which can serially transmit or receive 8-bit data. Serial I/O consists of; • serial I/O register SI • serial I/O mode register J1 • serial I/O transmission/reception completion flag (SIOF) • se[...]

4513/4514 Group User’s Manual HARD W ARE 1-37 FUNCTION BLOCK OPERATIONS Fig. 23 Serial I/O register state when transferring (1) Serial I/O register SI Serial I/O register SI is the 8-bit data transfer serial/parallel conver- sion register . Data can be set to register SI through registers A and B with the TSIAB instruction. The contents of regist[...]

1-38 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS (5) How to use serial I/O Figure 24 shows the serial I/O connection example. Serial I/O inter- rupt is not used in this example. In the actual wiring, pull up the wir ing betw een each pin with a resistor . Figure 25 shows the data transfer timing and T able 13 sho ws the dat[...]

4513/4514 Group User’s Manual HARD W ARE 1-39 FUNCTION BLOCK OPERATIONS Fig. 25 Timing of serial I/O data transfer S IN S OUT SCK S OUT S IN S 0 S 7 ’S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 0 S 7 ’ S 1 S 3 S 4 S 5 S 6 S 7 M 0 M 7 ’ M 1 M 2 M 3 M 4 M 5 M 6 M 7 M 0 M 7 ’M 1 M 2 M 3 M 4 M 5 M 6 M 7 S 2 M 0 –M 7 : the contents of master serial I/O S [...]

1-40 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS T able 13 Processing sequence of data transfer fr om master to slave 1-b yte data is serially transf erred on this process. Subsequently , data can be transferred continuously by repeating the process from *. When an external clock is selected as a synchronous clock, the cloc[...]

4513/4514 Group User’s Manual HARD W ARE 1-41 FUNCTION BLOCK OPERATIONS A-D CONVERTER The 4513/4514 Group has a built-in A-D conversion circuit that performs conversion by 10-bit successive comparison method. T able 14 shows the characteristics of this A-D conv er ter . This A- D converter can also be used as an 8-bit comparator to compare analog[...]

1-42 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS Q1 3 Q1 2 Q1 1 Q1 0 A-D control register Q1 Not used Analog input pin selection bits (Note 2) at reset : 0000 2 at RAM back-up : state retained 0 1 Q1 2 0 0 0 0 1 1 1 1 Q1 1 0 0 1 1 0 0 1 1 This bit has no function, but read/write is enabled. Selected pins A IN0 A IN1 A IN2 A[...]

4513/4514 Group User’s Manual HARD W ARE 1-43 FUNCTION BLOCK OPERATIONS T able 16 Change of successive comparison register AD during A-D con version Comparison v oltage (V ref ) value Change of successive comparison register AD At starting conversion ± ± ± ± ± (7) Operation description A-D conv ersion is star ted with the A-D con version sta[...]

1-44 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS Fig. 28 Setting registers 0 ✕✕ 1 (Bit 3) (Bit 0) A-D control register Q2 A IN4 function selected A-D conversion mode A-D control register Q1 A IN4 pin selected ✕ 100 (Bit 3) (Bit 0) ✕ : Set an arbitrary value (8) A-D con version timing char t Figure 27 shows the A-D c[...]

4513/4514 Group User’s Manual HARD W ARE 1-45 FUNCTION BLOCK OPERATIONS (10) Operation at comparator mode The A-D con verter is set to comparator mode by setting bit 3 of the register Q2 to “1.” Belo w , the operation at comparator mode is described. (11) Comparator register In comparator mode, the built-in DA comparator is connected to the c[...]

1-46 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS (15) Notes f or the use of A-D conver sion 2 Do not change the operating mode (both A-D conv ersion mode and comparator mode) of A-D conv erter with bit 3 of register Q2 while A-D converter is operating. When the operating mode of A-D con ver ter is changed from the comparato[...]

4513/4514 Group User’s Manual HARD W ARE 1-47 FUNCTION BLOCK OPERATIONS V OL T A GE COMP ARA T OR The 4513/4514 Group has 2 voltage comparator circuits that perform compar ison of v oltage betw een 2 pins. T able 17 sho ws the characteristics of this voltage comparison. T able 17 V oltage comparator characteristics Characteristics 2 circuits (CMP[...]

1-48 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS V oltage compar ator control register Q3 (Note 2) at reset : 0000 2 at RAM back-up : state retained Q3 3 Q3 2 Q3 1 Q3 0 V oltage comparator (CMP1) in valid V oltage comparator (CMP1) v alid V oltage comparator (CMP0) in valid V oltage comparator (CMP0) v alid CMP1- > CMP1+[...]

4513/4514 Group User’s Manual HARD W ARE 1-49 FUNCTION BLOCK OPERATIONS RESET FUNCTION System reset is performed by applying “L” level to RESET pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions. Then when “H” level is [...]

1-50 HARD W ARE 4513/4514 Group User’s Manual FUNCTION BLOCK OPERATIONS (1) Power-on reset Reset can be performed automatically at power on (power-on re- set) by connecting resistors, a diode, and a capacitor to RESET pin. Connect RESET pin and the external circuit at the shortest dis- tance. Fig. 34 Power-on reset circuit example (2) Internal st[...]

4513/4514 Group User’s Manual HARD W ARE 1-51 FUNCTION BLOCK OPERATIONS • Program counter (PC) ......................................................................................................... . Address 0 in page 0 is set to prog ram counter . • Interrupt enable flag (INTE) .............................................................[...]

1-52 HARD W ARE 4513/4514 Group User’s Manual V OL T A GE DR OP DETECTION CIRCUIT The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value. Fig. 37 V oltage dr op detection cir cuit operation waveform Fig. 36 V olta ge drop detection reset cir [...]

4513/4514 Group User’s Manual HARD W ARE 1-53 RAM BACK-UP MODE The 4513/4514 Group has the RAM back-up mode. When the EPOF and POF instructions are e xecuted continuously , system enters the RAM back-up state. The POF instruction is equal to the NOP instruction when the EPOF instruction is not ex- ecuted before the POF instruction. As oscillation[...]

1-54 HARD W ARE 4513/4514 Group User’s Manual (4) Return signal An external wakeup signal is used to return from the RAM back-up mode because the oscillation is stopped. T able 21 shows the retur n condition for each return source. (5) Ports P0 and P1 control registers • Key-on wakeup control register K0 Register K0 controls the ports P0 and P1[...]

4513/4514 Group User’s Manual HARD W ARE 1-55 Fig. 38 State transition Fig. 39 Set source and clear source of the P flag Fig. 40 Start condition identified example using the SNZP in- struction S R Q Power down flag P POF instruction Reset input or voltage drop detection circuit output ● Set source POF instruction is executed ● Clear source Re[...]

1-56 HARD W ARE 4513/4514 Group User’s Manual T able 22 K ey-on wakeup control register , pull-up control register , and interrupt contr ol register K0 3 K0 2 K0 1 K0 0 Key-on wakeup control register K0 PU0 3 PU0 2 PU0 1 PU0 0 Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup [...]

4513/4514 Group User’s Manual HARD W ARE 1-57 CLOCK CONTROL The clock control circuit consists of the following circuits. • System clock generating circuit • Control circuit to stop the clock oscillation Fig. 41 Clock control circuit structure T able 23 Clock control register MR Note : “R” represents read enabled, and “W” represents w[...]

1-58 HARD W ARE 4513/4514 Group User’s Manual Clock signal f(X IN ) is obtained by externally connecting a ceramic resonator . Connect this external circuit to pins X IN and X OUT at the shortest distance. A feedbac k resistor is built in betw een pins X IN and X OUT . When an external clock signal is input, connect the clock source to X IN and l[...]

4513/4514 Group User’s Manual HARD W ARE 1-59 LIST OF PRECAUTIONS ➀ Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up; • connect a bypass capacitor (approx. 0.1 µ F) between pins V DD and V SS at the shortest distance, • equalize its wiring in width and length, and • use relatively[...]

1-60 HARD W ARE 4513/4514 Group User’s Manual ➉ A-D converter-1 When the operating mode of the A-D converter is changed from the comparator mode to the A-D conversion mode with the bit 3 of register Q2 in a program, be careful about the following notes. • Clear the bit 2 of register V2 to “0” to change the operating mode of the A-D conver[...]

4513/4514 Group User’s Manual HARD W ARE 1-61 16 V oltage compar ator function When the voltage comparator function is valid with the voltage comparator control register Q3, it is operating even in the RAM back-up mode . Accordingly , be careful about such state because it causes the increase of the operation current in the RAM back- up mode. In [...]

1-62 HARD W ARE 4513/4514 Group User’s Manual SYMBOL The symbols shown below are used in the following instruction function table and instruction list. Symbol A B DR E Q1 Q2 Q3 AD J1 SI V1 V2 I1 I2 W1 W2 W3 W4 W6 MR K0 PU0 FR0 X Y Z DP PC PC H PC L SK SP CY R1 R2 R3 R4 T1 T2 T3 T4 Contents Register A (4 bits) Register B (4 bits) Register D (3 bit[...]

4513/4514 Group User’s Manual HARD W ARE 1-63 LIST OF INSTRUCTION FUNCTION Group- ing RAM addresses Function (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15 (PC L ) ← a 6 –a 0 (PC H ) ← p (PC L ) ← a 6 –a 0 (PC H ) ← p (PC L ) ← (DR 2 –DR 0 , A 3 –A 0 ) (SP) ←[...]

1-64 HARD W ARE 4513/4514 Group User’s Manual LIST OF INSTRUCTION FUNCTION (continued) Function (T1F) = 1 ? After skipping (T1F) ← 0 (T2F) = 1 ? After skipping (T2F) ← 0 (T3F) = 1 ? After skipping (T3F) ← 0 (T4F) = 1 ? After skipping (T4F) ← 0 (A) ← (P0) (P0) ← (A) (A) ← (P1) (P1) ← (A) (A 2 –A 0 ) ← (P2 2 –P2 0 ) (A 3 ) ←[...]

4513/4514 Group User’s Manual HARD W ARE 1-65 LIST OF INSTRUCTION FUNCTION (continued ) Mnemonic TK0A T AK0 TPU0A T APU0 TFR0A* T ABSI TSIAB T AJ1 TJ1A SST SNZSI Function (K0) ← (A) (A) ← (K0) (PU0) ← (A) (A) ← (PU0) (FR0) ← (A) (A) ← (SI 3 –SI 0 ) (B) ← (SI 7 –SI 4 ) (SI 3 –SI 0 ) ← (A) (SI 7 –SI 4 ) ← (B) (A) ← (J1) [...]

1-66 HARD W ARE 4513/4514 Group User’s Manual INSTR UCTION CODE T ABLE (f or 4513 Gr oup) D 3 –D 0 Hex. notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F D 9 –D 4 00 NOP – POF SNZP DI EI RC SC – – AM AMC TY A – TBA – 000001 01 BLA CLD – INY RD SD – DEY AND OR[...]

4513/4514 Group User’s Manual HARD W ARE 1-67 INSTR UCTION CODE T ABLE (contin ued) (f or 4513 Group) – – TJ1A – TQ1A TQ2A TQ3A – – – – – – – TW1A TW2A TW3A TW4A – TW6A – – TMRA TI1A TI2A – – TK0A – – – – T1AB T2AB T3AB T4AB – – – – TSIAB TA D A B – TR3AB – – – TR1AB – – T AJ1 – TA Q 1 T[...]

1-68 HARD W ARE 4513/4514 Group User’s Manual INSTR UCTION CODE T ABLE (f or 4514 Group) NOP – POF SNZP DI EI RC SC – – AM AMC TY A – TBA – BLA CLD – INY RD SD – DEY AND OR TEAB – CMA RAR TA B TA Y SZB 0 SZB 1 SZB 2 SZB 3 SZD SEAn SEAM – – TDA T ABE – – – – SZC BMLA – – – – – – – SNZ0 SNZ1 SNZI0 SNZI1 –[...]

4513/4514 Group User’s Manual HARD W ARE 1-69 INSTR UCTION CODE T ABLE ( contin ued ) (f or 4514 Group) – – TJ1A – TQ1A TQ2A TQ3A – – – – – – – TW1A TW2A TW3A TW4A – TW6A – – TMRA TI1A TI2A – – TK0A – – – – T1AB T2AB T3AB T4AB – – – – TSIAB TA D A B – TR3AB – – – TR1AB – – T AJ1 – TA Q 1[...]

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation 1-70 HARD W ARE 4513/4514 Group User’s Manual MACHINE INSTRUCTIONS (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) (E 7 –E 4 ) ← (B) (E 3 –E 0 ) ← (A) (B) ← (E 7 –E 4 ) (A) ←[...]

Skip condition Datailed description Carry flag CY 4513/4514 Group User’s Manual HARD W ARE 1-71 MACHINE INSTRUCTIONS T ransfers the contents of register B to register A. T ransfers the contents of register A to register B . T ransfers the contents of register Y to register A. T ransfers the contents of register A to register Y . T ransfers the co[...]

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation 1-72 HARD W ARE 4513/4514 Group User’s Manual MACHINE INSTRUCTIONS Note : p is 0 to 1 5 for M34513M2, p is 0 to 31 for M34513M4/E4, p is 0 to 47 for M34513M6 and M34514M6, and p is 0 to 63[...]

Skip condition Datailed description Carry flag CY 4513/4514 Group User’s Manual HARD W ARE 1-73 MACHINE INSTRUCTIONS Continuous description – – – Overflow = 0 – – – – (CY) = 0 – – – – (Mj(DP)) = 0 j = 0 to 3 (A) = (M(DP)) (A) = n – – – 0/1 – – – 1 0 – – 0/1 – – – – – Loads the value n in the immedia[...]

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation 1-74 HARD W ARE 4513/4514 Group User’s Manual MACHINE INSTRUCTIONS B a BL p, a BLA p BM a BML p, a BMLA p RT I RT RT S DI EI SNZ0 SNZ1 01 1a 6 a 5 a 4 a 3 a 2 a 1 a 0 00 111p 4 p 3 p 2 p 1[...]

Skip condition Datailed description Carry flag CY 4513/4514 Group User’s Manual HARD W ARE 1-75 MACHINE INSTRUCTIONS – – – – – – – – Skip at uncondition – – (EXF0) = 1 (EXF1) = 1 Branch within a page : Branches to address a in the identical page. Branch out of a page : Branches to address a in page p. Branch out of a page : Br[...]

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation 1-76 HARD W ARE 4513/4514 Group User’s Manual MACHINE INSTRUCTIONS MACHINE INSTRUCTIONS (continued ) SNZI0 SNZI1 TAV 1 TV1A TAV 2 TV2A T AI1 TI1A T AI2 TI2A TAW 1 TW1A TAW 2 TW2A TAW 3 TW3[...]

Skip condition Datailed description Carry flag CY 4513/4514 Group User’s Manual HARD W ARE 1-77 MACHINE INSTRUCTIONS When bit 2 (I1 2 ) of register I1 is “1” : Skips the next instruction when the level of INT0 pin is “H.” When bit 2 (I1 2 ) of register I1 is “0” : Skips the next instruction when the level of INT0 pin is “L.” When [...]

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation 1-78 HARD W ARE 4513/4514 Group User’s Manual MACHINE INSTRUCTIONS MACHINE INSTRUCTIONS (continued ) T AB1 T1AB T AB2 T2AB T AB3 T3AB T AB4 T4AB TR1AB TR3AB SNZT1 SNZT2 SNZT3 SNZT4 1 1 1 1[...]

Skip condition Datailed description Carry flag CY 4513/4514 Group User’s Manual HARD W ARE 1-79 MACHINE INSTRUCTIONS – – – – – – – – – – – – – – – – – – – – – – – – (T1F) = 1 (T2F) =1 (T3F) = 1 (T4F) = 1 T ransfers the contents of timer 1 to registers A and B. T ransfers the contents of registers A [...]

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation 1-80 HARD W ARE 4513/4514 Group User’s Manual MACHINE INSTRUCTIONS MACHINE INSTRUCTIONS (continued ) IAP0 OP0A IAP1 OP1A IAP2 IAP3 OP3A IAP4* OP4A* IAP5* OP5A* CLD RD SD SZD TK0A T AK0 TPU[...]

Skip condition Datailed description Carry flag CY 4513/4514 Group User’s Manual HARD W ARE 1-81 MACHINE INSTRUCTIONS – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – (D(Y)) = 0 (Y) = 0 to 7 – – – – – T ransfers the input of port P0 to register A. Outp[...]

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation 1-82 HARD W ARE 4513/4514 Group User’s Manual MACHINE INSTRUCTIONS MACHINE INSTRUCTIONS (continued ) T ABSI TSIAB T AJ1 TJ1A SST SNZSI T ABAD T ALA TA D A B TA Q 1 TQ1A ADST SNZAD TA Q 2 T[...]

Skip condition Datailed description Carry flag CY 4513/4514 Group User’s Manual HARD W ARE 1-83 MACHINE INSTRUCTIONS – – – – – (SIOF) = 1 – – – – – – (ADF) = 1 – – – – – (P) = 1 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – T ransfers the content[...]

1-84 HARD W ARE 4513/4514 Group User’s Manual V1 3 V1 2 V1 1 V1 0 V2 3 V2 2 V2 1 V2 0 Serial I/O interrupt enable bit A-D interrupt enable bit Timer 4 interrupt enab le bit Timer 3 interrupt enab le bit Interrupt control register V1 Timer 2 interrupt enab le bit Timer 1 interrupt enab le bit External 1 interrupt enable bit External 0 interrupt en[...]

4513/4514 Group User’s Manual HARD W ARE 1-85 0 1 0 1 0 1 0 1 W2 1 0 0 1 1 Stop (state initialized) Operating Instruction clock divided by 4 Instruction clock divided by 16 Stop (state retained) Operating Count start synchronous circuit not selected Count start synchronous circuit selected Prescaler control bit Prescaler dividing ratio selection [...]

1-86 HARD W ARE 4513/4514 Group User’s Manual Selected pins A IN0 A IN1 A IN2 A IN3 A IN4 (Not available for the 4513 Group) A IN5 (Not available for the 4513 Group) A IN6 (Not available for the 4513 Group) A IN7 (Not available for the 4513 Group) This bit has no function, but read/write is enabled. Instruction clock signal divided by 8 Instructi[...]

4513/4514 Group User’s Manual HARD W ARE 1-87 K0 3 K0 2 K0 1 K0 0 Key-on wakeup control register K0 PU0 3 PU0 2 PU0 1 PU0 0 Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Pins P1 2 and P1 3 key-on wakeup control bit Pins P1 0 a[...]

1-88 HARD W ARE 4513/4514 Group User’s Manual T able 25 Product of built-in PR OM version Product M34513E4SP/FP M34513E8FP M34514E8FP ROM type One Time PR OM version [shipped in blank] PROM size ( ✕ 10 bits) 4096 words 8192 words 8192 words RAM size ( ✕ 4 bits) 256 words 384 words 384 words Package SP: 32P4B FP: 32P6B-A 32P6B-A 42P2R-A Fig. 4[...]

4513/4514 Group User’s Manual HARD W ARE 1-89 Fig. 52 Flow of writing and test of the product shipped in blank Fig. 51 PROM memory map (1) PROM mode The built-in PROM version has a PROM mode in addition to a nor- mal operation mode. The PR OM mode is used to write to and read from the built-in PROM. In the PROM mode, the programming adapter can b[...]

1-90 HARD W ARE 4513/4514 Group User’s Manual BUILT-IN PROM VERSION[...]

CHAPTER 2 CHAPTER 2 APPLICA TION 2.1 I/O pins 2.2 Interrupts 2.3 Timers 2.4 Serial I/O 2.5 A-D converter 2.6 Voltage comparator 2.7 Reset 2.8 Voltage drop detection circuit 2.9 RAM back-up 2.10 Oscillation circuit[...]

2-2 APPLICA TION 2.1 I/O pins 4513/4514 Group User’s Manual 2.1 I/O pins The 4513/4514 Group has the twenty-eight I/O pins (eighteen I/O pins for 4513 Group), three input pins. (Ports P2 0 –P2 2 , P3 0 , P3 1 , D 6 and D 7 are also used as serial I/O pins S CK , S OUT , S IN , and INT0, INT1, CNTR0 and CNTR1 pins, respectively). This section de[...]

4513/4514 Group User’s Manual APPLICA TION 2-3 2.1 I/O pins (4) Port P3 Port P3 is a 4-bit I/O port for the 4514 Group, and a 2-bit I/O port for the 4513 Group. ■ Input/output of port P3 ● ● ● ● Data input to port P3 Set the output latch of specified port P3i (i=0 to 3) to “1” with the OP3A instruction. If the output latch is set to[...]

2-4 APPLICA TION 2.1 I/O pins 4513/4514 Group User’s Manual (7) Port D D 0 –D 7 are eight independent I/O ports. ■ Input/output of port D Each pin of port D has an independent 1-bit wide I/O function. For I/O of ports D 0 –D 7 , select one of port D with the register Y of the data pointer first. ● Data input to port D Set the output latch[...]

4513/4514 Group User’s Manual APPLICA TION 2-5 2.1 I/O pins (2) Key-on wakeup control register K0 Register K0 controls the ON/OFF of the key-on wakeup function of ports P0 0 –P0 3 and P1 0 –P1 3 . Set the contents of this register through register A with the TK0A instruction. The contents of register K0 is transferred to register A with the T[...]

2-6 APPLICA TION 2.1 I/O pins 4513/4514 Group User’s Manual (4) Direction register FR0 (The 4513 Group does not have this register.) Register FR0 is used to switch to input/output of P5 0 –P5 3 . Set the contents of this register through register A with the TFR0A instruction. Table 2.1.4 shows the direction register FR0. Table 2.1.4 Direction r[...]

4513/4514 Group User’s Manual APPLICA TION 2-7 2.1 I/O pins 2.1.3 Port application examples (1) Key input by key scan Key matrix can be set up by connecting keys externally because port D output structure is an N- channel open-drain and port P0 has the pull-up resistor. Outline: The connecting required external part is just keys. Specifications: [...]

2-8 APPLICA TION 2.1 I/O pins 4513/4514 Group User’s Manual Fig. 2.1.2 Key scan input timing D 0 D 1 D 2 D 3 IAP0 IAP0 IAP0 IAP0 IAP0 “H” “L” “H” “L” “H” “L” “H” “L” Input to SW1–SW4 Input to SW13–SW16 Input to SW9–SW12 Input to SW5–SW8 Input to SW1–SW4 Key input period Switching key input selection port [...]

4513/4514 Group User’s Manual APPLICA TION 2-9 2.1 I/O pins 2.1.4 Notes on use (1) Note when an I/O port except port P5 is used as an input port Set the output latch to “1” and input the port value before input. If the output latch is set to “0,” “L” level can be input. (2) Noise and latch-up prevention Connect an approximate 0.1 µ F[...]

2-10 APPLICA TION 2.1 I/O pins 4513/4514 Group User’s Manual Table 2.1.6 connections of unused pins Pin X OUT VDCE D 0 –D 5 D 6 /CNTR0 D 7 /CNTR1 P2 0 /S CK P2 1 /S OUT P2 2 /S IN P3 0 /INT0 P3 1 /INT1 P3 2 , P3 3 P4 0 /A IN4 –P4 3 /A IN7 P5 0 –P5 3 ( Note 1 ) A IN0 /CMP0- A IN1 /CMP0+ A IN2 /CMP1- A IN3 /CMP1+ P0 0 –P0 3 P1 0 –P1 3 Con[...]

APPLICA TION 2.2 Interrupts 2-11 4513/4514 Group User’s Manual 2.2 Interrupts The 4513/4514 Group has eight interrupt sources : external (INT0, INT1), timer 1, timer 2, timer 3, timer 4, A-D, and serial I/O. This section describes individual types of interrupts, related registers, application examples using interrupts and notes. 2.2.1 Interrupt f[...]

APPLICA TION 2.2 Interrupts 2-12 4513/4514 Group User’s Manual (4) Timer 2 interrupt The interrupt request occurs by the timer 2 underflow. ■ Timer 2 interrupt processing ● When the interrupt is used The interrupt occurrence is enabled when the bit 3 of the interrupt control register V1 and the interrupt enable flag INTE are set to “1.” W[...]

APPLICA TION 2.2 Interrupts 2-13 4513/4514 Group User’s Manual (7) A-D interrupt The interrupt request occurs by the end of the A-D conversion. ■ A-D interrupt processing ● When the interrupt is used The interrupt occurrence is enabled when the bit 2 of the interrupt control register V2 and the interrupt enable flag INTE are set to “1.” W[...]

APPLICA TION 2.2 Interrupts 2-14 4513/4514 Group User’s Manual (2) Interrupt control register V1 Interrupt enable bits of external 0, external 1, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. In addition, the TAV1 instruction can be used to transfer the contents of[...]

APPLICA TION 2.2 Interrupts 2-15 4513/4514 Group User’s Manual Interrupt control register I1 at reset : 0000 2 at RAM back-up : state retained R/W This bit has no function, but read/write is enabled. Falling waveform (“L” level of INT0 pin is recognized with the SNZI0 instruction)/“L” level Rising waveform (“H” level of INT0 pin is re[...]

APPLICA TION 2.2 Interrupts 2-16 4513/4514 Group User’s Manual 2.2.3 Interrupt application examples (1) External 0 interrupt The INT0 pin is used for external 0 interrupt, of which valid waveforms can be chosen, which can recognize the change of both edges (“H” → “L” or “L” → “H”). Outline: An external 0 interrupt can be used [...]

APPLICA TION 2.2 Interrupts 2-17 4513/4514 Group User’s Manual (6) Timer 4 interrupt Constant period interrupts by a setting value to timer 4 can be used. Outline: The constant period interrupts by the timer 4 underflow signal can be used. Specifications: Prescaler, timer 3 and timer 4 divide the system clock frequency f(X IN ) = 4.0 MHz, and the[...]

APPLICA TION 2.2 Interrupts 2-18 4513/4514 Group User’s Manual Fig. 2.2.2 INT0 interrupt setting example Note: The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more of system clock. ➁ Set Port Port used for INT0 interrupt is set to input port. 0 b3 b0 b3 b0 ✕ 1 ✕✕ Both edges detection selected ( TI[...]

APPLICA TION 2.2 Interrupts 2-19 4513/4514 Group User’s Manual Fig. 2.2.3 INT1 interrupt operation example P3 1 /INT1 P3 1 /INT1 “H” “H” “L” “L” An interrupt occurs after the valid waveform “falling” is detected. An interrupt occurs after the valid waveform “rising” is detected.[...]

APPLICA TION 2.2 Interrupts 2-20 4513/4514 Group User’s Manual Fig. 2.2.4 INT1 interrupt setting example Note: The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more of system clock. ➁ Set Port Port used for INT1 interrupt is set to input port. 0 b3 b0 b3 b0 ✕ 1 ✕✕ Both edges detection selected ( TI[...]

APPLICA TION 2.2 Interrupts 2-21 4513/4514 Group User’s Manual Fig. 2.2.5 Timer 1 constant period interrupt setting example b3 b0 01 b3 b0 1 g0 h b3 b0 1 11 0 0 b3 b0 ➀ Disable Interrupts Timer 1 interrupt is temporarily disabled. Interrupt enable flag INTE Interrupt control register V1 “0” ✕✕ ✕ All interrupts disabled ( DI instructio[...]

APPLICA TION 2.2 Interrupts 2-22 4513/4514 Group User’s Manual Fig. 2.2.6 Timer 2 constant period interrupt setting example 0 b3 b0 ➀ Disable Interrupts Timer 2 interrupt is temporarily disabled. Interrupt enable flag INTE Interrupt control register V1 “0” ✕✕ ✕ All interrupts disabled ( DI instruction) Timer 2 interrupt occurrence dis[...]

APPLICA TION 2.2 Interrupts 2-23 4513/4514 Group User’s Manual Fig. 2.2.7 Timer 3 constant period interrupt setting example g0 h 0 b3 b0 ➀ Disable Interrupts Timer 3 interrupt is temporarily disabled. Interrupt enable flag INTE Interrupt control register V2 “0” ✕✕ ✕ All interrupts disabled ( DI instruction) Timer 3 interrupt occurrenc[...]

APPLICA TION 2.2 Interrupts 2-24 4513/4514 Group User’s Manual Fig. 2.2.8 Timer 4 constant period interrupt setting example 0 b3 b0 ➀ Disable Interrupts Timer 4 interrupt is temporarily disabled. Interrupt enable flag INTE Interrupt control register V2 “0” ✕✕ ✕ All interrupts disabled ( DI instruction) Timer 4 interrupt occurrence dis[...]

APPLICA TION 2.2 Interrupts 2-25 4513/4514 Group User’s Manual 2.2.4 Notes on use (1) Setting of INT0 interrupt valid waveform Depending on the input state of P3 0 /INT0 pin, the external interrupt request flag (EXF0) may be set to “1” when the interrupt valid waveform is changed. Accordingly, set a value to the bit 2 of register I1, and exec[...]

APPLICA TION 2.3 Timers 2-26 4513/4514 Group User’s Manual 2.3 Timer s The 4513/4514 Group has four 8-bit timers (each has a reload register) and a 16-bit fixed dividing frequency timer which has the watchdog timer function. This section describes individual types of timers, related registers, application examples using timers and notes. 2.3.1 Ti[...]

APPLICA TION 2.3 Timers 2-27 4513/4514 Group User’s Manual 2.3.2 Related registers (1) Interrupt control register V1 The timer 1 interrupt enable bit is assigned to bit 2, and the timer 2 interrupt enable bit is assigned to bit 3. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to t[...]

APPLICA TION 2.3 Timers 2-28 4513/4514 Group User’s Manual (3) Timer control register W1 The timer 1 count start synchronous circuit control bit is assigned to bit 0, the timer 1 control bit is assigned to bit 1, the prescaler dividing ratio selection bit is assigned to bit 2, and the prescaler control bit is assigned to bit 3. Set the contents o[...]

APPLICA TION 2.3 Timers 2-29 4513/4514 Group User’s Manual (5) Timer control register W3 The timer 3 count source selection bits are assigned to bits 0 and 1, the timer 3 count start synchronous circuit control bit is assigned to bit 2 and the timer 3 control bit is assigned to bit 3. Set the contents of this register through register A with the [...]

APPLICA TION 2.3 Timers 2-30 4513/4514 Group User’s Manual 2.3.3 Timer application examples (1) Timer operation: measurement of constant period The constant period by the setting timer count value can be measured. Outline: The constant period by the timer 1 underflow signal can be measured. Specifications: Timer 1 and prescaler divides the system[...]

APPLICA TION 2.3 Timers 2-31 4513/4514 Group User’s Manual (4) CNTR1 output control: square wave output control Outline: The output/stop of square wave from timer 3 every timer 4 underflow can be controlled. Specifications: 4 kHz square wave is output from timer 3 at system clock fr equency f(X IN ) = 4.0 MHz. Also, timer 4 controls ON/OFF of squ[...]

APPLICA TION 2.3 Timers 2-32 4513/4514 Group User’s Manual Fig. 2.3.3 Constant period measurement setting example g0 h 0 b3 b0 ➀ Disable Interrupts Timer 1 interrupt is temporarily disabled. Interrupt enable flag INTE Interrupt control register V1 “0” ✕✕ ✕ All interrupts disabled ( DI instruction) Timer 1 interrupt occurrence disabled[...]

APPLICA TION 2.3 Timers 2-33 4513/4514 Group User’s Manual Fig. 2.3.4 CNTR0 output setting example g0 h 0 b3 b0 ➀ Disable Interrupts Timer 1 interrupt is temporarily disabled. Interrupt enable flag INTE Interrupt control register V1 “0” ✕✕ ✕ All interrupts disabled ( DI instruction) Timer 1 interrupt occurrence disabled ( TV1A instruc[...]

APPLICA TION 2.3 Timers 2-34 4513/4514 Group User’s Manual 0 b3 b0 ➀ Disable Interrupts Timer 2 interrupt is temporarily disabled. Interrupt enable flag INTE Interrupt control register V1 “0” ✕✕ ✕ All interrupts disabled ( DI instruction) Timer 2 interrupt occurrence disabled ( TV1A instruction) b3 b0 00 ➁ Stop Timer Operation Timer[...]

APPLICA TION 2.3 Timers 2-35 4513/4514 Group User’s Manual Fig. 2.3.6 CNTR0 output control setting example b3 b0 ➀ Disable Interrupts Timer 3 and timer 4 interrupt are temporarily disabled. Interrupt enable flag INTE Interrupt control register V2 “0” ✕✕ All interrupts disabled ( DI instruction) Timer 3 and timer 4 interrupt occurrence d[...]

APPLICA TION 2.3 Timers 2-36 4513/4514 Group User’s Manual Fig. 2.3.7 Timer start by external input setting example (1) 0 b3 b0 ➀ Disable Interrupts Timer 1 interrupt is temporarily disabled. Interrupt enable flag INTE Interrupt control register V1 “0” ✕✕ All interrupts disabled ( DI instruction) Timer 1 interrupt occurrence disabled ( [...]

APPLICA TION 2.3 Timers 2-37 4513/4514 Group User’s Manual Fig. 2.3.8 Timer start by external input setting example (2) ( TI1A instruction) b3 b0 1 0 0 Processing in interrupt service routine ➇ Stop Timer Timer 1 control disabled Interrupt control register I1 ✕ b3 b0 10 1 ➈ Reset Timer Timer 1 reload register R1 Timer 1 control enabled “5[...]

APPLICA TION 2.3 Timers 2-38 4513/4514 Group User’s Manual Fig. 2.3.9 Watchdog timer setting example g0 h • • • • • • ➀ Activate Watchdog Timer Watchdog timer is activated. Watchdog timer enable flag WEF “1” Watchdog timer enable flag WEF set ( WRST instruction) Main routine (every 20 ms) Reset Flag WDF Watchdog timer flag WDF1 [...]

APPLICA TION 2.3 Timers 2-39 4513/4514 Group User’s Manual 2.3.4 Notes on use (1) Prescaler Stop the prescaler operation to change its frequency dividing ratio. (2) Count source Stop timer 1, 2, 3, or 4 counting to change its count source. (3) Reading the count values Stop timer 1, 2, 3, or 4 counting and then execute the TAB1 , TAB2 , TAB3 , or [...]

APPLICA TION 2.4 Serial I/O 2-40 4513/4514 Group User’s Manual 2.4 Serial I/O The 4513/4514 Group has a clock-synchronous serial I/O which can be used to transmit and receive 8-bit data. This section describes serial I/O functions, related registers, application examples using serial I/O and notes. 2.4.1 Carrier functions Serial I/O consists of t[...]

APPLICA TION 2.4 Serial I/O 2-41 4513/4514 Group User’s Manual 2.4.2 Related registers (1) Serial I/O register SI Serial I/O register SI is the 8-bit data transfer serial/parallel conversion register. Data can be set to register SI through registers A and B with the TSIAB instruction. (2) Serial I/O mode register J1 Serial I/O synchronous clock s[...]

APPLICA TION 2.4 Serial I/O 2-42 4513/4514 Group User’s Manual 2.4.3 Operation description Figure 2.4.2 shows the serial I/O connection example, Figure 2.4.3 shows the serial I/O register state, and Figure 2.4.4 shows the serial I/O transfer timing. Fig. 2.4.2 Serial I/O connection example Fig. 2.4.3 Serial I/O register state when transmitting/re[...]

APPLICA TION 2.4 Serial I/O 2-43 4513/4514 Group User’s Manual Fig. 2.4.4 Serial I/O transfer timing S IN S OUT Slave S CK SST instruction S OUT S IN S 0 S 7 ’S 1 S 2 S 3 S 4 S 5 S 6 S 7 SST instruction Control signal S 0 S 7 ’ S 1 S 3 S 4 S 5 S 6 S 7 M 0 M 7 ’ M 1 M 2 M 3 M 4 M 5 M 6 M 7 M 0 M 7 ’M 1 M 2 M 3 M 4 M 5 M 6 M 7 S 2 Master M [...]

APPLICA TION 2.4 Serial I/O 2-44 4513/4514 Group User’s Manual The full duplex communication of master and slave is described using the connection example shown in Figure 2.4.2. (1) Transmit/receive operation of master ➀ The transmit data is written into the serial I/O register SI with the TSIAB instruction. When the TSIAB instruction is execut[...]

APPLICA TION 2.4 Serial I/O 2-45 4513/4514 Group User’s Manual (2) Transmit/receive operation of slave ➀ The transmit data is written into the serial I/O register SI with the TSIAB instruction. When the TSIAB instruction is executed, the contents of register A are transferred to the low-order bits of register SI and the contents of register B a[...]

APPLICA TION 2.4 Serial I/O 2-46 4513/4514 Group User’s Manual Fig. 2.4.5 Master serial I/O setting example g0 h b3 b0 ➀ Disable Interrupts Serial I/O interrupt is temporarily disabled. Interrupt enable flag INTE Interrupt control register V2 “0” ✕ ✕ All interrupts disabled ( DI instruction) Serial I/O interrupt occurrence disabled ( TV[...]

APPLICA TION 2.4 Serial I/O 2-47 4513/4514 Group User’s Manual Fig. 2.4.6 Slave serial I/O example b3 b0 ➀ Disable Interrupts Serial I/O interrupt is temporarily disabled. Interrupt enable flag INTE Interrupt control register V2 “0” ✕ ✕ All interrupts disabled ( DI instruction) Serial I/O interrupt occurrence disabled ( TV2A instruction[...]

APPLICA TION 2.4 Serial I/O 2-48 4513/4514 Group User’s Manual 2.4.5 Notes on use (1) Note when an external clock is used as a synchronous clock: • An external clock is selected as the synchronous clock, the clock is not controlled internally. • Serial transfer is continued as long as an external clock is input. If an external clock is input [...]

APPLICA TION 2.5 A-D converter 2-49 4513/4514 Group User’s Manual 2.5 A-D con verter The 4513/4514 Group has an A-D converter with the 10-bit successive comparison method: 4 channels for the 4513 Group, 8 channels for the 4514 Group. This A-D converter can also be used as a comparator to compare analog voltages input from the analog input pin wit[...]

APPLICA TION 2.5 A-D converter 2-50 4513/4514 Group User’s Manual 2.5.1 Related registers (1) A-D control register Q1 Analog input pin selection bits are assigned to register Q1. Set the contents of this register through register A with the TQ1A instruction. The TAQ1 instruction can be used to transfer the contents of register Q1 to register A. T[...]

APPLICA TION 2.5 A-D converter 2-51 4513/4514 Group User’s Manual 2.5.2 A-D converter application examples (1) A-D conversion mode Outline: Analog input signal from a sensor can be converted into digital values. Specifications: Analog voltage values from a sensor is converted into digital values by using a 10- bit successive comparison method. Us[...]

APPLICA TION 2.5 A-D converter 2-52 4513/4514 Group User’s Manual 2.5.3 Notes on use (1) Note when the A-D conversion starts again When the A-D conversion starts again with the ADST instruction during A-D conversion, the previous input data is invalidated and the A-D conversion starts again. (2) A-D control register Q2 Select A IN4 –A IN7 with [...]

APPLICA TION 2.5 A-D converter 2-53 4513/4514 Group User’s Manual (5) A-D converter is used at the comparator mode The analog input voltage is higher than the comparison voltage as a result of comparison, the contents of ADF flag retains “0,” not set to “1.” In this case, the A-D interrupt does not occur even when the usage of the A-D int[...]

APPLICA TION 2.6 Voltage comparator 2-54 4513/4514 Group User’s Manual 2.6 V olta ge comparator The 4513/4514 Group has two voltage comparators; CMP0-, CMP0+, CMP1-, CMP1+. This section describes the voltage comparator function, related registers, and notes. 2.6.1 Voltage comparator function (1) CMP0 ■ Voltage comparison The voltage of CMP0- is[...]

APPLICA TION 2.6 Voltage comparator 2-55 4513/4514 Group User’s Manual 2.6.3 Notes on use ● Voltage comparator function When the voltage comparator function is valid with the voltage comparator control register Q3, it is operating even in the RAM back-up mode. Accordingly, be careful about such state because it causes the increase of the operat[...]

APPLICA TION 2-56 4513/4514 Group User’s Manual 2.7 Reset System reset is performed by applying “L” level to the RESET pin for 1 machine cycle or more when the following conditions are satisfied: the value of supply voltage is the minimum value or more of the recommended operating conditions oscillation is stabilized. Then when “H” level [...]

APPLICA TION 2-57 4513/4514 Group User’s Manual • Program counter (PC) ............................................................................................ Address 0 in page 0 is set to program counter. • Interrupt enable flag (INTE) ................................................................................... • Power down fla[...]

APPLICA TION 2-58 4513/4514 Group User’s Manual 2.8 Voltage drop detection circuit 2.8 V oltage dr op detection cir cuit The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value. Figure 2.8.1 shows the voltage drop detection reset circuit, and [...]

APPLICA TION 2-59 4513/4514 Group User’s Manual 2.9 RAM back-up 2.9 RAM back-up 2.9.1 RAM back-up mode The system enters RAM back-up mode when the POF instruction is executed after the EPOF instruction is executed. Table 2.9.1 shows the function and state retained at RAM back-up mode. Also, Table 2.9.2 shows the return source from this state. (1)[...]

APPLICA TION 2-60 4513/4514 Group User’s Manual 2.9 RAM back-up Remarks Set the port using the key-on wakeup function selected with register K0 to “H” level before going into the RAM back-up state because the port P0 shares the falling edge detection circuit with port P1. Select the return level (“L” level or “H” level) with the bit 2[...]

APPLICA TION 2-61 4513/4514 Group User’s Manual 2.9 RAM back-up (2) Pull-up control register PU0 Pull-up control register PU0 controls the pull-up functions of ports P0 0 –P0 3 , P1 0 –P1 3 . Set the contents of this register through register A with the TPU0A instruction. The TAPU0 instruction can be used to transfer the contents of register [...]

APPLICA TION 2-62 4513/4514 Group User’s Manual 2.9 RAM back-up (4) Interrupt control register I2 The interrupt valid waveform for INT1 pin/return level selection bit is assigned to bit 2, the INT1 pin edge detection circuit control bit is assigned to bit 1, and the INT1 pin timer 1 control enable bit is assigned to bit 1. Set the contents of thi[...]

APPLICA TION 2-63 4513/4514 Group User’s Manual 2.10 Oscillation circuit 2.10 Oscillation circuit The 4513/4514 Group has an internal oscillation circuit to produce the clock required for microcomputer operation. The clock signal f(X IN ) is obtained by connecting a ceramic resonator to X IN pin and X OUT pin. 2.10.1 Oscillation circuit (1) f(X I[...]

APPLICA TION 2-64 4513/4514 Group User’s Manual 2.10 Oscillation circuit 2.10.2 Oscillation operation System clock is supplied to CPU and peripheral device as the standard clock for the microcomputer operation. For the 4513/4514 Group, the clock (f(X IN )), (f(X IN )/2) which is supplied from the oscillation circuit is selected with the register [...]

CHAPTER 3 CHAPTER 3 APPENDIX 3.1 Electrical characteristics 3.2 Typical characteristics 3.3 List of precautions 3.4 Notes on noise 3.5 Mask ROM confirmation form 3.6 Mark specification form 3.7 Package outline[...]

APPENDIX 3.1 Electrical characteristics 3-2 4513/4514 Group User’s Manual Parameter Supply voltage Input voltage P0, P1, P2, P3, P4, P5, RESET , X IN , VDCE Input voltage D 0 –D 7 Input v oltage A IN0 –A IN7 Output voltage P0, P1, P3, P4, P5, RESET Output voltage D 0 –D 7 Output voltage X OUT Power dissipation Operating temperature range St[...]

4513/4514 Group User’s Manual APPENDIX 3-3 3.1 Electrical characteristics Symbol V DD V RAM V SS V IH V IH V IH V IH V IL V IL V IL I OH (peak) I OH (avg) I OL (peak) I OL (peak) I OL (peak) I OL (peak) I OL (avg) I OL (avg) I OL (avg) I OL (avg) Σ I OH (avg) Σ I OL (avg) Parameter Supply voltage RAM back-up voltage (at RAM back-up mode) Supply[...]

APPENDIX 3.1 Electrical characteristics 3-4 4513/4514 Group User’s Manual V DD = 2.5 V to 5.5 V V DD = 2.0 V to 5.5 V V DD = 2.5 V to 5.5 V V DD = 4.0 V to 5.5 V V DD = 2.5 V to 5.5 V V DD = 2.0 V to 5.5 V V DD = 4.0 V to 5.5 V V DD = 2 .5 V to 5.5 V V DD = 2 .0 V to 5.5 V V DD = 2.5 V to 5.5 V V DD = 4 .0 V to 5.5 V V DD = 2 .5 V to 5.5 V V DD =[...]

4513/4514 Group User’s Manual APPENDIX 3-5 3.1 Electrical characteristics 3.1.3 Electrical characteristics Table 3.1.4 Electrical characteristics (Mask ROM v ersion:T a = –20 °C to 85 °C, V DD = 2.0 V to 5.5 V , unless otherwise noted) (One Time PR OM v ersion:T a = –20 °C to 85 °C , V DD = 2.5 V to 5.5 V , unless otherwise noted) Symbol [...]

APPENDIX 3.1 Electrical characteristics 3-6 4513/4514 Group User’s Manual 3.1.4 A-D converter recommended operating conditions Table 3.1.5 A-D converter recommended operating conditions (Comparator mode included, T a = –20 °C to 85 °C, unless otherwise noted) Symbol V DD V IA f(X IN ) Parameter Supply voltage Analog input voltage Oscillation [...]

4513/4514 Group User’s Manual APPENDIX 3-7 3.1 Electrical characteristics 3.1.7 Basic timing diagram 3.1.6 Voltage comparator characteristics Table 3.1.8 Voltage comparator recommended operating conditions (T a = –20 °C to 85 °C, unless otherwise noted) Conditions V DD = 3.0 V to 5.5 V V DD = 3.0 V to 5.5 V Parameter Supply voltage V oltage c[...]

3-8 APPENDIX 3.2 Typical characteristics 4513/4514 Group User’s Manual 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2 2.5 3 3.5 4 4.5 5 5.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2 2.5 3 3.5 4 4.5 5 5.5 (2) CPU operating, high-speed mod[...]

4513/4514 Group User’s Manual APPENDIX 3-9 3.2 Typical characteristics Supply voltage V DD (V) Supply current I DD (mA) Supply voltage V DD (V) Supply current I DD (mA) (3) Ta = 25 °C (4) A-D operating, high-speed mode Ta = 25 °C f(X IN ) = 4 MHz f(X IN ) = 1 MHz 0 2 1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.1 [...]

3-10 APPENDIX 3.2 Typical characteristics 4513/4514 Group User’s Manual 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 2 2.5 3 3.5 4 4.5 5 5.5 Supply voltage V DD (V) Supply current I DD (nA) (5) RAM back-up Ta = 25 °C[...]

4513/4514 Group User’s Manual APPENDIX 3-11 3.2 Typical characteristics 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 3.2.2 V OL –I OL characteristics (1) Ports P0, P1, P4, P5, S CK , S OUT (2) Port P3, RESET pin Ta = 25 °C Ta = 25 °C Output voltage V OL (V) Output current I OL (mA) Output volta[...]

3-12 APPENDIX 3.2 Typical characteristics 4513/4514 Group User’s Manual 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 (3) Pins D 0 –D 5 Output voltage V OL (V) Output current I OL (mA) Output voltage V OL (V) Output current I OL (mA) (4) Pins D 6 /CNTR0, D 7 /CNTR1 V DD = 6 V V DD = 5 V V DD = 4 V[...]

4513/4514 Group User’s Manual APPENDIX 3-13 3.2 Typical characteristics 0 50 100 150 200 250 300 350 2 2.5 3 3.5 4 4.5 5 5.5 6 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 3.2.3 V OH –I OH characteristics (Port P5) Ta = 25 °C Output voltage V OH (V) Output current I OH (mA) Supply voltage V DD (V) Pull-up re[...]

3-14 APPENDIX 3.2 Typical characteristics 4513/4514 Group User’s Manual 3.2.5 A-D converter typical characteristics Fig. 3.2.1 A-D conversion characteristics data Figure 3.2.1 shows the A-D accuracy measurement data. (1) Non-linearity error ......................... This means a deviation from the ideal characteristics between V 0 to V 1022 of ac[...]

4513/4514 Group User’s Manual APPENDIX 3-15 3.2 Typical characteristics (1) V DD = 3.072 V, f(X IN ) = 2 MHz, high-speed mode -4.5 -3 -1.5 0 1.5 3 4.5 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 STEP No. ERROR / 1LSB WIDTH(mV) 1 LSB WID TH ERR O R -4.5 -3 -1.5 0 1.5 3 4.5 256 272 288 304 320 336 352 368 384 400 416 432 448 464 480[...]

3-16 APPENDIX 3.2 Typical characteristics 4513/4514 Group User’s Manual (2) V DD = 5.12 V, f(X IN ) = 4 MHz, high-speed mode -7.5 -5 -2.5 0 2.5 5 7.5 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 STEP No. ERROR / 1LSB WIDTH(mV) 1 LSB WID TH ERR O R -7.5 -5 -2.5 0 2.5 5 7.5 256 272 288 304 320 336 352 368 384 400 416 432 448 464 480 [...]

4513/4514 Group User’s Manual APPENDIX 3-17 3.2 Typical characteristics -25 -20 -15 -10 -5 0 5 10 15 20 25 0 0.5 1 1.5 2 2.5 3 -100 -80 -60 -40 -20 0 20 40 60 80 100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 3.2.6 Analog input current characteristics pins A IN0 –A IN7 (1) V DD = 3.0 V, f(X IN ) = 2 MHz, middle-speed mode Ta = 25 °C Analog input voltage [...]

3-18 APPENDIX 3.2 Typical characteristics 4513/4514 Group User’s Manual -200 -160 -120 -80 -40 0 40 80 120 160 200 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -50 -40 -30 -20 -10 0 10 20 30 40 50 0 0.5 1 1.5 2 2.5 3 (3) V DD = 3.0 V, f(X IN ) = 2 MHz, high-speed mode Ta = 25 °C Analog input voltage V AIN (V) Analog input current I AIN (nA) (4) V DD = 5.0 V,[...]

4513/4514 Group User’s Manual APPENDIX 3-19 3.2 Typical characteristics 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 2 2.5 3 3.5 4 4.5 5 5.5 6 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 2 2.5 3 3.5 4 4.5 5 5.5 6 3.2.7 V DD –V IH /V IL characteristics (1) RESET pin Ta = 25 °C Supply voltage V DD (V) V IH /V IL (V) (2) Ports P0, P1, P2, P3, P4, P5, D, X IN pin,[...]

3-20 APPENDIX 3.2 Typical characteristics 4513/4514 Group User’s Manual 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 2 2.5 3 3.5 4 4.5 5 5.5 6 (3) Pins INT0, INT1, CNTR0, CNTR1, S CK , S IN Ta = 25 °C Supply voltage V DD (V) V IH /V IL (V) V IH (rating value) V IL (rating value) V IH 3.2.8 Detection voltage temperature characteristics of voltage drop det[...]

4513/4514 Group User’s Manual APPENDIX 3-21 3.3 List of precautions 3.3 List of precautions ➀ Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up; • connect a bypass capacitor (approx. 0.1 µ F) between pins V DD and V SS at the shortest distance, • equalize its wiring in width and leng[...]

3-22 APPENDIX 3.3 List of precautions 4513/4514 Group User’s Manual ➉ A-D con ver ter-1 When the operating mode of the A-D converter is changed from the comparator mode to the A-D conversion mode with the bit 3 of register Q2 in a program, be careful about the following notes. • Clear the bit 2 of register V2 to “0” to change the operatin[...]

4513/4514 Group User’s Manual APPENDIX 3-23 3.3 List of precautions 16 V oltage compar ator function When the voltage comparator function is valid with the voltage comparator control register Q3, it is operating even in the RAM back-up mode . Accordingly , be careful about such state because it causes the increase of the operation current in the [...]

3-24 APPENDIX 3.4 Notes on noise 4513/4514 Group User’s Manual 3.4 Notes on noise Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 3.4.1 Shortest wiring length The wiring on a prin[...]

4513/4514 Group User’s Manual APPENDIX 3-25 3.4 Notes on noise (3) Wiring for clock input/output pins • Make the length of wiring which is connected to clock I/O pins as short as possible. • Make the length of wiring across the grounding lead of a capacitor which is connected to an oscillator and the V SS pin of a microcomputer as short as po[...]

3-26 APPENDIX 3.4 Notes on noise 4513/4514 Group User’s Manual ( 5 ) Wiring to V PP pin of O ne Time PROM version In the built-in PROM version of the 4513/4514 Group, the CNV SS pin is also used as the built-in PROM power supply input pin V PP . ● When the V PP pin is also used as the CNV SS pin Connect an approximately 5 k Ω resistor to the [...]

4513/4514 Group User’s Manual APPENDIX 3-27 3.4 Notes on noise 3.4.3 Wiring to analog input pins • Connect an approximately 100 Ω to 1 k Ω resistor to an analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible. • Connect an approximately 1000 pF capaci[...]

3-28 APPENDIX 3.4 Notes on noise 4513/4514 Group User’s Manual Fig. 3.4.9 Wiring to a signal line where potential levels change frequently (3) Oscillator protection using V SS pattern As for a two-sided printed circuit board, print a V SS pattern on the underside (soldering side) of the position (on the component side) where an oscillator is moun[...]

4513/4514 Group User’s Manual APPENDIX 3-29 3.4 Notes on noise <The main routine> • Assigns a single word of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition: N+1 ≥ As the main routine execution cycle [...]

3-30 APPENDIX 4513/4514 Group User’s Manual 3.5 Mask ROM order confirmation form 3.5 Mask ROM order confirmation form 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will pro[...]

4513/4514 Group User’s Manual APPENDIX 3-31 3.5 Mask ROM order confirmation form ✽ 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We[...]

3-32 APPENDIX 4513/4514 Group User’s Manual 3.5 Mask ROM order confirmation form ✽ 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We[...]

4513/4514 Group User’s Manual APPENDIX 3-33 3.5 Mask ROM order confirmation form ✽ 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We[...]

3-34 APPENDIX 4513/4514 Group User’s Manual 3.5 Mask ROM order confirmation form ✽ 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We[...]

4513/4514 Group User’s Manual APPENDIX 3-35 3.5 Mask ROM order confirmation form ✽ 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We[...]

3-36 APPENDIX 4513/4514 Group User’s Manual 3.6 Mark specification form 3.6 Mark specification form 32P4B (32-PIN SHRINK DIP) MARK SPECIFICA TION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed). A. Standard Mitsubishi Mark Note1 : If [...]

4513/4514 Group User’s Manual APPENDIX 3-37 3.6 Mark specification form 32P6B (32-PIN LQFP) MARK SPECIFICA TION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B), and enter the Mitsubishi catalog name and the special mark (if needed). A. Standard Mitsubishi Mark B. Customer’s P ar ts Number + Mitsubishi catalog[...]

3-38 APPENDIX 4513/4514 Group User’s Manual 3.6 Mark specification form 42P2R-A (42-PIN SHRINK SOP) MARK SPECIFICA TION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed). A. Standard Mitsubishi Mark C. Special Mark Required B. Customer’s[...]

4513/4514 Group User’s Manual APPENDIX 3-39 3.7 Package outline 3.7 Package outline SDIP32-P-400-1.78 Weight(g) – 2.2 JEDEC Code EIAJ Package Code Lead Material Alloy 42/Cu Alloy 32P4B Plastic 32pin 400mil SDIP Symbol Min Nom Max A A 2 b b 1 b 2 c E D L Dimension in Millimeters A 1 0.51 – – –3 . 8– 0.35 0. 45 0.55 0.9 1. 0 1.3 0.63 0. 7[...]

3-40 APPENDIX 4513/4514 Group User’s Manual 3.7 Package outline SSOP42-P-450-0.80 Weight(g) – JEDEC Code 0.63 EIAJ Package Code Lead Material Alloy 42/Cu Alloy 42P2R-A Plastic 42pin 450mil SSOP Symbol Min Nom Max A A 2 b c D E L L 1 y Dimension in Millimeters H E A 1 I 2 – – .35 0 .05 0 .13 0 .3 17 .2 8 – .63 11 .3 0 – – – .27 1 –[...]

MITSUBISHI SEMICONDUCTORS USER’S MANUAL 4513/4514 Group Dec. First Edition 1998 Editioned by Committee of editing of Mitsubishi Semiconductor USER’S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation.[...]

Rev. Rev. No. date 1.0 First Edition 981211 REVISION DESCRIPTION LIST 4513/4514 GROUP USER'S MANUAL (1/1) Revision Description[...]

User’ s Man ual 4513/4514 Group © 1998 MITSUBISHI ELECTRIC CORPORATION. New publication, effective Dec. 1998. Specifications subject to change without notice.[...]