Sundance Spas ST201 инструкция обслуживания

ST201 Fast Ethernet MAC See Sundance Technology ’ s website at www.sundanceti.com for the latest information. Sundance Technology Publication: 2 Rev: A Date: November 1 998 PRELIMINARY draft 2 FEATURES • Single chip 10/100BASE, half or full duplex Ethernet Media Access Controller • IEEE 802.3u compliant MI I • I EEE 802.3x full duplex flow [...]

2 Sundance Technology ST201 PRELIMINARY draft 2 BLOCK DIAGRA M PHYLNKN RSTN PCICLK GNTN IDSEL INTAN WAKE REQN AD[31..0] CBEN[3:0] PAR FRAMEN IRDYN TRDYN DEVSELN STOPN PERRN SERRN VDET PCI TXD[3..0] TXEN TXCLK RXD[3..0] RXCLK RXER RXDV CRS COL MDC MDIO MII ED[7..0] EA[15..0] EWEN EOEN LEDPWRN LEDLNKN LEDDPLXN LEDSPDN GPIO0 GPIO1 RSTOUT X25I X25O CLK[...]

3 Sundance Technology ST201 PRELIMINARY draft 2 ORDERING INFORMATION K C TEMPERATURE RANGE PACKAGE TYPE DEVICE NUMBER/DESCRIPTION ST201 C=Commercial (0 to +70C) K=Plastic Quad Flat Pack ST201 Fast Ethernet MAC Sundance products are available in several combinations of packages and operating temperature ranges. The order number is formed by a combin[...]

4 Sundance Technology ST201 PRELIMINARY draft 2 PIN DIAGRAM[...]

5 Sundance Technology ST201 PRELIMINARY draft 2 PIN DESIGNATION S PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME 1 VC C (5V) 33 AD9 65 EA2 97 RXCLK 2 CBEN3 34 GND (5V) 66 EA3 98 RXDV 3 IDSEL 35 AD8 67 EA4 99 RXD0 4 AD23 36 CBEN0 68 EA5 100 RXD1 5 AD22 37 AD7 69 EA6 101 RXD2 6 AD21 38 AD6 70 EA7 102 RXD3 7 AD20 39 AD5 71 EA8 103[...]

6 Sundance Technology ST201 PRELIMINARY draft 2 PIN DESCRIPTIONS PIN NAME PIN TYPE PIN DESCRIPTION PCI INTERFACE RSTN INPUT Reset, asserted LOW. R STN will cause the ST201 to reset all of its functional blocks. R STN must be asserted for a minimum duration of 10 PCICLK cycles. PCICLK INPUT PCI Bus Clock. This clock is used to drive the PCI bus inte[...]

7 Sundance Technology ST201 PRELIMINARY draft 2 TRDYN IN/OUT Target Ready, asserted LOW. A bus target asserts TRDYN to indicate valid read data phases, and to indicate it is ready to accept data during write data phases. A bus master will monitor TRDYN. DEVSELN IN/OUT Device Select, asserted LOW. T he ST201 asserts DEVSELN when it is selected as a [...]

8 Sundance Technology ST201 PRELIMINARY draft 2 COL INPUT Collision. C OL is asserted by the PHY to a signal collision condition is detected on the physical medium. C OL is asynchronous to RXCLK and TXCLK . MDC OUTPUT Management Data Clock. M DC is used to synchronize the read and write operations of MDIO. MDIO IN/OUT Management Data Input/Output. [...]

9 Sundance Technology ST201 PRELIMINARY draft 2 LEDPWRN OUTPUT Power Status LED. (This pin is shared with EA9) . The operation of this pin varies based on the setting in the I/O Registers, AsicCtrl bit 14 (the LEDMode bit). In Mode 0, LOW when power is applied, and toggling when frame transmission is in progress. In Mode 1, this pin is always LOW w[...]

10 Sundance Technology ST201 PRELIMINARY draft 2 ACRONYMS AND GLOSSARY LAN Local Area Network MAC Media Access Control Layer, or a device implementing the functions of this layer (a Media Access Con- troller) PCI Peripheral Component Interface NIC Network Interface Cards FIFO First In First Out MII Media Independent Interface EPROM Erasable Program[...]

11 Sundance Technology ST201 PRELIMINARY draft 2 P CI BUS INTERFACE The PCI Bus Interface (PBI) implements the proce- dures and algorithms needed to link the ST201 to a PCI bus. The ST201 can be either a PCI bus mas- ter or slave. The PBI i s also responsible f or manag- ing the DMA interface s and the host processors access to the ST201 r egister [...]

12 Sundance Technology ST201 PRELIMINARY draft 2 E XPANSION ROM INTERFACE The ST201 provides su pport f or an optional Expan- sion ROM. The ST201 supports th e A tmel AT29C512 (64K x 8) Flash EPRO M device. T he Expansion ROM is configured through the PCI configuration register, which maps the ROM into the memory space of the host system . Th e ROM[...]

13 Sundance Technology ST201 PRELIMINARY draft 2 dress register. Setting the ReceiveBroadcast and ReceiveMulticast bits in the ReceiveMode register will allow the ST201 to receive all broadcast and m ulticast frames, respectively . The ReceiveMultic- astHash bit in ReceiveMode enables a filtering mechanism for Ethernet multicast frames. This fil- t[...]

14 Sundance Technology ST201 PRELIMINARY draft 2 T XDMA AND FRAME TRANSMISSION The TxDMA block transfers frame data from a host system to the ST201 based on a linked list of frame descriptors called T FDs . The frame to be transmit- ted is divided into data fragments (or buffers) within the host system ’ s memory. The host system cre- ates a list[...]

15 Sundance Technology ST201 PRELIMINARY draft 2 T he TxDMAListPtr I /O register with in the ST201 c ontains the physical address that points to the head of the TxDMAList . TxDMAListPtr must point to addresses which are on 8-byte boundaries. A v alue of zero in the TxDMAListPtr register i mplies there are no pending TFD ’ s for the ST201 to pro- [...]

16 Sundance Technology ST201 PRELIMINARY draft 2 are independent of each other in general. A special case is when a transmit under run o ccurs . In this case t he current frame being transmitted is t he only f rame in the TxFIFO. Wh en a transmit under run o ccurs, the ST201 stops TxDMA operation and generates an interrupt with a TxUnderrun error f[...]

17 Sundance Technology ST201 PRELIMINARY draft 2 received and transferred by RxDMA, a RxDMA- Complete interrupt will be generated for each frame. T he host system must create a RxDMAList a nd the a ssociated buffers prior to reception of a frame . One approach calls for the host system to a llocate a block of full size (i.e. large enough to hold a [...]

18 Sundance Technology ST201 PRELIMINARY draft 2 S ystems using the ST201 can be programmed to generate an interrupt based upon the number of bytes that have been received in a frame . The RxEarlyThresh register sets the value for early receive threshold . A s soon as the number of bytes that have been received is greater than the value in RxEarlyT[...]

19 Sundance Technology ST201 PRELIMINARY draft 2 STATISTIC S T he ST201 implements 16 statistics counters of various widths. Each statistic implemented com- plies to the corresponding definition given in the IEEE 802.3 standard. S etting the StatisticsEnable bit in the MACCtrl register enables the gathering of statistics. Reading a statistics regis[...]

20 Sundance Technology ST201 PRELIMINARY draft 2 disable the use of M W I and MRL. MWIDisable and MRLDisable a re cleared by default, enabling MWI and MRL . The ST201 provides a set of registers that control the PCI burst behavior. These registers allow a trade-off to be made between PCI bus efficiency and under run/ overrun frequency. Arbitration [...]

21 Sundance Technology ST201 PRELIMINARY draft 2 D 1, D2, or D3 . W hen the ST201 detects a W ake Packet, it signals a wake event on PMEN (if PMEN assertion is enabled), and sets the WakePktEvent bit in the W akeEvent register. The ST201 can sig- nal that a w ake event has occurred w hen it receives a pre-defined frame from another station. The hos[...]

22 Sundance Technology ST201 PRELIMINARY draft 2 network via transmission of a special frame. Once the ST201 h as been placed in Magic Packet mode and put to sleep, it scans all incoming frames addressed to it for a data sequence consisting of 16 consecutive repetitions of its own 48-bit Ether- net MAC StationAddress. This sequence can be located a[...]

23 Sundance Technology ST201 PRELIMINARY draft 2 3. Set MgmtClk 4. Write the desired data bit to MgmtData 5. W ait a minimum of 200 ns To perform a Z cycle used during the Turnaround portion of a register read frame, the host system should follow the procedure below. 1. Clear MgmtClk 2. W ait a minimum of 200 ns 3. Set MgmtClk 4. Clear MgmtDir 5. W[...]

24 Sundance Technology ST201 PRELIMINARY draft 2 8. Verify EepromBusy is false. 9. Issue WriteRegister command (opcode = 01 aaaa aaaa) Step 4 through 8 may be skipped for certain types of EEPROM devices. ADAPTER TXDMA SEQUENCE Beginning with the host system writing to the TxD- MAListPtr register (when starting from an empty TxDMAList, for instance)[...]

25 Sundance Technology ST201 PRELIMINARY draft 2 tion of the “ first TFD ” in the TxDMAList. Restore the TxDMANextPtr of the “ first TFD ” , and restart this process. 4. Copy the value of the “ first TFD ’ s ” TxDMANex- tPtr into the TxDMANextPtr field of the inserted TFD. 5. Update the TxDMANextPtr field of the “ first TFD ” with[...]

26 Sundance Technology ST201 PRELIMINARY draft 2 host system then returns to the operating sys- tem an indication of readiness to be powered down (making sure to leave the ReceiveMode register set to receive the appropriate W ake/ Magic packets). The operating system eventu- ally writes to the PowerMgmtCtrl register, plac- ing the ST201 in one of t[...]

27 Sundance Technology ST201 PRELIMINARY draft 2 REGISTERS AND DATA STRUCTURES DMA DATA STRUCTURES A T FD i s used to move data, which is to be transmitted onto a LAN, from host system memory to the TxFIFO within the ST201. A TFD is 16 to 512 bytes in length, and it ’ s location in host system memory is indicated by the value in the TxDMAListPtr [...]

28 Sundance Technology ST201 PRELIMINARY draft 2 TXDMAFRAGADDR Class .................... DMA Data Structures, TFD Base Address ...... Start of TFD Address Offset ..... 0x00+n·8 for nth fragment Access Mode ....... Read/Write Width ................... 32 bits BIT BIT NAME BIT DESCRIPTION 31..0 TxDMAFragAddr Transmit Fragment Address contains the p[...]

29 Sundance Technology ST201 PRELIMINARY draft 2 TXDMAFRAGLEN Class .................... DMA Data Structures, TFD Base Address ...... Start of TFD A ddress Offset ..... 0x04+n·8 for nth fragment Access Mode ....... Read/Write Width ................... 32 bits Transmit Fragment Length (TxDMAFragLen) contains fragment length and control information [...]

30 Sundance Technology ST201 PRELIMINARY draft 2 TXDMANEXTPTR Class .................... DMA Data Structures, TFD Base Address ...... Start of TFD Address Offset ..... 0x00 Access Mode ....... Read/Write Width ................... 32 bits BIT BIT NAME BIT DESCRIPTION 31..0 TxDMANextPtr Transmit Next Pointer, the first double word in the TFD contains[...]

31 Sundance Technology ST201 PRELIMINARY draft 2 TXFRAMECONTROL Class .................... DMA Data Structures, TFD Base Address ...... Start of TFD Address Offset ..... 0x04 Access Mode ....... Read/Write Width ................... 32 bits T xFrameControl c ontains frame control information for the TxDMA function and the transmit function. BIT BIT [...]

32 Sundance Technology ST201 PRELIMINARY draft 2 RXDMANEXTPTR Class .................... DMA Data Structures, RFD Base Address ...... Start of RFD Address Offset ..... 0x00 Access Mode ....... Read/Write Width ................... 32 bits BIT BIT NAME BIT DESCRIPTION 31..0 RxDMANextPtr The first dword in the RFD contains the physical address of the [...]

33 Sundance Technology ST201 PRELIMINARY draft 2 RXFRAMESTATUS Class .................... DMA Data Structures, RFD Base Address ...... Start of RFD Address Offset ..... 0x04 Access Mode ....... Read/Write Width ................... 32 bits The second dword in the RFD is ReceiveFrameStatus. At the end of a RxDMA frame transfer, the ST201 writes the v[...]

34 Sundance Technology ST201 PRELIMINARY draft 2 22..21 Reserved Reserved for future use. Should be set to 0. 23 DribbleBits Indicates that the frame had accompanying dribble bits. This bit is informational only, and does not indicate a frame error. 24 RxDMAOverflow Indicates that the RFD had insufficient buffer space for the frame data and there w[...]

35 Sundance Technology ST201 PRELIMINARY draft 2 RXDMAFRAGADDR Class .................... DMA Data Structures, RFD Base Address ...... Start of RFD Address Offset ..... 0x00+n·8 for nth fragment Access Mode ....... Read/Write Width ................... 32 bits BIT BIT NAME BIT DESCRIPTION 31..0 RxDMAFragAddr The third and all subsequent odd dwords [...]

36 Sundance Technology ST201 PRELIMINARY draft 2 RXDMAFRAGLEN Class .................... DMA Data Structures, RFD Base Address ...... Start of RFD Address Offset ..... 0x04+n·8 for nth fragment Access Mode ....... Read/Write Width ................... 32 bits The fourth and all subsequent even dwords in the RFD contains fragment length and control [...]

37 Sundance Technology ST201 PRELIMINARY draft 2 WAKE EVENT DATA STRUCTURES The first Wake Event Data Structure is the Pseudo P acket. A Pseudo P acket is a set of patterns loaded into the ST201 TxFIFO which specify bytes to be examined within received frames. A CRC is calculated over these bytes and compared with a CRC value supplied in the Pseudo[...]

38 Sundance Technology ST201 PRELIMINARY draft 2 PSEUDOPATTERN Class .................... Wake Event Data Structures, Pseudo P acket Base Address ...... Start of Pseudo Packet Address Offset ..... 0x00 thru 0x00+n-1 for nth PseudoPattern Access Mode ....... Write only Width ................... 8 bits BIT BIT NAME BIT DESCRIPTION 3..0 ByteCount Byte[...]

39 Sundance Technology ST201 PRELIMINARY draft 2 TERMINATOR Class .................... Wake Event Data Structures, Pseudo P acket Base Address ...... Start of Pseudo Packet Address Offset ..... 0x00+n for n PseudoPattern Access Mode ....... Write only Width ................... 8 bits BIT BIT NAME BIT DESCRIPTION 7..0 Terminator A value of 0x00 indi[...]

40 Sundance Technology ST201 PRELIMINARY draft 2 PSEUDOCRC Class .................... Wake Event Data Structures, Pseudo P acket Base Address ...... Start of Pseudo Packet Address Offset ..... 0x00+n+1 for n PseudoPatterns Access Mode ....... Write only Width ................... 32 bits The 32-bit CRC as defined in the IEEE 802.3 Ethernet standard [...]

41 Sundance Technology ST201 PRELIMINARY draft 2 MAGICSYNCSTREAM Class .................... Wake Event Data Structures, Magic Packet Base Address ...... Start of Magic Packet Address Offset ..... 0x00 Access Mode ....... Read only Width ................... 48 bits BIT BIT NAME BIT DESCRIPTION 47..0 MagicSyncStream A stream of 6 bytes with the value[...]

42 Sundance Technology ST201 PRELIMINARY draft 2 MAGICSEQUENCE Class .................... Wake Event Data Structures, Magic Packet Base Address ...... Start of Magic Packet Address Offset ..... 0x06 Access Mode ....... Read only Width ................... 768 bits BIT BIT NAME BIT DESCRIPTION 767..0 MagicSequence A sequence of 96 bytes, consisting o[...]

43 Sundance Technology ST201 PRELIMINARY draft 2 I/O REGISTERS T he host interacts with the ST201 mainly through slave registers, which occupy 128 bytes in the host sys- tem ’ s I/O space, memory space, or both. Generally, registers are referred to as “ I/O registers ” , implying that the registers may in fact be mapped and accessed by the ho[...]

44 Sundance Technology ST201 PRELIMINARY draft 2 McstFramesRcvdOk McstFramesXmtdOk BcstFramesRcvdOk BcstFramesXmtdOk 0x7c FramesAbortXSColls Frames WEXDeferral FramesLostRxErrors Frames WDeferedXmt 0x78 SingleColFrames MultipleColFrames LateCollisions CarrierSenseErrors 0x74 PhyCtrl TxReleaseThresh ReceiveMode 0x5c FramesReceivedOk FramesTransmitte[...]

45 Sundance Technology ST201 PRELIMINARY draft 2 ASICCTRL Class .................... I/O Registers, Control and Status Base Address ...... IoBaseAddress register value Address Offset ..... 0x30 Access Mode ....... Read/Write Width ................... 32 bits AsicCtrl provides chip-specific, non-host-related settings. The contents of the least signi[...]

46 Sundance Technology ST201 PRELIMINARY draft 2 10..8 ForcedConfig These bits are used to place the ST201 into Forced Configuration mode. The bit values are latched in from ED[2..0] pins with a logic inversion at the end of RSTN or power on reset. 000: no forced configuration 001: forced configuration mode 1 010-111: reserved Note: Wh en ForcedCon[...]

47 Sundance Technology ST201 PRELIMINARY draft 2 19 DMA When set, together with GlobalReset, RxReset, or TxReset bits, will reset RxDMA and TxDMA Logic, including: TxDMAListPtr, RxDMAL- istPtr, TxDMAComplete TxDMAInProg RxDMAComplete and RxEarly- Enable in DMACtrl and RxDMAStatus. W hen cleared, reset will not have action on the DMA Logic. This bit[...]

48 Sundance Technology ST201 PRELIMINARY draft 2 DEBUGCTRL Class .................... I/O Registers, Control and Status Base Address ...... IoBaseAddress register value Address Offset ..... 0x1a Access Mode ....... Read/Write Width ................... 16 bits DebugCtrl selects the functions of the GPIO pins. DebugCtrl is cleared by reset. BIT BIT N[...]

49 Sundance Technology ST201 PRELIMINARY draft 2 H ASHTABLE Class .................... I/O Registers, Control and Status Base Address ...... IoBaseAddress register value Address Offset ..... 0x66, 0x64, 0x62, 0x60 Access Mode ....... Read/Write Width ................... 64 bits (accessible as 4, 16 bit words) T he host stores the 64-bit hash table [...]

50 Sundance Technology ST201 PRELIMINARY draft 2 M ACCTRL Class .................... I/O Registers, Control and Status Base Address ...... IoBaseAddress register value Address Offset ..... 0x50 Access Mode ....... Read/Write Width ................... 32 bits This register provides for setting of MAC-specific parameters. It is cleared upon reset. BI[...]

51 Sundance Technology ST201 PRELIMINARY draft 2 9 RcvFCS This bit is set by the host if it is desired for the receive frame ’ s FCS to be passed to the host as part of the data in the RxFIFO. The state of RcvFCS does not affect the ST201 ’ s checking of the frame ’ s FCS and its posting of FCS error status. RcvFCS is cleared by a system rese[...]

52 Sundance Technology ST201 PRELIMINARY draft 2 T he loopback modes available to a host system when using the ST201 are shown in Table 3. External loopback type is controlled by the Mll PHY device. The host system must enable a loopback mode within MII PHY d evice using the MII Management Interface. For the true “ on-the-wire ” loopback mode ,[...]

53 Sundance Technology ST201 PRELIMINARY draft 2 M AXFRAMESIZE Class .................... I/O Registers, Control and Status Base Address ...... IoBaseAddress register value Address Offset ..... 0x5a Access Mode ....... Read/Write Width ................... 16 bits Sets the maximum frame size for received frames. BIT BIT NAME BIT DESCRIPTION 15..0 Ma[...]

54 Sundance Technology ST201 PRELIMINARY draft 2 R ECEIVEMODE Class .................... I/O Registers, Control and Status Base Address ...... IoBaseAddress register value Address Offset ..... 0x5c Access Mode ....... Read/Write Width ................... 8 bits Each bit in ReceiveMode, when set, enables reception of a different type of frame. Recei[...]

55 Sundance Technology ST201 PRELIMINARY draft 2 S TATIONADDRESS Class .................... I/O Registers, Control and Status Base Address ...... IoBaseAddress register value Address Offset ..... 0x47 Access Mode ....... Read/Write Width ................... 8 bits StationAddress is used to define the individual destination address that the ST201 wi[...]

56 Sundance Technology ST201 PRELIMINARY draft 2 T XFRAMEID Class .................... I/O Registers, Control and Status Base Address ...... IoBaseAddress register value Address Offset ..... 0x5c Access Mode ....... Read Width ................... 8 bits TxFrameId contains the frame ID for the currently transmitting or most recently transmitted fram[...]

57 Sundance Technology ST201 PRELIMINARY draft 2 T XSTATUS Class .................... I/O Registers, Control and Status Base Address ...... IoBaseAddress register value Address Offset ..... 0x4 6 Access Mode ....... Read (write to advance queue) Width ................... 8 bits The TxStatus register returns the status of frame transmission or trans[...]

58 Sundance Technology ST201 PRELIMINARY draft 2 WAKEEVENT Class .................... I/O Registers, Control and Status Base Address ...... IoBaseAddress register value Address Offset ..... 0x45 Access Mode ....... Read/Write Width ................... 8 bits W akeEvent contains enable bits to control which types of events can generate a wake event [...]

59 Sundance Technology ST201 PRELIMINARY draft 2 FIFOCTRL Class .................... I/O Registers, FIFO Control Base Address ...... IoBaseAddress register value Address Offset ..... 0x3a Access Mode ....... Read/Write Width ................... 16 bits The bits in this register provide various control and indications of TxFIFO and RxFIFO diagnostic[...]

60 Sundance Technology ST201 PRELIMINARY draft 2 R XEARLYTHRES H Class .................... I/O Registers, FIFO Control Base Address ...... IoBaseAddress register value Address Offset ..... 0x3e Access Mode ....... Read/Write Width ................... 16 bits The value stored in this register defines the number of bytes of the top of the frame that[...]

61 Sundance Technology ST201 PRELIMINARY draft 2 T XRELEASETHRES H Class .................... I/O Registers, FIFO Control Base Address ...... IoBaseAddress register value Address Offset ..... 0x5d Access Mode ....... Read/Write Width ................... 8 bits The value in TxReleaseThresh determines how much data of a frame must be transmitted befo[...]

62 Sundance Technology ST201 PRELIMINARY draft 2 T XSTARTTHRES H Class .................... I/O Registers, FIFO Control Base Address ...... IoBaseAddress register value Address Offset ..... 0x3c Access Mode ....... Read/Write Width ................... 16 bits The value in TxStartThresh is used to control when frames are transmitted. Transmission of[...]

63 Sundance Technology ST201 PRELIMINARY draft 2 C OUNTDOW N Class .................... I/O Registers, Interrupt Base Address ...... IoBaseAddress register value Address Offset ..... 0x 48 Access Mode ....... Read/Write Width ................... 16 bits Countdown is a programmable down-counter that will generate an interrupt upon its expiration. If[...]

64 Sundance Technology ST201 PRELIMINARY draft 2 I NTENABL E Class .................... I/O Registers, Interrupt Base Address ...... IoBaseAddress register value Address Offset ..... 0x4c Access Mode ....... Read/Write Width ................... 16 bits Enables individual interrupts as specified in the IntStatus register. Setting a bit in IntEnable [...]

65 Sundance Technology ST201 PRELIMINARY draft 2 I NTSTATU S Class .................... I/O Registers, Interrupt Base Address ...... IoBaseAddress register value Address Offset ..... 0x4e Access Mode ....... Read/Write Width ................... 16 bits IntStatus register indicates the source of interrupts and indications on the ST201. Bits 1 throug[...]

66 Sundance Technology ST201 PRELIMINARY draft 2 9 TxDMAComplete This bit indicates that a frame TxDMA has completed, and the TFD in question had the TxDMAIndicate bit in its TFC set. This bit can be acknowledged by writing a 1 to this bit. The host should examine the TxDMAListPtr to determine which frame(s) have been transferred by TxDMA. Those fr[...]

67 Sundance Technology ST201 PRELIMINARY draft 2 INTSTATUSACK Class .................... I/O Registers, Interrupt Base Address ...... IoBaseAddress register value Address Offset ..... 0x4a Access Mode ....... Read only Width ................... 16 bits IntStatusAck is another version of the IntStatus register, having the same bit definition as IntS[...]

68 Sundance Technology ST201 PRELIMINARY draft 2 9 TxDMAComplete This bit indicates that a frame TxDMA has completed, and the TFD in question had the TxDMAIndicate bit in its TFC set. This bit can be acknowledged by writing a 1 to this bit. The host should examine the TxDMAListPtr to determine which frame(s) have been transferred by TxDMA. Those fr[...]

69 Sundance Technology ST201 PRELIMINARY draft 2 D MACTRL Class .................... I/O Registers, DMA Base Address ...... IoBaseAddress register value Address Offset ..... 0x00 Access Mode ....... Read/Write Width ................... 32 bits DMACtrl controls some of the bus master functions in the RxDMA and TxDMA engines, and contains sta- tus bi[...]

70 Sundance Technology ST201 PRELIMINARY draft 2 15 DMAHaltBusy This read-only bit indicates that a DMA Halt operation (TxDMAHalt or RxDMAHalt) is in progress and the drivers should wait for this bit to be cleared before performing other actions. 16 Reserved Reserved for future use. Should be set to 0. 17 RxEarlyEnable This read/write bit determine[...]

71 Sundance Technology ST201 PRELIMINARY draft 2 31 MasterAbort This read-only bit is set when the ST201 experiences a master abort sequence when operating as a bus master. This bit indicates a fatal error, and must be cleared before further TxDMA or RxDMA operation can proceed. This bit is cleared by the GlobalReset/DMA bit. BIT BIT NAME BIT DESCR[...]

72 Sundance Technology ST201 PRELIMINARY draft 2 R XDMABURSTTHRES H Class .................... I/O Registers, DMA Base Address ...... IoBaseAddress register value Address Offset ..... 0x14 Access Mode ....... Read/Write Width ................... 8 bits RxDMABurstThresh sets the threshold when the ST201 makes RxDMA bus master requests, based upon th[...]

73 Sundance Technology ST201 PRELIMINARY draft 2 R XDMALISTPT R Class .................... I/O Registers, DMA Base Address ...... IoBaseAddress register value Address Offset ..... 0x10 Access Mode ....... Read/Write Width ................... 32 bits RxDMAListPtr holds the physical address of the current RxDMA Frame Descriptor in the RxDMAList. A va[...]

74 Sundance Technology ST201 PRELIMINARY draft 2 R XDMASTATU S Class .................... I/O Registers, DMA Base Address ...... IoBaseAddress register value Address Offset ..... 0x0c Access Mode ....... Read only Width ................... 32 bits RxDMAStatus shows the status of various operations in the RxDMA Logic. Host systems should read this r[...]

75 Sundance Technology ST201 PRELIMINARY draft 2 20 RxOversizedFrame Indicates the frame size was equal to or greater than the value set in the MaxFrameSize register. This bit is undefined until RxDMACom- plete bit is set. 22..21 Reserved Reserved for future use. Should be set to 0. 23 DribbleBits Indicates that the frame had accompanying dribble b[...]

76 Sundance Technology ST201 PRELIMINARY draft 2 R XDMAPOLLPERIO D Class .................... I/O Registers, DMA Base Address ...... IoBaseAddress register value Address Offset ..... 0x16 Access Mode ....... Read/Write Width ................... 8 bits The value in RxDMAPollPeriod determines the rate at which the current RFD is polled, looking for R[...]

77 Sundance Technology ST201 PRELIMINARY draft 2 R XDMAURGENTTHRES H Class .................... I/O Registers, DMA Base Address ...... IoBaseAddress register value Address Offset ..... 0x15 Access Mode ....... Read/Write Width ................... 8 bits The value in RxDMAUrgentThresh sets a threshold at which the RxDMA engine will make a urgent bus[...]

78 Sundance Technology ST201 PRELIMINARY draft 2 T XDMABURSTTHRES H Class .................... I/O Registers, DMA Base Address ...... IoBaseAddress register value Address Offset ..... 0x08 Access Mode ....... Read/Write Width ................... 8 bits TxDMABurstThresh determines the threshold for when the ST201 makes TxDMA bus master requests, bas[...]

79 Sundance Technology ST201 PRELIMINARY draft 2 T XDMALISTPT R Class .................... I/O Registers, DMA Base Address ...... IoBaseAddress register value Address Offset ..... 0x04 Access Mode ....... Read/Write Width ................... 32 bits TxDMAListPtr holds the physical address of the current TxDMA Frame Descriptor in the TxDMAList. A va[...]

80 Sundance Technology ST201 PRELIMINARY draft 2 T XDMAPOLLPERIO D Class .................... I/O Registers, DMA Base Address ...... IoBaseAddress register value Address Offset ..... 0x0a Access Mode ....... Read/Write Width ................... 8 bits The value in TxDMAPollPeriod determines the interval at which the current TFD is polled. When a ze[...]

81 Sundance Technology ST201 PRELIMINARY draft 2 T XDMAURGENTTHRES H Class .................... I/O Registers, DMA Base Address ...... IoBaseAddress register value Address Offset ..... 0x09 Access Mode ....... Read/Write Width ................... 8 bits When the number of used bytes in the TxFIFO falls below the value in the TxDMAUrgentThresh, the [...]

82 Sundance Technology ST201 PRELIMINARY draft 2 E EPROMCTR L Class .................... I/O Registers, External Interface Control Base Address ...... IoBaseAddress register value Address Offset ..... 0x36 Access Mode ....... Read/Write Width ................... 16 bits EepromCtrl provides the host with a method for issuing commands to the ST201 ?[...]

83 Sundance Technology ST201 PRELIMINARY draft 2 E EPROMDAT A Class .................... I/O Registers, External Interface Control Base Address ...... IoBaseAddress register value Address Offset ..... 0x34 Access Mode ....... Read/Write Width ................... 16 bits EepromData is a 16-bit data register for use with the adapter ’ s serial EEPR[...]

84 Sundance Technology ST201 PRELIMINARY draft 2 E XPROMADD R Class .................... I/O Registers, External Interface Control Base Address ...... IoBaseAddress register value Address Offset ..... 0x40 Access Mode ....... Read/Write Width ................... 32 bits ExpRomAddr holds the address to be used for direct I/O accesses of the Expansio[...]

85 Sundance Technology ST201 PRELIMINARY draft 2 E XPROMDAT A Class .................... I/O Registers, External Interface Control Base Address ...... IoBaseAddress register value Address Offset ..... 0x44 Access Mode ....... Read/Write Width ................... 8 bits ExpRomData is the data port for performing direct I/O byte-wide accesses of the [...]

86 Sundance Technology ST201 PRELIMINARY draft 2 PHYCTRL Class .................... I/O Registers, External Interface Control Base Address ...... IoBaseAddress register value Address Offset ..... 0x5e Access Mode ....... Read/Write Width ................... 8 bits This register contains control bits for the M II M anagement Interface. The MII Manag[...]

87 Sundance Technology ST201 PRELIMINARY draft 2 S TATISTICS Reading a statistic register will clear it. The statistics gathering must be enabled by setting the StatisticsEn- able bit in MACCtrl for the statistics registers to count events . BROADCASTFRAMESRECEIVEDOK Class .................... I/O Registers, Statistics Base Address ...... IoBaseAdd[...]

88 Sundance Technology ST201 PRELIMINARY draft 2 BROADCASTFRAMESTRANSMITTEDOK Class .................... I/O Registers, Statistics Base Address ...... IoBaseAddress register value Address Offset ..... 0x7c Access Mode ....... Read (also clears register)/ Write Width ................... 8 bits BIT BIT NAME BIT DESCRIPTION 7..0 Broadcast- FramesTrans[...]

89 Sundance Technology ST201 PRELIMINARY draft 2 CARRIERSENSEERRORS Class .................... I/O Registers, Statistics Base Address ...... IoBaseAddress register value Address Offset ..... 0x74 Access Mode ....... Read (also clears register)/ Write Width ................... 8 bits BIT BIT NAME BIT DESCRIPTION 3..0 CarrierSenseErrors This statisti[...]

90 Sundance Technology ST201 PRELIMINARY draft 2 F RAMESABORTEDDUETOXSCOLL S Class .................... I/O Registers, Statistics Base Address ...... IoBaseAddress register value Address Offset ..... 0x7b Access Mode ....... Read (also clears register)/ Write Width ................... 8 bits BIT BIT NAME BIT DESCRIPTION 7..0 FramesAbortedDu- eToXSC[...]

91 Sundance Technology ST201 PRELIMINARY draft 2 F RAMESLOSTRXERROR S Class .................... I/O Registers, Statistics Base Address ...... IoBaseAddress register value Address Offset ..... 0x79 Access Mode ....... Read (also clears register)/ Write Width ................... 8 bits BIT BIT NAME BIT DESCRIPTION 7..0 FramesLostRxEr- rors This stat[...]

92 Sundance Technology ST201 PRELIMINARY draft 2 FRAMESRECEIVEDOK Class .................... I/O Registers, Statistics Base Address ...... IoBaseAddress register value Address Offset ..... 0x72 Access Mode ....... Read (also clears register)/ Write Width ................... 16 bits BIT BIT NAME BIT DESCRIPTION 7..0 FramesReceive- dOk This statistic[...]

93 Sundance Technology ST201 PRELIMINARY draft 2 FRAMESTRANSMITTEDOK Class .................... I/O Registers, Statistics Base Address ...... IoBaseAddress register value Address Offset ..... 0x70 Access Mode ....... Read (also clears register)/ Write Width ................... 16 bits BIT BIT NAME BIT DESCRIPTION 7..0 FramesTransmitte- dOk This sta[...]

94 Sundance Technology ST201 PRELIMINARY draft 2 FRAMESWITHDEFERREDXMISSION Class .................... I/O Registers, Statistics Base Address ...... IoBaseAddress register value Address Offset ..... 0x78 Access Mode ....... Read (also clears register)/ Write Width ................... 8 bits BIT BIT NAME BIT DESCRIPTION 7..0 FramesWithDe- ferredXmis[...]

95 Sundance Technology ST201 PRELIMINARY draft 2 FRAMESWITHEXCESSIVEDEFERAL Class .................... I/O Registers, Statistics Base Address ...... IoBaseAddress register value Address Offset ..... 0x7a Access Mode ....... Read (also clears register)/ Write Width ................... 8 bits BIT BIT NAME BIT DESCRIPTION 7..0 FramesWithExces- siveDef[...]

96 Sundance Technology ST201 PRELIMINARY draft 2 LATECOLLISIONS Class .................... I/O Registers, Statistics Base Address ...... IoBaseAddress register value Address Offset ..... 0x75 Access Mode ....... Read (also clears register)/ Write Width ................... 8 bits BIT BIT NAME BIT DESCRIPTION 7..0 LateCollisions This statistic counts[...]

97 Sundance Technology ST201 PRELIMINARY draft 2 MULTICASTFRAMESRECEIVEDOK Class .................... I/O Registers, Statistics Base Address ...... IoBaseAddress register value Address Offset ..... 0x7f Access Mode ....... Read (also clears register)/ Write Width ................... 8 bits BIT BIT NAME BIT DESCRIPTION 7..0 MulticastFrames- Received[...]

98 Sundance Technology ST201 PRELIMINARY draft 2 MULTICASTFRAMESTRANSMITTEDOK Class .................... I/O Registers, Statistics Base Address ...... IoBaseAddress register value Address Offset ..... 0x7e Access Mode ....... Read (also clears register)/ Write Width ................... 8 bits BIT BIT NAME BIT DESCRIPTION 7..0 Multicast- FramesTrans[...]

99 Sundance Technology ST201 PRELIMINARY draft 2 MULTIPLECOLLISIONFRAMES Class .................... I/O Registers, Statistics Base Address ...... IoBaseAddress register value Address Offset ..... 0x76 Access Mode ....... Read (also clears register)/ Write Width ................... 8 bits BIT BIT NAME BIT DESCRIPTION 7..0 MultipleCollision- Frames T[...]

100 Sundance Technology ST201 PRELIMINARY draft 2 OCTETSRECEIVEDOK Class .................... I/O Registers, Statistics Base Address ...... IoBaseAddress register value Address Offset ..... 0x68 Access Mode ....... Read (also clears register)/ Write Width ................... 32 bits BIT BIT NAME BIT DESCRIPTION 19..0 OctetsReceivedOk This statistic[...]

101 Sundance Technology ST201 PRELIMINARY draft 2 OCTETSTRANSMITTEDOK Class .................... I/O Registers, Statistics Base Address ...... IoBaseAddress register value Address Offset ..... 0x6c Access Mode ....... Read (also clears register)/ Write Width ................... 32 bits BIT BIT NAME BIT DESCRIPTION 19..0 OctetsTransmitte- dOk This s[...]

102 Sundance Technology ST201 PRELIMINARY draft 2 SINGLECOLLISIONFRAMES Class .................... I/O Registers, Statistics Base Address ...... IoBaseAddress register value Address Offset ..... 0x77 Access Mode ....... Read (also clears register)/ Write Width ................... 8 bits BIT BIT NAME BIT DESCRIPTION 7..0 SingleCollision- Frames This[...]

103 Sundance Technology ST201 PRELIMINARY draft 2 P CI CONFIGURATION REGISTERS PCI based systems u se a slot-specific block of configuration registers to perform c onfiguration of devices on the PCI bus. The configuration registers are accessed with PCI Configuration Cycles . The P CI bus sup- ports two types of Configuration Cycles. Type 0 cycles [...]

104 Sundance Technology ST201 PRELIMINARY draft 2 byte 3 byte 2 byte 1 byte 0 Offset FIGURE 12: ST201 PCI Register Layout Reserved PowerMgmtCtrl 0x54 Reserved 0x60 Reserved 0x5c Reserved 0x58 PowerMgmtCap NextItemPtr CapId 0x50 Reserved 0x4c Reserved 0x48 Reserved 0x44 Reserved 0x40 MinGnt InterruptPin InterruptLine 0x3c MaxLat Reserved 0x38 ExpRom[...]

105 Sundance Technology ST201 PRELIMINARY draft 2 C ACHELINESIZ E Class .................... PCI Configuration Registers, Configuration Base Address ...... PCI device configuration header start Address Offset ..... 0x0c Access Mode ....... Read/Write Width ................... 8 bits BIT BIT NAME BIT DESCRIPTION 7..0 CacheLineSize The system BIOS wr[...]

106 Sundance Technology ST201 PRELIMINARY draft 2 CAPPTR Class .................... PCI Configuration Registers, Configuration Base Address ...... PCI device configuration header start Address Offset ..... 0x34 Access Mode ....... Read Only Width ................... 8 bits BIT BIT NAME BIT DESCRIPTION 7..0 CapPtr This is a hard-coded value pointing[...]

107 Sundance Technology ST201 PRELIMINARY draft 2 CLASSCODE Class .................... PCI Configuration Registers, Configuration Base Address ...... PCI device configuration header start Address Offset ..... 0x09 Access Mode ....... Read Only Width ................... 24 bits BIT BIT NAME BIT DESCRIPTION 23..0 ClassCode This register identifies th[...]

108 Sundance Technology ST201 PRELIMINARY draft 2 CONFIGCOMMAND Class .................... PCI Configuration Registers, Configuration Base Address ...... PCI device configuration header start Address Offset ..... 0x04 Access Mode ....... Read/Write Width ................... 16 bits This register provides control over the adapter ’ s ability to ge[...]

109 Sundance Technology ST201 PRELIMINARY draft 2 CONFIGSTATUS Class .................... PCI Configuration Registers, Configuration Base Address ...... PCI device configuration header start Address Offset ..... 0x06 Access Mode ....... Read/Write Width ................... 16 bits This register is used to record status information for PCI bus event[...]

110 Sundance Technology ST201 PRELIMINARY draft 2 DEVICEID Class .................... PCI Configuration Registers, Configuration Base Address ...... PCI device configuration header start Address Offset ..... 0x02 Access Mode ....... Read Only Width ................... 16 bits BIT BIT NAME BIT DESCRIPTION 15..0 DeviceId This register contains the 16[...]

111 Sundance Technology ST201 PRELIMINARY draft 2 E XPROMBASEADDRESS Class .................... PCI Configuration Registers, Configuration Base Address ...... PCI device configuration header start Address Offset ..... 0x30 Access Mode ....... Read/Write Width ................... 32 bits This read/write register allows the system to define the base [...]

112 Sundance Technology ST201 PRELIMINARY draft 2 HEADERTYPE Class .................... PCI Configuration Registers, Configuration Base Address ...... PCI device configuration header start Address Offset ..... 0x0e Access Mode ....... Read Only Width ................... 8 bits BIT BIT NAME BIT DESCRIPTION 7..0 HeaderType This register is hard-wired[...]

113 Sundance Technology ST201 PRELIMINARY draft 2 INTERRUPTLINE Class .................... PCI Configuration Registers, Configuration Base Address ...... PCI device configuration header start Address Offset ..... 0x3c Access Mode ....... Read/Write Width ................... 8 bits BIT BIT NAME BIT DESCRIPTION 7..0 InterruptLine This register is wri[...]

114 Sundance Technology ST201 PRELIMINARY draft 2 INTERRUPTPIN Class .................... PCI Configuration Registers, Configuration Base Address ...... PCI device configuration header start Address Offset ..... 0x3d Access Mode ....... Read Only Width ................... 8 bits BIT BIT NAME BIT DESCRIPTION 7..0 InterruptPin This register indicates[...]

115 Sundance Technology ST201 PRELIMINARY draft 2 IOBASEADDRESS Class .................... PCI Configuration Registers, Configuration Base Address ...... PCI device configuration header start Address Offset ..... 0x10 Access Mode ....... Read/Write Width ................... 32 bits The host uses this register to define the I/O base address for the [...]

116 Sundance Technology ST201 PRELIMINARY draft 2 LATENCYTIMER Class .................... PCI Configuration Registers, Configuration Base Address ...... PCI device configuration header start Address Offset ..... 0x0d Access Mode ....... Read/Write Width ................... 8 bits This register specifies, in units of PCI bus clocks, the value of the[...]

117 Sundance Technology ST201 PRELIMINARY draft 2 MAXLAT Class .................... PCI Configuration Registers, Configuration Base Address ...... PCI device configuration header start Address Offset ..... 0x3f Access Mode ....... Read Only Width ................... 8 bits BIT BIT NAME BIT DESCRIPTION 7..0 MaxLat MaxLat specifies, in 250 ns increme[...]

118 Sundance Technology ST201 PRELIMINARY draft 2 MEMBASEADDRESS Class .................... PCI Configuration Registers, Configuration Base Address ...... PCI device configuration header start Address Offset ..... 0x14 Access Mode ....... Read/Write Width ................... 32 bits The host uses this register to define the memory base address for [...]

119 Sundance Technology ST201 PRELIMINARY draft 2 MINGNT Class .................... PCI Configuration Registers, Configuration Base Address ...... PCI device configuration header start Address Offset ..... 0x3e Access Mode ....... Read Only Width ................... 8 bits BIT BIT NAME BIT DESCRIPTION 7..0 MinGnt MinGnt specifies, in 250 ns increme[...]

120 Sundance Technology ST201 PRELIMINARY draft 2 REVISIONID Class .................... PCI Configuration Registers, Configuration Base Address ...... PCI device configuration header start Address Offset ..... 0x08 Access Mode ....... Read Only Width ................... 8 bits BIT BIT NAME BIT DESCRIPTION 7..0 RevisionId This register provides a re[...]

121 Sundance Technology ST201 PRELIMINARY draft 2 SUBSYSTEMID Class .................... PCI Configuration Registers, Configuration Base Address ...... PCI device configuration header start Address Offset ..... 0x2e Access Mode ....... Read Only Width ................... 16 bits BIT BIT NAME BIT DESCRIPTION 15..0 SubsystemId This is the value read [...]

122 Sundance Technology ST201 PRELIMINARY draft 2 SUBSYSTEMVENDORID Class .................... PCI Configuration Registers, Configuration Base Address ...... PCI device configuration header start Address Offset ..... 0x2c Access Mode ....... Read Only Width ................... 16 bits BIT BIT NAME BIT DESCRIPTION 15..0 SubsystemVen- dorId This valu[...]

123 Sundance Technology ST201 PRELIMINARY draft 2 VENDORID Class .................... PCI Configuration Registers, Configuration Base Address ...... PCI device configuration header start Address Offset ..... 0x00 Access Mode ....... Read Only Width ................... 16 bits BIT BIT NAME BIT DESCRIPTION 15..0 VendorId This register contains the un[...]

124 Sundance Technology ST201 PRELIMINARY draft 2 CAPID Class .................... PCI Configuration Registers, Power Management Base Address ...... PCI device configuration header start Address Offset ..... 0x50 Access Mode ....... Read Only Width ................... 8 bits BIT BIT NAME BIT DESCRIPTION 7..0 CapId This register indicates the type o[...]

125 Sundance Technology ST201 PRELIMINARY draft 2 NEXTITEMPTR Class .................... PCI Configuration Registers, Power Management Base Address ...... PCI device configuration header start Address Offset ..... 0x51 Access Mode ....... Read Only Width ................... 8 bits BIT BIT NAME BIT DESCRIPTION 7..0 NextItemPtr This register points t[...]

126 Sundance Technology ST201 PRELIMINARY draft 2 POWERMGMTCAP Class .................... PCI Configuration Registers, Power Management Base Address ...... PCI device configuration header start Address Offset ..... 0x52 Access Mode ....... Read Only Width ................... 16 bits This register provides information about the adapter ’ s power m[...]

127 Sundance Technology ST201 PRELIMINARY draft 2 P OWERMGMTCTRL Class .................... PCI Configuration Registers, Power Management Base Address ...... PCI device configuration header start Address Offset ..... 0x54 Access Mode ....... Read/Write Width ................... 16 bits This register allows control over the power state and the power[...]

128 Sundance Technology ST201 PRELIMINARY draft 2 E EPROM DATA FORMAT Figure 13 s ummarizes the layout o f the EEPROM. byte 0 Offset FIGURE 13: EEPROM Data Layout ConfigParam 0x00 StationAddress2 0x14 StationAddress1 0x12 StationAddress0 0x10 SubSystemId 0x06 SubSystemVendorId 0x04 AsicCtrl 0x02 byte 1[...]

129 Sundance Technology ST201 PRELIMINARY draft 2 C ONFIGPARM Class .................... EEPROM Data Format Base Address ...... 0x00, address written to EepromCtrl register Address Offset ..... 0x00 Access Mode ....... Read Only Width ................... 16 bits This is loaded into the ST201 and controls various hardware functions related to PCI bu[...]

130 Sundance Technology ST201 PRELIMINARY draft 2 STATIONADDRESS Class .................... EEPROM Data Format Base Address ...... 0x00, address written to EepromCtrl register Address Offset ..... 0x10, 0x12, 0x14 Access Mode ....... Read Only Width ................... 48 bits This is the field to be programmed into the StationAddress register. OEM[...]

131 Sundance Technology ST201 PRELIMINARY draft 2 ASICCTRL Class .................... EEPROM Data Format Base Address ...... 0x00, address written to EepromCtrl register Address Offset ..... 0x02 Access Mode ....... Read Only Width ................... 16 bits This word supplies the value for the least significant byte of the AsicCtrl I/O Register. [...]

132 Sundance Technology ST201 PRELIMINARY draft 2 14..8 Reserved Reserved for future use. Should be set to 0. 15 ResetP olarity Setting this read/write bit will cause the RSTOUT p in to be asserted in the HIGH state (default after RESET). BIT BIT NAME BIT DESCRIPTION[...]

133 Sundance Technology ST201 PRELIMINARY draft 2 S UBSYSTEMVENDORID Class .................... EEPROM Data Format Base Address ...... 0x00, address written to EepromCtrl register Address Offset .... 0x04 Access Mode ....... Read Only Width ................... 16 bits BIT BIT NAME BIT DESCRIPTION 15..0 SubsystemVen- dorId This is the two-byte subsy[...]

134 Sundance Technology ST201 PRELIMINARY draft 2 SUBSYSTEMID Class .................... EEPROM Data Format Base Address ...... 0x00, address written to EepromCtrl register Address Offset .... 0x06 Access Mode ....... Read Only Width ................... 16 bits BIT BIT NAME BIT DESCRIPTION 15..0 SubsystemId This is the two-byte subsystem ID for the[...]

135 Sundance Technology ST201 PRELIMINARY draft 2 AB SOLUTE MA XIMUM RA TINGS Storage Temperature .................. -65ºC to +150ºC Ambient Temperature .................... -65ºC to +70ºC Supply Voltage ............................... -0.3V to +6.0V Environmental stresses above those listed in Ab so- lute Ma ximum Ra tings may cause permanent [...]

136 Sundance Technology ST201 PRELIMINARY draft 2 D C CHARACTERISTICS DC characteristics are defined over commercial operating ranges unless specified otherwise. PARAMETER S YMBOL PARAMETER DESCRIPTION TEST CONDITIONS MIN MAX UNIT PIN TYPE IT (TTL, PCI INPUT BUFFER) V IH In put high voltage 2 V V IL In put low voltage 0.8 V I IN In put leak age cu [...]

137 Sundance Technology ST201 PRELIMINARY draft 2 PIN TYPE OD6 (OPEN DRAIN OUTPUT BUFFER) V OL Output low voltage I OL = 6mA 0.4 V I OZ Output leakage current V IN = V DD /V SS -1 0 10 µA PIN TYPE OD8 (OPEN DRAIN OUTPUT BUFFER) V OL Output low voltage I OL = 8mA 0.4 V I OZ Output leakage current V IN = V DD /V SS -1 0 10 µA PIN TYPE PINS PCI INTE[...]

138 Sundance Technology ST201 PRELIMINARY draft 2 MISC INTERFACE ITU/OT4 GPIO0, GPIO1 OT4 RSTOUT OD8 LEDPWRN, LEDLNKN, LEDDPLXN, LEDSPDN OC4 CLK25 OSCI X25I OSCOH1 X25O PIN TYPE PINS TABLE 5: Pin Type Assignment[...]

139 Sundance Technology ST201 PRELIMINARY draft 2 SWITCHING CHARACTERISTIC S PARAMETER S YMBOL PARAMETER DESCRIPTION TEST CONDITIONS MIN MAX UNIT PCI INTERFACE T rc RSTN cycle 300 - - T cc PCICLK cycle 30 - - T ch PCICLK high 11 - - T cl PCICLK low 11 - - T rv PCICLK rise to bused signal valid 2 11 - T rvp PCICLK rise to REQN, GNTN valid 2 12 - T r[...]

140 Sundance Technology ST201 PRELIMINARY draft 2 T wh EWEN write cycle high 100 - - T wl EWEN write cycle low 90 - - EEPROM INTERFACE T skc EESK cycle 1us - - T skh EESK high 250 - - T skl EESK low 250 - - T cs EECS low 250 - - T pd EEDI valid w rt EESK rise 100 - - T cs k EECS setup wrt EESK rise 50 - - T csh EECS hold wrt EESK fall 0 - - T do s [...]

141 Sundance Technology ST201 PRELIMINARY draft 2 MII INTERFACE - M ANAGEMENT T cc MDC cycle 400 - - T ch MDC high 160 - - T cl MDC low 160 - - T su MDIO setup wrt MDC rise 10 - - T hd MDIO hold wrt MDC rise 10 - - T rv MDC rise to MDIO valid - 20 - MISC INTERFACE T cc CLK25 cycle -- 40 T ch CLK25 high 16 24 - T cl CLK25 low 16 24 - PARAMETER S YMB[...]

142 Sundance Technology ST201 PRELIMINARY draft 2 t abc ST2 01 RSTN PCICLK GNTN REQN BUSSED t rc t cl t cc t ch t rv t rvp t rvp t roz t su t sup2 t rzo t sup1 t hd t rstoff SIGNALS ANY SIGNAL ANY SIGNAL FIGURE 14: PCI Switching Characteristics EOEN EWEN E A[15..0] E D[7..0] t odv t a dv t dvz t os t wl t oh t ah t as t wh t dh t ds ST20 1 Read Loa[...]

143 Sundance Technology ST201 PRELIMINARY draft 2 EE CS EE SK EE DI EE DO D0 D15 A7 A0 t cs t skl t csk t skh t pd t dos t doh t csh ST201 FIGURE 16: EEPROM Switching Characteristics t skc[...]

144 Sundance Technology ST201 PRELIMINARY draft 2 ST201 t rv t rh t rh t cl t cc t ch t su t hd t cl t cc t ch t su t hd t su t hd t rv t rv t hd t cl t cc t ch TXD[3..0] TXEN TXCLK RXD[3..0] RX ER RX DV RX CLK MDIO MDC t su Transmit Receive Management FIGURE 17: MII Switching Characteristics[...]

Copyright Sundance Technology, Inc., 1998. The information contained in this data sheet is subject to change without notice. Sun - dance Technology assumes no responsibility for the use of any circuitry other than circuitry embodied in a Sundance Technology product. Nor does it convey or imply any license under patent or other rights. Sundance Tech[...]