Texas Instruments TAS3002 инструкция обслуживания

        2001 Digital Audio: Digital Speakers Data Manua l SLAS307B[...]

IMPORT ANT NOTICE T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify , before placing orders, that information being relied on is current and complete. All product[...]

1−1 1 Introduction 1.1 Description The T AS3002 device is a system-on-a-chip that replaces conventional analog equalization to perform digital parametric equalization, dynamic range compression, and loudness contour . Additionally , this device provides high-quality , soft digital volume, bass, and treble control. All control parameters are uploa[...]

1−2 • T wo I 2 C-selectable, single-ended analog input stereo channels • Equalization bypass mode • Single 3.3-V power supply • Power down without reloading the coefficients • Sampling rates of 32 kHz, 44.1 kHz, or 48 kHz • Master clock frequency of 256 f S or 512 f S • Can have crystal input to replace MCLK. Crystal input frequency[...]

1−3 Control PWR_DN TEST AINRP AINRM AINLM AINLP 24-Bit Stereo ADC RINA RINB AINRM AINRP AINLM AINLP LINA LINB Control CS1 SDA SCL Controller GPI0 GPI1 GPI2 GPI3 GPI4 GPI5 24-Bit Stereo DAC CAP_PLL MCLK XT ALO MCLKO CLKSEL SDIN2 SDIN1 SDA T A Control LRCLK/O SCLK/O SDOUT1 L L+R SDOUT2 32-Bit Audio Signal Processor AOUTL VCOM AOUTR L+R R 32-Bit Aud[...]

1−4 1.4 T erminal Assignments Figure 1−2 shows the terminal locations on the package outline, along with the signal name assigned to each terminal. 14 15 NC AV DD NC GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 ALLP ASS SDOUT1 SDOUT0 36 35 34 33 32 31 30 29 28 27 26 25 16 1 2 3 4 5 6 7 8 9 10 11 12 LINA V RFIL T AV SS(REF) AV SS INP A RESET CS1 PWR_DN TEST CA[...]

1−5 T able 1−1. T AS3002 T erminal Functions (Continued) TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION CAP_PLL 10 I Loop filter for internal phase-locked loop (PLL) CLKSEL 11 I Logic low selects 256 f S ; logic high selects 512 f S MCLK CS1 7 I I 2 C address bit A0; low = 68h, high = 6Ah DV DD 17 I Digital power supply (3.3 V) DV SS 18 I Di[...]

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2−1 2 Audio Data Formats 2.1 Serial Interface Formats The T AS3002 device works in master or slave mode. In the master mode, terminal 21 (IFM/S ) is tied high. This activates the master clock (MCLK) circuitry . A crystal can be connected across terminals 13 (XT ALI/MCLK) and 14 (XT ALO), or an external, TTL-compatible MCLK can be connected t o X [...]

2−2 2.2 Digital Output Modes The digital output modes (SDOUT1, SDOUT2, SDOUT0) are described in Sections 2.2.1 through 2.2.3. 2.2.1 MSB-First, Right-Justified, Serial-Interface Format Th e normal output mode for the MSB-first, right-justified, serial-interface format is for 16, 18, 20, or 24 bits. Figure 2−1 shows the following characteristics [...]

2−3 2.2.2 I 2 S Serial-Interface Format The normal output mode for the I 2 S serial-interface format is for 16, 18, 20, or 24 bits. Figure 2−2 shows the following characteristics of this protocol: • Left channel is transmitted when LRCLK is low . • SDIN is sampled with the rising edge of SCLK. • SDOUT is transmitted on the falling edge of[...]

2−4 2.2.3 MSB-Left-Justified, Serial-Interface Format The normal output mode for the MSB-left-justified, serial-interface format is for 16, 18, 20, or 24 bits. Figure 2−3 shows the following characteristics of this protocol: • Left channel is transmitted when LRCLK is high. • The SDIN data is justified to the leading edge of the LRCLK. • [...]

2−5 2.3 Switching Characteristics P ARAMETER MIN TYP MAX UNIT t c(SCLK) SCLK cycle time 325.5 ns t d(SLR) SCLK rising to LRCLK edge 20 ns t d(SDOUT) SDOUT valid from SCLK falling edge (see Note 1) (1/256 f S ) + 10 ns t su(SDIN) SDIN setup before SCLK rising edge 20 ns t h(SDIN) SDIN hold after SCLK rising edge 100 ns f (LRCLK) LRCLK frequency 32[...]

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3−1 3 Analog Input/Output The T AS3002 device contains a stereo 24-bit ADC with two single-ended inputs per channel. Selection of the A or B analog input is accomplished by setting a bit in the analog control register (ACR) by an I 2 C command. Additionally , the T AS3002 device has a stereo 24-bit digital-to-analog converter (DAC). 3.1 Analog In[...]

3−2 AOUTR 10 µ F 24-Bit DAC AOUTL VCOM + 0.1 µ F AGND Analog Output (Adjust Capacitors for Desired Low Frequency Response) Figure 3−2. VCOM Decoupling Network 3.2.2 Analog Output With Gain Because the maximum analog output from the T AS3002 device is 0.707 V rms , the output level can be increased by using an external amplifier . The circuit [...]

3−3 3.2.3 Reference V oltage Filter Figure 3−4 shows the T AS3002 reference voltage filter . 0.1 µ F 15 µ F + 0.1 µ F 1 µ F + 0.1 µ F 4 2 3 45 44 V REFP AV SS AV SS(REF) V RFIL T V REFM T AS3002 Figure 3−4. T AS3002 Reference V oltage Filter[...]

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4−1 4 Audio Control/Enhancement Functions 4.1 Soft V olume Update The T AS3002 device implements a TI proprietary soft volume update. This feature allows a smooth and pleasant-sounding change from one volume level to another over the entire range of volume control (18 dB to mute). The volume is adjustable by downloading a gain coefficient through[...]

4−2 SDIN2_L 7 Biquad Filters T one Soft V olume DRCE SDIN1_L ADC_L SDOUT1 7 Biquad Filters T one Soft V olume DRCE SDIN2_R SDIN1_R ADC_R SDOUT2 1/2 L + R_SUM Right Channel Mix Coefficients I 2 C Register Address 07h SDIN1 ^ SDIN2 ^ ADC = (3) 24-Bit Right Mix Coefficient Left Channel Mix Coefficients I 2 C Register Address 08h = (3) 24-Bit Left Mi[...]

4−3 4.6 Bass Control Th e bass gain level can be adjusted within the range of 15 dB to − 15 dB with 0.5-dB step resolution. The level changes are accomplished by downloading bass codes (shown in NO T AG) into the bass frequency control register . Alternatively , a limited range of bass control is available by asserting the bass-up or bass-down [...]

4−4 4.8 Analog Control Register (40h) The analog control register (ACR) allows control of de-emphasis, selection of the analog input channel to the ADC, and analog power down. An I 2 C master is required to write the appropriate command into the ACR. The ACR subaddress is 40h. Bit 7 6 5 4 3 2 1 0 T ype R/W R/W R/W R/W R/W R/W R/W R/W Default 0000[...]

4−5 4.9 Dynamic Loudness Contour The necessity for applying loudness compensation to playback systems to compensate for the fact that the ear perceives bass and treble less audibly at low levels than at high ones has been established since the first data was published by Fletcher and Munson in 1933. There are many equal-loudness contours in publi[...]

4−6 4.10 Dynamic Range Compression/Expansion (DRCE) Th e TAS3002 device provides the user with the ability to manage the dynamic range of the audio system. The DRCE receives data, and affects scaling after the volume/loudness block. As shown in Figure 4−4, the DRCE is applied after the volume/loudness control block as a DRCE scale factor. The D[...]

4−7 4.12 Main Control Register 1 (01h) The T AS3002 device contains two main control registers: main control register 1 (MCR1) and main control register 2 (MCR2). The MCR1 register contains the bits associated with load speed, SCLK frequency , serial-port mode, and serial-port word length. It is accessed via I 2 C with the address 01h. MCR1 (01h)[...]

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5−1 5 Filter Processor 5.1 Biquad Block The biquad block consists of seven digital biquad filters per channel organized in a cascade structure, as shown in Figure 5−1. Each of these biquad filters has five downloadable 24-bit (4.20) coef ficients. Each stereo channel has independent coefficients. Biquad 1 ... Biquad 0 Biquad 6 Figure 5−1. Biq[...]

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6−1 6I 2 C Serial Control Interface 6.1 Introduction Control parameters for the T AS3002 device can be loaded from a n I 2 C serial EEPROM by using the T AS3002 master interface mode. If no EEPROM is found, the T AS3002 device becomes a slave device and loads from another I 2 C master interface. Information loaded into the T AS3002 registers is d[...]

6−2 T able 6−1 lists the definitions used by the I 2 C protocol. T able 6−1. I 2 C Protocol Definitions DEFINITION DESCRIPTION T ransmitter The device that sends data Receiver The device that receives data Master The device that initiates a transfer , generates clock signals, and terminates the transfer Slave The device addressed by the maste[...]

6−3 6.3.2 T AS3002 I 2 C Readback Example The T AS3002 saves in a stack or first-in first-out (FIFO) buffer the last 7 bytes that were sent to it. When an I 2 C read command is sent to the device (LSB=high), it answers by popping the first byte off the stack. The T AS3002 then expects either a Send Ack command or an I 2 C Stop command from the ho[...]

6−4 T able 6−3 gives typical values of the wait states that can be expected with the various functions of the part: T able 6−3. I 2 C W ait States SYSTEM SAMPLING FREQUENCY 32 kHz 44.1 kHz 48 kHz Comment V olume 62 ms 49 ms 41 ms Not dependent on size of change Bass 231 ms 167 ms 153 ms 0 to −18 dB T reble 231 ms 167 ms 153 ms 0 to −18 dB[...]

6−5 6.4.3 W ait States If separate I 2 C/SMBus commands are sent too frequently , the T AS3002 device can generate a bus wait state. This happens when the device is busy while performing smoothing operations and changing volume, bass, and treble. Th e wait occurs after the bus acknowledge on the first data byte and can exceed the maximum allowabl[...]

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7−1 7 Microcontroller Operation The T AS3002 device contains an internal microcontroller programmed by T exas Instruments to perform housekeeping and interface functions. Additionally , it handles I 2 C communication and general purpose input functions. 7.1 General Description The microcontroller uses a 256 f S system clock and can access up to 8[...]

7−2 • Clears all the registers in the circuits • Purges the codec • Selects analog input A (RINA and LINA) and sets the input A active indicator (INP A ) low • Initializes the equalization parameters to AllPass filters • Sets the digital audio interface to the I 2 S 18-bit mode • Sets the bass/treble to 0 dB • Sets the mixer gain to[...]

7−3 Bass and treble cannot download in this mode. Mixer1 and Mixer2 registers can download in this mode or normal mode (FL bit = 0). Once the download is complete, the fast load bit must be cleared by writing a 0 into bit 7 of main control register 1 (MCR1). This puts the T AS3002 device into normal mode. 7.2.5 Codec Reset During initialization, [...]

7−4 7.3.1 Power-Down Timing Sequence PWR_DN Power-Down Mode RESET MCLK SCLK LRCLK SDA T A 1 ms Normal Operation Figure 7−2. Power-Down Timing Sequence In power-down mode, the T AS3002 device typically consumes less than 1 mA. 7.4 T est Mode T erminal 9 (TEST) is tied low in normal operation. This function is reserved for factory test and must n[...]

7−5 T able 7−1. GPI T erminal Programming GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 VOL_UP , +1 dB x VOL_DN, −1 dB x BASS_UP , +1 dB x BASS_DN, −1 dB x TREB_UP , +1 dB x TREB_DN, −1 dB x Shift 1 x x Mute x EQ1 x EQ2 x EQ3 x EQ4 x EQ5 x Shift 2 x x NOTE: x = Logic low Initially (after reset), the T AS3002 GPI is set to control volume, bass, and treble[...]

7−6 Start Power Up Initialize Default EEPROM Restore V olume and MCR Slave Write Initialize T AS3002 T AS3001 GPI Power Down Load Parameters and Coefficients to DSP V olume/Bass/T reble Up/Down Echo to T AS3001 Switch BQ Set Save V olume, Mute Save PWR_DN Stop PLL Stop DRC_OFF DRC Figure 7−3. Internal Interface Flow Chart[...]

7−7 7.7 External EEPROM Memory Maps T able 7−2 through T able 7−5 show the 512-byte and 2048-byte EEPROM memory maps. T able 7−2. 512-Byte EEPROM Memory Map 2.0 Channels ADDRESS BYTE NUMBER FUNCTION 000h 1 Signature (2Ah) 001h 1 ID byte = 0000 0000 002h 1 MCR 003h−00Bh 9 Mixer left gain 00Ch−014h 9 Mixer right gain 015h−01Ah 2 DRC (ra[...]

7−8 T able 7−3. 512-Byte EEPROM Memory Map 2.1 Channels (with T AS3001) ADDRESS BYTE NUMBER FUNCTION 000h 1 Signature (2Ah) 001h 1 ID byte = 0000 001 1 T AS3002 002h 1 MCR 003h−00Bh 9 Mixer left gain 00Ch−014h 9 Mixer right gain 015h−01Ah 6 DRC (ratio, threshold, energy α , attack α , decay α ) 01Bh 1 Bass 01Ch 1 T reble 01Dh−022h 6 [...]

7−9 T able 7−4. 2048-Byte EEPROM Memory Map—2.0 Speakers With Multiple Equalizations T AS3002 ADDRESS LEFT BIQUAD NUMBER OF BYTES FUNCTION CA TEGORY T AS3002 ADDRESS RIGHT BIQUAD T AS3001 000h 1 Signature (2Ah) 001h 1 1 0 0 0 0 0 1 0 002h 1 MCR 1EFh 003h−00Bh 9/3 Mixer left gain 1F0h−1F2h 00Ch−014h 9/3 Mixer right gain 1F3h−1F5h 015h?[...]

7−10 T able 7−5. 2048-Byte EEPROM Memory Map—2.1 Speakers With Multiple Equalizations T AS3002 ADDRESS NUMBER OF BYTES FUNCTION CA TEGORY T AS3001 ADDRESS LEFT CHANNEL T AS3001 ADDRESS RIGHT CHANNEL 000h 1 Signature (2Ah) 001h 1 1 0 0 0 0 0 0 1 002h 1 MCR 1EFh 003h−00Bh 9/3 Mixer left gain 1F0h−1F2h 00Ch−014h 9/3 Mixer right gain 1F3h?[...]

8−1 8 Electrical Characteristics 8.1 Absolute Maximum Ratings Over Operating T emperature Ranges † Supply voltage range: A V DD − 0.3 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DV DD − 0.3 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

8−2 8.4 ADC Digital Filter T A = 25 ° C, A V DD = 3.3 V , DV DD = 3.3 V , f S = 48 kHz, 20-bit I 2 S mode All terms characterized by frequency are scaled with the chosen sampling frequency , f S . See Figure 8−1 through Figure 8−4 for performance curves of the ADC digital filter . P ARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC decimation fi[...]

8−3 0.002 −0.002 Amplitude − dB 0.004 0.006 0.008 0 0 f − Frequency − Hz 0.1 f s 0.2 f s 0.3 f s 0.4 f s 0.5 f s Figure 8−3. ADC Digital Filter Pass-Band Characteristics −0.4 −1 Amplitude − dB −0.2 0 0.2 −0.6 −0.8 0 f − Frequency − Hz 1 f s 2 f s 3 f s 4 f s Figure 8−4. ADC High-Pass Filter Characteristics 8.5 Analog-t[...]

8−4 8.6 Input Multiplexer T A = 25 ° C, A V DD = 3.3 V , DV DD = 3.3 V , f S = 48 kHz, 20-bit I 2 S mode P ARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input impedance 20 k Ω Crosstalk 85 dB Full-scale input voltage range 1.7 V PP 8.7 DAC Interpolation Filter T A = 25 ° C, A V DD = 3.3 V , DV DD = 3.3 V , f S = 48 kHz, 20-bit I 2 S mode All term[...]

8−5 8.8 Digital-to-Analog Converter T A = 25 ° C, A V DD = 3.3 V , DV DD = 3.3 V , f S = 48 kHz, input = 0 dB-f S sine wave at 1 kHz P ARAMETER TEST CONDITIONS MIN TYP MAX UNIT SNR (EIAJ) A weighted 94 99 dB Dynamic range −60 dB, 1 kHz 92 96 dB Signal to (noise + distortion) ratio 0 dB, 1 kHz, 20 Hz to 20 kHz 83 dB Power supply rejection ratio[...]

8−6 8.10 I 2 C Serial Port Timing Characteristics MIN MAX UNIT f (SCL) SCL clock frequency 0 100 kHz t (buf) Bus free time between start and stop 4.7 µ s t (low) Low period of SCL clock 4.7 µ s t (high) High period of SCL clock 4.0 µ s t h(sta) Hold time repeated start 4.0 µ s t su (sta) Setup time repeated start 4.7 20 µ s t h(dat) Data hol[...]

9−1 9 System Diagrams Figure 9−1 and Figure 9−2 show the T AS3002 stereo and 2.1-channel applications, respectively . T AS3002 Master RESET Analog In +3.3 V DD Analog Out SPDIF or USB I 2 S EEPROM I 2 C Clock Select Logic B-T -V -EQ Switches NOTE: Items such as the PLL network and power supplies are omitted for clarity . Figure 9−1. Stereo [...]

9−2 L+R Mix Echoes Switches on GPIO T AS3002 Master RESET Analog In +3.3 V DD Analog Out (T o Satellite Amplifiers) SPDIF or USB I 2 S EEPROM I 2 C Clock Select Logic B-T -V -EQ-Sub V ol I 2 C T AS3001 Address = 6Ah I 2 S_OUT Slave Analog Ou t SDOUT2 I 2 S PCM1744 NOTE: Items such as the PLL network and power supplies are omitted for clarity . Fi[...]

10−1 10 Mechanical Information The T AS3002 device is packaged in a 48-terminal PFB package. The following illustration shows the mechanical dimensions for the PFB package. PFB (S-PQFP-G48) PLASTIC QUAD FLA TP ACK 4073176 / B 10/96 Gage Plane 0,13 NOM 0,25 0,45 0,75 Seating Plane 0,05 MIN 0,17 0,27 24 25 13 12 SQ 36 37 7,20 6,80 48 1 5,50 TYP SQ [...]

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