Texas Instruments TMS320C645x DSP инструкция обслуживания

TMS320C645x DSP Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) User's Guide Literature Number: SPRU975B August 2006[...]

2 SPRU975B – August 2006 Submit Documentation Feedback[...]

Contents Preface .............................................................................................................................. 10 1 Introduction .............................................................................................................. 11 1.1 Purpose of the Peripheral ............................................[...]

4.15 MDIO User PHY Select Register 1 (USERPHYSEL1) .................................................... 80 5 EMAC Port Registers ................................................................................................. 81 5.1 Introduction ...................................................................................................... [...]

5.48 Transmit Channel 0-7 Completion Pointer Register (TX n CP) ........................................... 134 5.49 Receive Channel 0-7 Completion Pointer Register (RX n CP) ........................................... 135 5.50 Network Statistics Registers ................................................................................. 136 Appendi[...]

List of Figures 1 EMAC and MDIO Block Diagram ........................................................................................ 12 2 Ethernet Configuration with MII Interface ............................................................................... 16 3 Ethernet Configuration with RMII Interface ........................................[...]

53 Receive Buffer Offset Register (RXBUFFEROFFSET) .............................................................. 109 54 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) .............................. 110 55 Receive Channel n Flow Control Threshold Register (RX n FLOWTHRESH) ..................................... 111 56 Recei[...]

List of Tables 1 Interface Selection Pins ................................................................................................... 16 2 EMAC and MDIO Signals for MII Interface ............................................................................. 17 3 EMAC and MDIO Signals for RMII Interface .......................................[...]

50 Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions .................................... 106 51 Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions ....................................... 107 52 Receive Maximum Length Register (RXMAXLEN) Field Descriptions ............................................ 108 53 Recei[...]

Preface SPRU975B – August 2006 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) and Physical layer (PHY) device Management Data Input/Output (MDIO) module integrated with TMS320C645x devices. Notational Conventions This document uses the following conventions. • Hex[...]

1 Introduction 1.1 Purpose of the Peripheral 1.2 Features User's Guide SPRU975B – August 2006 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) This document provides a functional description of the Ethernet Media Access Controller (EMAC) and Physical layer (PHY) device Management Data Input/Output (MDIO) module int[...]

www.ti.com 1.3 Functional Block Diagram Configuration bus DMA memory transfer controller Peripheral bus EMAC control module EMAC module MDIO module MII MDIO bus EMAC/MDIO interrupt Interrupt controller RMII GMII RGMII Introduction Figure 1 shows the three main functional modules of the EMAC/MDIO peripheral: • EMAC control module • EMAC module ?[...]

www.ti.com 1.4 Industry Standard(s) Compliance Statement Introduction The EMAC peripheral conforms to the IEEE 802.3 standard, describing the “Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer” specifications. ISO / IEC has also adopted the IEEE 802.3 standard and re-designated it as ISO/IEC 8802-[...]

www.ti.com 2 EMAC Functional Architecture 2.1 Clock Control 2.1.1 MII Clocking 2.1.2 RMII Clocking 2.1.3 GMII Clocking EMAC Functional Architecture This chapter discusses the architecture and basic function of the EMAC peripheral. The frequencies for the transmit and receive clocks are fixed by the IEEE 802.3 specification as shown below: • 2.5 M[...]

www.ti.com 2.1.4 RGMII Clocking 2.2 Memory Map EMAC Functional Architecture For timing purposes, data in 10/100 mode is transmitted and received with reference to MTCLK and MRCLK, respectively. For 1000 Mbps mode, receive timing is the same, but transmit is relative to GMTCLK. When the RGMII interface is selected by setting MACSEL to 11b, you must [...]

www.ti.com 2.3 System Level Connections 2.3.1 Media Independent Interface (MII) Connections MTCLK MTXD[3−0] MTXEN MCOL MCRS MRCLK MRXD[3−0] MRXDV MRXER MDCLK MDIO Physical layer device (PHY) System core Transformer 2.5 MHz or 25 MHz RJ−45 EMAC MDIO EMAC Functional Architecture The C645x device supports four different interfaces to a physical [...]

www.ti.com EMAC Functional Architecture Table 2 summarizes the individual EMAC and MDIO signals for the MII interface. For more information, refer to either the IEEE 802.3 standard or ISO/IEC 8802-3:2000(E). The EMAC module does not include a transmit error (MTXER) pin. If a transmit error occurs, CRC inversion is used to negate the validity of the[...]

www.ti.com 2.3.2 Reduced Media Independent Interface (RMII) Connections MTXD[1−0] MTXEN MCRSDV MREFCLK MRXD[1−0] MRXER MDCLK MDIO Physical layer device (PHY) System core Transformer RJ−45 EMAC MDIO EMAC Functional Architecture Figure 3 shows a device with integrated EMAC and MDIO interfaced via a RMII connection. This interface is only availa[...]

www.ti.com EMAC Functional Architecture The RMII interface has the same functionality as the MII, but it does so with a reduced number of pins, thus lowering the total cost for an application. In devices incorporating many PHY interfaces such as switches, the number of pins can add significant cost as the port counts increase. Table 3 summarizes th[...]

www.ti.com 2.3.3 Gigabit Media Independent Interface (GMII) Connections MTCLK MTXD[7−0] MTXEN MCOL MCRS MRCLK MRXD[7−0] MRXDV MRXER MDCLK MDIO Physical layer device (PHY) System core Transformer 2.5 MHz, 25 MHz, RJ−45 EMAC MDIO GMTCLK or 125 MHz EMAC Functional Architecture Figure 4 shows a device with integrated EMAC and MDIO interfaced via [...]

www.ti.com EMAC Functional Architecture Table 4 summarizes the individual EMAC and MDIO signals for the GMII interface. Table 4. EMAC and MDIO Signals for GMII Interface Signal Name I/O Description MTCLK I Transmit clock (MTCLK). The transmit clock is a continuous clock that provides the timing reference for transmit operations in 10/100 Mbps mode.[...]

www.ti.com 2.3.4 Reduced Gigabit Media Independent Interface (RGMII) Connections TXC TXD[3−0] TXCTL REFCLK RXC RXD[3−0] RXCTL MDCLK MDIO Physical layer device (PHY) System core Transformer 2.5 MHz 25 MHz, or 125 MHz RJ−45 EMAC MDIO EMAC Functional Architecture Figure 5 shows a device with integrated EMAC and MDIO interfaced via a RGMII connec[...]

www.ti.com EMAC Functional Architecture Table 5 summarizes the individual EMAC and MDIO signals for the RGMII interface. Table 5. EMAC and MDIO Signals for RGMII Interface Signal Name I/O Description TXC O Transmit clock (TXC). The transmit clock is a continuous clock that provides the timing reference for transmit operations. The TXD and TXCTL sig[...]

www.ti.com 2.4 Ethernet Protocol Overview 2.4.1 Ethernet Frame Format Preamble SFD Destination Source Len Data 7 1 6 6 2 46 − (RXMAXLEN - 18) 4 FCS Number of bytes Legend: SFD=Start Frame Delimiter; FCS=Frame Check Sequence (CRC) EMAC Functional Architecture Ethernet provides an unreliable, connectionless service to a networking application. A br[...]

www.ti.com 2.4.2 Multiple Access Protocol EMAC Functional Architecture Nodes in an ethernet local area network are interconnected by a broadcast channel. As a result, when an EMAC port transmits a frame, all of the adapters on the local network receive the frame. Carrier sense multiple access with collision detection (CSMA/CD) algorithms are used w[...]

www.ti.com 2.5 Programming Interface 2.5.1 Packet Buffer Descriptors EMAC Functional Architecture The buffer descriptor is a central part of the EMAC module. It determines how the application software describes ethernet packets to be sent and empty buffers to be filled with incoming packet data. The basic descriptor format is shown in Figure 7 and [...]

www.ti.com SOP | EOP 60 0 60 pBuf fer pNext Packet A 60 bytes 0 SOP Fragment 1 Packet B 512 1514 pBuf fer pNext 512 bytes EOP 0 0 −−− Packet B Fragment 3 500 bytes 502 pBuf fer −−− 500 pNext −−− pBuf fer pNext Packet B Fragment 2 502 bytes SOP | EOP 0 1514 bytes Packet C 1514 pBuf fer pNext (NULL) 1514 EMAC Functional Architecture[...]

www.ti.com 2.5.2 Transmit and Receive Descriptor Queues EMAC Functional Architecture The EMAC module processes descriptors in linked list chains ( Section 2.5.1 ). The lists controlled by the EMAC are maintained by the application software via the head descriptor pointer (HDP) registers. Since the EMAC supports eight channels for both transmit and [...]

www.ti.com 2.5.3 Transmit and Receive EMAC Interrupts EMAC Functional Architecture The EMAC processes descriptors in linked list chains ( Section 2.5.1 ), using the linked list queue mechanism ( Section 2.5.2 ). The EMAC synchronizes the descriptor list processing by using interrupts to the software application. The interrupts are controlled by the[...]

www.ti.com 2.5.4 Transmit Buffer Descriptor Format EMAC Functional Architecture A transmit (TX) buffer descriptor ( Figure 9 ) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 1 shows the transmit buffer descriptor described by a C structure. Figure 9. Transmit Descri[...]

www.ti.com 2.5.4.1 Next Descriptor Pointer 2.5.4.2 Buffer Pointer 2.5.4.3 Buffer Offset 2.5.4.4 Buffer Length 2.5.4.5 Packet Length 2.5.4.6 Start of Packet (SOP) Flag EMAC Functional Architecture The next descriptor pointer indicates the 32-bit word aligned memory address of the next buffer descriptor in the transmit queue. The pointer creates a li[...]

www.ti.com 2.5.4.7 End of Packet (EOP) Flag 2.5.4.8 Ownership (OWNER) Flag 2.5.4.9 End of Queue (EOQ) Flag 2.5.4.10 Teardown Complete (TDOWNCMPLT) Flag 2.5.4.11 Pass CRC (PASSCRC) Flag EMAC Functional Architecture When set, this flag indicates that the descriptor points to the last packet buffer for a given packet. For a single fragment packet, bot[...]

www.ti.com 2.5.5 Receive Buffer Descriptor Format EMAC Functional Architecture A receive (RX) buffer descriptor ( Figure 10 ) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 2 shows the receive descriptor described by a C structure. Figure 10. Receive Descriptor Form[...]

www.ti.com 2.5.5.1 Next Descriptor Pointer 2.5.5.2 Buffer Pointer 2.5.5.3 Buffer Offset 2.5.5.4 Buffer Length 2.5.5.5 Packet Length EMAC Functional Architecture The next descriptor pointer indicates the 32-bit word aligned memory address of the next buffer descriptor in the receive queue. The pointer creates a linked list of buffer descriptors. If [...]

www.ti.com 2.5.5.6 Start of Packet (SOP) Flag 2.5.5.7 End of Packet (EOP) Flag 2.5.5.8 Ownership (OWNER) Flag 2.5.5.9 End of Queue (EOQ) Flag 2.5.5.10 Teardown Complete (TDOWNCMPLT) Flag 2.5.5.11 Pass CRC (PASSCRC) Flag 2.5.5.12 Jabber Flag 2.5.5.13 Oversize Flag EMAC Functional Architecture When set, this flag indicates that the descriptor points [...]

www.ti.com 2.5.5.14 Fragment Flag 2.5.5.15 Undersized Flag 2.5.5.16 Control Flag 2.5.5.17 Overrun Flag 2.5.5.18 Code Error (CODEERROR) Flag 2.5.5.19 Alignment Error (ALIGNERROR) Flag 2.5.5.20 CRC Error (CRCERROR) Flag 2.5.5.21 No Match (NOMATCH) Flag EMAC Functional Architecture The EMAC sets this flag in the SOP buffer descriptor if the received p[...]

www.ti.com 2.6 EMAC Control Module Arbiter and bus switches CPU DMA Controllers 8K byte descriptor memory Configuration registers Interrupt logic Single interrupt to CPU EMAC interrupts MDIO interrupts Configuration bus T ransmit and Receive 2.6.1 Internal Memory 2.6.2 Bus Arbiter EMAC Functional Architecture The EMAC control module ( Figure 11 ) i[...]

www.ti.com 2.6.3 Interrupt Control 2.7 Management Data Input/Output (MDIO) Module 2.7.1 MDIO Module Components EMAC Functional Architecture The EMAC control module combines the multiple interrupt conditions generated by the EMAC and MDIO modules into a single interrupt signal that is mapped to a CPU interrupt via the CPU interrupt controller. The c[...]

www.ti.com EMAC control module Control registers and logic PHY monitoring Peripheral clock MDIO clock generator USERINT MDIO interface polling PHY MDCLK MDIO LINKINT Configuration bus 2.7.1.1 MDIO Clock Generator 2.7.1.2 Global PHY Detection and Link State Monitoring 2.7.1.3 Active PHY Monitoring 2.7.1.4 PHY Register User Access EMAC Functional Arc[...]

www.ti.com 2.7.2 MDIO Module Operational Overview 2.7.2.1 Initializing the MDIO Module EMAC Functional Architecture The MDIO module implements the 802.3 serial management interface to simultaneously interrogate and control up to two Ethernet PHYs, using a shared two-wired bus. It separately performs auto-detection and records the current link statu[...]

www.ti.com 2.7.2.2 Writing Data to a PHY Register 2.7.2.3 Reading Data From a PHY Register 2.7.2.4 Example of MDIO Register Access Code EMAC Functional Architecture The MDIO module includes a user access register (USERACCESS n ) to directly access a specified PHY device. To write a PHY register, perform the following: 1. Ensure that the GO bit in t[...]

www.ti.com EMAC Functional Architecture The implementation of these macros using the register layer Chip Support Library (CSL) is shown in Example 3 (USERACCESS0 is assumed). Note that this implementation does not check the ACK bit on PHY register reads; in other words, it does not follow the procedure outlined in Section 2.7.2.3 . As the ALIVE reg[...]

www.ti.com 2.8 EMAC Module 2.8.1 EMAC Module Components Clock and reset logic Receive DMA engine Interrupt controller Transmit DMA engine Control registers Configuration bus EMAC control module Configuration bus RAM State FIFO Receive FIFO Transmit MAC transmitter Statistics receiver MAC SYNC MII RMII GMII RGMII address Receive 2.8.1.1 Receive DMA [...]

www.ti.com 2.8.1.3 MAC Receiver 2.8.1.4 Receive Address 2.8.1.5 Transmit DMA Engine 2.8.1.6 Transmit FIFO 2.8.1.7 MAC Transmitter 2.8.1.8 Statistics Logic 2.8.1.9 State RAM 2.8.1.10 EMAC Interrupt Controller 2.8.1.11 Control Registers and Logic EMAC Functional Architecture The MAC receiver detects and processes incoming network frames, de-frames th[...]

www.ti.com 2.8.1.12 Clock and Reset Logic 2.8.2 EMAC Module Operational Overview EMAC Functional Architecture The clock and reset sub-module generates all the clocks and resets for the EMAC peripheral. After reset, initialization, and configuration of the EMAC, the application software running on the host may initiate transmit operations. Transmit [...]

www.ti.com 2.9 Media Independent Interfaces 2.9.1 Data Reception 2.9.1.1 Receive Control 2.9.1.2 Receive Inter-Frame Interval 2.9.1.3 Receive Flow Control EMAC Functional Architecture The EMAC supports four physical interfaces to external devices: Media Independent Interface (MII), Reduced Media Independent Interface (RMII), Gigabit Media Independe[...]

www.ti.com 2.9.1.4 Collision-Based Receive Buffer Flow Control 2.9.1.5 IEEE 802.3X Based Receive Buffer Flow Control EMAC Functional Architecture Collision-based receive buffer flow control provides a means of preventing frame reception when the EMAC is operating in half-duplex mode (FULLDUPLEX bit is cleared in MACCONTROL register). When receive f[...]

www.ti.com 2.9.2 Data Transmission 2.9.2.1 Transmit Control 2.9.2.2 CRC Insertion 2.9.2.3 Adaptive Performance Optimization (APO) 2.9.2.4 Interpacket-Gap (IPG) Enforcement 2.9.2.5 Back Off EMAC Functional Architecture The EMAC passes data to the PHY from the transmit FIFO (when enabled). Data is synchronized to the transmit clock rate. Transmission[...]

www.ti.com 2.9.2.6 Transmit Flow Control 2.9.2.7 Speed, Duplex, and Pause Frame Support EMAC Functional Architecture When enabled, incoming pause frames are acted upon to prevent the EMAC from transmitting any further frames. Incoming pause frames are only acted upon when the FULLDUPLEX and TXFLOWEN bits in the MACCONTROL register are set. Pause fr[...]

www.ti.com 2.10 Packet Receive Operation 2.10.1 Receive DMA Host Configuration 2.10.2 Receive Channel Enabling EMAC Functional Architecture To configure the receive DMA for operation, the host must perform the following actions: • Initialize the receive addresses • Initialize the RX n HDP registers to zero • Write the MACHASH1 and MACHASH2 re[...]

www.ti.com 2.10.3 Receive Channel Addressing 2.10.4 Hardware Receive QOS Support EMAC Functional Architecture The receive address block can store up to 32 addresses to be filtered or matched. Before enabling packet reception, all the address RAM locations should be initialized, including locations to be unused. The system software is responsible fo[...]

www.ti.com 2.10.5 Host Free Buffer Tracking 2.10.6 Receive Channel Teardown 2.10.7 Receive Frame Classification EMAC Functional Architecture The host must track free buffers for each enabled channel (including unicast, multicast, broadcast, and promiscuous) if receive QOS or receive flow control is used. Disabled channel free buffer values are don?[...]

www.ti.com 2.10.8 Promiscuous Receive Mode EMAC Functional Architecture When the promiscuous receive mode is enabled by setting the RXCAFEN bit in the RXMBPENABLE register, non-address matching frames that would normally be filtered are transferred to the promiscuous channel. Address matching frames that would normally be filtered due to errors are[...]

www.ti.com 2.10.9 Receive Overrun EMAC Functional Architecture Table 8. Receive Frame Treatment Summary (continued) RXMBPENABLE Bits ADDRESS MATCH RXCAFEN RXCEFEN RXCMFEN RXCSFEN Frame treatment 1 X 1 0 1 Proper/oversize/jabber/fragment/undersized/cod e/align/CRC data frames transferred to address match channel. No control frames are transferred. 1[...]

www.ti.com 2.11 Packet Transmit Operation 2.11.1 Transmit DMA Host Configuration 2.11.2 Transmit Channel Teardown 2.12 Receive and Transmit Latency EMAC Functional Architecture The transmit DMA is an eight channel interface. Priority between the eight queues may be either fixed or round robin as selected by the TXPTYPE bit in the MACCONTROL registe[...]

www.ti.com 2.13 Transfer Node Priority 2.14 Reset Considerations 2.14.1 Software Reset Considerations 2.14.2 Hardware Reset Considerations EMAC Functional Architecture Latency to system’s internal and external RAM can be controlled through the use of the transfer node priority allocation register in the C645x devices. Latency to descriptor RAM is[...]

www.ti.com 2.15 Initialization 2.15.1 Enabling the EMAC/MDIO Peripheral 2.15.2 EMAC Control Module Initialization EMAC Functional Architecture When the device is powered on, the EMAC peripheral is disabled. Prior to EMAC-specific initialization, the EMAC must be enabled; otherwise its registers cannot be written, and the reads will all return a val[...]

www.ti.com 2.15.3 MDIO Module Initialization EMAC Functional Architecture Example 4. EMAC Control Module Initialization Code Uint32 tmpval; /* // Globally disable EMAC/MDIO interrupts in the control module /* CSL_FINST(ECTL_REGS->EWCTL, ECTL_EWCTL_INTEN, DISABLE ); /* Wait about 100 cycles */ for( I=0; i<5; I++ ) tmpval = ECTL_REGS->EWCTL;[...]

www.ti.com 2.15.4 EMAC Module Initialization EMAC Functional Architecture The EMAC module sends and receives data packets over the network by maintaining up to 8 transmit and receive descriptor queues. The EMAC module configuration must also be kept current based on the PHY negotiation results returned from the MDIO module. Programming this module [...]

www.ti.com 2.16 Interrupt Support 2.16.1 EMAC Module Interrupt Events and Requests 2.16.1.1 Transmit Packet Completion Interrupts EMAC Functional Architecture The EMAC/MDIO generates 18 interrupt events, as follows: • TXPEND n : Transmit packet completion interrupt for transmit channels 7 through 0 • RXPEND n : Receive packet completion interru[...]

www.ti.com 2.16.1.2 Receive Packet Completion Interrupts 2.16.1.3 Statistics Interrupt EMAC Functional Architecture The receive DMA engine has eight channels, and each channel has a corresponding interrupt (RXPEND n ). The receive interrupts are level interrupts that remain asserted until cleared by the CPU. Each of the eight receive channel interr[...]

www.ti.com 2.16.1.4 Host Error Interrupt 2.16.2 MDIO Module Interrupt Events and Requests 2.16.2.1 Link Change Interrupt 2.16.2.2 User Access Completion Interrupt EMAC Functional Architecture The host error interrupt (HOSTPEND) is issued, if enabled, under error conditions due to the handling of buffer descriptors detected during transmit or receiv[...]

www.ti.com 2.16.3 Proper Interrupt Processing 2.16.4 Interrupt Multiplexing 2.17 Power Management 2.18 Emulation Considerations EMAC Functional Architecture All the interrupts signaled from the EMAC and MDIO modules are level-driven. If they remain active, their level remains constant. However, the CPU core requires edge-triggered interrupts. To pr[...]

www.ti.com 3 EMAC Control Module Registers 3.1 Introduction 3.2 EMAC Control Module Interrupt Control Register (EWCTL) EMAC Control Module Registers Table 11 lists the memory-mapped registers for the EMAC Control Module. See the device-specific data manual for the memory address of these registers. Table 11. EMAC Control Module Registers Offset Acr[...]

www.ti.com 3.3 EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) EMAC Control Module Registers The EMAC control module interrupt timer count register (EWINTTCNT) is used to control the generation of back-to-back interrupts from the EMAC and MDIO modules. The value of this timer count is loaded into an internal counter every time interr[...]

www.ti.com 4 MDIO Registers 4.1 Introduction MDIO Registers Table 14 lists the memory-mapped registers for the Management Data Input/Output (MDIO). See the device-specific data manual for the memory address of these registers. Table 14. Management Data Input/Output (MDIO) Registers Offset Acronym Register Description Section 0h VERSION MDIO Version[...]

www.ti.com 4.2 MDIO Version Register (VERSION) MDIO Registers The MDIO version register (VERSION) is shown in Figure 16 and described in Table 15 . Figure 16. MDIO Version Register (VERSION) 31 16 MODID R-7 15 8 7 0 REVMAJ REVMIN R-1 R-3 LEGEND: R = Read only; R/W = Read/Write; - n = value after reset Table 15. MDIO Version Register (VERSION) Field[...]

www.ti.com 4.3 MDIO Control Register (CONTROL) MDIO Registers The MDIO control register (CONTROL) is shown in Figure 17 and described in Table 16 . Figure 17. MDIO Control Register (CONTROL) 31 30 29 28 24 23 21 20 19 18 17 16 IDLE ENABLE Reserved HIGHEST_USER_CHANNEL Reserved PREAMBLE FAULT FAULT Reserved ENB R-1 R/W-0 R-0 R-1 R-0 R/W-0 R/WC-0 R/W[...]

www.ti.com 4.4 PHY Acknowledge Status Register (ALIVE) MDIO Registers The PHY acknowledge status register (ALIVE) is shown in Figure 18 and described in Table 17 . Figure 18. PHY Acknowledge Status Register (ALIVE) 31 16 ALIVE R/WC-0 15 0 ALIVE R/WC-0 LEGEND: R/W = Read/Write; R/WC = Read/Write 1 to clear; - n = value after reset Table 17. PHY Ackn[...]

www.ti.com 4.5 PHY Link Status Register (LINK) MDIO Registers The PHY link status register (LINK) is shown in Figure 19 and described in Table 18 . Figure 19. PHY Link Status Register (LINK) 31 16 LINK R-0 15 0 LINK R-0 LEGEND: R = Read only; - n = value after reset Table 18. PHY Link Status Register (LINK) Field Descriptions Bit Field Value Descri[...]

www.ti.com 4.6 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) MDIO Registers The MDIO link status change interrupt (unmasked) register (LINKINTRAW) is shown in Figure 20 and described in Table 19 . Figure 20. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) 31 16 Reserved R-0 15 2 1 0 Reserved LINKINTRAW R-0 R/[...]

www.ti.com 4.7 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) MDIO Registers The MDIO link status change interrupt (masked) register (LINKINTMASKED) is shown in Figure 21 and described in Table 20 . Figure 21. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) 31 16 Reserved R-0 15 2 1 0 Reserved LINKINT MASKED[...]

www.ti.com 4.8 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) MDIO Registers The MDIO user command complete interrupt (unmasked) register (USERINTRAW) is shown in Figure 22 and described in Table 21 . Figure 22. MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) 31 16 Reserved R-0 15 2 1 0 Reserved USERINTR[...]

www.ti.com 4.9 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) MDIO Registers The MDIO user command complete interrupt (Masked) register (USERINTMASKED) is shown in Figure 23 and described in Table 22 . Figure 23. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) 31 16 Reserved R-0 15 2 1 0 Reserved USERI[...]

www.ti.com 4.10 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) MDIO Registers The MDIO user command complete interrupt mask set register (USERINTMASKSET) is shown in Figure 24 and described in Table 23 . Figure 24. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) 31 16 Reserved R-0 15 2 1 0 Reserved U[...]

www.ti.com 4.11 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) MDIO Registers The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in Figure 25 and described in Table 24 . Figure 25. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) 31 16 Reserved R-0 15 2 1 [...]

www.ti.com 4.12 MDIO User Access Register 0 (USERACCESS0) MDIO Registers The MDIO user access register 0 (USERACCESS0) is shown in Figure 26 and described in Table 25 . Figure 26. MDIO User Access Register 0 (USERACCESS0) 31 30 29 28 26 25 21 20 16 GO WRITE ACK Reserved REGADR PHYADR R/WS-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 15 0 DATA R/W-0 LEGEND: R = Re[...]

www.ti.com 4.13 MDIO User PHY Select Register 0 (USERPHYSEL0) MDIO Registers The MDIO user PHY select register 0 (USERPHYSEL0) is shown in Figure 27 and described in Table 26 . Figure 27. MDIO User PHY Select Register 0 (USERPHYSEL0) 31 16 Reserved R-0 15 8 7 6 5 4 0 Reserved LINKSEL LINKINTENB Reserved PHYADRMON R-0 R/W-0 R/W-0 R-0 R/W-0 LEGEND: R[...]

www.ti.com 4.14 MDIO User Access Register 1 (USERACCESS1) MDIO Registers The MDIO user access register 1 (USERACCESS1) is shown in Figure 28 and described in Table 27 . Figure 28. MDIO User Access Register 1 (USERACCESS1) 31 30 29 28 26 25 21 20 16 GO WRITE ACK Reserved REGADR PHYADR R/WS-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 15 0 DATA R/W-0 LEGEND: R = Re[...]

www.ti.com 4.15 MDIO User PHY Select Register 1 (USERPHYSEL1) MDIO Registers The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 29 and described in Table 28 . Figure 29. MDIO User PHY Select Register 1 (USERPHYSEL1) 31 16 Reserved R-0 15 8 7 6 5 4 0 Reserved LINKSEL LINKINTENB Reserved PHYADRMON R-0 R/W-0 R/W-0 R-0 R/W-0 LEGEND: R[...]

www.ti.com 5 EMAC Port Registers 5.1 Introduction EMAC Port Registers Table 29 lists the memory-mapped registers for the Ethernet Media Access Controller (EMAC). See the device-specific data manual for the memory address of these registers. Table 29. Ethernet Media Access Controller (EMAC) Registers Offset Acronym Register Description Section 0h TX[...]

www.ti.com EMAC Port Registers Table 29. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description Section 15Ch RX7FREEBUFFER Receive Channel 7 Free Buffer Count Register Section 5.28 160h MACCONTROL MAC Control Register Section 5.29 164h MACSTATUS MAC Status Register Section 5.30 168h EMCONTROL Emulation Con[...]

www.ti.com EMAC Port Registers Table 29. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description Section 658h TX6CP Transmit Channel 6 Completion Pointer (Interrupt Section 5.48 Acknowledge) Register 65Ch TX7CP Transmit Channel 7 Completion Pointer (Interrupt Section 5.48 Acknowledge) Register 660h RX0CP Re[...]

www.ti.com EMAC Port Registers Table 29. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description Section 270h FRAME128T255 Transmit and Receive 128 to 255 Octet Frames Register Section 5.50.29 274h FRAME256T511 Transmit and Receive 256 to 511 Octet Frames Register Section 5.50.30 278h FRAME512T1023 Transmit[...]

www.ti.com 5.2 Transmit Identification and Version Register (TXIDVER) EMAC Port Registers The transmit identification and version register (TXIDVER) is shown in Figure 30 and described in Table 30 . Figure 30. Transmit Identification and Version Register (TXIDVER) 31 16 TXIDENT R-12 15 8 7 0 TXMAJORVER TXMINORVER R-10 R-7 LEGEND: R = Read only; - n[...]

www.ti.com 5.3 Transmit Control Register (TXCONTROL) EMAC Port Registers The transmit control register (TXCONTROL) is shown in Figure 31 and described in Table 31 . Figure 31. Transmit Control Register (TXCONTROL) 31 16 Reserved R-0 15 1 0 Reserved TXEN R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 31. Transmit Co[...]

www.ti.com 5.4 Transmit Teardown Register (TXTEARDOWN) EMAC Port Registers The transmit teardown register (TXTEARDOWN) is shown in Figure 32 and described in Table 32 . Figure 32. Transmit Teardown Register (TXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved TXTDNCH R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 32. [...]

www.ti.com 5.5 Receive Identification and Version Register (RXIDVER) EMAC Port Registers The receive identification and version register (RXIDVER) is shown in Figure 33 and described in Table 33 . Figure 33. Receive Identification and Version Register (RXIDVER) 31 16 RXIDENT R-12 15 8 7 0 RXMAJORVER RXMINORVER R-10 R-7 LEGEND: R = Read only; - n = [...]

www.ti.com 5.6 Receive Control Register (RXCONTROL) EMAC Port Registers The receive control register (RXCONTROL) is shown in Figure 34 and described in Table 34 . Figure 34. Receive Control Register (RXCONTROL) 31 16 Reserved R-0 15 1 0 Reserved RXEN R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 34. Receive Contro[...]

www.ti.com 5.7 Receive Teardown Register (RXTEARDOWN) EMAC Port Registers The receive teardown register (RXTEARDOWN) is shown in Figure 35 and described in Table 35 . Figure 35. Receive Teardown Register (RXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved RXTDNCH R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 35. Rec[...]

www.ti.com 5.8 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) EMAC Port Registers The transmit interrupt status (unmasked) register (TXINTSTATRAW) is shown in Figure 36 and described in Table 36 . Figure 36. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) 31 16 Reserved R-0 1 5 876543210 Reserved TX7 TX6 TX5 TX4 TX3 TX2 T[...]

www.ti.com 5.9 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) EMAC Port Registers The transmit interrupt status (Masked) register (TXINTSTATMASKED) is shown in Figure 37 and described in Table 37 . Figure 37. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) 31 16 Reserved R-0 1 5 876543210 Reserved TX7 TX6 TX5 TX4 TX3 TX[...]

www.ti.com 5.10 Transmit Interrupt Mask Set Register (TXINTMASKSET) EMAC Port Registers The transmit interrupt mask set register (TXINTMASKSET) is shown in Figure 38 and described in Table 38 . Figure 38. Transmit Interrupt Mask Set Register (TXINTMASKSET) 31 16 Reserved R-0 15 8 7 6 5 4 3 2 1 0 Reserved TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 MASK MASK MA[...]

www.ti.com 5.11 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) EMAC Port Registers The transmit interrupt mask clear register (TXINTMASKCLEAR) is shown in Figure 39 and described in Table 39 . Figure 39. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) 31 16 Reserved R-0 15 8 7 6 5 4 3 2 1 0 Reserved TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 [...]

www.ti.com 5.12 MAC Input Vector Register (MACINVECTOR) EMAC Port Registers The MAC input vector register (MACINVECTOR) is shown in Figure 40 and described in Table 40 . Figure 40. MAC Input Vector Register (MACINVECTOR) 31 30 29 18 17 16 USER LINK Reserved HOST STAT INT INT PEND PEND R-0 R-0 R-0 R-0 R-0 15 0 RXPEND TXPEND R-0 R-0 LEGEND: R = Read [...]

www.ti.com 5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) EMAC Port Registers The receive interrupt status (Unmasked) register (RXINTSTATRAW) is shown in Figure 41 and described in Table 41 . Figure 41. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) 31 16 Reserved R-0 1 5 876543210 Reserved RX7 RX6 RX5 RX4 RX3 RX2 RX1[...]

www.ti.com 5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) EMAC Port Registers The receive interrupt status (Masked) register (RXINTSTATMASKED) is shown in Figure 42 and described in Table 42 . Figure 42. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) 31 16 Reserved R-0 1 5 876543210 Reserved RX7 RX6 RX5 RX4 RX3 RX2 [...]

www.ti.com 5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) EMAC Port Registers The receive interrupt mask set register (RXINTMASKSET) is shown in Figure 43 and described in Table 43 . Figure 43. Receive Interrupt Mask Set Register (RXINTMASKSET) 31 16 Reserved R-0 15 8 7 6 5 4 3 2 1 0 Reserved RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 MASK MASK MASK [...]

www.ti.com 5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) EMAC Port Registers The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 44 and described in Table 44 . Figure 44. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) 31 16 Reserved R-0 15 8 7 6 5 4 3 2 1 0 Reserved RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 MAS[...]

www.ti.com 5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) EMAC Port Registers The MAC interrupt status (unmasked) register (MACINTSTATRAW) is shown in Figure 45 and described in Table 45 . Figure 45. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) 31 16 Reserved R-0 15 2 1 0 Reserved HOST STAT PEND PEND R-0 R-0 R-0 LEGEND: R[...]

www.ti.com 5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) EMAC Port Registers The MAC interrupt status (masked) register (MACINTSTATMASKED) is shown in Figure 46 and described in Table 46 . Figure 46. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) 31 16 Reserved R-0 15 2 1 0 Reserved HOST STAT PEND PEND R-0 R-0 R-0 LEGEND[...]

www.ti.com 5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) EMAC Port Registers The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure 47 and described in Table 47 . Figure 47. MAC Interrupt Mask Set Register (MACINTMASKSET) 31 16 Reserved R-0 15 2 1 0 Reserved HOST STAT MASK MASK R-0 R/WS-0 R/WS-0 LEGEND: R = Read only; R/W = R[...]

www.ti.com 5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) EMAC Port Registers The MAC interrupt mask clear register (MACINTMASKCLEAR) is shown in Figure 48 and described in Table 48 . Figure 48. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) 31 16 Reserved R-0 15 2 1 0 Reserved HOST STAT MASK MASK R-0 R/WC-0 R/WC-0 LEGEND: R = Read o[...]

www.ti.com 5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) EMAC Port Registers The receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) is shown in Figure 49 and described in Table 49 . Figure 49. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) 31 30 29 28 27 [...]

www.ti.com EMAC Port Registers Table 49. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions (continued) Bit Field Value Description 22 RXCEFEN Receive copy error frames enable bit. Enables frames containing errors to be transferred to memory. The appropriate error bit will be set in the frame EOP buffer[...]

www.ti.com 5.22 Receive Unicast Enable Set Register (RXUNICASTSET) EMAC Port Registers Table 49. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions (continued) Bit Field Value Description 2-0 RXMULTCH 0-3h Receive multicast channel select 0 Select channel 0 to receive multicast frames 1h Select channel [...]

www.ti.com 5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) EMAC Port Registers The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 51 and described in Table 51 . Figure 51. Receive Unicast Clear Register (RXUNICASTCLEAR) 31 16 Reserved R-0 15 8 7 6 5 4 3 2 1 0 Reserved RXCH7EN RXCH6EN RXCH5EN RXCH4EN RXCH3EN RXCH2EN RXCH1EN [...]

www.ti.com 5.24 Receive Maximum Length Register (RXMAXLEN) EMAC Port Registers The receive maximum length register (RXMAXLEN) is shown in Figure 52 and described in Table 52 . Figure 52. Receive Maximum Length Register (RXMAXLEN) 31 16 Reserved R-0 15 0 RXMAXLEN R/W-1518 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 52. Rec[...]

www.ti.com 5.25 Receive Buffer Offset Register (RXBUFFEROFFSET) EMAC Port Registers The receive buffer offset register (RXBUFFEROFFSET) is shown in Figure 53 and described in Table 53 . Figure 53. Receive Buffer Offset Register (RXBUFFEROFFSET) 31 16 Reserved R-0 15 0 RXBUFFEROFFSET R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after r[...]

www.ti.com 5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) EMAC Port Registers The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) is shown in Figure 54 and described in Table 54 . Figure 54. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) 31 16 Reserved R-0 15 8 7 0 Re[...]

www.ti.com 5.27 Receive Channel 0-7 Flow Control Threshold Register (RX nFLOWTHRESH) EMAC Port Registers The receive channel 0-7 flow control threshold register (RX n FLOWTHRESH) is shown in Figure 55 and described in Table 55 . Figure 55. Receive Channel n Flow Control Threshold Register (RX n FLOWTHRESH) 31 16 Reserved R-0 15 8 7 0 Reserved RX n [...]

www.ti.com 5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER) EMAC Port Registers The receive channel 0-7 free buffer count register (RXnFREEBUFFER) is shown in Figure 56 and described in Table 56 . Figure 56. Receive Channel n Free Buffer Count Register (RX n FREEBUFFER) 31 16 Reserved R-0 15 0 RX n FREEBUF WI-0 tLEGEND: R = Read [...]

www.ti.com 5.29 MAC Control Register (MACCONTROL) EMAC Port Registers The MAC control register (MACCONTROL) is shown in Figure 57 and described in Table 57 . Figure 57. MAC Control Register (MACCONTROL) 31 24 Reserved R-0 23 19 18 17 16 Reserved RGMIIEN GIGFORCE RMIIDUPLEX- MODE R-0 R/W-0 R/W-0 R/W-0 15 14 13 12 11 10 9 8 RMIISPEED RXOFFLENBLOCK RX[...]

www.ti.com EMAC Port Registers Table 57. MAC Control Register (MACCONTROL) Field Descriptions (continued) Bit Field Value Description 1 Receive flow control enabled. For full-duplex mode, outgoing pause frames are sent when receive FIFO flow control is triggered. 11 CMDIDLE Command Idle bit 0 Idle not commanded 1 Idle commanded (read IDLE in the MA[...]

www.ti.com 5.30 MAC Status Register (MACSTATUS) EMAC Port Registers The MAC status register (MACSTATUS) is shown in Figure 58 and described in Table 58 . Figure 58. MAC Status Register (MACSTATUS) 31 30 24 IDLE Reserved R-0 R-0 23 20 19 18 16 TXERRCODE Reserved TXERRCH R-0 R-0 R-0 15 12 11 10 8 RXERRCODE Reserved RXERRCH R-0 R-0 R-0 7 5 4 3 2 1 0 R[...]

www.ti.com EMAC Port Registers Table 58. MAC Status Register (MACSTATUS) Field Descriptions (continued) Bit Field Value Description 15-12 RXERRCODE Receive host error code. These bits indicate that EMAC detected receive DMA related host errors. The host should read this field after a host error interrupt (HOSTPEND) to determine the error. Host erro[...]

www.ti.com 5.31 Emulation Control Register (EMCONTROL) EMAC Port Registers The emulation control register (EMCONTROL) is shown in Figure 59 and described in Table 59 . Figure 59. Emulation Control Register (EMCONTROL) 31 16 Reserved R-0 15 2 1 0 Reserved SOFT FREE R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Tabl[...]

www.ti.com 5.32 FIFO Control Register (FIFOCONTROL) EMAC Port Registers The FIFO control register (FIFOCONTROL) is shown in Figure 60 and described in Table 60 . Figure 60. FIFO Control Register (FIFOCONTROL) 31 23 22 16 Reserved RXFIFOFLOWTHRESH R-0 R/W-2 15 5 4 0 Reserved TXCELLTHRESH R-0 R/W-24 LEGEND: R/W = Read/Write; R = Read only; - n = valu[...]

www.ti.com 5.33 MAC Configuration Register (MACCONFIG) EMAC Port Registers The MAC configuration register (MACCONFIG) is shown in Figure 61 and described in Table 61 . Figure 61. MAC Configuration Register (MACCONFIG) 31 24 23 16 TXCELLDEPTH RXCELLDEPTH R-24 R-68 15 8 7 0 ADDRESSTYPE MACCFIG R-2 R-3 LEGEND: R/W = Read/Write; R = Read only; - n = va[...]

www.ti.com 5.34 Soft Reset Register (SOFTRESET) EMAC Port Registers The Soft Reset Register (SOFTRESET) is shown in Figure 62 and described in Table 62 . Figure 62. Soft Reset Register (SOFTRESET) 31 16 Reserved R-0 15 1 0 Reserved SOFTRESET R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 62. Soft Reset Register (SO[...]

www.ti.com 5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) EMAC Port Registers The MAC source address low bytes register (MACSRCADDRLO) is shown in Figure 63 and described in Table 63 . Figure 63. MAC Source Address Low Bytes Register (MACSRCADDRLO) 31 16 Reserved R-0 15 8 7 0 MACSRCADDR0 MACSRCADDR1 R/W-0 R/W-0 LEGEND: R/W = Read/Write; [...]

www.ti.com 5.36 MAC Source Address High Bytes Register (MACSRCADDRHI) EMAC Port Registers The MAC Source Address High Bytes Register (MACSRCADDRHI) is shown in Figure 64 and described in Table 64 . Figure 64. MAC Source Address High Bytes Register (MACSRCADDRHI) 31 24 23 16 MACSRCADDR2 MACSRCADDR3 R/W-0 R/W-0 15 8 7 0 MACSRCADDR4 MACSRCADDR5 R/W-0 [...]

www.ti.com 5.37 MAC Hash Address Register 1 (MACHASH1) EMAC Port Registers The MAC hash registers allow group addressed frames to be accepted on the basis of a hash function of the address. The hash function creates a 6-bit data value (hash_fun) from the 48-bit destination address (DA) as follows: Hash_fun(0)=DA(0) XOR DA(6) XOR DA(12) XOR DA(18) X[...]

www.ti.com 5.38 MAC Hash Address Register 2 (MACHASH2) EMAC Port Registers The MAC hash address register 2 (MACHASH2) is shown in Figure 66 and described in Table 66 . Figure 66. MAC Hash Address Register 2 (MACHASH2) 31 16 MACHASH2 R/W-0 15 0 MACHASH2 R/W-0 LEGEND: R/W = Read/Write; - n = value after reset Table 66. MAC Hash Address Register 2 (MA[...]

www.ti.com 5.39 Back Off Test Register (BOFFTEST) EMAC Port Registers The back off test register (BOFFTEST) is shown in Figure 67 and described in Table 67 . Figure 67. Back Off Random Number Generator Test Register (BOFFTEST) 31 26 25 16 Reserved RNDNUM R-0 R-0 15 12 11 10 9 0 COLLCOUNT Reserved TXBACKOFF R-0 R-0 R-0 LEGEND: R = Read only; - n = v[...]

www.ti.com 5.40 Transmit Pacing Algorithm Test Register (TPACETEST) EMAC Port Registers The Transmit Pacing Algorithm Test Register (TPACETEST) is shown in Figure 68 and described in Table 68 . Figure 68. Transmit Pacing Algorithm Test Register (TPACETEST) 31 16 Reserved R-0 15 5 4 0 Reserved PACEVAL R-0 R-0 LEGEND: R = Read only; - n = value after[...]

www.ti.com 5.41 Receive Pause Timer Register (RXPAUSE) EMAC Port Registers The receive pause timer register (RXPAUSE) is shown in Figure 69 and described in Table 69 . Figure 69. Receive Pause Timer Register (RXPAUSE) 31 16 Reserved R-0 15 0 PAUSETIMER R-0 LEGEND: R = Read only; - n = value after reset Table 69. Receive Pause Timer Register (RXPAUS[...]

www.ti.com 5.42 Transmit Pause Timer Register (TXPAUSE) EMAC Port Registers The Transmit Pause Timer Register (TXPAUSE) is shown in Figure 70 and described in Table 70 . Figure 70. Transmit Pause Timer Register (TXPAUSE) 31 16 Reserved R-0 15 0 PAUSETIMER R-0 LEGEND: R = Read only; - n = value after reset Table 70. Transmit Pause Timer Register (TX[...]

www.ti.com 5.43 MAC Address Low Bytes Register (MACADDRLO) EMAC Port Registers The MAC address low bytes register (MACADDRLO) is shown in Figure 71 and described in Table 71 . Figure 71. MAC Address Low Bytes Register (MACADDRLO) 31 21 20 19 18 16 Reserved VALID MATCH CHANNEL FILT R-0 R/W-x R/W-x R/W-x 15 8 7 0 MACADDR0 MACADDR1 R/W-0 R/W-0 LEGEND:[...]

www.ti.com 5.44 MAC Address High Bytes Register (MACADDRHI) EMAC Port Registers The MAC address high bytes register (MACADDRHI) is shown in Figure 72 and described in Table 72 . Figure 72. MAC Address High Bytes Register (MACADDRHI) 31 24 23 16 MACADDR2 MACADDR3 R/W-0 R/W-0 15 8 7 0 MACADDR4 MACADDR5 R/W-0 R/W-0 LEGEND: R/W = Read/Write; - n = valu[...]

www.ti.com 5.45 MAC Index Register (MACINDEX) EMAC Port Registers The MAC index register (MACINDEX) is shown in Figure 73 and described in Table 73 . Figure 73. MAC Index Register (MACINDEX) 31 16 Reserved R-0 15 5 4 0 Reserved MACINDEX R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 73. MAC Index Register (MACINDEX[...]

www.ti.com 5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP) EMAC Port Registers The transmit channel 0-7 DMA head descriptor pointer register (TXnHDP) is shown in Figure 74 and described in Table 74 . Figure 74. Transmit Channel n DMA Head Descriptor Pointer Register (TX n HDP) 31 16 TX n HDP R/W-x 15 0 TX n HDP R/W-x LEGEND:[...]

www.ti.com 5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RXnHDP) EMAC Port Registers The receive channel 0-7 DMA head descriptor pointer register (RXnHDP) is shown in Figure 75 and described in Table 75 . Figure 75. Receive Channel n DMA Head Descriptor Pointer Register (RX n HDP) 31 16 RX n HDP R/W-x 15 0 RX n HDP R/W-x LEGEND: R/[...]

www.ti.com 5.48 Transmit Channel 0-7 Completion Pointer Register (TX nCP) EMAC Port Registers The Transmit Channel 0-7 Completion Pointer Register (TX n CP) is shown in Figure 76 and described in Table 76 . Figure 76. Transmit Channel n Completion Pointer Register (TX n CP) 31 16 TX n CP R/W-x 15 0 TX n CP R/W-x LEGEND: R/W = Read/Write; - n = valu[...]

www.ti.com 5.49 Receive Channel 0-7 Completion Pointer Register (RX nCP) EMAC Port Registers The receive channel 0-7 completion pointer register (RX n CP) is shown in Figure 77 and described in Table 77 . Figure 77. Receive Channel n Completion Pointer Register (RX n CP) 31 16 RX n CP R/W-x 15 0 RX n CP R/W-x LEGEND: R/W = Read/Write; - n = value a[...]

www.ti.com 5.50 Network Statistics Registers 5.50.1 Good Receive Frames Register (RXGOODFRAMES) 5.50.2 Broadcast Receive Frames Register (RXBCASTFRAMES) EMAC Port Registers The EMAC has a set of statistics that record events associated with frame traffic. The statistics values are cleared to zero 38 clocks after the rising edge of reset. When the G[...]

www.ti.com 5.50.3 Multicast Receive Frames Register (RXMCASTFRAMES) 5.50.4 Pause Receive Frames Register (RXPAUSEFRAMES) 5.50.5 Receive CRC Errors Register (RXCRCERRORS) 5.50.6 Receive Alignment/Code Errors Register (RXALIGNCODEERRORS) EMAC Port Registers The total number of good multicast frames received on the EMAC. A good multicast frame is defi[...]

www.ti.com 5.50.7 Receive Oversized Frames Register (RXOVERSIZED) 5.50.8 Receive Jabber Frames Register (RXJABBER) 5.50.9 Receive Undersized Frames Register (RXUNDERSIZED) 5.50.10 Receive Frame Fragments Register (RXFRAGMENTS) EMAC Port Registers The total number of oversized frames received on the EMAC. An oversized frame is defined as having all [...]

www.ti.com 5.50.11 Filtered Receive Frames Register (RXFILTERED) 5.50.12 Receive QOS Filtered Frames Register (RXQOSFILTERED) 5.50.13 Receive Octet Frames Register (RXOCTETS) 5.50.14 Good Transmit Frames Register (TXGOODFRAMES) EMAC Port Registers The total number of frames received on the EMAC that the EMAC address matching process indicated shoul[...]

www.ti.com 5.50.15 Broadcast Transmit Frames Register (TXBCASTFRAMES) 5.50.16 Multicast Transmit Frames Register (TXMCASTFRAMES) 5.50.17 Pause Transmit Frames Register (TXPAUSEFRAMES) 5.50.18 Deferred Transmit Frames Register (TXDEFERRED) 5.50.19 Transmit Collision Frames Register (TXCOLLISION) EMAC Port Registers The total number of good broadcast[...]

www.ti.com 5.50.20 Transmit Single Collision Frames Register (TXSINGLECOLL) 5.50.21 Transmit Multiple Collision Frames Register (TXMULTICOLL) 5.50.22 Transmit Excessive Collision Frames Register (TXEXCESSIVECOLL) 5.50.23 Transmit Late Collision Frames Register (TXLATECOLL) 5.50.24 Transmit Underrun Error Register (TXUNDERRUN) EMAC Port Registers Th[...]

www.ti.com 5.50.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE) 5.50.26 Transmit Octet Frames Register (TXOCTETS) 5.50.27 Transmit and Receive 64 Octet Frames Register (FRAME64) 5.50.28 Transmit and Receive 65 to 127 Octet Frames Register (FRAME65T127) 5.50.29 Transmit and Receive 128 to 255 Octet Frames Register (FRAME128T255) EMAC Port[...]

www.ti.com 5.50.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511) 5.50.31 Transmit and Receive 512 to 1023 Octet Frames Register (FRAME512T1023) 5.50.32 Transmit and Receive 1024 to RXMAXLEN Octet Frames Register (FRAME1024TUP) 5.50.33 Network Octet Frames Register (NETOCTETS) EMAC Port Registers The total number of 256-byte t[...]

www.ti.com 5.50.34 Receive FIFO or DMA Start of Frame Overruns Register (RXSOFOVERRUNS) 5.50.35 Receive FIFO or DMA Middle of Frame Overruns Register (RXMOFOVERRUNS) 5.50.36 Receive DMA Start of Frame and Middle of Frame Overruns Register (RXDMAOVERRUNS) EMAC Port Registers The total number of frames received on the EMAC that had either a FIFO or D[...]

www.ti.com Appendix A Glossary Appendix A Broadcast MAC Address — A special Ethernet MAC address used to send data to all Ethernet devices on the local network. The broadcast address is FFh-FFh-FFh-FFh-FFh-FFh. The LSB of the first byte is odd, qualifying it as a group address; however, its value is reserved for broadcast. It is classified separa[...]

www.ti.com Appendix A Jumbo Packets — Jumbo frames are defined as those packets whose length exceeds the standard Ethernet MTU, which is 1500 kbytes. For the C64x+ devices, it is recommended not to use packets exceeding 35K in length. The PHY that you use can place additional limits on to the length of the packets that you can transfer in a syste[...]

www.ti.com Appendix B Revision History Appendix B Table B-1 lists the changes made since the previous version of this document. Table B-1. Document Revision History Reference Additions/Modifications/Deletions Section 2.1 Changed Section 2.1 . Section 2.1.2 Changed Section 2.1.2 . Section 2.15.4 Changed Step 19 . Figure 3 Changed Figure 3 . Table 3 [...]

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