Texas Instruments TMS320DM357 инструкция обслуживания

TMS320DM357 DMSoC Universal Serial Bus (USB) Controller User's Guide Literature Number: SPRUGH3 November 2008[...]

2 SPRUGH3 – November 2008 Submit Documentation Feedback[...]

Contents Preface ....................................................................................................................................... 11 1 Introduction ....................................................................................................................... 14 1.1 Purpose of the Peripheral ..........................[...]

www.ti.com 4.17 Transmit CPPI Masked Status Register (TCPPIMSKSR) .......................................................... 95 4.18 Transmit CPPI Raw Status Register (TCPPIRAWSR) ............................................................. 95 4.19 Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) .........................................[...]

www.ti.com 4.66 Type Register (Host mode only) (HOST_TYPE0) ................................................................ 129 4.67 Transmit Type Register (Host mode only) (HOST_TXTYPE) ................................................... 129 4.68 NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) ................................................[...]

www.ti.com List of Figures 1 Functional Block Diagram ................................................................................................. 15 2 Interrupt Service Routine Flow Chart .................................................................................... 25 3 CPU Actions at Transfer Phases ...................................[...]

www.ti.com 53 Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1) ........................................................ 106 54 Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2) ........................................................ 107 55 Receive CPPI DMA State Word 3 (RCPPIDMASTATEW3) ........................................................ 107 56 [...]

www.ti.com List of Tables 1 USB Pins .................................................................................................................... 23 2 PERI_TXCSR Register Bit Configuration for Bulk IN Transactions ................................................. 37 3 PERI_RXCSR Register Bit Configuration for Bulk OUT Transactions .........[...]

www.ti.com 50 Transmit CPPI DMA State Word 4 (TCPPIDMASTATEW4) Field Descriptions .................................. 103 51 Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5) Field Descriptions .................................. 104 52 Transmit CPPI Completion Pointer (TCPPICOMPPTR) Field Descriptions ....................................... 105 53 Re[...]

www.ti.com 101 Transmit Hub Port (TXHUBPORT) Field Descriptions ............................................................... 140 102 Receive Function Address (RXFUNCADDR) Field Descriptions ................................................... 141 103 Receive Hub Address (RXHUBADDR) Field Descriptions ..............................................[...]

Preface SPRUGH3 – November 2008 Read This First About This Manual This document describes the universal serial bus (USB) controller in the TMS320DM357 Digital Media System-on-Chip (DMSoC). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is [...]

Notational Conventions www.ti.com SPRUG28 — TMS320DM357 DMSoC 64-Bit Timer User's Guide. Describes the operation of the software-programmable 64-bit timer in the TMS320DM357 Digital Media System-on-Chip (DMSoC). Timer 0 and Timer 1 are used as general-purpose (GP) timers and can be programmed in 64-bit mode, dual 32-bit unchained mode, or du[...]

www.ti.com Notational Conventions SPRUG37 — TMS320DM357 DMSoC Pulse-Width Modulator (PWM) Peripheral User's Guide. Describes the pulse-width modulator (PWM) peripheral in the TMS320DM357 Digital Media System-on-Chip (DMSoC). SPRUG38 — TMS320DM357 DMSoC DDR2 Memory Controller User's Guide. Describes the DDR2 memory controller in the TM[...]

1 Introduction 1.1 Purpose of the Peripheral 1.2 Features 1.3 Features Not Supported User's Guide SPRUGH3 – November 2008 Universal Serial Bus (USB) Controller This document describes the universal serial bus (USB) controller in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The controller supports high-speed USB peripheral mode and h[...]

1.4 Functional Block Diagram Internal bus CPPI DMA engine FIFO encode/ decode Packet USB PHY 2.0 USB 24 MHz oscillator crystal Registers, interrupts, endpoint control, and packet scheduling www.ti.com Introduction The USB functional block diagram is shown in Figure 1 . Figure 1. Functional Block Diagram SPRUGH3 – November 2008 Universal Serial Bu[...]

1.5 Supported Use Case Examples Introduction www.ti.com The USB supports the following user cases: Detailed information about the architecture and operation of the USB controller follows in Section 2 . Programming examples are also provided for each of the operational modes of the controller. User Case 1: An example of how to initialize the USB con[...]

www.ti.com Introduction User Case 2: An example of how to program the USB Endpoints in peripheral mode Example 2. Programming the USB Endpoints in Peripheral Mode // DMA channel number. Valid values are 0, 1, 2, or 3. int CHAN_NUM = 0; // Fifo sizes: uncomment the desired size. // This example uses 64-byte fifo. // int fifosize = 0; // 8 bytes // i[...]

Introduction www.ti.com User Case 3: An example of how to program the USB endpoints in host mode Example 3. Programming the USB Endpoints in Host Mode // DMA channel number. Valid values are 0, 1, 2, or 3. int CHAN_NUM = 0; // Fifo sizes: uncomment the desired size. // This example uses 64-byte fifo. // int fifosize = 0; // 8 bytes // int fifosize [...]

www.ti.com Introduction Example 3. Programming the USB Endpoints in Host Mode (continued) usbRegs->TXFIFOSZ = fifosize | ((double_buffer & 1) < < 4); usbRegs->TXFIFOADDR = fifo_start_address + (1 < < (fifosize+double_buffer)); usbRegs->RXMAXP = FIFO_MAXP; usbRegs->TXMAXP = FIFO_MAXP; //Configure the endpoint switch (devi[...]

Introduction www.ti.com User Case 4: An example of how to do host negotiation to support USB If the HOSTREQ bit in the DEVCTL register is set, host negotiation is performed by the hardware when the device enters suspend mode. The bit is cleared when host negotiation is complete. User Case 5: An example of how to program the USB DMA controller Examp[...]

www.ti.com Introduction Example 4. Programming the USB DMA Controller (continued) usbRegs->CHANNEL[i].RCPPIDMASTATEW6 = 0; tx_desc[i] = 0; rx_desc[i] = 0; } // Routine to flush TX fifo. // Must call this routine twice for double-buffered FIFO void flush_tx_fifo(int ep) { int index_save; int status; index_save = usbRegs->INDEX; // Save the ind[...]

1.6 Industry Standard(s) Compliance Statement Introduction www.ti.com Example 4. Programming the USB DMA Controller (continued) // Increment descriptor counter tx_desc[ch]++; } // Routine to start the RX DMA for a given channel void start_rx_dma(int ch) { int index_save; index_save = usbRegs->INDEX; // Save the index to restore later // Must hav[...]

2 Peripheral Architecture 2.1 Clock Control 2.2 Signal Descriptions 2.3 Indexed and Non-Indexed Registers www.ti.com Peripheral Architecture Information related to clock generation and control for the USB peripheral will be added in a future revision of this document. Clocks for USB are generated based on a crystal oscillator on the M24XI and M24XO[...]

2.4 USB PHY Initialization 2.5 Dynamic FIFO Sizing 3 USB Controller Host and Peripheral Modes Operation USB Controller Host and Peripheral Modes Operation www.ti.com The following bits in USBPHY_CTL must be cleared to enable the USB controller: OSCPDWN and PHYPDWN. The following bits in USBPHY_CTL must be set to enable the level comparators: VBDTCT[...]

Read interrupt status register Resume interrupt ? Resume routine Y es No A device or B device ? SESSREQ interrupt ? No Vbus error interrupt ? Y es Y es A device B device Session req routine routine Vbus error ? Host or peripheral Peripheral Host ? Connect interrupt Connect routine Y es routine Babble ? Y es Babble interrupt EP0 Y es Host EP0 routin[...]

3.1 USB Controller Peripheral Mode Operation 3.1.1 Peripheral Mode: Control Transactions USB Controller Host and Peripheral Modes Operation www.ti.com • Soft connect - After a reset, the SOFTCONN bit of POWER register (bit 6) is cleared to 0. The controller will therefore appear disconnected until the software has set the SOFTCONN bit to 1. The a[...]

3.1.1.1 Zero Data Requests 3.1.1.2 Write Requests www.ti.com USB Controller Host and Peripheral Modes Operation Note: The Setup packet associated with any standard device request should include an 8-byte command. Any setup packet containing a command field of anything other than 8 bytes will be automatically rejected by the controller. Zero data re[...]

3.1.1.3 Read Requests USB Controller Host and Peripheral Modes Operation www.ti.com If the length of the data associated with the request (indicated by the wLength field in the command) is greater than the maximum packet size for endpoint 0, further data packets will be sent. In this case, PERI_CSR0 should be written to set the SERV_RXPKTRDY bit, b[...]

3.1.1.4 Endpoint 0 States Idle Tx state Rx state Sequence #1 Sequence #2 Sequence #3 www.ti.com USB Controller Host and Peripheral Modes Operation When the USB controller is operating as a peripheral device, the endpoint 0 control needs three modes – IDLE, TX and RX – corresponding to the different phases of the control transfer and the states [...]

Int Setup IN data phase Int IN data phase Int IN data phase Int Status phase (OUT) Int Sequence #1 Idle TX state Idle set TxPktRdy Load FIFO and and set DataEnd Load FIFO and set TxPktRdy Unload device req. and clear RxPktRdy Load FIFO and set TxPktRdy CPU actions Status phase Setup CPU actions Sequence #2 RxPktRdy and clear Unload FIFO OUT data Id[...]

3.1.1.5 Endpoint 0 Service Routine www.ti.com USB Controller Host and Peripheral Modes Operation An Endpoint 0 interrupt is generated when: • The controller sets the RXPKTRDY bit of PERI_CSR0 (bit 0) after a valid token has been received and data has been written to the FIFO. • The controller clears the TXPKTRDY bit of PERI_CSR0 (bit 1) after t[...]

Service endpoint 0 Read endpoint 0 CSR Sent stall ? Y es Clear SentStall bit state −> IDLE No No Set ServicedSetupEnd state −> IDLE Setup end ? Y es State Y es No = IDLE ? IDLE mode TX mode No = TX ? State Y es RX mode = RX* ? State Y es * By default USB Controller Host and Peripheral Modes Operation www.ti.com Figure 5. Service Endpoint [...]

IDLE mode RxPktRdy set? Return No Y es Set ServiceRxPktRdy Unload FIFO Decode command Y es Command has data phase ? No Process command Set DataEnd Set ServicedRxPktRdy Return Data No phase = IN ? State −> TX Y es Return State −> RX Return www.ti.com USB Controller Host and Peripheral Modes Operation 3.1.1.5.1 IDLE Mode IDLE mode is the mo[...]

TX mode W rite  MaxP bytes to FIFO Last packet ? No Y es Set TxPktRdy and set DataEnd state −> IDLE Return TxPktRdy Set USB Controller Host and Peripheral Modes Operation www.ti.com 3.1.1.5.2 TX Mode When the endpoint is in TX state all arriving IN tokens need to be treated as part of a data phase until the required amount of data has been [...]

RXmode RxPktRdy set ? Return No Y es ReadCount0 register(n) Unloadnbytes fromFIFO Last packet ? No Y es Set ServicedRxPktRdy Set ServicedRxPktRdy andDataEnd state->IDLE Return www.ti.com USB Controller Host and Peripheral Modes Operation 3.1.1.5.3 RX Mode In RX mode, all arriving data should be treated as part of a data phas[...]

USB Controller Host and Peripheral Modes Operation www.ti.com 3.1.1.5.4 Error Handling A control transfer may be aborted due to a protocol error on the USB, the host prematurely ending the transfer, or if the software wishes to abort the transfer (e.g., because it cannot process the command). The controller automatically detects protocol errors and[...]

3.1.2 Bulk Transactions 3.1.2.1 Peripheral Mode: Bulk In Transactions www.ti.com USB Controller Host and Peripheral Modes Operation A Bulk IN transaction is used to transfer non-periodic data from the USB peripheral device to the host. The following optional features are available for use with a Tx endpoint used in peripheral mode for Bulk IN trans[...]

3.1.2.2 Peripheral Mode: Bulk OUT Transactions USB Controller Host and Peripheral Modes Operation www.ti.com 3.1.2.1.2 Operation When data is to be transferred over a Bulk IN pipe, a data packet needs to be loaded into the FIFO and the PERI_TXCSR register written to set the TXPKTRDY bit (bit 0). When the packet has been sent, the TXPKTRDY bit will [...]

www.ti.com USB Controller Host and Peripheral Modes Operation 3.1.2.2.1 Setup In configuring an Rx endpoint for Bulk OUT transactions, the RXMAXP register must be written with the maximum packet size (in bytes) for the endpoint. This value should be the same as the wMaxPacketSize field of the Standard Endpoint Descriptor for the endpoint. In additi[...]

3.1.3 Interrupt Transactions USB Controller Host and Peripheral Modes Operation www.ti.com 3.1.2.2.3 Error Handling If the software wants to shut down the Bulk OUT pipe, it should set the SENDSTALL bit (bit 5 of PERI_RXCSR). When the controller receives the next packet it will send a STALL to the host, set the SENTSTALL bit (bit 6 of PERI_RXCSR) an[...]

3.1.4 Isochronous Transactions 3.1.4.1 Isochronous IN Transactions www.ti.com USB Controller Host and Peripheral Modes Operation An Isochronous IN transaction is used to transfer periodic data from the function controller to the host. The following optional features are available for use with a Tx endpoint used in Peripheral mode for Isochronous IN[...]

3.1.4.2 Isochronous OUT Transactions USB Controller Host and Peripheral Modes Operation www.ti.com An interrupt is generated whenever a packet is sent to the host and the software may use this interrupt to load the next packet into the FIFO and set the TXPKTRDY bit in the PERI_TXCSR register (bit 0) in the same way as for a Bulk Tx endpoint. As the[...]

www.ti.com USB Controller Host and Peripheral Modes Operation 3.1.4.2.1 Setup In configuring an Rx endpoint for Isochronous OUT transactions, the RXMAXP register must be written with the maximum packet size (in bytes) for the endpoint. This value should be the same as the wMaxPacketSize field of the Standard Endpoint Descriptor for the endpoint. In[...]

3.2 USB Controller Host Mode Operation 3.2.1 Host Mode: Control Transactions USB Controller Host and Peripheral Modes Operation www.ti.com • Entry into Suspend mode . When operating as a host, the controller can be prompted to enter Suspend mode by setting the SUSPENDM bit in the POWER register. When this bit is set, the controller will complete [...]

3.2.1.1 Setup Phase Transaction scheduled TxPktRdy and SetupPkt both set ? SETUP token sent DA T A0 oacket sent ? received Stall No Y es Y es No RxStall set TxPktRdy cleared Error Count cleared interrupt generated Command not supported by target TxPktRdy cleared Error Count cleared Interrupt generated Y es ? No ACK received Transaction complete No [...]

3.2.1.2 IN Data Phase USB Controller Host and Peripheral Modes Operation www.ti.com 3. At the end of the attempt to send the data, the controller will generate an Endpoint 0 interrupt. The software should then read HOST_CSR0 to establish whether the RXSTALL bit (bit 2), the ERROR bit (bit 4) or the NAK_TIMEOUT bit (bit 7) has been set. If RXSTALL i[...]

IN token sent ? received ST ALL No Y es Y es No RxStall set ReqPkt cleared Error Count cleared Interrupt generated Problem in data sent Y es ? Data0/1 received Transaction complete No NAK received ? Y es ? NAK limit reached No Y es Error count cleared incremented Error count NAK T imeout set Endpoint halted Interrupt generated ? Error count=3 No Er[...]

For each OUT packet specified in SETUP phase TxPktRdy set ? OUT token sent DA T A0/1 packet sent ? received Stall No Y es Y es No RxStall set TxPktRdy cleared Error Count cleared interrupt generated Command could not be completed TxPktRdy cleared Error Count cleared Interrupt generated Y es ? No ACK received Transaction complete No NAK received ? Y[...]

3.2.1.4 IN Status Phase (following SETUP Phase or OUT Data Phase) IN token sent ? received ST ALL No Y es Y es No RxStall set ReqPkt cleared Error Count cleared Interrupt generated Y es ? Data1 received Transaction complete No NAK received ? Y es ? NAK limit reached No Y es Error count cleared incremented Error count NAK T imeout set Endpoint halte[...]

3.2.1.5 OUT Status Phase (following IN Data Phase) USB Controller Host and Peripheral Modes Operation www.ti.com 3. When the controller generates the Endpoint 0 interrupt, read HOST_CSR0 to establish whether the RXSTALL bit (bit 2), the ERROR bit (bit 4), the NAK_TIMEOUT bit (bit 7) or RXPKTRDY bit (bit 0) has been set. If RXSTALL bit is set, it in[...]

Completion of IN data phase OUT token sent ? received Stall No Y es Y es No RxStall set TxPktRdy cleared Error Count cleared interrupt generated Command could not be completed TxPktRdy cleared Error Count cleared Interrupt generated Y es ? No ACK received Transaction complete No NAK received ? Y es ? NAK limit reached No Y es Error count cleared in[...]

3.2.2 Bulk Transactions 3.2.2.1 Host Mode: Bulk IN Transactions USB Controller Host and Peripheral Modes Operation www.ti.com A Bulk IN transaction may be used to transfer non-periodic data from the external USB peripheral to the host. The following optional features are available for use with an Rx endpoint used in host mode to receive the data: ?[...]

3.2.2.2 Bulk OUT Transactions www.ti.com USB Controller Host and Peripheral Modes Operation 3.2.2.1.2 Operation When Bulk data is required from the USB peripheral device, the software should set the REQPKT bit in the corresponding HOST_RXCSR register (bit 5). The controller will then send an IN token to the selected peripheral endpoint and waits fo[...]

3.2.3 Host Mode: Interrupt Transactions USB Controller Host and Peripheral Modes Operation www.ti.com • The HOST_TXINTERVAL register needs to be written with the required value for the NAK limit (2 - 215 frames/microframes), or cleared to 0 if the NAK timeout feature is not required. • The relevant interrupt enable bit in the INTRTXE register s[...]

3.2.4 Isochronous Transactions 3.2.4.1 Host Mode: Isochronous IN Transactions www.ti.com USB Controller Host and Peripheral Modes Operation An Isochronous IN transaction is used to transfer periodic data from the USB peripheral to the host. The following optional features are available for use with an Rx endpoint used in Host mode to receive this d[...]

3.2.4.2 Host Mode: Isochronous Out Transactions USB Controller Host and Peripheral Modes Operation www.ti.com FIFO unload requests will probably be irregular. If the data sink for the endpoint is going to some external hardware, it may be better to minimize the requirement for additional buffering by waiting until the end of each frame before unloa[...]

3.3 DMA Operation 3.3.1 DMA Transmit Operation 3.3.1.1 Transmit Buffer 3.3.1.2 CPPI Transmit Buffer Descriptor www.ti.com USB Controller Host and Peripheral Modes Operation 3.2.4.2.2 Operation The operation starts when the software writes to the FIFO and sets TXPKTRDY bit of HOST_TXCSR (bit 0). This triggers the controller to send an OUT token foll[...]

USB Controller Host and Peripheral Modes Operation www.ti.com • End of queue (EOQ) (only valid on EOP) • Packet Length (only valid with SOP) Transmit buffer descriptors contain 16 bytes (4 words) and must begin on 16-byte aligned addresses. Transmit buffer descriptors may be linked together to form packets. Buffer descriptor SOP and EOP bits ar[...]

3.3.1.3 Transmit DMA State www.ti.com USB Controller Host and Peripheral Modes Operation Table 9. Transmit Buffer Descriptor Word 3 (continued) Bits Name Value Description 28 EOQ End of Queue: The End of Queue bit is set by the DMA controller to indicate that all packets in the queue have been transmitted and the Tx queue is empty. This bit is vali[...]

3.3.1.4 Transmit Queue SOP descriptor Buffer Descriptor Buf fer EOP descriptor Buffer Tx queue head descriptor pointer 3.3.1.5 Operation USB Controller Host and Peripheral Modes Operation www.ti.com Figure 14 shows a Tx queue. Tx queue provide a logical queue of DMA packets for transmission through a channel. Each channel has one dedicated Tx queue[...]

3.3.1.6 Transparent Mode and RNDIS Mode Transmit DMA Operation www.ti.com USB Controller Host and Peripheral Modes Operation clear the Ownership bit in the DMA packet’s SOP buffer descriptor and issue an interrupt to the processor by writing the DMA packet’s last buffer descriptor address to the queue’s Tx DMA State Completion Pointer (TCPPIC[...]

3.3.1.7 DMA Channel TearDown 3.3.2 DMA Receive Operation 3.3.2.1 Receive Buffer USB Controller Host and Peripheral Modes Operation www.ti.com RNDIS Mode Setup The setup of RNDIS mode DMA is similar to the default Transparent Mode as mentioned in the previous section. The following steps need to be taken for setting up RNDIS mode Tx DMA: • After r[...]

3.3.2.2 CPPI Receive Buffer Descriptor www.ti.com USB Controller Host and Peripheral Modes Operation Rx buffer descriptors provide information about a single corresponding Rx data buffer. Every Rx buffer has a single Rx buffer descriptor that stores the following information: • Pointer to the data buffer • Pointer to the next buffer descriptor [...]

3.3.2.3 Receive DMA State USB Controller Host and Peripheral Modes Operation www.ti.com Table 13. Receive Buffer Descriptor Word 3 Bit Field Value Description 31 SOP Start of Packet: SOP Indicates that the descriptor buffer is the first buffer in the packet. Software should clear the SOP bit when setting up the descriptor. 0 Not start of packet buf[...]

3.3.2.4 Receive Queue SOP descriptor Buffer Descriptor Buf fer Descriptor Descriptor Buf fer Buf fer EOP descriptor Buffer Rx queue head descriptor pointer 3.3.2.5 Operation www.ti.com USB Controller Host and Peripheral Modes Operation Figure 15 shows an Rx Queue. Rx queue provide a logical queue of processor memory space for DMA packets to be rece[...]

USB Controller Host and Peripheral Modes Operation www.ti.com The software enables packet reception on a given channel by writing the address of the first buffer descriptor in the queue (nonzero value) to the channel’s head descriptor pointer (RCCPIDMASTATEW1) in the channel’s Rx DMA state. When packet reception begins on a given channel, the D[...]

3.3.2.6 Receive Abort Handling 3.3.2.7 RNDIS Mode and Transparent Mode Receive DMA Operation www.ti.com USB Controller Host and Peripheral Modes Operation The DMA controller sets ‘Rx Abort’ bit used to identify Rx packets which were aborted due to lack of buffers. Software must take care to inspect any Rx SOP packet for this bit and ignore all [...]

3.3.2.8 DMA Teardown Procedure 3.4 Interrupt Handling USB Controller Host and Peripheral Modes Operation www.ti.com If RXn_AUTOREQ (where n is the channel number) of AUTOREQ register is set with binary 11, IN tokens will be generated and sent to the target USB peripheral device even after the End Of DMA Packet is reached. This feature is useful to [...]

www.ti.com USB Controller Host and Peripheral Modes Operation Table 15. USB Interrupt Conditions (continued) Interrupt Description USB[3] SOF started USB[2] Reset Signaling detected (In Peripheral Mode) Babble detected (In Host Mode) USB[1] Resume signaling detected USB[0] Suspend Signaling detected SPRUGH3 – November 2008 Universal Serial Bus (U[...]

3.4.1 USB Core Interrupts 3.4.2 DMA Interrupts 3.5 Test Modes USB Controller Host and Peripheral Modes Operation www.ti.com There are two methods available for software to access USB core interrupts, selectable by the UINT bit of CTRLR. The UINT bit cleared to 0 selects the PDR 2.0 compliant register set (INTSRCR, INTSETR, INTCLRR, INTMSKR, INTMSKS[...]

3.5.1 TEST_SE0_NAK 3.5.2 TEST_J 3.5.3 TEST_K www.ti.com USB Controller Host and Peripheral Modes Operation To enter the Test_SE0_NAK test mode, the software should set the Test_SE0-NAK bit by writing 0x01 to the TestMode register. The controller will then go into a mode in which it responds to any valid IN token with a NAK. To enter the Test_J test[...]

3.5.4 TEST_PACKET 3.5.5 FIFO_ACCESS USB Controller Host and Peripheral Modes Operation www.ti.com To execute the Test_Packet, the software should: 1. Start a session (if the core is being used in Host mode). 2. Write the standard test packet (shown below) to the Endpoint 0 FIFO. 3. Write 0x8 to the TestMode register to enter Test_Packet test mode. [...]

3.5.6 FORCE_HOST www.ti.com USB Controller Host and Peripheral Modes Operation The Force Host test mode enables the user to instruct the core to operate in Host mode, regardless of whether it is actually connected to any peripheral, i.e., the state of the CID input and the LINESTATE and HOSTDISCON signals are ignored. (While in this mode, the state[...]

3.6 Reset Considerations 3.6.1 Software Reset Considerations 3.6.2 Hardware Reset Considerations 3.6.3 USB Reset Considerations 3.7 Interrupt Support 3.8 EDMA Event Support 3.9 Power Management USB Controller Host and Peripheral Modes Operation www.ti.com The USB controller has two reset sources: hardware reset and the soft reset (RESET bit in CTRL[...]

4 Registers www.ti.com Registers Table 16 lists the memory-mapped registers for the universal serial bus (USB). See the device-specific data manual for the memory address of these registers. The base address is 01C6 4000h. Note: In some cases, a single register address can have different names or meanings depending on the mode (host/peripheral) or [...]

Registers www.ti.com Table 16. Universal Serial Bus (USB) Registers (continued) Offset Acronym Register Description Section 124h RCPPIDMASTATEW1 Receive CPPI DMA State Word 1 Section 4.38 128h RCPPIDMASTATEW2 Receive CPPI DMA State Word 2 Section 4.39 12Ch RCPPIDMASTATEW3 Receive CPPI DMA State Word 3 Section 4.40 130h RCPPIDMASTATEW4 Receive CPPI [...]

www.ti.com Registers Table 16. Universal Serial Bus (USB) Registers (continued) Offset Acronym Register Description Section 1DCh TCPPICOMPPTR Transmit CPPI Completion Pointer Section 4.36 1E0h RCPPIDMASTATEW0 Receive CPPI DMA State Word 0 Section 4.37 1E4h RCPPIDMASTATEW1 Receive CPPI DMA State Word 1 Section 4.38 1E8h RCPPIDMASTATEW2 Receive CPPI [...]

Registers www.ti.com Table 16. Universal Serial Bus (USB) Registers (continued) Offset Acronym Register Description Section 41Bh HOST_NAKLIMIT0 Sets the NAK response timeout on Endpoint 0 Section 4.68 (Index register set to select Endpoint 0) HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the Section 4.69 NAK response [...]

www.ti.com Registers Table 16. Universal Serial Bus (USB) Registers (continued) Offset Acronym Register Description Section Target Endpoint 1 Control Registers, Valid Only in Host Mode 488h TXFUNCADDR Address of the target function that has to be accessed Section 4.83 through the associated Transmit Endpoint. 48Ah TXHUBADDR Address of the hub that [...]

Registers www.ti.com Table 16. Universal Serial Bus (USB) Registers (continued) Offset Acronym Register Description Section 49Eh RXHUBADDR Address of the hub that has to be accessed through the Section 4.87 associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. 49Fh RXHUBPORT Por[...]

www.ti.com Registers Table 16. Universal Serial Bus (USB) Registers (continued) Offset Acronym Register Description Section 51Dh HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the Section 4.71 NAK response timeout on Bulk transactions for host Receive endpoint. Control and Status Register for Endpoint 2 520h TXMAXP Max[...]

4.1 Control Register (CTRLR) Registers www.ti.com Table 16. Universal Serial Bus (USB) Registers (continued) Offset Acronym Register Description Section 546h PERI_RXCSR Control Status Register for Peripheral Receive Endpoint Section 4.62 (peripheral mode) HOST_RXCSR Control Status Register for Host Receive Endpoint Section 4.63 (host mode) 548h RXC[...]

4.2 Status Register (STATR) 4.3 RNDIS Register (RNDISR) www.ti.com Registers The Status Register (STATR) is shown in Figure 17 and described in Table 18 . Figure 17. Status Register (STATR) 31 16 Reserved R-0 15 1 0 Reserved DRVVBUS R-0 R-0 LEGEND: R = Read only; - n = value after reset Table 18. Status Register (STATR) Field Descriptions Bit Field[...]

4.4 Auto Request Register (AUTOREQ) Registers www.ti.com The Auto Request Register (AUTOREQ) is shown in Figure 19 and described in Table 20 . Figure 19. Auto Request Register (AUTOREQ) 31 16 Reserved R-0 1 5 876543210 Reserved Rx4 Rx3 Rx2 Rx1 R-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 20. Aut[...]

4.5 USB Interrupt Source Register (INTSRCR) www.ti.com Registers The USB Interrupt Source Register (INTSRCR) is shown in Figure 20 and described in Table 21 . Figure 20. USB Interrupt Source Register (INTSRCR) 31 25 24 16 Reserved USB R-0 R-0 15 13 12 8 7 5 4 0 Reserved RX Reserved TX R-0 R-0 R-0 R-0 LEGEND: R = Read only; - n = value after reset T[...]

4.6 USB Interrupt Source Set Register (INTSETR) Registers www.ti.com The USB Interrupt Source Set Register (INTSETR) is shown in Figure 21 and described in Table 22 . Figure 21. USB Interrupt Source Set Register (INTSETR) 31 25 24 16 Reserved USB R-0 W-0 15 13 12 8 7 5 4 0 Reserved RX Reserved TX R-0 W-0 R-0 W-0 LEGEND: R = Read only; W = Write onl[...]

4.7 USB Interrupt Source Clear Register (INTCLRR) www.ti.com Registers The USB Interrupt Source Clear Register (INTCLRR) is shown in Figure 22 and described in Table 23 . Figure 22. USB Interrupt Source Clear Register (INTCLRR) 31 25 24 16 Reserved USB R-0 W-0 15 13 12 8 7 5 4 0 Reserved RX Reserved TX R-0 W-0 R-0 W-0 LEGEND: R = Read only; W = Wri[...]

4.8 USB Interrupt Mask Register (INTMSKR) Registers www.ti.com The USB Interrupt Mask Register (INTMSKR) is shown in Figure 23 and described in Table 24 . Figure 23. USB Interrupt Mask Register (INTMSKR) 31 25 24 16 Reserved USB R-0 R-0 15 13 12 8 7 5 4 0 Reserved RX Reserved TX R-0 R-0 R-0 R-0 LEGEND: R = Read only; - n = value after reset Table 2[...]

4.9 USB Interrupt Mask Set Register (INTMSKSETR) www.ti.com Registers The USB Interrupt Mask Set Register (INTMSKSETR) is shown in Figure 24 and described in Table 25 . Figure 24. USB Interrupt Mask Set Register (INTMSKSETR) 31 25 24 16 Reserved USB R-0 W-0 15 13 12 8 7 5 4 0 Reserved RX Reserved TX R-0 W-0 R-0 W-0 LEGEND: R = Read only; W = Write [...]

4.10 USB Interrupt Mask Clear Register (INTMSKCLRR) Registers www.ti.com The USB Interrupt Mask Clear Register (INTMSKCLRR) is shown in Figure 25 and described in Table 26 . Figure 25. USB Interrupt Mask Clear Register (INTMSKCLRR) 31 25 24 16 Reserved USB R-0 W-0 15 13 12 8 7 5 4 0 Reserved RX Reserved TX R-0 W-0 R-0 W-0 LEGEND: R = Read only; W =[...]

4.11 USB Interrupt Source Masked Register (INTMASKEDR) www.ti.com Registers The USB Interrupt Source Masked Register (INTMASKEDR) is shown in Figure 26 and described in Table 27 . Figure 26. USB Interrupt Source Masked Register (INTMASKEDR) 31 25 24 16 Reserved USB R-0 R-0 15 13 12 8 7 5 4 0 Reserved RX Reserved TX R-0 R-0 R-0 R-0 LEGEND: R = Read [...]

4.12 USB End of Interrupt Register (EOIR) 4.13 USB Interrupt Vector Register (INTVECTR) Registers www.ti.com The USB End of Interrupt Register (EOIR) is shown in Figure 27 and described in Table 28 . Figure 27. USB End of Interrupt Register (EOIR) 31 16 Reserved R-0 15 8 7 0 Reserved VECTOR R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = v[...]

4.14 Transmit CPPI Control Register (TCPPICR) 4.15 Transmit CPPI Teardown Register (TCPPITDR) www.ti.com Registers The Transmit CPPI Control Register (TCPPICR) is shown in Figure 29 and described in Table 30 . Figure 29. Transmit CPPI Control Register (TCPPICR) 31 16 Reserved R-0 15 1 0 Reserved TCPPI_ENABLE R-0 R/W-0 LEGEND: R/W = Read/Write; R = [...]

4.16 CPPI DMA End of Interrupt Register (CPPIEOIR) Registers www.ti.com Note: This register was previously named TCPPIEOIR, and that name will continue to exist in the CSL for backward compatibility. The CPPI DMA End of Interrupt Register (CPPIEOIR) is shown in Figure 31 and described in Table 32 . Figure 31. CPPI DMA End of Interrupt Register (CPP[...]

4.17 Transmit CPPI Masked Status Register (TCPPIMSKSR) 4.18 Transmit CPPI Raw Status Register (TCPPIRAWSR) www.ti.com Registers The Transmit CPPI Masked Status Register (TCPPIMSKSR) is shown in Figure 32 and described in Table 33 . Figure 32. Transmit CPPI Masked Status Register (TCPPIMSKSR) 31 16 Reserved R-0 15 4 3 0 Reserved MASKED COMP_PENDING [...]

4.19 Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) 4.20 Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR) Registers www.ti.com The Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) is shown in Figure 34 and described in Table 35 . Figure 34. Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) 31 16 Reserved R[...]

4.21 Receive CPPI Control Register (RCPPICR) 4.22 Receive CPPI Masked Status Register (RCPPIMSKSR) www.ti.com Registers The Receive CPPI Control Register (RCPPICR) is shown in Figure 36 and described in Table 37 . Figure 36. Receive CPPI Control Register (RCPPICR) 31 16 Reserved R-0 15 1 0 Reserved RCPPI_ENABLE R-0 R/W-0 LEGEND: R/W = Read/Write; R[...]

4.23 Receive CPPI Raw Status Register (RCPPIRAWSR) 4.24 Receive CPPI Interrupt Enable Set Register (RCPPIENSETR) Registers www.ti.com The Receive CPPI Raw Status Register (RCPPIRAWSR) is shown in Figure 38 and described in Table 39 . Figure 38. Receive CPPI Raw Status Register (RCPPIRAWSR) 31 16 Reserved R-0 15 4 3 0 Reserved COMP_PENDING R-0 R-0 L[...]

4.25 Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR) 4.26 Receive Buffer Count 0 Register (RBUFCNT0) www.ti.com Registers The Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR) is shown in Figure 40 and described in Table 41 . Figure 40. Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR) 31 16 Reserved R-0 15 4 3 0 Res[...]

4.27 Receive Buffer Count 1 Register (RBUFCNT1) 4.28 Receive Buffer Count 2 Register (RBUFCNT2) Registers www.ti.com The Receive Buffer Count 1 Register (RBUFCNT1) is shown in Figure 42 and described in Table 43 . Figure 42. Receive Buffer Count 1 Register (RBUFCNT1) 31 16 Reserved R-0 15 0 BUFCNT R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n [...]

4.29 Receive Buffer Count 3 Register (RBUFCNT3) 4.30 Transmit CPPI DMA State Word 0 (TCPPIDMASTATEW0) www.ti.com Registers The Receive Buffer Count 3 Register (RBUFCNT3) is shown in Figure 44 and described in Table 45 . Figure 44. Receive Buffer Count 3 Register (RBUFCNT3) 31 16 Reserved R-0 15 0 BUFCNT R/W-0 LEGEND: R/W = Read/Write; R = Read only[...]

4.31 Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1) 4.32 Transmit CPPI DMA State Word 2 (TCPPIDMASTATEW2) Registers www.ti.com The Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1) is shown in Figure 46 and described in Table 47 . Figure 46. Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1) 31 16 SOP_DESCRIPTOR_PTR R/W-0 15 2 1 0 SOP_DESCRIPTOR_PTR[...]

4.33 Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3) 4.34 Transmit CPPI DMA State Word 4 (TCPPIDMASTATEW4) www.ti.com Registers Table 48. Transmit CPPI DMA State Word 2 (TCPPIDMASTATEW2) Field Descriptions (continued) Bit Field Value Description 0 Reserved 0 Reserved The Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3) is shown in Figure 48 and de[...]

4.35 Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5) 4.36 Transmit CPPI Completion Pointer (TCPPICOMPPTR) Registers www.ti.com Table 50. Transmit CPPI DMA State Word 4 (TCPPIDMASTATEW4) Field Descriptions (continued) Bit Field Value Description 15-0 CURR_BUFFER_LENGTH 0-FFFFh Current Buffer Length Indicates how many valid bytes remain in the curre[...]

4.37 Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0) 4.38 Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1) www.ti.com Registers Table 52. Transmit CPPI Completion Pointer (TCPPICOMPPTR) Field Descriptions Bit Field Value Description 31-2 DESC_ADDR 0-3FFF FFFFh Descriptor Address This field contains the 30-bit word aligned pointer of the end of packe[...]

Registers www.ti.com Figure 53. Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1) 31 16 RXQ_HEAD_PTR R/W-0 15 2 1 0 RXQ_HEAD_PTR Reserved R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 54. Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1) Field Descriptions Bit Field Value Description 31-2 RXQ_HEAD_PTR 0-1FFF FFFFh Rec[...]

4.39 Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2) 4.40 Receive CPPI DMA State Word 3 (RCPPIDMASTATEW3) www.ti.com Registers The Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2) is shown in Figure 54 and described in Table 55 . Figure 54. Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2) 31 16 SOP_DESCRIPTOR_PTR R/W-0 15 2 1 0 SOP_DESCRIPTOR_PTR Res[...]

Registers www.ti.com Universal Serial Bus (USB) Controller 108 SPRUGH3 – November 2008 Submit Documentation Feedback[...]

4.41 Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4) 4.42 Receive CPPI DMA State Word 5 (RCPPIDMASTATEW5) www.ti.com Registers The Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4) is shown in Figure 56 and described in Table 57 . Figure 56. Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4) 31 0 CURR_BUFFER_PTR R/W-0 LEGEND: R/W = Read/Write; - n = val[...]

4.43 Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6) 4.44 Receive CPPI Completion Pointer (RCPPICOMPPTR) Registers www.ti.com The Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6) is shown in Figure 58 and described in Table 59 . Figure 58. Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6) 31 16 SOP_BUFFER_BYTECNT R/W-0 15 0 CURR_BUFFER_BYTECNT R/W-0 L[...]

4.45 Function Address Register (FADDR) 4.46 Power Management Register (POWER) www.ti.com Registers Table 60. Receive CPPI Completion Pointer (RCPPICOMPPTR) Field Descriptions (continued) Bit Field Value Description 0 RDBK_MODE Readback / Compare Mode 0 Compare Mode. Indicates that the value that is presented on bits 31:2 of the read data should be [...]

4.47 Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX) 4.48 Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) Registers www.ti.com Table 62. Power Management Register (POWER) Field Descriptions (continued) Bit Field Value Description 3 RESET 0-1 This bit is set when Reset signaling is present on the bus. Note: This bi[...]

4.49 Interrupt Enable Register for INTRTX (INTRTXE) 4.50 Interrupt Enable Register for INTRRX (INTRRXE) www.ti.com Registers Figure 63. Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) 31 16 Reserved R-0 15 5 4 3 2 1 0 Reserved EP4RX EP3RX EP2RX EP1RX Reserved R-0 R-0 R-0 R-0 R-0 R-0 LEGEND: R = Read only; - n = value after reset Table 64. [...]

Registers www.ti.com Figure 65. Interrupt Enable Register for INTRRX (INTRRXE) 15 8 Reserved R-0 7 543210 Reserved EP4RX EP3RX EP2RX EP1RX Reserved R-0 R/W-1 R/W-1 R/W-1 R/W-1 R-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 66. Interrupt Enable Register for INTRRX (INTRRXE) Field Descriptions Bit Field Value Description 1[...]

4.51 Interrupt Register for Common USB Interrupts (INTRUSB) www.ti.com Registers The Interrupt Register for Common USB Interrupts (INTRUSB) is shown in Figure 66 and described in Table 67 . Reading this register causes all bits to be cleared. Note: Unless the UINT bit of CTRLR is set, do not read or write this register directly. Use the INTSRCR reg[...]

4.52 Interrupt Enable Register for INTRUSB (INTRUSBE) Registers www.ti.com The Interrupt Enable Register for INTRUSB (INTRUSBE) is shown in Figure 67 and described in Table 68 . Note: Unless the UINT bit of CTRLR is set, do not read or write this register directly. Use the INTMSKSETR/INTMSKCLRR registers instead. Figure 67. Interrupt Enable Registe[...]

4.53 Frame Number Register (FRAME) 4.54 Index Register for Selecting the Endpoint Status and Control Registers (INDEX) www.ti.com Registers The Frame Number Register (FRAME) is shown in Figure 68 and described in Table 69 . Figure 68. Frame Number Register (FRAME) 15 11 10 0 Reserved FRAMENUMBER R-0 R-0 LEGEND: R = Read only; - n = value after rese[...]

4.55 Register to Enable the USB 2.0 Test Modes (TESTMODE) Registers www.ti.com The Register to Enable the USB 2.0 Test Modes (TESTMODE) is shown in Figure 70 and described in Table 71 . Figure 70. Register to Enable the USB 2.0 Test Modes (TESTMODE) 7 6 5 4 3 2 1 0 FORCE_HOST FIFO_ACCESS FORCE_FS FORCE_HS TEST_PACKET TEST_K TEST_J TEST_SE0_NAK R/W-[...]

4.56 Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) www.ti.com Registers The Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) is shown in Figure 71 and described in Table 72 . Figure 71. Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) 15 11 10 0 Reserved MAXPAYLOAD R-0 R/W-0 LEGEND: R/W = Rea[...]

4.57 Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) Registers www.ti.com The Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) is shown in Figure 72 and described in Table 73 . Figure 72. Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) 15 9 8 Reserved FLUSHFIFO R-0 W-0 7 6 5 4 3 2 1 0[...]

4.58 Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) www.ti.com Registers The Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) is shown in Figure 73 and described in Table 74 . Figure 73. Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) 15 11 10 9 8 Reserved DATATOGWREN DATATOG FLUSHFIFO R-0 W-0 R/W-0 W[...]

4.59 Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) Registers www.ti.com The Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) is shown in Figure 74 and described in Table 75 . Figure 74. Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) 15 14 13 12 11 10 9 7 Reserved ISO MODE DMAEN FRC[...]

4.60 Control Status Register for Host Transmit Endpoint (HOST_TXCSR) www.ti.com Registers The Control Status Register for Host Transmit Endpoint (HOST_TXCSR) is shown in Figure 75 and described in Table 76 . Figure 75. Control Status Register for Host Transmit Endpoint (HOST_TXCSR) 15 14 13 12 11 10 9 8 Reserved MODE DMAEN FRCDATATOG DMAMODE DATATO[...]

4.61 Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) Registers www.ti.com The Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) is shown in Figure 76 and described in Table 77 . Figure 76. Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) 15 11 10 0 Reserved MAXPAYLOAD R-0 R/W-0 LEGEND: R/W = Read/W[...]

4.62 Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) www.ti.com Registers The Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) is shown in Figure 77 and described in Table 78 . Figure 77. Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) 15 14 13 12 11 10 8 Reserved ISO DMAEN DISNYET DMAMO[...]

4.63 Control Status Register for Host Receive Endpoint (HOST_RXCSR) Registers www.ti.com The Control Status Register for Host Receive Endpoint (HOST_RXCSR) is shown in Figure 78 and described in Table 79 . Figure 78. Control Status Register for Host Receive Endpoint (HOST_RXCSR) 15 14 13 12 11 10 9 8 Reserved DMAEN DISNYET DMAMODE DATATOGWREN DATAT[...]

www.ti.com Registers SPRUGH3 – November 2008 Universal Serial Bus (USB) Controller 127 Submit Documentation Feedback[...]

4.64 Count 0 Register (COUNT0) 4.65 Receive Count Register (RXCOUNT) Registers www.ti.com The Count 0 Register (COUNT0) is shown in Figure 79 and described in Table 80 . Figure 79. Count 0 Register (COUNT0) 15 7 6 0 Reserved EP0RXCOUNT R-0 R-0 LEGEND: R = Read only; - n = value after reset Table 80. Count 0 Register (COUNT0) Field Descriptions Bit [...]

4.66 Type Register (Host mode only) (HOST_TYPE0) 4.67 Transmit Type Register (Host mode only) (HOST_TXTYPE) www.ti.com Registers The Type Register (Host mode only) (HOST_TYPE0) is shown in Figure 81 and described in Table 82 . Figure 81. Type Register (Host mode only) (HOST_TYPE0) 7 6 5 0 SPEED Reserved R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read [...]

4.68 NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) 4.69 Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) Registers www.ti.com The NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) is shown in Figure 83 and described in Table 84 . Figure 83. NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) 7 5 4 0 Reserved EP0NAKLIMIT R-0 [...]

4.70 Receive Type Register (Host mode only) (HOST_RXTYPE) 4.71 Receive Interval Register (Host mode only) (HOST_RXINTERVAL) www.ti.com Registers The Receive Type Register (Host mode only) (HOST_RXTYPE) is shown in Figure 85 and described in Table 86 . Figure 85. Receive Type Register (Host mode only) (HOST_RXTYPE) 76543 0 SPEED PROT RENDPN R/W-0 R/[...]

4.72 Configuration Data Register (CONFIGDATA) Registers www.ti.com Table 87. Receive Interval Register (Host mode only) (HOST_RXINTERVAL) Field Descriptions Bit Field Value Description 7-0 POLINTVL_NAKLIMIT 0-FFh For Interrupt and Isochronous transfers, defines the polling interval for the currently-selected transmit endpoint For Bulk endpoints, th[...]

www.ti.com Registers SPRUGH3 – November 2008 Universal Serial Bus (USB) Controller 133 Submit Documentation Feedback[...]

4.73 Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) Registers www.ti.com The Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) is shown in Figure 88 and described in Table 89 . Figure 88. Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) 31 0 DATA R/W-0 LEGEND: R/W = Read/Write; - n = value after reset Table 89. Transmit [...]

4.74 Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) 4.75 Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) www.ti.com Registers The Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) is shown in Figure 89 and described in Table 90 . Figure 89. Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) 31 0 DATA R/W-0 LEGEND[...]

4.76 Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) 4.77 Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) Registers www.ti.com The Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) is shown in Figure 91 and described in Table 92 . Figure 91. Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) 31 0 DATA R/W-0 LEGEND[...]

4.78 OTG Device Control Register (DEVCTL) www.ti.com Registers The OTG Device Control Register (DEVCTL) is shown in Figure 93 and described in Table 94 . Figure 93. OTG Device Control Register (DEVCTL) 76543210 BDEVICE FSDEV LSDEV VBUS HOSTMODE HOSTREQ SESSION R-0 R-0 R-0 R-0 R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value afte[...]

4.79 Transmit Endpoint FIFO Size (TXFIFOSZ) 4.80 Receive Endpoint FIFO Size (RXFIFOSZ) Registers www.ti.com Section 2.5 describes dynamically setting endpoint FIFO sizes. The Transmit Endpoint FIFO Size (TXFIFOSZ) is shown in Figure 94 and described in Table 95 . Figure 94. Transmit Endpoint FIFO Size (TXFIFOSZ) 7 5 4 3 0 Reserved DPB SZ R-0 R/W-0 [...]

4.81 Transmit Endpoint FIFO Address (TXFIFOADDR) 4.82 Receive Endpoint FIFO Address (RXFIFOADDR) www.ti.com Registers Section 2.5 describes dynamically setting endpoint FIFO sizes. The Transmit Endpoint FIFO Address (TXFIFOADDR) is shown in Figure 96 and described in Table 97 . Figure 96. Transmit Endpoint FIFO Address (TXFIFOADDR) 15 13 12 0 Reser[...]

4.83 Transmit Function Address (TXFUNCADDR) 4.84 Transmit Hub Address (TXHUBADDR) 4.85 Transmit Hub Port (TXHUBPORT) Registers www.ti.com The Transmit Function Address (TXFUNCADDR) is shown in Figure 98 and described in Table 99 . Figure 98. Transmit Function Address (TXFUNCADDR) 7 6 0 Reserved FUNCADDR R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read [...]

4.86 Receive Function Address (RXFUNCADDR) 4.87 Receive Hub Address (RXHUBADDR) 4.88 Receive Hub Port (RXHUBPORT) www.ti.com Registers The Receive Function Address (RXFUNCADDR) is shown in Figure 101 and described in Table 102 . Figure 101. Receive Function Address (RXFUNCADDR) 7 6 0 Reserved FUNCADDR R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read on[...]

Registers www.ti.com Universal Serial Bus (USB) Controller 142 SPRUGH3 – November 2008 Submit Documentation Feedback[...]

Appendix A Revision History www.ti.com Appendix A Table A-1 lists the changes made since the previous version of this document. Table A-1. Document Revision History Reference Additions/Modifications/Deletions Section 1 Added note. Section 1.3 Added section. Section 2.4 Changed section. Section 3.1.1 Renamed section. Section 3.1.2.1 Renamed section.[...]

IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders[...]