Texas Instruments TMS320DM643X DMP инструкция обслуживания

TMS320DM643x DMP Universal Asynchronous Receiver/Transmitter (UART) User's Guide Literature Number: SPRU997C December 2009[...]

2 SPRU997C – December 2009 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated[...]

Preface ....................................................................................................................................... 6 1 Introduction ........................................................................................................................ 7 1.1 Purpose of the Peripheral ....................................[...]

www.ti.com List of Figures 1 UART Block Diagram ....................................................................................................... 9 2 UART Clock Generation Diagram ....................................................................................... 10 3 Relationships Between Data Bit, BCLK, and UART Input Clock ............[...]

www.ti.com List of Tables 1 UART Supported Features/Characteristics by Instance ............................................................... 8 2 Baud Rate Examples for 27 MHz UART Input Clock ................................................................. 11 3 UART Signal Descriptions ...........................................................[...]

Preface SPRU997C – December 2009 Read This First About This Manual This document describes the universal asynchronous receiver/transmitter (UART) peripheral in the TMS320DM643x Digital Media Processor (DMP) . Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the [...]

User's Guide SPRU997C – December 2009 Universal Asynchronous Receiver/Transmitter (UART) 1 Introduction This document describes the universal asynchronous receiver/transmitter (UART) peripheral in the TMS320DM643x Digital Media Processor (DMP) . 1.1 Purpose of the Peripheral The UART peripheral is based on the industry standard TL16C550 asyn[...]

Introduction www.ti.com Table 1 summarizes the capabilities supported on the UART. Note that the number of UARTs and their supported features vary on each device, see the device-specific data manual for more details. Table 1. UART Supported Features/Characteristics by Instance Feature Support 5, 6, 7 or 8-bit characters Supported Even, odd, or no P[...]

8 Receiver Buf fer Register Divisor Latch (LS) Divisor Latch (MS) Baud Generator Receiver FIFO Line Status Register T ransmitter Holding Register Modem Control Register Line Control Register T ransmitter FIFO Interrupt Enable Register Interrupt Identification Register FIFO Control Register Interrupt/ Event Control Logic S e l e c t Data Bus Buf fer[...]

Divisor + UART input clock frequency Desired baud rate 16 Processor generator Clock DLH:DLL UAR T input clock DSP input clock UAR T Receiver timing and control T ransmitter timing and control Baud generator BCLK Other logic Peripheral Architecture www.ti.com 2 Peripheral Architecture 2.1 Clock Generation and Control The UART bit clock is sourced fr[...]

BCLK Each bit lasts 16 BCLK cycles. When receiving, the UAR T samples the bit in the 8th cycle. D0 TX, RX D1 D2 P ARITY D7 D6 D5 STOP2 ST OP1 D1 D4 D2 D3 ST AR T D0 TX, RX UAR T input clock n UAR T input clock cycles, where n = divisor in DLH:DLL n BCLK www.ti.com Peripheral Architecture Figure 3. Relationships Between Data Bit, BCLK, and UART Inpu[...]

Peripheral Architecture www.ti.com 2.2 Signal Descriptions The UARTs utilize a minimal number of signal connections to interface with external devices. The UART signal descriptions are included in Table 3 . Note that the number of UARTs and their supported features vary on each device, see the device-specific data manual for more details. Table 3. [...]

www.ti.com Peripheral Architecture 2.4.3 Data Format The UART transmits in the following format: 1 START bit + data bits (5, 6, 7, 8) + 1 PARITY bit (optional) + STOP bit (1, 1.5, 2) It transmits 1 START bit; 5, 6, 7, or 8 data bits, depending on the data width selection; 1 PARITY bit, if parity is selected; and 1, 1.5, or 2 STOP bits, depending on[...]

Peripheral Architecture www.ti.com 2.6 Operation 2.6.1 Transmission The UART transmitter section includes a transmitter hold register (THR) and a transmitter shift register (TSR). When the UART is in the FIFO mode, THR is a 16-byte FIFO. Transmitter section control is a function of the UART line control register (LCR). Based on the settings chosen [...]

www.ti.com Peripheral Architecture 2.6.3 FIFO Modes The following two modes can be used for servicing the receiver and transmitter FIFOs: • FIFO interrupt mode. The FIFO is enabled and the associated interrupts are enabled. Interrupts are sent to the CPU to indicate when specific events occur. • FIFO poll mode. The FIFO is enabled but the assoc[...]

rts Receiver FIFO D[7:0] UAR T Serial to Parallel Flow Control Transmitter FIFO Parallel to Serial Flow Control Parallel to Serial Flow Control Serial to Parallel Flow Control UAR T Transmitter FIFO Receiver FIFO D[7:0] DMP Of f-chip tx cts rx rx rts tx cts Peripheral Architecture www.ti.com 2.6.3.2 FIFO Poll Mode When the receiver FIFO is enabled [...]

RX R TS Start Start Start Stop Stop Bits N Bits N+1 Start Stop TX CTS Start Stop Bits0−7 Start Stop Bits 0−7 Start Stop Bits 0−7 www.ti.com Peripheral Architecture 2.6.4.1 RTS Behavior RTS data flow control originates in the receiver block (see Figure 1 ). When the receiver FIFO level reaches a trigger level of 1, 4, 8, or 14 (see Figure 6 ),[...]

Peripheral Architecture www.ti.com 2.7 Reset Considerations 2.7.1 Software Reset Considerations Two bits in the power and emulation management register (PWREMU_MGMT) control resetting the parts of the UART: • The UTRST bit controls resetting the transmitter only. If UTRST = 1, the transmitter is active; if UTRST = 0, the transmitter is in reset. [...]

UAR T interrupt request to CPU IER(ETBEI) IER(ERBI) T ransmitter holding register empty Receiver data ready THREINT RDRINT Overrun error IER(ELSI) R TOINT Conditions Enable bits UART interrupt requests Arbiter Parity error Framing error Break RLSINT Receiver time-out www.ti.com Peripheral Architecture Table 5. UART Interrupt Requests Descriptions U[...]

Peripheral Architecture www.ti.com 2.10 DMA Event Support In the FIFO mode, the UART generates the following two DMA events: • Receive event (URXEVT): The trigger level for the receiver FIFO (1, 4, 8, or 14 characters) is set with the RXFIFTL bit in the FIFO control register (FCR). Every time the trigger level is reached or a receiver time-out oc[...]

www.ti.com Registers 2.13 Exception Processing 2.13.1 Divisor Latch Not Programmed Since the processor reset signal has no effect on the divisor latch, the divisor latch will have an unknown value after power up. If the divisor latch is not programmed after power up, the baud clock (BCLK) will not operate and will instead be set to a constant logic[...]

Registers www.ti.com 3.1 Receiver Buffer Register (RBR) The receiver buffer register (RBR) is shown in Figure 9 and described in Table 7 . The UART receiver section consists of a receiver shift register (RSR) and a receiver buffer register (RBR). When the UART is in the FIFO mode, RBR is a 16-byte FIFO. Timing is supplied by the 16x receiver clock.[...]

www.ti.com Registers 3.2 Transmitter Holding Register (THR) The transmitter holding register (THR) is shown in Figure 10 and described in Table 8 . The UART transmitter section consists of a transmitter hold register (THR) and a transmitter shift register (TSR). When the UART is in the FIFO mode, THR is a 16-byte FIFO. Transmitter section control i[...]

Registers www.ti.com 3.3 Interrupt Enable Register (IER) The interrupt enable register (IER) is used to individually enable or disable each type of interrupt request that can be generated by the UART. Each interrupt request that is enabled in IER is forwarded to the CPU. IER is shown in Figure 11 and described in Table 9 . Access considerations: IE[...]

www.ti.com Registers 3.4 Interrupt Identification Register (IIR) The interrupt identification register (IIR) is a read-only register at the same address as the FIFO control register (FCR), which is a write-only register. When an interrupt is generated and enabled in the interrupt enable register (IER), IIR indicates that an interrupt is pending in [...]

Registers www.ti.com Table 11. Interrupt Identification and Interrupt Clearing Information IIR Bits Priority Level 3 2 1 0 Interrupt Type Interrupt Source Event That Clears Interrupt None 0 0 0 1 None None None 1 0 1 1 0 Receiver line status Overrun error, parity error, framing For an overrun error, reading the line error, or break is detected. sta[...]

www.ti.com Registers Figure 13. FIFO Control Register (FCR) 31 16 Reserved R-0 15 8 Reserved R-0 76543210 RXFIFTL Reserved DMAMODE1 (1) TXCLR RXCLR FIFOEN W-0 R-0 W-0 W1C-0 W1C-0 W-0 LEGEND: R = Read only; W = Write only; W1C = Write 1 to clear (writing 0 has no effect); - n = value after reset (1) Always write 1 to the DMAMODE1 bit. After a hardwa[...]

Registers www.ti.com 3.6 Line Control Register (LCR) The line control register (LCR) is shown in Figure 14 and described in Table 13 . The system programmer controls the format of the asynchronous data communication exchange by using LCR. In addition, the programmer can retrieve, inspect, and modify the content of LCR; this eliminates the need for [...]

www.ti.com Registers Table 13. Line Control Register (LCR) Field Descriptions (continued) Bit Field Value Description 2 STB Number of STOP bits generated. STB specifies 1, 1.5, or 2 STOP bits in each transmitted character. When STB = 1, the WLS bit determines the number of STOP bits. The receiver clocks only the first STOP bit, regardless of the nu[...]

Registers www.ti.com 3.7 Modem Control Register (MCR) The modem control register (MCR) is shown in Figure 15 and described in Table 16 . The modem control register provides the ability to enable/disable the autoflow functions, and enable/disable the loopback function for diagnostic purposes. Figure 15. Modem Control Register (MCR) 31 16 Reserved R-[...]

www.ti.com Registers 3.8 Line Status Register (LSR) The line status register (LSR) is shown in Figure 16 and described in Table 17 . LSR provides information to the CPU concerning the status of data transfers. LSR is intended for read operations only; do not write to this register. Bits 1 through 4 record the error conditions that produce a receive[...]

Registers www.ti.com Table 17. Line Status Register (LSR) Field Descriptions (continued) Bit Field Value Description 4 BI Break indicator. The BI bit is set whenever the receive data input (RX) was held low for longer than a full-word transmission time. A full-word transmission time is defined as the total time to transmit the START, data, PARITY, [...]

www.ti.com Registers Table 17. Line Status Register (LSR) Field Descriptions (continued) Bit Field Value Description 0 DR Data-ready (DR) indicator for the receiver. If the DR bit is set and the corresponding interrupt enable bit is set (ERBI = 1 in IER), an interrupt request is generated. In non-FIFO mode: 0 Data is not ready, or the DR bit was cl[...]

Registers www.ti.com Figure 17. Divisor LSB Latch (DLL) 31 16 Reserved R-0 15 8 7 0 Reserved DLL R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 18. Divisor LSB Latch (DLL) Field Descriptions Bit Field Value Description 31-8 Reserved 0 Reserved 7-0 DLL 0-Fh The 8 least-significant bits (LSBs) of the 16-bit divisor f[...]

www.ti.com Registers 3.10 Peripheral Identification Registers (PID1 and PID2) The peripheral identification registers (PID) contain identification data (class, revision, and type) for the peripheral. PID1 is shown in Figure 19 and described in Table 20 . PID2 is shown in Figure 20 and described in Table 21 . Figure 19. Peripheral Identification Reg[...]

Registers www.ti.com 3.11 Power and Emulation Management Register (PWREMU_MGMT) The power and emulation management register (PWREMU_MGMT) is shown in Figure 21 and described in Table 22 . Figure 21. Power and Emulation Management Register (PWREMU_MGMT) 31 16 Reserved R-0 15 14 13 12 1 0 Rsvd UTRST URRST Reserved FREE R/W-0 R/W-0 R/W-0 R-0 R/W-0 LEG[...]

www.ti.com Appendix A Revision History Table 23 lists the changes made since the previous version of this document. Table 23. Document Revision History Reference Additions/Modifications/Deletions Section 2.1 Changed first paragraph. 37 SPRU997C – December 2009 Revision History Submit Documentation Feedback Copyright © 2009, Texas Instruments Inc[...]

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