IBM uPD78081 manual

µ PD78081 µ PD78081(A) µ PD78082 µ PD78082(A) µ PD78P083 µ PD78P083(A) µ PD78P081(A2) µ PD78083 SUBSERIES 8-BIT SINGLE-CHIP MICROCONTROLLER Document No. U12176EJ2V0UM00 (2nd edition) (O. D. No. IEU-886) Date Published May 1997 N Printed in Japan © 1992 1994[...]

NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Envi[...]

FIP, IEBus, and QTOP are trademarks of NEC Corporation. MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT and PC DOS are trademarks of International Business Machines Corporation. HP9000 Series 300, HP9000 Series 700, and HP-UX are trademarks of Hew[...]

The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. The information in this document is subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes n[...]

NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC El[...]

Major Revision in This Edition Page Description Throughout The following products have been already developed µ PD78081CU- ××× , 78081GB- ××× -3B4, 78082CU- ××× , 78082GB- ××× -3B4, 78P083CU, 78P083DU, 78P083GB-3B4 The following products have been added µ PD78081GB- ××× -3BS-MTX, 78082GB- ××× -3BS-MTX, 78P083GB-3BS-MTX, 78081GB([...]

PREFACE Readers This manual has been prepared for user engineers who want to understand the functions of the µ PD78083 subseries and design and develop its application systems and programs. Caution In the µ PD78083 Subseries, the µ PD78P083DU is not designed to maintain the reliability required for use in customers’ mass-produced equipment. Pl[...]

To know application examples of the functions provided in the µ PD78083 Subseries: → Refer to Application Note separately provided. Legend Data representation weight : High digits on the left and low digits on the right Active low representations : ××× (line over the pin and signal names) Note : Description of note in the text. Caution : Info[...]

Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Related documents for µ PD78054 subseries Document name Document No. Japanese English µ PD78083 Subseries User’s Manual U12176J This Manual µ PD78081, 78082 Data Sheet U11415J U11415E µ [...]

Development Tool Documents (User’s Manuals) Document name Document No. Japanese English RA78K Series Assembler Package Operation EEU-809 EEU-1399 Language EEU-815 EEU-1404 RA78K Series Structured Assembler Preprocessor EEU-817 EEU-1402 RA78K0 Assembler Package Structured assembly language U11789J U11789E Assembly language U11801J U11801E Operatio[...]

Documents for Embedded Software (User’s Manual) Document name Document No. Japanese English 78K/0 Series Real-Time OS Basics U11537J — Installation U11536J — Technicals U11538J — OS for 78K/0 Series MX78K0 Basics EEU-5010 — Fuzzy Knowledge Data Creation Tool EEU-829 EEU-1438 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support S[...]

– i – CONTENTS CHAPTER 1 OUTLINE ..................................................................................................................... 1 1.1 Features ............................................................................................................................. 1 1.2 Applications ...................................[...]

– ii – 3.2.3 Special Function Register (SFR) ......................................................................................... 37 3.3 Instruction Address Addressing ..................................................................................... 40 3.3.1 Relative Addressing ..........................................................[...]

– iii – 6.4 8-Bit Timer/Event Counters 5 and 6 Operations ............................................................ 90 6.4.1 Interval timer operations ...................................................................................................... 90 6.4.2 External event counter operation ...............................................[...]

– iv – 12.4 Interrupt Servicing Operations ........................................................................................ 181 12.4.1 Non-maskable interrupt request acknowledge operation .................................................... 181 12.4.2 Maskable interrupt request acknowledge operation .....................................[...]

– v – A.5 System-Upgrade Method from Other In-Circuit Emulators to 78K/0 Series In-Circuit Emulator ............................................................................................................ 240 APPENDIX B EMBEDDED SOFTW ARE .......................................................................................... 243 B.1 Real[...]

– vi – FIGURE (1/4) Fig. No. Title Page 2-1 Pin Input/Output Circuit of List ............................................................................................ 23 3-1 Memory Map ( µ PD78081) .................................................................................................. 25 3-2 Memory Map ( µ PD78082) .............[...]

– vii – FIGURE (2/4) Fig. No. Title Page 6-10 8-Bit T imer Mode Control Register Setting for External Event Counter Operation ............. 93 6-1 1 External Event Counter Operation T imings (with Rising Edge Specification) .................... 93 6-12 8-Bit T imer Mode Control Register Settings for Square-Wave Output Operation .............. 9[...]

– viii – FIGURE (3/4) Fig. No. Title Page 1 1-6 Baud Rate Generator Control Register Format (2/2) ......................................................... 145 1 1-7 Asynchronous Serial Interface T ransmit/Receive Data Format .......................................... 157 1 1-8 Asynchronous Serial Interface T ransmission Completion Interrupt Re[...]

– ix – FIGURE (4/4) Fig. No. Title Page 15-6 PROM Read T iming ........................................................................................................... 213 A-1 Development T ool Configuration ........................................................................................ 232 A-2 EV -9200G-44 Drawing (For Reference On[...]

– x – T ABLE (1/2) T able. No. Title Page 1-1 Differences between the µ PD78081, 78082 and 78P083, the µ PD78081(A), 78082(A) and 78P083(A), and the µ PD78081(A2) ............................................................................ 13 2-1 T ype of Input/Output Circuit of Each Pin ......................................................[...]

– xi – T ABLE (2/2) T able. No. Title Page 12-1 Interrupt Source List ........................................................................................................... 172 12-2 V arious Flags Corresponding to Interrupt Request Sources .............................................. 175 12-3 T imes from Maskable Interrupt Request Genera[...]

– xii – [MEMO][...]

1 CHAPTER 1 OUTLINE CHAPTER 1 OUTLINE 1.1 Features On-chip ROM and RAM Note The capacities of internal PROM and internal high-speed RAM can be changed by means of the memory size switching register (IMS). Instruction execution time changeable from high speed (0.4 µ s: In main system clock 5.0 MHz operation) to low speed (12.8 µ s: In main system [...]

2 CHAPTER 1 OUTLINE 1.2 Applications µ PD78081, 78082, 78P083: Airbags, CRT displays, keyboards, air conditioners, hot water dispensers, boilers, fan heaters, dashboards, etc. µ PD78081(A), 78082(A), 78P083(A), 78081(A2): Automobile electrical control devices, gas detector cutoff devices, various safety devices, etc. 1.3 Ordering Information Part[...]

3 CHAPTER 1 OUTLINE 1.4 Quality Grade Part number Package Quality grade µ PD78081CU- ××× 42-pin plastic shrink DIP (600 mil) Standard µ PD78081GB- ××× -3B4 44-pin plastic QFP (10 × 10 mm) Standard µ PD78081GB- ××× -3BS-MTX 44-pin plastic QFP (10 × 10 mm) Standard µ PD78082CU- ××× 42-pin plastic shrink DIP (600 mil) Standard µ PD7[...]

4 CHAPTER 1 OUTLINE 1.5 Pin Configuration (Top View) (1) Normal operating mode 42-pin plastic shrink DIP (600 mil) µ PD78081CU- ××× , 78082CU- ××× , 78P083CU, 78P083CU(A) 42-pin ceramic shrink DIP (with window) (600 mil) µ PD78P083DU 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 V SS P54 P53 P52 P51 P50 P100/TI5/TO5 P101/TI6/TO6 P70[...]

5 CHAPTER 1 OUTLINE • 44-pin plastic QFP (10 × 10 mm) µ PD78081GB- ××× -3B4, 78081GB- ××× -3BS-MTX µ PD78082GB- ××× -3B4, 78082GB- ××× -3BS-MTX µ PD78P083GB-3B4, 78P083GB-3BS-MTX µ PD78081GB(A)- ××× -3B4, 78082GB(A)- ××× -3B4 µ PD78P083GB(A)-3B4, 78P083GB(A)-3BS-MTX Note µ PD78P081GB(A2)- ××× -3B4 Note Under developmen[...]

6 CHAPTER 1 OUTLINE Pin Identifications ANI0 to ANI7 : Analog Input P100, P101 : Port 10 ASCK : Asynchronous Serial Clock PCL : Programmable Clock AV DD : Analog Power Supply RESET : Reset AV REF : Analog Reference Voltage RxD : Receive Data AV SS : Analog Ground SCK2 : Serial Clock BUZ : Buzzer Clock SI2 : Serial Input IC : Internally Connected SO[...]

7 CHAPTER 1 OUTLINE (2) PROM programming mode • 42-pin plastic shrink DIP (600 mil) µ PD78P083CU, 78P083CU(A) • 42-pin ceramic shrink DIP (with window) (600 mil) µ PD78P083DU Cautions 1. (L) : Individually connect to V SS via a pull-down resistor. 2. V SS : Connect to the ground. 3. RESET : Set to the low level. 4. Open : Do not connect anyth[...]

8 CHAPTER 1 OUTLINE Note Under development Cautions 1. (L) : Connect individually to V SS via a pull-down resistor. 2. V SS : Connect to the ground. 3. RESET : Set to the low level. 4. Open : Do not connect anything. A0 to A14 : Address Bus RESET : Reset CE : Chip Enable V DD : Power Supply D0 to D7 : Data Bus V PP : Programming Power Supply OE : O[...]

9 CHAPTER 1 OUTLINE 1.6 78K/0 Series Development The following shows the 78K/0 Series products development. Subseries names are shown inside frames. Note Under planning 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin 100-pin 100-pin 80-pin 80-pin 100-pin 100-pin 100-pin µPD780308Y µP[...]

10 CHAPTER 1 OUTLINE The following table shows the differences among subseries functions. Function ROM Timer 8-bit 10-bit 8-bit Serial interface I/O External Subseries name capacity 8-bit 16-bit Watch WDT A/D A/D D/A expansion Control µ PD78075B 32K to 40K 4 ch 1 ch 1 ch 1 ch 8 ch — 2 ch 3 ch (UART: 1 ch) 88 1.8 V Available µ PD78078 48K to 60K[...]

11 CHAPTER 1 OUTLINE 1.7 Block Diagram Remarks 1. The internal ROM and high-speed RAM capacities depend on the product. 2. Pin connection in parentheses is intended for the µ PD78P083. P100/TI5/TO5 P101/TI6/TO6 SI2/R X D/P70 SO2/T X D/P71 SCK2/ASCK/P72 ANI0/P10- ANI7/P17 AV DD AV SS AV REF INTP1/P01- INTP3/P03 BUZ/P36 PCL/P35 PORT 0 PORT 1 PORT 3 [...]

12 CHAPTER 1 OUTLINE 1.8 Outline of Function Part Number µ PD78081 µ PD78082 µ PD78083 Item Internal memory ROM Mask ROM PROM 8 Kbytes 16 Kbytes 24 Kbytes Note High-speed RAM 256 bytes 384 bytes 512 bytes Note Memory space 64 Kbytes General register 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Instruction cycle Instruction execution[...]

13 CHAPTER 1 OUTLINE 1.9 Differences between the µ PD78081, 78082 and 78P083, the µ PD78081(A), 78082(A) and 78P083(A), and the µ PD78081(A2) Table 1-1 Differences between the µ PD78081, 78082 and 78P083, the µ PD78081(A), 78082(A) and 78P083(A), and the µ PD78081(A2) Part Number µ PD78081 µ PD78081(A) µ PD78081(A2) µ PD78082 µ PD78082(A[...]

14 CHAPTER 1 OUTLINE [MEMO][...]

15 CHAPTER 2 PIN FUNCTION CHAPTER 2 PIN FUNCTION 2.1 Pin Function List 2.1.1 Normal operating mode pins (1) Port pins Note When P10/ANI0-P17/ANI7 pins are used as the analog inputs for the A/D converter, set the port 1 to the input mode. The on-chip pull-up resistor is automatically disabled. Pin Name Input/Output Function After Reset Alternate Fun[...]

16 CHAPTER 2 PIN FUNCTION Pin Name Input/Output Function After Reset Alternate Function INTP1 Input External interrupt request input by which the active edge Input P01 INTP2 (rising edge, falling edge, or both rising and falling edges) P02 INTP3 can be specified. P03 SI2 Input Serial interface serial data input. Input P70/RxD SO2 Output Serial inte[...]

17 CHAPTER 2 PIN FUNCTION 2.2 Description of Pin Functions 2.2.1 P00 to P03 (Port 0) These are 4-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input. The following operating modes can be specified bit-wise. (1) Port mode P00 functions as input-only port and P01 to P03 function as input[...]

18 CHAPTER 2 PIN FUNCTION 2.2.3 P30 to P37 (Port 3) These are 8-bit input/output ports. Beside serving as input/output ports, they function as clock output and buzzer output. The following operating modes can be specified bit-wise. (1) Port mode These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output port[...]

19 CHAPTER 2 PIN FUNCTION 2.2.5 P70 to P72 (Port 7) This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/ output and clock input/output functions. The following operating modes can be specified bit-wise. (1) Port mode Port 7 functions as a 3-bit input/output port. Bit-wise specif[...]

20 CHAPTER 2 PIN FUNCTION 2.2.7 AV REF A/D converter reference voltage input pin. When A/D converter is not used, connect this pin to V SS . 2.2.8 AV DD Analog power supply pin of A/D converter. Always use the same voltage as that of the V DD pin even when A/D converter is not used. 2.2.9 AV SS This is a ground voltage pin of A/D converter. Always [...]

21 CHAPTER 2 PIN FUNCTION 2.2.15 IC (Mask ROM version only) The IC (Internally Connected) pin is provided to set the test mode to check the µ PD78083 Subseries at delivery. Connect it directly to the V SS with the shortest possible wire in the normal operating mode. When a voltage difference is produced between the IC pin and V SS pin because the [...]

22 CHAPTER 2 PIN FUNCTION Pin Name Input/Output Input/Output Recommended Connection for Unused Pins Circuit Type P00 2 Input Connect to V SS . P01/INTP1 8-A Input/Output Independently connect to V SS via a resistor. P02/INTP2 P03/INTP3 P10/ANI0-P17/ANI7 11 Input/Output Independently connect to V DD or V SS via P30-P32 5-A a resistor. P33, P34 8-A P[...]

23 CHAPTER 2 PIN FUNCTION Figure 2-1. Pin Input/Output Circuit of List IN pull-up enable V DD P-ch IN/OUT input enable output disable data V DD P-ch N-ch Type 2 Type 5-A Schmitt-Triggered Input with Hysteresis Characteristics Type 11 Type 8-A pull-up enable V DD P-ch IN/OUT output disable data V DD P-ch N-ch pull-up enable V DD P-ch IN/OUT output d[...]

24 CHAPTER 2 PIN FUNCTION [MEMO][...]

25 CHAPTER 3 CPU ARCHITECTURE CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Spaces Figures 3-1 to 3-3 shows memory maps. Figure 3-1. Memory Map ( µ PD78081) Data memory space General Registers 32 × 8 bits Internal ROM 8192 × 8 bits CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Unusable Program memory space Internal High-s[...]

26 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map ( µ PD78082) Data memory space General Registers 32 × 8 bits Internal ROM 16384 × 8 bits CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Unusable Program memory space Internal High-speed RAM 384 × 8 bits Special Function Registers (SFRs) 256 × 8 bits FF00H FEFFH[...]

27 CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map ( µ PD78P083) Data memory space General Registers 32 × 8 bits Internal PROM 24576 × 8 bits CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Unusable Program memory space Internal High-speed RAM 512 × 8 bits Special Function Registers (SFRs) 256 × 8 bits FF00H FEF[...]

28 CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory is mask ROM with a 8192 × 8-bit configuration in the µ PD78081, and a 16384 × 8-bit configuration in the µ PD78082, and PROM with a 24576 × 8-bit configuration in the µ PD78P083. The internal program memory space stores programs and table data. Norma[...]

29 CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory space The internal high speed RAM configuration is 256 × 8-bit in the µ PD78081, 384 × 8-bit in the µ PD78082 and 512 × 8-bit in the µ PD8P083. In this area, four banks of general registers, each bank consisting of eight 8-bit registers, are allocated in the 32-byte area FEE0H to FEFFH.[...]

30 CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Data Memory Addressing ( µ PD78081) General Registers 32 × 8 bits Internal ROM 8192 × 8 bits Unusable Internal High-speed RAM 256 × 8 bits Special Function Registers (SFRs) 256 × 8 bits SFR Addressing Register Addressing Short Direct Addressing Direct Addressing Register Indirect Addressing Based Addre[...]

31 CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Data Memory Addressing ( µ PD78082) General Registers 32 × 8 bits Internal ROM 16384 × 8 bits Unusable Internal High-speed RAM 384 × 8 bits Special Function Registers (SFRs) 256 × 8 bits SFR Addressing Register Addressing Short Direct Addressing Direct Addressing Register Indirect Addressing Based Addr[...]

32 CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Data Memory Addressing ( µ PD78P083) General Registers 32 × 8 bits Internal PROM 24576 × 8 bits Unusable Internal High-speed RAM 512 × 8 bits Special Function Registers (SFRs) 256 × 8 bits SFR Addressing Register Addressing Short Direct Addressing Direct Addressing Register Indirect Addressing Based Ad[...]

33 CHAPTER 3 CPU ARCHITECTURE 70 IE Z RBS1 AC RBS0 0 ISP CY PC 15 0 3.2 Processor Registers The µ PD78083 subseries units incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter, a program status word and[...]

34 CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When IE = 0, all interrupts except the non-maskable interrupt are disabled (DI status). When IE = 1, interrupts are enabled (EI status). At this time, acknowledgment of interrupts is controlled with an inservice p[...]

35 CHAPTER 3 CPU ARCHITECTURE RETI and RETB Instruction PSW PC15-PC8 PC15-PC8 PC7-PC0 Register Pair Lower SP SP + 2 SP Register Pair Upper RET Instruction POP rp Instruction SP + 1 PC7-PC0 SP SP + 2 SP SP + 1 SP + 2 SP SP + 1 SP SP + 3 Interrupt and BRK Instruction PSW PC15-PC8 PC15-PC8 PC7-PC0 Register Pair Lower SP SP _ 2 SP _ 2 Register Pair Upp[...]

36 CHAPTER 3 CPU ARCHITECTURE BANK0 BANK1 BANK2 BANK3 FEFFH FEF8H FEE0H HL DE BC AX H 15 0 7 0 L D E B C A X 16-Bit Processing 8-Bit Processing FEF0H FEE8H BANK0 BANK1 BANK2 BANK3 FEFFH FEF8H FEE0H RP3 RP2 RP1 RP0 R7 15 0 7 0 R6 R5 R4 R3 R2 R1 R0 16-Bit Processing 8-Bit Processing FEF0H FEE8H 3.2.2 General registers A general register is mapped at [...]

37 CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special Function Register (SFR) Unlike a general register, each special-function register has special functions. It is allocated in the FF00H to FFFFH area. The special-function register can be manipulated like the general register, with the operation, transfer and bit manipulation instructions. Manipulatable bit[...]

38 CHAPTER 3 CPU ARCHITECTURE Address Special-Function Register (SFR) Name Symbol R/W After Reset FF00H Port0 P0 R/W √√ — 00H FF01H Port1 P1 √√ — FF03H Port3 P3 √√ — FF05H Port5 P5 √√ — FF07H Port7 P7 √√ — FF0AH Port10 P10 √√ — FF1FH A/D conversion result register ADCR R √√ — Undefined FF20H Port mode regis[...]

39 CHAPTER 3 CPU ARCHITECTURE Address Special-Function Register (SFR) Name Symbol R/W After Reset FFEAH Priority order specify flag register 1L PR1L R/W √√ — FFH FFECH External interrupt mode register 0 INTM0 — √ — 00H FFEDH External interrupt mode register 1 INTM1 — √ — FFF0H Memory size switching register IMS — √ — (Note) [...]

40 CHAPTER 3 CPU ARCHITECTURE 15 0 PC + 15 0 876 S 15 0 PC α jdisp8 When S = 0, all bits of α are 0. When S = 1, all bits of α are 1. PC indicates the start address of the instruction after the BR instruction. ... 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents. The contents of PC are norm[...]

41 CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. The CALL !addr16 and BR !addr16 instruction can branch in the entire memory spa[...]

42 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. Before the CALLT [addr5] instruction is executed, table indirect addressin[...]

43 CHAPTER 3 CPU ARCHITECTURE 70 rp 07 AX 15 0 PC 87 3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration][...]

44 CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register which functions as an accumulator (A and AX) in the general register is automatically (illi[...]

45 CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] This addressing accesses a general register as an operand. The general register accessed is specified by the register bank select flags (RBS0 and RBS1) and register specify code (Rn or RPn) in an instruction code. Register addressing is carried out when an instruction with the follo[...]

46 CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] This addressing directly addresses the memory indicated by the immediate data in an instruction word. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP cod[...]

47 CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space to which this address is applied is a 256-byte space of addresses FE20H through FF1FH. An internal high-speed RAM and a special-function register (SFR) a[...]

48 CHAPTER 3 CPU ARCHITECTURE 15 0 Short Direct Memory Effective Address 1 111111 87 0 7 OP code saddr-offset α [Description example] MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H Operation code 0 0 0 1 0 0 0 1 OP code 0 0 1 1 0 0 0 0 30H (saddr-offset) 0 1 0 1 0 0 0 0 50H (immediate data) [Illustration] When 8-bit immedi[...]

49 CHAPTER 3 CPU ARCHITECTURE 15 0 SFR Effective Address 1 111111 87 0 7 OP code sfr-offset 1 3.4.5 Special-Function Register (SFR) addressing [Function] The memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH[...]

50 CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] This addressing addresses the memory with the contents of a register pair specified as an operand. The register pair to be accessed is specified by the register bank select flags (RBS0 and RBS1) and register pair specify code in an instruction code. This addressing can be c[...]

51 CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] This addressing addresses the memory by adding 8-bit immediate data to the contents of the HL register pair which is used as a base register and by using the result of the addition. The HL register pair to be accessed is in the register bank specified by the register bank select flags [...]

52 CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] This addressing addresses the memory by adding the contents of the HL register, which is used as a base register, to the contents of the B or C register specified in the instruction word, and by using the result of the addition. The HL, B, and C registers to be accessed are reg[...]

53 CHAPTER 4 PORT FUNCTIONS CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The µ PD78083 Subseries units incorporate an input port and thirty-two input/output ports. Figure 4-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. Besides port functions, the port[...]

54 CHAPTER 4 PORT FUNCTIONS Pin Name Input/Output Function Dual-Function Pin P00 Input Port 0 Input only — P01 Input/output 4-bit input/output port Input/output is specifiable bit-wise. When INTP1 P02 used as the input port, it is possible to connect INTP2 P03 a pull-up resistor by software. INTP3 P10-P17 Input/output Port 1 ANI0-ANI7 8-bit input[...]

55 CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration A port consists of the following hardware: Table 4-2. Port Configuration Item Configuration Control register Port mode register (PMm: m = 0, 1, 3, 5, 7, 10) Pull-up resistor option register (PUOH, PUOL) Port Total: 33 ports (1 input, 32 inputs/outputs) Pull-up resistor Total: 32 (software specifiab[...]

56 CHAPTER 4 PORT FUNCTIONS Figure 4-2. P00 Block Diagram Figure 4-3. P01 to P03 Block Diagram PUO : Pull-up resistor option register PM : Port mode register RD : Port 0 read signal WR : Port 0 write signal P00 RD Internal bus P-ch WR PM WR PORT RD WR PUO V DD P01/INTP1 P03/INTP3 Selector PUO0 Output Latch (P01 to P03) PM01-PM03 Internal bus[...]

57 CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 Port 1 is an 8-bit input/output port with output latch. It can specify the input mode/output mode in 1-bit units with a port mode register 1 (PM1). When P10 to P17 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL). Du[...]

58 CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 3 Port 3 is an 8-bit input/output port with output latch. P30 to P37 pins can specify the input mode/output mode in 1-bit units with the port mode register 3 (PM3). When P30 to P37 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option regist[...]

59 CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 5 Port 5 is an 8-bit input/output port with output latch. P50 to P57 pins can specify the input mode/output mode in 1-bit units with the port mode register 5 (PM5). When P50 to P57 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option regist[...]

60 CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 7 This is a 3-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 7 (PM7). When pins P70 to P72 are used as input port pins, an on-chip pull-up resistor can be used as a 3-bit unit by means of pull-up resistor option register L (PUOL). Dual[...]

61 CHAPTER 4 PORT FUNCTIONS Figure 4-8. P71 and P72 Block Diagram PUO : Pull-up resistor option register PM : Port mode register RD : Port 7 read signal WR : Port 7 write signal P-ch WR PM WR PORT RD WR PUO V DD Selector PUO7 Output Latch (P71 and P72) PM71, PM72 Internal bus Alternate Function P71/SO2/TxD, P72/SCK2/ASCK[...]

62 CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 10 This is an 2-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 10 (PM10). When pins P100 to P101 are used as input port pins, an on-chip pull-up resistor can be used as an 2-bit unit by means of pull-up resistor option register H (PUOH[...]

63 CHAPTER 4 PORT FUNCTIONS 4.3 Port Function Control Registers The following two types of registers control the ports. • Port mode registers (PM0, PM1, PM3, PM5, PM7, PM10) • Pull-up resistor option register (PUOH, PUOL) (1) Port mode registers (PM0, PM1, PM3, PM5, PM7, PM10) These registers are used to set port input/output in 1-bit units. PM[...]

64 CHAPTER 4 PORT FUNCTIONS Table 4-3. Port Mode Register and Output Latch Settings when Using Dual-Functions P01 to P03 INTP1 to INTP3 Input 1 × P10 to P17 Note ANI0 to ANI7 Input 1 × P35 PCL Output 0 0 P36 BUZ Output 0 0 P100 TI5 Input 1 × TO5 Output 0 0 P101 TI6 Input 1 × TO6 Output 0 0 Dual-functions Name P ×× PM ×× Input/Output Pin Nam[...]

65 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Port Mode Register Format PM0 PM1 1 1 PM03 PM02 PM01 1 76 54 3 21 0 Symbol PM3 PM5 FF20H FF21H FF23H FF25H FFH FFH FFH FFH R/W R/W R/W R/W Address After Reset R/W PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 PM7 FF27H FFH R/W 1 1 1 1 [...]

66 CHAPTER 4 PORT FUNCTIONS (2) Pull-up resistor option register (PUOH, PUOL) This register is used to set whether to use an internal pull-up resistor at each port or not. A pull-up resistor is internally used at bits which are set to the input mode at a port where on-chip pull-up resistor use has been specified with PUOH, PUOL. No on-chip pull-up [...]

67 CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the [...]

68 CHAPTER 4 PORT FUNCTIONS [MEMO][...]

69 CHAPTER 5 CLOCK GENERATOR CHAPTER 5 CLOCK GENERATOR 5.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following type of system clock oscillator is available. Main system clock oscillator This circuit oscillates at frequencies of 1 to 5.0 MHz. Oscillation can be stopped by[...]

70 CHAPTER 5 CLOCK GENERATOR Figure 5-1. Block Diagram of Clock Generator Main System Clock Oscillator X2 X1 STOP PCC2 PCC1 Internal Bus Standby Control Circuit 2 f XX 2 2 f XX 2 3 f XX 2 4 f XX Prescaler Clock to Peripheral Hardware Prescaler Oscillation Mode Selection Register f XX CPU Clock (f CPU ) Scaler Selector f X 2 f X MCS Processor Clock [...]

71 CHAPTER 5 CLOCK GENERATOR 5.3 Clock Generator Control Register The clock generator is controlled by the following two registers: • Processor clock control register (PCC) • Oscillation mode selection register (OSMS) (1) Processor clock control register (PCC) The PCC sets whether to use CPU clock selection and the ratio of division. The PCC is[...]

72 CHAPTER 5 CLOCK GENERATOR Write to OSMS (MCS 0) f XX Max. 2/f X Operating at f XX = f X /2 (MCS = 0) Operating at f XX = f X /2 (MCS = 0) MCS Main System Clock Scaler Control 0 1 Scaler used Scaler not used 00 0 0 OSMS FFF2H 76 543 2 Symbol 1 0 MCS 0 0 Address After Reset R/W 00H W 0 (2) Oscillation mode selection register (OSMS) This register s[...]

73 CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pi[...]

74 CHAPTER 5 CLOCK GENERATOR Figure 5-6. Examples of Oscillator with Bad Connection (1/2) (a) Wiring of connection circuits (b) Signal conductors intersect is too long with each other (c) Changing high current is too near a (d) Current flows through the grounding line signal conductor of the ocsillator (potential at points A, B, and C fluctuate) IC[...]

75 CHAPTER 5 CLOCK GENERATOR Figure 5-6. Examples of Oscillator with Bad Connection (2/2) (c) Signals are fetched 5.4.2 Scaler The scaler divides the main system clock oscillator output (f XX ) and generates various clocks. IC X2 X1[...]

76 CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode. • Main system clock f XX • CPU clock f CPU • Clock to peripheral hardware The following clock generator functions and operations are determined with the[...]

77 CHAPTER 5 CLOCK GENERATOR 5.6 Changing CPU Clock Settings 5.6.1 Time required for CPU clock switchover The CPU clock can be switched over by means of bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC). The actual switchover operation is not performed directly after writing to the PCC, but operation continues on the pre-swit[...]

78 CHAPTER 5 CLOCK GENERATOR 5.6.2 CPU clock switching procedure This section describes CPU clock switching procedure. Figure 5-7. CPU Clock Switching (1) The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released by setting the RESET signal to high level, main system clock starts oscillation. At th[...]

79 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 The timers incorporated into the µ PD78083 subseries are outlined below. (1) 8-bit timers/event counters 5 and 6 (TM5 and TM6) This can be used to serve as an interval timer, an external event counter, square wave output with any selected frequency PWM, et[...]

80 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 6.1 8-Bit Timer/Event Counters 5 and 6 Functions The 8-bit timer/event counters 5 and 6 (TM5 and TM6) have the following functions. • Interval timer • External event counter • Square-wave output • PWM output (1) 8-bit interval timer Interrupt requests are generated at the preset time intervals[...]

81 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 6-3. 8-Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges Minimum pulse width Maximum pulse width Resolution MCS [...]

82 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 6.2 8-Bit Timer/Event Counters 5 and 6 Configurations The 8-bit timer/event counters 5 and 6 consist of the following hardware. Table 6-4. 8-Bit Timer/Event Counters 5 and 6 Configurations Item Configuration Timer register 8 bits × 2 (TM5, TM6) Register Compare register: 8 bits × 2 (CR50, CR60) Time[...]

83 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Figure 6-2. Block Diagram of 8-Bit Timer/Event Counters 5 and 6 Output Control Circuit Note PM100 : Bit 0 of port mode register 10 (PM10) PM101 : Bit 1 of PM10 Remarks 1. The section in the broken line is an output control circuit. 2. n = 5, 6 RESET LVRn LVSn TMCn1 TMCn6 OVFn INTTMn TCEn INTTMn R S Q [...]

84 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (1) Compare registers 50 and 60 (CR50, CR60) These are 8-bit registers to compare the value set to CR50 to the 8-bit timer register 5 (TM5) count value, and the value set to CR60 to the 8-bit timer register 6 (TM6) count value, and, if they match, generate an interrupt request (INTTM5 and INTTM6, resp[...]

85 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Figure 6-3. Timer Clock Select Register 5 Format Note The timer output (PWM output) cannot be used in cases where the clock is being input from an external source. Caution When rewriting TCL5 to other data, stop the timer operation beforehand. Remarks 1. f XX : Main system clock frequency (f X or f X [...]

86 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (2) Timer clock select register 6 (TCL6) This register sets count clocks of 8-bit timer register 6. TCL6 is set with an 8-bit memory manipulation instruction. RESET input sets TCL6 to 00H. Figure 6-4. Timer Clock Select Register 6 Format Note When clock is input from the external, timer output (PWM ou[...]

87 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (3) 8-bit timer mode control register 5 (TMC5) This register enables/stops operation of 8-bit timer register 5, sets the operating mode of 8-bit timer register 5 and controls operation of 8-bit timer/event counter 5 output control circuit. It sets R-S type flip-flop (timer output F/F 1,2) setting/rese[...]

88 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (4) 8-bit timer mode control register 6 (TMC6) This register enables/stops operation of 8-bit timer register 6, sets the operating mode of 8-bit timer register 6 and controls operation of 8-bit timer/event counter 6 output control circuit. It sets R-S type flip-flop (timer output F/F 1,2) setting/rese[...]

89 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 (5) Port mode register 10 (PM10) This register sets port 10 input/output in 1-bit units. When using the P100/TI5/TO5 and P101/TI6/TO6 pins for timer output, set PM100, PM101, and output latches of P100 and P101 to 0. PM10 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets P[...]

90 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 6.4 8-Bit Timer/Event Counters 5 and 6 Operations 6.4.1 Interval timer operations By setting the 8-bit timer mode control registers 5 and 6 (TMC5 and TMC6) as shown in Figure 6-8, it can be operated as an interval timer. The 8-bit timer/event counters 5 and 6 operate as interval timers which generate [...]

91 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Count Clock TMn Count Value INTTMn TCEn CRn0 TOn Interval Time Interval Time Interval Time Interrupt Request Acknowledge Interrupt Request Acknowledge N N N N Clear Count start Clear t 00 01 N 00 01 N 00 01 N Figure 6-9. Interval Timer Operation Timings Remarks 1. Interval time = (N + 1) × t : N = 00[...]

92 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Table 6-5. 8-Bit Timer/Event Counters 5 and 6 Interval Times Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 0000 TIn input cycle 2 8 × TIn input cycle TIn input edge cycle 0001 TIn input cycle 2 8 × TIn input cycle TIn input edge cycle Setting [...]

93 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 6.4.2 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI5/PI00/TO5 and TI6/ P101/TO6 pins with 8-bit timer registers 5 and 6 (TM5 and TM6). TM5 and TM6 are incremented each time the valid edge specified with the timer clock sele[...]

94 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 6.4.3 Square-wave output This makes the value set in advance in the 8-bit conveyor register 50, 60 (CR50, CR60) to be the interval. It operates as a square wave output at the desired frequency. The TO5/P100/TI5 or TO6/P101/TI6 pin output status is reversed at intervals of the count value preset to CR5[...]

95 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Table 6-6. 8-Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges Minimum Pulse Width Maximum Pulse Width Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 — 1/f X —2 8 × 1/f X — 1/f X (200 ns) (51.2 µ s) (200 ns) 1/f X 2 × 1/f X 2 8 × 1/f X 2 9 × 1/f X 1/f X 2 × 1/f X (200 [...]

96 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 6.4.4 PWM output operations Setting the 8-bit timer mode control registers 5 and 6 (TMC5 and TMC6) as shown in Figure 6-13 allows operation as PWM output. Pulses with the duty ratio determined by the values preset in the 8-bit compare registers 50 and 60 (CR50 and CR60) output from the TO5/P100/TI5 or[...]

97 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Figure 6-14. PWM Output Operation Timing (Active high setting) Remark n = 5, 6 Figure 6-15. PWM Output Operation Timings (CRn0 = 00H, active high setting) Remark n = 5, 6 Count Clock TMn Count Value CRn0 TCEn INTTMn TOn 01 02 FF 00 01 02 N N+1 N+2 N+3 00 OVFn MN N 00 Inactive Level CRn0 Changing (M ?[...]

98 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Figure 6-16. PWM Output Operation Timings (CRn0 = FFH, active high setting) Remark n = 5, 6 Count Clock TMn Count Value CRn0 TCEn INTTMn TOn 01 02 FF 00 01 02 FF 00 01 02 00 OVFn FF FF FF 00 Inactive Level Inactive Level Active Level Inactive Level Active Level[...]

99 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Figure 6-17. PWM Output Operation Timings (CRn0 changing, active high setting) Caution If CRn0 is changed during TMn operation, the value changed is not reflected until TMn overflows. Remark n = 5, 6 Count Clock TMn Count Value CRn0 TCEn INTTMn TOn OVFn Active Level Inactive Level 00 FF N+2 N+1 N 02 0[...]

100 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 6.5 Cautions on 8-Bit Timer/Event Counters 5 and 6 (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be gener- ated after timer start. This is because 8-bit timer registers 5 and 6 (TM5 and TM6) are started asynchronously with the[...]

101 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 Count Pulse CR50, CR60 TM5, TM6 Count Value X-1 X FFH 00H 01H 02H M N (3) Operation after compare register change during timer count operation If the values after the 8-bit compare registers 50 and 60 (CR50 and CR60) are changed are smaller than those of 8-bit timer registers 5 and 6 (TM5 and TM6), T[...]

102 CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 [MEMO][...]

103 CHAPTER 7 WATCHDOG TIMER CHAPTER 7 WATCHDOG TIMER 7.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (WDTM) (The watchdog timer and interval timer cannot be used at the same time[...]

104 CHAPTER 7 WATCHDOG TIMER (2) Interval timer mode Interrupt requests are generated at the preset time intervals. Table 7-2. Interval Times Interval Time MCS = 1 CS = 0 2 11 × 1/f XX 2 11 × 1/f X (410 µ s) 2 12 × 1/f X (819 µ s) 2 12 × 1/f XX 2 12 × 1/f X (819 µ s) 2 13 × 1/f X (1.64 ms) 2 13 × 1/f XX 2 13 × 1/f X (1.64 ms) 2 14 × 1/f[...]

105 CHAPTER 7 WATCHDOG TIMER Prescaler f XX 2 4 f XX 2 5 f XX 2 6 f XX 2 7 f XX 2 8 f XX 2 9 Selector Watchdog Timer Mode Register Internal Bus Internal Bus TCL22 TCL21 TCL20 f XX /2 3 f XX 2 11 Timer Clock Select Register 2 3 WDTM4 WDTM3 8-Bit Counter TMMK4 RUN TMIF4 INTWDT Maskable Interrupt Request INTWDT Non-Maskable Interrupt Request RESET Con[...]

106 CHAPTER 7 WATCHDOG TIMER 7.3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer. • Timer clock select register 2 (TCL2) • Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer count clock. TCL2 is set with 8-bit memory mani[...]

107 CHAPTER 7 WATCHDOG TIMER Figure 7-2. Timer Clock Select Register 2 Format TCL27 7 TCL26 6 TCL25 0 4 0 3210 FF42H Address TCL2 Symbol TCL22 TCL21 TCL20 5 00H After Reset R/W R/W 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 TCL22 TCL21 TCL20 f XX /2 3 f XX /2 4 f XX /2 5 f XX /2 6 f XX /2 7 f XX /2 8 f XX /2 9 f XX /2 11 MCS=1 f X /2 3 f X /2 [...]

108 CHAPTER 7 WATCHDOG TIMER RUM 7 0 6 0 WDTM4 4 WDTM3 3210 FFF9H Address WDTM Symbol 000 5 00H After Reset R/W R/W RUN 0 1 Watchdog Timer Operation Mode Selection Note 3 Count stop Counter is cleared and counting starts. WDTM3 × 0 1 Watchdog Timer Operation Mode Selection Note 1 Interval timer mode Note 2 (Maskable interrupt occurs upon generatio[...]

109 CHAPTER 7 WATCHDOG TIMER 7.4 Watchdog Timer Operations 7.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any inadvertent program loop. The watchdog timer count clock (inadvertent program loop detection time interval) can be selected with bits 0 to 2[...]

110 CHAPTER 7 WATCHDOG TIMER 7.4.2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0. A count clock (interval time) can be selected by the bits 0 to 2 (TCL20 to TCL2[...]

111 CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT CLOE PCL/P35 Pin Output ** CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT 8.1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSI. Clocks selected with the timer clock select regis[...]

112 CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT 8.2 Clock Output Control Circuit Configuration The clock output control circuit consists of the following hardware. Table 8-1. Clock Output Control Circuit Configuration Item Configuration Timer clock select register 0 (TCL0) Port mode register 3 (PM3) Figure 8-2. Clock Output Control Circuit Block Diagram[...]

113 CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT 8.3 Clock Output Function Control Registers The following two types of registers are used to control the clock output function. • Timer clock select register 0 (TCL0) • Port mode register 3 (PM3) (1) Timer clock select register 0 (TCL0) This register sets PCL output clock. TCL0 is set with a 1-bit or 8[...]

114 CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT PM37 7 PM36 6 PM35 PM34 4 PM33 3210 FF23H Address PM3 Symbol PM32 PM31 PM30 5 FFH After Reset R/W R/W PM3n 0 1 P3n Pin Input/Output Mode Selection (n=0 to 7) Output mode (output buffer ON) Input mode (output buffer OFF) (2) Port mode register 3 (PM3) This register set port 3 input/output in 1-bit units. Wh[...]

115 CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT Internal Bus f XX /2 9 f XX /2 10 f XX /2 11 TCL27 TCL26 TCL25 3 PM36 Selector Timer Clock Select Register 2 Port Mode Register 3 BUZ / P36 P36 Output Latch CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT 9.1 Buzzer Output Control Circuit Functions The buzzer output control circuit outputs 1.2 kHz, 2.4 kHz, 4.9 k[...]

116 CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT 9.3 Buzzer Output Function Control Registers The following two types of registers are used to control the buzzer output function. • Timer clock select register 2 (TCL2) • Port mode register 3 (PM3) (1) Timer clock select register 2 (TCL2) This register sets the buzzer output frequency. TCL2 is set wit[...]

117 CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT Figure 9-2. Timer Clock Select Register 2 Format TCL27 7 TCL26 6 TCL25 0 4 0 3210 FF42H Address TCL2 Symbol TCL22 TCL21 TCL20 5 00H After Reset R/W R/W 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 TCL22 TCL21 TCL20 f XX /2 3 f XX /2 4 f XX /2 5 f XX /2 6 f XX /2 7 f XX /2 8 f XX /2 9 f XX /2 11 MCS=1 f[...]

118 CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT PM37 7 PM36 6 PM35 PM34 4 PM33 3210 FF23H Address PM3 Symbol PM32 PM31 PM30 5 FFH After Reset R/W R/W PM3n 0 1 P3n Pin Input /Output Mode Selection (n=0 to 7) Output mode (output buffer ON) Input mode (output buffer OFF) (2) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units.[...]

119 CHAPTER 10 A/D CONVERTER CHAPTER 10 A/D CONVERTER 10.1 A/D Converter Functions The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an 8-bit resolution. The conversion method is based on successive approximation and the conversion result is held in the 8-bit A/D conversion result registe[...]

120 CHAPTER 10 A/D CONVERTER Figure 10-1. A/D Converter Block Diagram Notes 1. Selector to select the number of channels to be used for analog input. 2. Selector to select the channel for A/D conversion. 3. External interrupt mode register 1 (INTM1) bits 0 and 1. ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Selector A /D [...]

121 CHAPTER 10 A/D CONVERTER (1) Successive approximation register (SAR) This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string and holds the result from the most significant bit (MSB). When held to the least significant bit (LSB) (end of A/D conversion), the contents[...]

122 CHAPTER 10 A/D CONVERTER 10.3 A/D Converter Control Registers The following three types of registers are used to control the A/D converter. • A/D converter mode register (ADM) • A/D converter input select register (ADIS) • External interrupt mode register 1 (INTM1) (1) A/D converter mode register (ADM) This register sets the analog input [...]

123 CHAPTER 10 A/D CONVERTER Figure 10-2. A/D Converter Mode Register Format Notes 1. Set so that the A/D conversion time is 19.1 µ s or more. 2. Setting prohibited because A/D conversion time is less than 19.1 µ s. Cautions 1. The following sequence is recommended for power consumption reduction of A/D converter when the standby function is used[...]

124 CHAPTER 10 A/D CONVERTER (2) A/D converter input select register (ADIS) This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels or ports. Pins other than those selected as analog input can be used as input/output ports. ADIS is set with an 8-bit memory manipulation instruction. RESET input sets AD[...]

125 CHAPTER 10 A/D CONVERTER (3) External interrupt mode register 1 (INTM1) This register sets the valid edge for INTP3. INTM1 is set with an 8-bit memory manipulation instruction. RESET input sets INTM1 to 00H. Figure 10-4. External Interrupt Mode Register 1 Format 0 7 0 6 00 4 0 3210 FFEDH Address INTM1 Symbol 0 ES41 ES40 5 00H After Reset R/W R/[...]

126 CHAPTER 10 A/D CONVERTER 10.4 A/D Converter Operations 10.4.1 Basic operations of A/D converter (1) Set the number of analog input channels with A/D converter input select register (ADIS). (2) From among the analog input channels set with ADIS, select one channel for A/D conversion with A/D converter mode register (ADM). (3) Sample the voltage [...]

127 CHAPTER 10 A/D CONVERTER SAR ADCR INTAD A / D Converter Operation Sampling Time Sampling A / D Conversion Conversion Time Undefined 80H C0H or 40H Conversion Result Conversion Result Figure 10-5. A/D Converter Basic Operation A/D conversion operations are performed continuously until bit 7 (CS) of A/D converter mode register (ADM) is reset (0) [...]

128 CHAPTER 10 A/D CONVERTER 10.4.2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (the value stored in A/D conversion result register (ADCR)) is shown by the following expression. ADCR = INT ( × 256 + 0.5) or (ADCR – 0.5) ×≤ V IN &[...]

129 CHAPTER 10 A/D CONVERTER ADM Rewrite CS=1, TRG=1 Standby State ANIn INTP3 A /D Conversion ADCR INTAD ANIn ANIn ANIn ANIm ANIm ANIn ANIn Standby State Standby State ADM Rewrite CS=1, TRG=1 ANIm ANIm ANIm 10.4.3 A/D converter operating mode Using the A/D converter input select register (ADIS) and the A/D converter mode register (ADM), select one [...]

130 CHAPTER 10 A/D CONVERTER Conversion Start CS=1, TRG=0 A /D Conversion ADCR INTAD ANIn ANIn ANIm ANIn ANIm ANIm ANIn ANIn ADM Rewrite CS=1, TRG=0 ADM Rewrite CS=0, TRG=0 Conversion suspended Conversion results are not stored Stop (2) A/D conversion operation in software start When bit 6 (TRG) and bit 7 (CS) of A/D converter mode register (ADM) a[...]

131 CHAPTER 10 A/D CONVERTER 10.5 A/D Converter Cautions (1) Power consumption in standby mode The A/D converter operates on the main system clock. Therefore, its operation stops in STOP mode. As a current still flows in the AV REF pin at this time, this current must be cut in order to minimize the overall system power dissipation. In Figure 10-9, [...]

132 CHAPTER 10 A/D CONVERTER (3) Noise countermeasures In order to maintain 8-bit resolution, attention must be paid to noise on pins AV REF and ANI0 to ANI7. Since the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 10-10 in order to re[...]

133 CHAPTER 10 A/D CONVERTER A /D Conversion ADCR INTAD ANIn ANIn ANIm ANIm ANIn ANIn ANIm ANIm ADM Rewrite (Start of ANIn Conversion) ADM Rewrite (Start of ANIm Conversion) ADIF is set but ANIm conversion has not ended (6) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the A/D converter mode register (ADM) i[...]

134 CHAPTER 10 A/D CONVERTER [MEMO][...]

135 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 11.1 Serial Interface Channel 2 Functions Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not car[...]

136 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 11.2 Serial Interface Channel 2 Configuration Serial interface channel 2 consists of the following hardware. Table 11-1. Serial Interface Channel 2 Configuration Item Configuration Register Transmit shift register (TXS) Receive shift register (RXS) Receive buffer register (RXB) Control register Serial opera[...]

137 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 Internal Bus Asynchronous Serial Interface Mode Register Asynchronous Serial Interface Status Register Receive Buffer Register (RXB/SIO2) Direction Control Circuit Receive Shift Register (RXS) Reception Control Circuit RxD/SI2/ P70 TxD/SO2/ P71 INTSR/INTCSI2 CSIE2 CSIM 22 CSCK INTSER SCK Output Control Circ[...]

138 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 TPS3 TPS2 TPS1 TPS0 Internal Bus MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Control Register 4 TXE CSIE2 5-Bit Counter Selector Selector Decoder 1/2 Selector Transmit Clock 1/2 Selector Receive Clock Match Match MDL0-MDL3 5-Bit Counter RXE Start Bit Detection Selector f xx -f xx /2 10 TPS0-TPS3 SCK CSCK ASCK/S[...]

139 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 (1) Transmit shift register (TXS) This register is used to set the transmit data. The data written in TXS is transmitted as serial data. If the data length is specified as 7 bits, bits 0 to 6 of the data written in TXS are transferred as transmit data. Writing data to TXS starts the transmit operation. TXS [...]

140 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 11.3 Serial Interface Channel 2 Control Registers Serial interface channel 2 is controlled by the following four registers. • Serial Operating Mode Register 2 (CSIM2) • Asynchronous Serial Interface Mode Register (ASIM) • Asynchronous Serial Interface Status Register (ASIS) • Baud Rate Generator Con[...]

141 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 6543210 7 Symbol ASIM TXE RXE PS1 PS0 CL SL ISRM SCK FF70H 00H R/W Address After Reset R/W SCK 0 1 Clock Selection in Asynchronous Serial Interface Mode Input clock from off-chip to ASCK pin Dedicated baud rate generator output Note ISRM 0 1 Control of Reception Completion Interrupt in Case of Error Generat[...]

142 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 Table 11-2. Serial Interface Channel 2 Operating Mode Settings (1) Operation Stop Mode (2) 3-wire Serial I/O Mode (3) Asynchronous Serial Interface Mode Notes 1. Can be used freely as port function. 2. Can be used as P70 (CMOS input/output) when only transmitter is used. Remark × : Don’t care PM ×× : P[...]

143 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 PE 6543210 7 Symbol ASIS 0 0 0 0 0 FE OVE FF71H 00H R Address After Reset R/W OVE 0 1 Overrun Error Flag Overrun error not generated Overrun error generated Note 1 (When next receive operation is completed before data from receive buffer register is read) FE 0 1 Framing Error Flag Framing error not generate[...]

144 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 Baud Rate Generator Input Clock Selection MDL3 MDL2 MDL1 MDL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 f SCK /16 f SCK /17 f SCK /18 f SCK /19 f SCK /20 f SCK /21 f SCK /22 f SCK /23 f SCK /24 f SCK /25 f SCK /26 f SCK /2[...]

145 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 Figure 11-6. Baud Rate Generator Control Register Format (2/2) 5-Bit Counter Source Clock Selection TPS3 TPS2 TPS1 TPS0 n MCS=1 MCS=0 00 00 f XX /2 10 f XX /2 10 (4.9 kHz) f X /2 11 (2.4 kHz) 11 01 01 f XX f X (5.0 MHz) f X /2 (2.5 MHz) 1 01 10 f XX /2 f X /2 (2.5 MHz) f X /2 2 (1.25 MHz) 2 01 11 f XX /2 2 [...]

146 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (a) Generation of baud rate transmit/receive clock by means of main system clock The transmit/receive clocks generated by scaling the main system cl[...]

147 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 (b) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with the following expression. [Baud rate] = [Hz] where[...]

148 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 11.4 Serial Interface Channel 2 Operation Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode 11.4.1 Operation stop mode In the operation stop mode, serial transfer is not performed, and therefore power co[...]

149 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 SL 6543210 7 Symbol ASIM TXE RXE PS1 PS0 CL ISRM SCK FF70H 00H R/W Address After Reset R/W RXE 0 1 Receive Operation Control Receive operation stopped Receive operation enabled TXE 0 1 Transmit Operation Control Transmit operation stopped Transmit operation enabled (b) Asynchronous serial interface mode reg[...]

150 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 6543210 7 Symbol CSIM2 CSIE2 0 0 0 0 CSIM 22 CSCK 0 CSCK 0 1 Clock Selection in 3-wire Serial I/O Mode Input clock from off-chip to SCK2 pin Dedicated baud rate generator output CSIM22 0 1 First Bit Specification MSB LSB CSIE2 0 1 Operation Control in 3-wire Serial I/O Mode Operation stopped Operation enabl[...]

151 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 Note When SCK is set to 1 and the baud rate generator output is selected, the ASCK pin can be used as an input/output port. Caution The serial transmit/receive operation must be stopped before changing the operating mode. (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-b[...]

152 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 PE 6543210 7 Symbol ASIS 0 0 0 0 0 FE OVE FF71H 00H R Address After Reset R/W OVE 0 1 Overrun Error Flag Overrun error not generated Overrun error generated Note 1 (When next receive operation is completed before data from receive buffer register is read) FE 0 1 Framing Error Flag Framing error not generate[...]

153 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 Baud Rate Generator Input Clock Selection MDL3 MDL2 MDL1 MDL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 f SCK /16 f SCK /17 f SCK /18 f SCK /19 f SCK /20 f SCK /21 f SCK /22 f SCK /23 f SCK /24 f SCK /25 f SCK /26 f SCK /27 f SCK [...]

154 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 5-Bit Counter Source Clock Selection TPS3 TPS2 TPS1 TPS0 n MCS=1 MCS=0 00 00 f XX /2 10 f X /2 10 (4.9 kHz) f X /2 11 (2.4 kHz) 11 01 01 f XX f X (5.0 MHz) f X /2 (2.5 MHz) 1 01 10 f XX /2 f X /2 (2.5 MHz) f X /2 2 (1.25 MHz) 2 01 11 f XX /2 2 f X /2 2 (1.25 MHz) f X /2 3 (625 kHz) 3 10 00 f XX /2 3 f X /2 [...]

155 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (i) Generation of baud rate transmit/receive clock by means of main system clock The transmit/receive clock is generated by scaling the main system [...]

156 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 (ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with the following expression. [Baud rate] = [Hz] wher[...]

157 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 (2) Communication operation (a) Data format The transmit/receive data format is as shown in Figure 11-7. Figure 11-7. Asynchronous Serial Interface Transmit/Receive Data Format 1 Data frame is configured from the following bits. • Start bits .................. 1 bit • Character bits ......... 7 bits/8 b[...]

158 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) error can be detected. With 0 parity and no parity, an[...]

159 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 D1 D2 D6 D7 Parity D0 TxD (Output) INTST STOP START D1 D2 D6 D7 Parity D0 TxD (Output) INTST STOP START (c) Transmission A transmit operation is started by writing transmit data to the transmit shift register (TXS). The start bit, parity bit and stop bit(s) are added automatically. When the transmit operati[...]

160 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 D1 D2 D6 D7 Parity D0 RxD (Input) INTSR STOP START (d) Reception When the RXE bit of the asynchronous serial interface mode register (ASIM) is set (1), a receive operation is enabled and sampling of the RxD pin input is performed. RxD pin input sampling is performed using the serial clock specified by ASIM.[...]

161 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 (e) Receive errors Three kinds of errors can occur during a receive operation: a parity error, framing error, or overrun error. When a data reception results error flag is set in the asynchronous serial interface register (ASIS), a reception error interrupt request (INTSER) is generated. The reception error[...]

162 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 (3) UART mode cautions (a) In cases where bit 7 (TXE) of the asynchronous serial interface mode register (ASIM) has been cleared and a transmit operation has been terminated during transmission, be sure to set 1 in TXE after setting FFH in the transmit shift register (TXS) before executing the next transmis[...]

163 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 11.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional synchronous clocked serial interface, such as the 75X/XL series, 78K series, 17K series, etc. Communication is performed using three lines: the[...]

164 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM to 00H. When the 3-wire serial I/O mode is selected, 00H should be set in ASIM. 6543210 7 Symbol ASIM TXE RXE PS1 PS0 CL SL ISRM SCK FF70H 00H R/W Address After Res[...]

165 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 Baud Rate Generator Input Clock Selection MDL3 MDL2 MDL1 MDL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 f SCK /16 f SCK /17 f SCK /18 f SCK /19 f SCK /20 f SCK /21 f SCK /22 f SCK /23 f SCK /24 f SCK /25 f SCK /26 f SCK /2[...]

166 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 5-Bit Counter Source Clock Selection TPS3 TPS2 TPS1 TPS0 n MCS=1 MCS=0 00 00 f XX /2 10 f X /2 10 (4.9 kHz) f X /2 11 (2.4 kHz) 11 01 01 f XX f X (5.0 MHz) f X /2 (2.5 MHz) 1 01 10 f XX /2 f X /2 (2.5 MHz) f X /2 2 (1.25 MHz) 2 01 11 f XX /2 2 f X /2 2 (1.25 MHz) f X /2 3 (625 kHz) 3 10 00 f XX /2 3 f X /2 [...]

167 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 When the internal clock is used as the serial clock in the 3-wire serial I/O mode, set BRGC as described below. BRGC Setting is not required if an external serial clock is used. (i) When the baud rate generator is not used: Select a serial clock frequency with TPS0-TPS3. Be sure then to set MDL0 to MDL3 to [...]

168 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 SI2 SCK2 12345678 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO2 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SRIF Transfer Start at the Falling Edge of SCK2 End of Transfer (2) Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/ received bit by bit i[...]

169 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 Figure 11-13. Circuit of Switching in Transfer Bit Order Start bit switching is realized by switching the bit order for data write to SIO2. The SIO2 shift order remains unchanged. Thus, switching between MSB-first and LSB-first must be performed before writing data to the shift register. (4) Transfer start [...]

170 CHAPTER 11 SERIAL INTERFACE CHANNEL 2 [MEMO][...]

171 CHAPTER 12 INTERRUPT FUNCTION CHAPTER 12 INTERRUPT FUNCTION 12.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in the interrupt disabled status. It does not undergo interrupt priority control and is given top priority over all ot[...]

172 CHAPTER 12 INTERRUPT FUNCTION 12.2 Interrupt Sources and Configuration There are a total of 13 interrupts, combining non-maskable interrupts, maskable interrupts and software interrupts (see Table 12-1 ). Table 12-1. Interrupt Source List Interrupt Source Name Trigger Non- — INTWDT Watchdog timer overflow (with Internal 0004H (A) maskable wat[...]

173 CHAPTER 12 INTERRUPT FUNCTION Internal Bus IE PR ISP MK IF Interrupt Request Priority Control Circuit Vector Table Address Generator Standby Release Signal Internal Bus Priority Control Circuit Vector Table Address Generator Standby Release Signal Interrupt Request Figure 12-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-ma[...]

174 CHAPTER 12 INTERRUPT FUNCTION Internal Bus Priority Control Circuit Vector Table Address Generator Interrupt Request External Interrupt Mode Register (INTM0, INTM1) Edge Detector Interrupt Request IE PR ISP MK IF Priority Control Circuit Vector Table Address Generator Standby Release Signal Internal Bus Figure 12-1. Basic Configuration of Inter[...]

175 CHAPTER 12 INTERRUPT FUNCTION 12.3 Interrupt Function Control Registers The following five types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H, IF1L) • Interrupt mask flag register (MK0L, MK0H, MK1L) • Priority specify flag register (PR0L, PR0H, PR1L) • External interrupt mode re[...]

176 CHAPTER 12 INTERRUPT FUNCTION Cautions 1. TMIF4 flag is R/W enabled only when a watchdog timer is used as an interval timer. If a watchdog timer is used in watchdog timer mode 1, set TMIF4 flag to 0. 2. Set 0 to the bits 1, 5 to 7 of IF0L and bits 0, 1, 5 to 7 of IF0H and IF1L. (1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interru[...]

177 CHAPTER 12 INTERRUPT FUNCTION Cautions 1. If TMMK4 flag is read when a watchdog timer is used in watchdog timer mode 1, MK0 value becomes undefined. 2. Because port 0 has a dual function as the external interrupt request input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set.[...]

178 CHAPTER 12 INTERRUPT FUNCTION Cautions 1. If a watchdog timer is used in watchdog timer mode 1, set TMPR4 flag to 1. 2. Set 1 to the bits 1, 5 to 7 of PR0L and bits 0, 1, 5 to 7 of PR0H and PR1L. (3) Priority specify flag registers (PR0L, PR0H, and PR1L) The priority specify flag is used to set the corresponding maskable interrupt priority orde[...]

179 CHAPTER 12 INTERRUPT FUNCTION (4) External interrupt mode register (INTM0, INTM1) These registers set the valid edge for INTP1 to INTP3. INTM0 and INTM1 are set by 8-bit memory manipulation instructions. RESET input sets these registers to 00H. Figure 12-5. External Interrupt Mode Register 0 Format Caution Set 0 to the bits 0 to 3. Figure 12-6.[...]

180 CHAPTER 12 INTERRUPT FUNCTION (5) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple interrupt processing are mapped. Besides 8-bit unit read/write, this re[...]

181 CHAPTER 12 INTERRUPT FUNCTION 12.4 Interrupt Servicing Operations 12.4.1 Non-maskable interrupt request acknowledge operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge disable state. It does not undergo interrupt priority control and has highest priority over all other interrupt[...]

182 CHAPTER 12 INTERRUPT FUNCTION WDTM4=1 (with watchdog timer mode selected)? Overflow in WDT? WDTM3=0 (with non-maskable interrupt selected)? Interrupt request generation WDT interrupt servicing? Interrupt control register unaccessed? Interrupt service start Interrupt request held pending Reset processing Interval timer Start No Yes Yes No Yes No[...]

183 CHAPTER 12 INTERRUPT FUNCTION Figure 12-10. Non-Maskable Interrupt Request Acknowledge Operation (a) If a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution (b) If two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution Main Routine NMI Re[...]

184 CHAPTER 12 INTERRUPT FUNCTION 12.4.2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mask (MK) flag is cleared to 0. A vectored interrupt request is acknowledged in an interrupt enable state (with IE flag set to 1). However, a low-[...]

185 CHAPTER 12 INTERRUPT FUNCTION Figure 12-11. Interrupt Request Acknowledge Processing Algorithm Start × × IF=1? × × MK=0? × × PR=0? Any Simultaneously generated ×× PR=0 interrupt requests? Any Simultaneously generated high-priority interrupt requests? IE=1? ISP=1? Vectored interrupt servicing Interrupt request reserve Interrupt request r[...]

186 CHAPTER 12 INTERRUPT FUNCTION Figure 12-12. Interrupt Request Acknowledge Timing (Minimum Time) Remark 1 clock : (f CPU : CPU clock) Figure 12-13. Interrupt Request Acknowledge Timing (Maximum Time) Remark 1 clock : (f CPU : CPU clock) f CPU 1 f CPU 1 Instruction Instruction PSW and PC Save, Jump to Interrupt Servicing 6 Clocks Interrupt Servic[...]

187 CHAPTER 12 INTERRUPT FUNCTION 12.4.3 Software interrupt request acknowledge operation A software interrupt request is acknowledged by BRK instruction execution. Software interrupt cannot be disabled. If a software interrupt request is acknowledged, the contents are saved to the stack in the order of first, program status word (PSW), then the pr[...]

188 CHAPTER 12 INTERRUPT FUNCTION Table 12-4. Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing Maskable Interrupt Request PR=0 PR=1 IE=1 IE=0 IE=1 IE=0 Non-maskable interrupt D DDDD Maskable interrupt ISP=0 E E D D D ISP=1 E E D E D Software interrupt E E D E D Remarks 1. E : Multiple interrupt enable 2. D : Multiple inte[...]

189 CHAPTER 12 INTERRUPT FUNCTION Main Processing INTxx Servicing INTyy Servicing INTxx (PR=0) 1 Instruction Execution IE=0 INTyy (PR=1) EI IE=0 EI RETI RETI Main Processing EI INTxx (PR=1) INTyy (PR=0) IE=0 EI RETI INTxx Servicing INTzz (PR=0) IE=0 EI RETI INTyy Servicing IE=0 RETI INTzz Servicing Figure 12-14. Multiple Interrupt Example (1/2) Exa[...]

190 CHAPTER 12 INTERRUPT FUNCTION Main Processing INTxx Servicing INTyy Servicing INTxx (PR=0) 1 Instruction Execution IE=0 INTyy (PR=0) IE=0 RETI RETI EI Figure 12-14 Multiple Interrupt Example (2/2) Example 3. Example of when a multiple interrupt is not generated because interrupts are not enabled. Because interrupts are not enabled (the EI instr[...]

191 CHAPTER 12 INTERRUPT FUNCTION 12.4.5 Interrupt request reserve There are some instructions which, though an interrupt request may be generated while they are being executed, will reserve the acknowledgment of the request until after execution of the next instruction. These instructions (interrupt request reserve instructions) are shown below. ?[...]

192 CHAPTER 12 INTERRUPT FUNCTION The interrupt request reserve timing is shown in Figure 12-15. Figure 12-15. Interrupt Request Hold Remarks 1. Instruction N: Instruction that holds interrupts requests 2. Instruction M: Instructions other than instruction N 3. The operation of ×× IF (interrupt request) is not affected by ×× PR (priority level)[...]

193 CHAPTER 13 STANDBY FUNCTION CHAPTER 13 STANDBY FUNCTION 13.1 Standby Function and Configuration 13.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operat[...]

194 CHAPTER 13 STANDBY FUNCTION Address FFFAH 04H After Reset R/W R/W 0 0 0 0 1 Selection of Oscillation Stabilization Time when STOP Mode is Released 2 12 /f xx 2 14 /f xx 2 15 /f xx 2 16 /f xx 2 17 /f xx OSTS2 7 0 Symbol OSTS 6 0 5 0 4 0 3 0 2 OSTS2 1 OSTS1 0 OSTS0 0 0 1 1 0 Other than above OSTS1 MCS = 1 MCS = 0 2 12 /f x (819 s) 2 14 /f x (3.28[...]

195 CHAPTER 13 STANDBY FUNCTION 13.2 Standby Function Operations 13.2.1 HALT mode (1) HALT mode set and operating status The HALT mode is set by executing the HALT instruction. The operating status in the HALT mode is described below. Table 13-1. HALT Mode Operating Status Item HALT Mode Operating Status Clock generator Can be oscillated. Supply to[...]

196 CHAPTER 13 STANDBY FUNCTION HALT Instruction Wait Standby Release Signal Operating Mode Clock HALT Mode Wait Oscillation Operating Mode (2) HALT mode clear The HALT mode can be cleared with the following three types of sources. (a) Clear upon unmasked interrupt request An unmasked interrupt request is used to clear the HALT mode. If interrupt a[...]

197 CHAPTER 13 STANDBY FUNCTION (c) Clear upon RESET input As is the case with normal reset operation, a program is executed after branch to the reset vector address. Figure 13-3. HALT Mode Release by RESET Input Remarks 1. f X : main system clock oscillation frequency 2. Values in parentheses when operated at f x = 5.0 MHz Table 13-2. Operation af[...]

198 CHAPTER 13 STANDBY FUNCTION 13.2.2 STOP mode (1) STOP mode set and operating status The STOP mode is set by executing the STOP instruction. Cautions 1. When the STOP mode is set, the X2 pin is internally connected to V DD via a pull-up resistor to minimize the leakage current at the crystal oscillator. Thus, do not use the STOP mode in a system[...]

199 CHAPTER 13 STANDBY FUNCTION STOP Instruction Wait (Time set by OSTS) Oscillation Stabilization Wait Status Operating Mode Oscillation Operationg Mode STOP Mode Oscillation Stop Oscillation Standby Release Signal Clock (2) STOP mode release The STOP mode can be cleared with the following two types of sources. (a) Release by unmasked interrupt re[...]

200 CHAPTER 13 STANDBY FUNCTION RESET Signal Operating Mode Clock Reset Period STOP Mode Oscillation Stop Oscillation Stabilization Wait Status Operating Mode Oscillation Wait (2 17 /f x : 26.2 ms) STOP Instruction Oscillation (b) Release by RESET input The STOP mode is cleared and after the lapse of oscillation stabilization time, reset operation [...]

201 CHAPTER 14 RESET FUNCTION RESET Count Clock Reset Control Circuit Watchdog Timer Stop Over- flow Reset Signal Interrupt Function CHAPTER 14 RESET FUNCTION 14.1 Reset Function The following two operations are available to generate the reset signal. (1) External reset input with RESET pin (2) Internal reset by watchdog timer overrun time detectio[...]

202 CHAPTER 14 RESET FUNCTION RESET Internal Reset Signal Port Pin Delay Delay Hi-Z X1 Normal Operation Reset Period (Oscillation Stop) Oscillation Stabilization Time Wait Normal Operation (Reset Processing) Stop Status (Oscillation Stop) STOP Instruction Execution RESET Internal Reset Signal Port Pin Delay Delay Hi-Z X1 Normal Operation Reset Peri[...]

203 CHAPTER 14 RESET FUNCTION Table 14-1. Hardware Status after Reset (1/2) Hardware Status after Reset Program counter (PC) Note1 The contents of reset vector tables (0000H and 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) 02H Data memory Undefined Note2 General register Undefined Note2 Port 0, Port 1, Port 3, Port 5, Port[...]

204 CHAPTER 14 RESET FUNCTION Table 14-1. Hardware Status after Reset (2/2) Hardware Status after Reset Interrupt Request flag register (IF0L, IF0H, IF1L) 00H Mask flag register (MK0L, MK0H, MK1L) FFH Priority specify flag register (PR0L, PR0H, PR1L) FFH External interrupt mode register (INTM0, INTM1) 00H Notes 1. During reset input or oscillation [...]

205 CHAPTER 15 µ PD78P083 CHAPTER 15 µ PD78P083 The µ PD78P083 is a single-chip microcontroller with an on-chip one-time PROM or with an on-chip EPROM which has program write, erasure and rewrite capability. Differences between the µ PD78P083 and mask ROM versions are shown in Table 15-1. Table 15-1. Differences between the µ PD78P083 and Mask[...]

206 CHAPTER 15 µ PD78P083 Caution If using mask ROM versions, do not specify any values in the IMS other than when resetting. The IMS settings to give the same memory map as mask ROM versions are shown in Table 15-2. Table 15-2. Examples of Memory Size Switching Register Settings Relevant Mask ROM Version IMS Setting µ PD78081 82H µ PD78082 64H [...]

207 CHAPTER 15 µ PD78P083 RESET V PP V DD CE OE PGM D0-D7 15.2 PROM Programming The µ PD78P083 incorporate a 24-Kbyte PROM as program memory, respectively. To write a program into the µ PD78P083 PROM, make the device enter the PROM programming mode by setting the levels of the V PP and RESET pins as specified. For the connection of unused pins, [...]

208 CHAPTER 15 µ PD78P083 (3) Standby mode Setting CE to H sets the standby mode. In this mode, data output becomes high impedance irrespective of the status of OE. (4) Page data latch mode Setting CE to H, PGM to H, and OE to L at the start of the page write mode sets the page data latch mode. In this mode, 1-page 4-byte data is latched in the in[...]

209 CHAPTER 15 µ PD78P083 15.2.2 PROM write procedure Figure 15-2. Page Program Mode Flowchart Start Address = G V DD = 6.5 V, V PP = 12.5 V X = 0 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Latch X = X + 1 0.1-ms program pulse Verify 4 Bytes Pass Address = N? No Pass V DD = 4.5 to 5.5 V, V PP = V DD All byt[...]

210 CHAPTER 15 µ PD78P083 Figure 15-3. Page Program Mode Timing Page Data Latch Page Program Program Verify Data Input Data Output A2-A14 A0, A1 D0-D7 V PP V DD V PP V DD +1.5 V DD V DD V IH CE PGM OE V IL V IH V IL V IH V IL[...]

211 CHAPTER 15 µ PD78P083 Figure 15-4. Byte Program Mode Flowchart Start Address = G V DD = 6.5 V, V PP = 12.5 V X = 0 X = X + 1 0.1-ms program pulse Verify Address = N? V DD = 4.5 to 5.5 V, V PP = V DD All bytes verified? End of write Fail Fail Pass Yes All Pass No Pass Defective product No Yes X = 10? Address = Address + 1 Remark: G = Start addr[...]

212 CHAPTER 15 µ PD78P083 Figure 15-5. Byte Program Mode Timing Cautions 1. Be sure to apply V DD before applying V PP , and remove it after removing V PP . 2. V PP must not exceed +13.5 V including overshoot voltage. 3. Disconnecting/inserting the device from/to the on-board socket while +12.5 V is being applied to the V PP pin may have an advers[...]

213 CHAPTER 15 µ PD78P083 15.2.3 PROM reading procedure PROM contents can be read onto the external data bus (D0 to D7) using the following procedure. (1) Fix the RESET pin low, and supply +5 V to the V PP pin. Unused pins are handled as shown in paragraph, (2) “PROM programming mode” in section 1.5 Pin Configuration (Top View) . (2) Supply +5[...]

214 CHAPTER 15 µ PD78P083 15.3 Erasure Procedure ( µ PD78P083DU Only) With the µ PD78P083DU, it is possible to erase ( or set all contents to FFH) the data contents written in the program memory, and rewrite the memory. The data can be erased by exposing the window to light with a wavelength of approximately 400 nm or shorter. Typically, data is[...]

215 CHAPTER 16 INSTRUCTION SET CHAPTER 16 INSTRUCTION SET This chapter describes each instruction set of the µ PD78083 subseries as list table. For details of its operation and operation code, refer to the separate document “78K/0 series USER’S MANUAL—Instruction (IEU-1372) .”[...]

216 CHAPTER 16 INSTRUCTION SET 16.1 Legends Used in Operation List 16.1.1 Operand identifiers and description methods Operands are described in “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more descri[...]

217 CHAPTER 16 INSTRUCTION SET 16.1.2 Description of “operation” column A : A register; 8-bit accumulator X : X register B : B register C : C register D : D register E : E register H : H register L : L register AX : AX register pair; 16-bit accumulator BC : BC register pair DE : DE register pair HL : HL register pair PC : Program counter SP : S[...]

218 CHAPTER 16 INSTRUCTION SET 16.2 Operation List Clock Flag Note 1 Note 2 ZA C C Y r, #byte 2 4 – r ← byte saddr, #byte 3 6 7 (saddr) ← byte sfr, #byte 3 – 7 sfr ← byte A, r Note 3 12 – A ← r r, A Note 3 12 – r ← A A, saddr 2 4 5 A ← (saddr) saddr, A 2 4 5 (saddr) ← A A, sfr 2 – 5 A ← sfr sfr, A 2 – 5 sfr ← A A, !add[...]

219 CHAPTER 16 INSTRUCTION SET Clock Flag Note 1 Note 2 ZA C C Y rp, #word 3 6 – rp ← word saddrp, #word 4 8 10 (saddrp) ← word sfrp, #word 4 – 10 sfrp ← word AX, saddrp 2 6 8 AX ← (saddrp) saddrp, AX 2 6 8 (saddrp) ← AX MOVW AX, sfrp 2 – 8 AX ← sfrp sfrp, AX 2 – 8 sfrp ← AX AX, rp Note 3 1 4 – AX ← rp rp, AX Note 3 1 4 ?[...]

220 CHAPTER 16 INSTRUCTION SET Clock Flag Note 1 Note 2 ZA C C Y A, #byte 2 4 – A, CY ← A – byte ×× × saddr, #byte 3 6 8 (saddr), CY ← (saddr) – byte ×× × A, r Note 3 2 4 – A, CY ← A – r ×× × r, A 2 4 – r, CY ← r – A ×× × A, saddr 2 4 5 A, CY ← A – (saddr) ×× × A, !addr16 3 8 9 A, CY ← A – (addr16) ×× [...]

221 CHAPTER 16 INSTRUCTION SET Clock Flag Note 1 Note 2 ZA C C Y A, #byte 2 4 – A ← A byte × saddr, #byte 3 6 8 (saddr) ← (saddr) byte × A, r Note 3 24 – A ← A r × r, A 2 4 – r ← r A × A, saddr 2 4 5 A ← A (saddr) × A, !addr16 3 8 9 A ← A (addr16) × A, [HL] 1 4 5 A ← A (HL) × A, [HL + byte] 2 8 9 A ← A (HL + byte) × A,[...]

222 CHAPTER 16 INSTRUCTION SET Clock Flag Note 1 Note 2 ZA C C Y ADDW AX, #word 3 6 – AX, CY ← AX + word ×× × SUBW AX, #word 3 6 – AX, CY ← AX – word ×× × CMPW AX, #word 3 6 – AX – word ×× × MULU X 2 16 – AX ← A × X DIVUW C 2 25 – AX (Quotient), C (Remainder) ← AX ÷ C r1 2 – r ← r + 1 ×× saddr 2 4 6 (saddr) ?[...]

223 CHAPTER 16 INSTRUCTION SET Clock Flag Note 1 Note 2 ZA C C Y CY, saddr.bit 3 6 7 CY ← CY (saddr.bit) × CY, sfr.bit 3 – 7 CY ← CY sfr.bit × AND1 CY, A.bit 2 4 – CY ← CY A.bit × CY, PSW.bit 3 – 7 CY ← CY PSW.bit × CY, [HL].bit 2 6 7 CY ← CY (HL).bit × CY, saddr.bit 3 6 7 CY ← CY (saddr.bit) × CY, sfr.bit 3 – 7 CY ← CY [...]

224 CHAPTER 16 INSTRUCTION SET Clock Flag Note 1 Note 2 ZA C C Y (SP – 1) ← (PC + 3) H , (SP – 2) ← (PC + 3) L , PC ← addr16, SP ← SP – 2 (SP – 1) ← (PC + 2) H , (SP – 2) ← (PC + 2) L , CALLF !addr11 2 5 – PC 15 – 11 ← 00001, PC 10 – 0 ← addr11, SP ← SP – 2 (SP – 1) ← (PC + 1) H , (SP – 2) ← (PC + 1) L , [...]

225 CHAPTER 16 INSTRUCTION SET Clock Flag Note 1 Note 2 ZA C C Y saddr.bit, $addr16 3 8 9 PC ← PC + 3 + jdisp8 if(saddr.bit) = 1 sfr.bit, $addr16 4 – 11 PC ← PC + 4 + jdisp8 if sfr.bit = 1 BT A.bit, $addr16 3 8 – PC ← PC + 3 + jdisp8 if A.bit = 1 PSW.bit, $addr16 3 – 9 PC ← PC + 3 + jdisp8 if PSW.bit = 1 [HL].bit, $addr16 3 10 11 PC ?[...]

226 CHAPTER 16 INSTRUCTION SET 16.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ[...]

227 CHAPTER 16 INSTRUCTION SET Second Operand [HL + byte] #byte A r Note sfr saddr !addr16 PSW [DE] [HL] [HL + B] $addr16 1 None First Operand [HL + C] A ADD MOV MOV MOV MOV MOV MOV MOV MOV ROR ADDC XCH XCH XCH XCH XCH XCH XCH ROL SUB ADD ADD ADD ADD ADD RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC AND SUB SUB SUB SUB SUB OR SUBC SUBC SUBC SUBC SUBC XOR[...]

228 CHAPTER 16 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand First Operand AX ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW rp MOVW MOVW Note INCW DECW PUSH POP sfrp MOVW MOVW saddrp MOVW MOVW !addr16 MOVW SP MOVW MOVW Note Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, [...]

229 CHAPTER 16 INSTRUCTION SET AX !addr16 !addr11 [addr5] $addr16 (4) Call/instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand First Operand Basic instruction BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound BT instruction BF BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RE[...]

230 CHAPTER 16 INSTRUCTION SET [MEMO][...]

231 APPENDIX A DEVELOPMENT TOOLS APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems which employ the µ PD78083 subseries. Figure A-1 shows the configuration of the development tools.[...]

232 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration Embedded software • Real-time OS, OS • Fuzzy inference development support system PROM programmer control software • PG-1500 controller Language processing software • Assembler package • C compiler package • C library source file • System simulator • Screen [...]

233 APPENDIX A DEVELOPMENT TOOLS A.1 Language Processing Software RA78K/0 This assembler converts a program written in mnemonics into an object code executable with a Assembler Package microprocontroller. Further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. Used in c[...]

234 APPENDIX A DEVELOPMENT TOOLS A.2 PROM Programming Tools A.2.1 Hardware PG-1500 This is a PROM programmer capable of programming the single-chip microcontroller with on-chip PROM programmer PROM by manipulating from the stand-alone or host machine through connection of the separately available programmer adapter and the attached board. It can al[...]

235 APPENDIX A DEVELOPMENT TOOLS A.3 Debugging Tools A.3.1 Hardware IE-78000-R-A This in-circuit emulator helps users in debugging hardware and software of an application system In-circuit emulator that includes a 78K/0 series device. This in-circuit emulator supports integrated debugger (supporting integrated (ID78K0). It is used with emulation pr[...]

236 APPENDIX A DEVELOPMENT TOOLS A.3.2 Software (1/3) SM78K0 This simulator can debug target system at C source level or assembler level while simulating System simulator operation of target system on host machine. SM78K0 runs on Windows. By using SM78K0, logic and performance of application can be verified without in-circuit emulator independently[...]

237 APPENDIX A DEVELOPMENT TOOLS A.3.2 Software (2/3) ID78K0 This is control program that debugs 78K/0 series. Integrated debugger This program employs Windows on personal computer and OSF/Motif™ on EWS as graphical user interface, and provides appearance and operability conforming to interface. In addition debugging functions supporting C langua[...]

238 APPENDIX A DEVELOPMENT TOOLS A.3.2 Software (3/3) SD78K/0 This program controls IE-78000-R on host machine with IE-78000-R and host machine Screen debugger connected with serial interface (RS-232-C). It is used with optional device file (DF78083). Part Number: µ S ×××× SD78K0 DF78083 Note File containing device-specific information. Device[...]

239 APPENDIX A DEVELOPMENT TOOLS A.4 OS for IBM PC As the OS for IBM PC, the following is supported. To run SM78K0, ID78K0, or FE9200 (refer to B.2 Fuzzy Inference Development Support System ), Windows (Ver. 3.0 to Ver. 3.1) is necessary. OS Version PC DOS Ver. 5.02 to 6.3 J6.1/V Note to J6.3/V Note IBM DOS™ J5.02/V Note MS-DOS Ver. 5.0 to 6.22 5[...]

240 APPENDIX A DEVELOPMENT TOOLS A.5 System-Upgrade Method from Other In-Circuit Emulators to 78K/0 Series In-Circuit Emulator If you already have an in-circuit emulator for the 78K series or the 75X/XL series, you can use that in-circuit emulator as the equivalent of the 78K/0 series in-circuit emulator IE-78000-R or IE-78000-R-A by replacing the [...]

241 APPENDIX A DEVELOPMENT TOOLS Drawing and Footprint for Conversion Socket (EV-9200G-44) Figure A-2. EV-9200G-44 Drawing (For Reference Only) A F D 1 E EV-9200G-44 B C M N O L K R Q I H P J G EV-9200G-44-G0E ITEM MILLIMETERS INCHES A B C D E F G H I J K L M N O P Q R 15.0 10.3 10.3 15.0 4-C 3.0 0.8 5.0 12.0 14.7 5.0 12.0 14.7 8.0 7.8 2.0 1.35 0.3[...]

242 APPENDIX A DEVELOPMENT TOOLS Figure A-3. EV-9200G-44 Footprint (For Reference Only) 0.031 × 0.394=0.315 0.031 × 0.394=0.315 A F D E B G H I J C L K EV-9200G-44-P1E ITEM MILLIMETERS INCHES A B C D E F G H I J K L 15.7 11.0 11.0 15.7 5.00 ± 0.08 5.00 ± 0.08 0.5 ± 0.02 1.57 ± 0.03 2.2 ± 0.1 1.57 ± 0.03 0.618 0.433 0.433 0.618 0.197 0.197 0[...]

243 APPENDIX B EMBEDDED SOFTWARE APPENDIX B EMBEDDED SOFTWARE This section describes the embedded software which are provided for the µ PD78083 subseries to allow users to develop and maintain the application program for these subseries.[...]

244 APPENDIX B EMBEDDED SOFTWARE B.1 Real-time OS MX78K0 µ ITRON-specification subset OS. Nucleus of MX78K0 is supplied. OS This OS performs task management, event management, and time management. It controls the task execution sequence for task management and selects the task to be executed next. Part Number: µ S ×××× MX78K0- ∆∆∆ Remar[...]

245 APPENDIX B EMBEDDED SOFTWARE B.2 Fuzzy Inference Development Support System FE9000/FE9200 This program supports input of fuzzy knowledge data (fuzzy rule and membership function), Fuzzy Knowledge Data editing (edit), and evaluation (simulation) Creation Tool FE9200 operations on Windows. Part Number: µ S ×××× FE9000 (PC-9800 series) µ S ?[...]

246 APPENDIX B EMBEDDED SOFTWARE [MEMO][...]

247 APPENDIX C REGISTER INDEX APPENDIX C REGISTER INDEX C.1 Register Index 8-bit timer mode control register (TMC5) ............................................................................................................ 87 8-bit timer register 5 (TM5) .............................................................................................[...]

248 APPENDIX C REGISTER INDEX [P] P0: Port0 ........................................................................................................................................... 17, 55 P1: Port1 ........................................................................................................................................... 17, 57 P3[...]

249 APPENDIX D REVISION HISTORY APPENDIX D REVISION HISTORY Major revisions by edition and revised chapters are shown below. Edition Major revisions from previous version Revised Chapter 2nd The following products have been already developed Throughout µ PD78081CU- ××× , 78081GB- ××× -3B4, 78082CU- ××× , 78082GB- ××× -3B4, 78P083CU, 78[...]

250 APPENDIX D REVISION HISTORY Edition Major revisions from previous version Revised Chapter 2nd Figure A-1. Development Tool Configuration has been changed. APPENDIX A DEVELOPMENT TOOLS APPENDIX A DEVELOPMENT TOOLS The following Development Tools have been added: IE-78000-R-A, IE-70000-98-IF-B, IE-70000-98-N-IF, IE-70000-PC-IF-B, IE-78000-R-SV3, [...]

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