Renesas SH7781 manual

Revision Date: Jan. 10 , 2008 32 Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH™ RISC Engine Family SH7780 Series Rev.1.00 REJ09B0261-0100 SH7785[...]

Rev.1.00 Jan. 10, 2008 Page ii of xxx REJ09B0261-0100 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor g rants[...]

Rev.1.00 Jan. 10, 2008 Page iii of xxx REJ09B0261-0100 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MP U/ MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manua l. If the descriptions under General Precautions[...]

Rev.1.00 Jan. 10, 2008 Page iv of xxx REJ09B0261-0100[...]

Rev.1.00 Jan. 10, 2008 Page v of xxx REJ09B0261-0100 Preface This LSI is a RISC (Reduced Instruction Set Co mput er) microcomp uter which includes a Renesas Technology- original RISC CPU (SH- 4A) and va rious pe ripheral fu nctions requi red to con figure a system. Target Users: This manual was written for users who will be u sing this LSI in the d[...]

Rev.1.00 Jan. 10, 2008 Page vi of xxx REJ09B0261-0100 Abbreviations ALU Arithmetic Logic Unit ASID Address Space Identifier BGA Ball Grid Array CMT Timer/Counter (Compare Mat ch Timer) CPG Clock Pulse Generat or CPU Central P rocessing Unit DDR Double Data R ate DDRIF DDR-SDRAM Interface DMA Direct Memory Access DMAC Direct Memory Access Controller[...]

Rev.1.00 Jan. 10, 2008 Page vii of xxx REJ09B0261-0100 MSB Most Significan t Bit PC Program Count er PCI Peripheral Compone nt Interconnect PCIC PCI (local bus) Controller PFC Pin Functi on Cont roller RISC Reduce d Instructi on Set Compute r RTC Realtime Clock SCIF Serial Communication Interface with FIFO SIOF Serial Interface with FIFO SSI Serial[...]

Rev.1.00 Jan. 10, 2008 Page viii of xxx REJ09B0261-0100 All trademarks and registered tradema rks ar e the property of th eir respective owners.[...]

Rev.1.00 Jan. 10, 2008 Page ix of xxx REJ09B0261-0100 Contents Section 1 Overview .................................................................................................................. 1 1.1 Features of t he SH 7785 ......................................................................................................... .1 1.2 Block Dia[...]

Rev.1.00 Jan. 10, 2008 Page x of xxx REJ09B0261-0100 5.2.2 Exce ption Event Regi ster (EXPEVT )................................................................... 91 5.2.3 Inter rupt Event Register (I NTEVT) ...................................................................... 92 5.2.4 Non-S upport Detection Excep tion Register (EXPMASK) .........[...]

Rev.1.00 Jan. 10, 2008 Page xi of xxx REJ09B0261-0100 7.1.1 Address Space s ................................................................................................... 146 7.2 Register Desc riptions ......................................................................................................... 1 52 7.2.1 Page Table Entry High Regi[...]

Rev.1.00 Jan. 10, 2008 Page xii of xxx REJ09B0261-0100 7.8.1 Ove rview of 32-Bit Addr es s Extended Mode ..................................................... 199 7.8.2 Transition t o 32-Bit Addr ess Extended Mode .................................................... 200 7.8.3 Privilege d Space Mapping Buffer (PMB) Config uration ...................[...]

Rev.1.00 Jan. 10, 2008 Page xiii of xxx REJ09B0261-0100 8.7 Store Que ues ................................................................................................................... ... 238 8.7.1 SQ C onfiguration ................................................................................................ 238 8.7.2 Writing to SQ .......[...]

Rev.1.00 Jan. 10, 2008 Page xiv of xxx REJ09B0261-0100 10.4 Interrupt Sourc es .............................................................................................................. .. 324 10.4.1 NMI Interrupts .................................................................................................... 324 10.4.2 IRQ Interr upts ...[...]

Rev.1.00 Jan. 10, 2008 Page xv of xxx REJ09B0261-0100 11.5.9 Bus Arbitration ................................................................................................... 448 11.5.10 Master Mo de ....................................................................................................... 450 11.5.11 Slave Mode .....................[...]

Rev.1.00 Jan. 10, 2008 Page xvi of xxx REJ09B0261-0100 12.5.11 Method for Se curing Time Re quired for Initialization, Self-Refresh Cancellation, etc. ................................................................................................ 549 12.5.12 Regarding the Suppor ted Clock Ratio .....................................................[...]

Rev.1.00 Jan. 10, 2008 Page xvii of xxx REJ09B0261-0100 14.4.2 Channel Prio rity .................................................................................................. 706 14.4.3 DMA Transfer Types .......................................................................................... 709 14.4.4 DMA Transfer Flow ....................[...]

Rev.1.00 Jan. 10, 2008 Page xviii of xxx REJ09B0261-0100 16.4.1 Reset Reque st ..................................................................................................... 769 16.4.2 Using Watchdog Ti mer Mode ............................................................................ 771 16.4.3 Using Interval Timer Mode .................[...]

Rev.1.00 Jan. 10, 2008 Page xix of xxx REJ09B0261-0100 18.3.4 Timer Control Registers (T CRn) ( n = 0 to 5) ..................................................... 807 18.3.5 Input Capture Regist er 2 (TCPR2) ..................................................................... 809 18.4 Operation ......................................................[...]

Rev.1.00 Jan. 10, 2008 Page xx of xxx REJ09B0261-0100 19.3.26 Color Palette 4 Transparent Co lor Register ( CP4TR) ........................................ 887 19.3.27 Display Off M ode Output Re gister (DOOR) ...................................................... 890 19.3.28 Color Detection Regi ster (C DE R) ......................................[...]

Rev.1.00 Jan. 10, 2008 Page xxi of xxx REJ09B0261-0100 19.4.12 Scroll Disp lay ..................................................................................................... 950 19.4.13 Wraparound Di splay ........................................................................................... 951 19.4.14 Upper-Left Overflow Display .....[...]

Rev.1.00 Jan. 10, 2008 Page xxii of xxx REJ09B0261-0100 20.3.21 MC Command FIFO (MCCF) .......................................................................... 1000 20.3.22 MC Status Regist er (MCS R) ............................................................................ 1003 20.3.23 MC Frame Width Setting Register (M CWR ) ................[...]

Rev.1.00 Jan. 10, 2008 Page xxiii of xxx REJ09B0261-0100 21.3.12 Serial Port Regist er n (SCS PTR) ...................................................................... 1066 21.3.13 Line Status Regist er n (SCLS R) ....................................................................... 1069 21.3.14 Serial Error Regist er n (SCRE R) ...............[...]

Rev.1.00 Jan. 10, 2008 Page xxiv of xxx REJ09B0261-0100 23.2 Input/Output P ins ............................................................................................................. 1 153 23.3 Register Desc riptions ....................................................................................................... 115 3 23.3.1 Control R[...]

Rev.1.00 Jan. 10, 2008 Page xxv of xxx REJ09B0261-0100 24.4.1 Operations in MMC Mode ................................................................................ 1209 24.5 MMCIF Interrupt Sources ................................................................................................ 1239 24.6 Operations when Using DM A.................[...]

Rev.1.00 Jan. 10, 2008 Page xxvi of xxx REJ09B0261-0100 26.4 Operation ...................................................................................................................... ... 1314 26.4.1 Bus Form at ....................................................................................................... 1314 26.4.2 Non-Compressed M[...]

Rev.1.00 Jan. 10, 2008 Page xxvii of xxx REJ09B0261-0100 Section 28 General Purpose I/O Ports (GPIO) ........................................................... 1377 28.1 Features ....................................................................................................................... ..... 1377 28.2 Register Desc riptions ...........[...]

Rev.1.00 Jan. 10, 2008 Page xxviii of xxx REJ09B0261-0100 28.2.37 Port L Pull-Up Control Register (P LPUPR ) ..................................................... 1438 28.2.38 Port M Pull-Up Control Register (P MPUPR) ................................................... 1439 28.2.39 Port N Pull-Up Control Register (P NPUPR) .........................[...]

Rev.1.00 Jan. 10, 2008 Page xxix of xxx REJ09B0261-0100 30.3.2 Interrupt Source Regi ster (S DINT) ................................................................... 1492 30.3.3 Bypass Register (SDB PR) ................................................................................ 1493 30.3.4 Boundary Scan Regist er (SDBSR) .....................[...]

Rev.1.00 Jan. 10, 2008 Page xxx of xxx REJ09B0261-0100 Appendix ............................................................................................................................ 162 7 A. Package Dime nsions ........................................................................................................ 1627 B. Mode Pin Settings .[...]

1. Overview Rev.1.00 Jan. 10, 2008 Page 1 of 1658 REJ09B0261-0100 Section 1 Overview The SH7785 incorporates a DDR2 -SDRAM interface, a PCI controll er, a DMA controller, timers, serial interfaces, audio interfa ces, a graphics da ta translation accelerator (GDTA) that supports YUV data c onversion and motion co mpensati on processing, a nd a dis p[...]

1. Overview Rev.1.00 Jan. 10, 2008 Page 2 of 1658 REJ09B0261-0100 Item Features CPU • Renesas Technology original architecture • 32-bit internal data bus • General-register files: ⎯ Sixteen 32-bit general registers (eight 32- bit shadow registers) ⎯ Seven 32-bit control registers ⎯ Four 32-bit system registers • RISC-type instruction [...]

1. Overview Rev.1.00 Jan. 10, 2008 Page 3 of 1658 REJ09B0261-0100 Item Features FPU • On-chip floating-point coprocessor • Supports single (32-bit) and double (64- bit) precisions • Supports IEEE754-compliant data types a nd exceptions • Two rounding modes: Round to Nearest and Round to Zero • Handling of denormalized nu mbers: Truncation[...]

1. Overview Rev.1.00 Jan. 10, 2008 Page 4 of 1658 REJ09B0261-0100 Item Features Memory management unit (MMU) • 4-Gbyte address space, 256 addr ess s pace identifiers (8-bit ASID) • Supports single virtual memory mode and multiple virtual m emory mode • Multiple page sizes: 1, 4, 8, 64, or 256 Kbytes, or 1, 4, or 64 Mbytes • 4-entry fully as[...]

1. Overview Rev.1.00 Jan. 10, 2008 Page 5 of 1658 REJ09B0261-0100 Item Features URAM • 128-Kbyte large-capacity memory • Three independent read/write ports • 8-/16-/32-bit access by the CPU or the FPU • 8-/16-/32-bit access by the DMAC Interrupt controller (INTC) • Nine independent external int errupts: NMI and IRQ7 to IRQ0 ⎯ NMI: Falli[...]

1. Overview Rev.1.00 Jan. 10, 2008 Page 6 of 1658 REJ09B0261-0100 Item Features Local bus state controller (LBSC) • A dedicated Local-bus interfac e ⎯ Controls the external memory space divid ed into seven 64-Mbyte (max.) areas ⎯ The interface type, bus width, and wa it-cycle insertio n can be set for each area. • SRAM interface ⎯ Wait-cy[...]

1. Overview Rev.1.00 Jan. 10, 2008 Page 7 of 1658 REJ09B0261-0100 Item Features DDR2-SDRAM bus controller (DBSC) • A dedicated DDR2-SDRAM bus interface ⎯ Multi-bank support: Supports mult i-bank (fou r banks) operation ⎯ Number of banks: Supports four or eight banks (however, no more than four banks can be opened conc urrently) ⎯ Selectable[...]

1. Overview Rev.1.00 Jan. 10, 2008 Page 8 of 1658 REJ09B0261-0100 Item Features PCI bus controller (PCIC) • PCI bus controller (supports a subset of revision 2.2) ⎯ 32-bit bus (33 MHz or 66 MHz) • Operation as PCI master/target • Operation in PCI host/normal mode ⎯ Built-in bus arbiter (host mode) • Operates with up to four external bus[...]

1. Overview Rev.1.00 Jan. 10, 2008 Page 9 of 1658 REJ09B0261-0100 Item Features Watchdog timer (WDT) • Number of channels: One • Single-channel watchdog time r (operation in watchdog-timer or interval-tim er mode is selectable) • Selectable reset function: Power-on or manual res et Timer unit (TMU) • Number of channels: Six • 6-channel au[...]

1. Overview Rev.1.00 Jan. 10, 2008 Page 1 0 of 1658 REJ09B0261-0100 Item Features Display unit (DU) • Display plane ⎯ 6 planes (a maximum number at 480 dots x 234 dots) ⎯ 4 planes (a maximum number at 854 dots x 480 dots) ⎯ 3 planes (a maximum number at 800 dots x 600 dots) • CRT scanning method: Non-interlac ed, interlaced, interlaced sy[...]

1. Overview Rev.1.00 Jan. 10, 2008 Page 1 1 of 1658 REJ09B0261-0100 Item Features Synchronized serial I/O with FIFO (SIOF) • Number of channels: One (max.) • Supports full-duplex operatio n • Separate 64-byte (32 bits x 16) FI FOs for transmission and recepti on • Supports the input and output of 8-/16-bit mo naural and 16-bit stereophonic [...]

1. Overview Rev.1.00 Jan. 10, 2008 Page 1 2 of 1658 REJ09B0261-0100 Item Features Serial sound interface (SSI) • Number of channels: Two (max.) • Supports transfer of compressed and non-co mpressed data • Selectable frame size NAND flash memory controller (FLCTL) • Number of channels: One (max.) • Exclusively for NAND-type flash memory ?[...]

1. Overview Rev.1.00 Jan. 10, 2008 Page 1 3 of 1658 REJ09B0261-0100 1.2 Block Diagram A block diagram of t he SH7785 is give n as figure 1.1. ROM NOR Flash PC Card/ATA3 DDR2-SDRAM DDR2-400/600 1 GB max SH-4A Superscalar CPU FPU MMU 32 KB I-cache 32 KB O-cache 8 KB ILRAM 16 KB OLRAM 32 bit/16 bit 300 MHz 32 bit 33/66 MHz PCI bus 64 * /32/16 /8 bit 1[...]

1. Overview Rev.1.00 Jan. 10, 2008 Page 1 4 of 1658 REJ09B0261-0100 1.3 Pin Arrangement Table Table 1.2 Pin Function No. Pin Name I/O Function No. Pin Name I/O Function 1 MDQ0 IO DDR data 0 28 MDQ27 IO DDR data 27 2 MDQ1 IO DDR data 1 29 MDQ28 IO DDR data 28 3 MDQ2 IO DDR data 2 30 MDQ29 IO DDR data 29 4 MDQ3 IO DDR data 3 31 MDQ30 IO DDR data 30 5[...]

1. Overview Rev.1.00 Jan. 10, 2008 Page 1 5 of 1658 REJ09B0261-0100 No. Pin Name I/O Function No. Pin Name I/O Function 55 MA10 O DDR address 10 87 D12 IO Local bus data 12 56 MA11 O DDR address 11 88 D13 IO Local bus data 13 57 MA12 O DDR address 12 89 D14 IO Local bus data 14 58 MA13 O DDR address 13 90 D15 IO Local bus data 15 59 MA14 O DDR addr[...]

1. Overview Rev.1.00 Jan. 10, 2008 Page 1 6 of 1658 REJ09B0261-0100 No. Pin Name I/O Function No. Pin Name I/O Function 119 A12 O Local bus a ddress 12 140 RD / FRAME O/O Read strobe/MPX IF FRAME 120 A13 O Local bus a ddress 13 141 R/ W O Read/Write 121 A14 O Local bus a ddress 14 142 BS O Bus start 122 A15 O Local bus a ddress 15 143 WE0 / REG O/O[...]

1. Overview Rev.1.00 Jan. 10, 2008 Page 1 7 of 1658 REJ09B0261-0100 No. Pin Name I/O Function No. Pin Name I/O Function 155 D37/AD5/DR5 IO/IO/O Loc al bus data 37/PCI address data 5/Digital red 5 168 D50/AD18 IO/IO Local bus data 50/PCI address data 18 156 D38/AD6/DG0 IO/IO/O Local bus data 38/PCI address data 6/Digital green 0 169 D51/AD19 IO/IO L[...]

1. Overview Rev.1.00 Jan. 10, 2008 Page 1 8 of 1658 REJ09B0261-0100 No. Pin Name I/O Function No. Pin Name I/O Function 181 D63/AD31 IO/IO Local bus d ata 63/PCI address data 31 199 REQ2 I Bus request 2 (PCI host) 182 WE4 / CBE0 O/IO Write enable 4/PCI command/byte enable 0 200 REQ3 I Bus request 3 (PCI host) 183 WE5 / CBE1 O/IO Write enable 5/PCI [...]

1. Overview Rev.1.00 Jan. 10, 2008 Page 1 9 of 1658 REJ09B0261-0100 No. Pin Name I/O Function No. Pin Name I/O Function 217 BREQ / BSACK I Bus request (Master mode)/ Bus acknowledgement (Slave mode) 233 ASEBRK / BRKACK I H-UDI emulator 218 BACK / BSREQ O Bus acknowledgement (Master mode)/Bus request (Slave mode) 234 AUDCK O H-UDI emulator clock 219[...]

1. Overview Rev.1.00 Jan. 10, 2008 Page 2 0 of 1658 REJ09B0261-0100 No. Pin Name I/O Function No. Pin Name I/O Function 249 SIOF_SCK/ HAC0_BITCLK/ SSI0_CLK IO/I/IO SIOF serial clock/HAC0 bit clock/SSI0 serial bit clock 256 SCIF5_RXD/ HAC1_SDIN/ SSI1_SCK I/I/IO SCIF5 receive data/HAC1 serial data/SSI1 serial data 250 SIOF_MCLK/ HAC_RES I/O SIOF mast[...]

1. Overview Rev.1.00 Jan. 10, 2008 Page 2 1 of 1658 REJ09B0261-0100 No. Pin Name I/O Function No. Pin Name I/O Function 269 MODE11/ SCIF4_SCK/ FD3 I/IO/IO Mode control 11/SCIF4 serial clock/NAND flash data 3 274 MRESETOUT / IRQOUT O/O Manual reset output/Interrupt req uest output 270 MODE12/ DRAK3/ CE2B I/O/O Mode control 12/DMA channel 3 transfer [...]

1. Overview Rev.1.00 Jan. 10, 2008 Page 2 2 of 1658 REJ09B0261-0100 1.4 Pin Arrangement Package: 436-p in FC-BGA, 19 mm x 19 mm, ball pitch: 0.8 mm A B C D E F G H J K L M N P R T U V W Y AA A B C D E F G H J K L M N P R T U V W Y AA AB AB 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 [...]

1. Overview Rev.1.00 Jan. 10, 2008 Page 2 3 of 1658 REJ09B0261-0100 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 VSS A25 SCIF5_TXD /HAC1_ SYNC/SSI1_ WS SCIF5_SCK /HAC1_SD OUT/SSI1_ SDATA SIOF_MCLK / HAC_RES SIOF_TXD/ HAC0_SDO UT/SSI0_ SDATA SCIF1_ TXD SCIF1_ SCK SCIF0_SC[...]

1. Overview Rev.1.00 Jan. 10, 2008 Page 2 4 of 1658 REJ09B0261-0100 1.5 Physical Memory Address Map The SH7785 supports 32-bit virtual address space, and suppor ts both 29-bit and 32-bit physical address spaces. For details of ma ppings from the virtual addre ss space to the physical address spaces, see section 7, Memory Ma nagement Unit (MMU). Fig[...]

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 2 5 of 1658 REJ09B0261-0100 Section 2 Programming Model The programm ing model of this LSI i s explained in t his section. T h is LSI h as registers an d data formats as shown bel ow. 2.1 Data Formats The data forma ts supported i n this LSI are shown i n figure 2 .1. Byte (8 bits) Word (16 bits) Lon[...]

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 2 6 of 1658 REJ09B0261-0100 2.2 Register Descriptions 2.2.1 Privileged Mode and Banks (1) Processing Modes This LSI has two processing modes, user m ode and pri vileged mode . This LSI normally operates in user mode, and switches to pr ivileged mode when an exception occurs or an interrupt is accepte[...]

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 2 7 of 1658 REJ09B0261-0100 (DBR), whic h can only be accessed in privil eged mode. Some bits of the status register (s uch as the RB bit) can only be acce ssed in privileged mode. (4) System Registers System registers comprise the multiply-and-accumulate register s (M ACH/MACL), the procedure regist[...]

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 2 8 of 1658 REJ09B0261-0100 Table 2.1 Initial Register Va lues Type Registers Initial Value * General registers R0_BANK0 to R7_BANK0, R0_BANK1 to R7_BANK1, R8 to R15 Undefined SR MD bit = 1, RB bit = 1, BL bit = 1, FD bit = 0, IMASK = B'1111, reserved bits = 0, others = undefined GBR, SSR, SPC, [...]

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 2 9 of 1658 REJ09B0261-0100 31 0 R0 _ BANK0 * 1, * 2 R1 _ BANK0 * 2 R2 _ BANK0 * 2 R3 _ BANK0 * 2 R4 _ BANK0 * 2 R5 _ BANK0 * 2 R6 _ BANK0 * 2 R7 _ BANK0 * 2 R8 R9 R10 R11 R12 R13 R14 R15 SR GBR MACH MACL PR PC (a) Re g ister confi g uration in user mode 31 0 R0 _ BANK1 * 1, * 3 R1 _ BANK1 * 3 R2 _ B[...]

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 3 0 of 1658 REJ09B0261-0100 2.2.2 General Re gisters Figure 2.3 s hows the relat ionship bet ween the processi ng modes an d general regi sters. This L SI has twenty-fo ur 32-bit general registers (R 0_BANK0 t o R7_BANK 0, R0_BAN K1 to R7_BANK1, and R8 to R15). Howeve r, only 16 of these can be acces[...]

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 3 1 of 1658 REJ09B0261-0100 Note on Pr ogrammin g: As the user's R 0 to R7 are a ssigned to R0_BAN K0 to R7_ BANK0, an d after an except ion or interrupt R0 to R7 are assigned t o R0_BANK1 to R7_BANK1, i t is not necessary for the interrupt handle r to save an d restore the use r's R0 to R [...]

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 3 2 of 1658 REJ09B0261-0100 7. Single -precision float ing-poin t extended regi ster matrix, XMTRX: XMT RX comprises all 16 XF registers. XMTRX = XF0 XF4 XF8 XF12 XF1 XF5 XF 9 XF13 XF2 XF6 XF10 XF14 XF3 XF7 XF11 XF15 FPR0_BANK0 FPR1_BANK0 FPR2_BANK0 FPR3_BANK0 FPR4_BANK0 FPR5_BANK0 FPR6_BANK0 FPR7_BA[...]

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 3 3 of 1658 REJ09B0261-0100 2.2.4 Contr ol Registers (1) Status Register (S R) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BIt: 0111000000000000 MD RB BL FD M Q IMASK S T Initial value: R R / W R / W R / W RRRRRRRRRRRR R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BIt: 0000000011110000 Initial value[...]

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 3 4 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 27 to 16 — All 0 R Reserved For details on reading/writing this bit, see Ge neral Precautions on Handling of Product. 15 FD 0 R/W FPU Disable Bit When this bit is set to 1 and an FPU instruction is not in a delay slot, a general[...]

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 3 5 of 1658 REJ09B0261-0100 (2) Saved Status Register (SSR) (32 bi ts, Privileged Mode, Initial Value = Undefined) The contents of SR are sa ved to SSR in the event of an excep tion or interrupt. (3) Saved Progra m Counter (SPC) (32 bits, Priv ileged Mode, Initial Val ue = Undefined) The address of a[...]

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 3 6 of 1658 REJ09B0261-0100 (4) Floating-P oint Status/Contr ol Register (FPSCR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0000000000000100 RRRRRRRRRR R / W R / W R / W R / W R / W R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000001 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W[...]

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 3 7 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 17 to 12 Cause 000000 R/W 11 to 7 Enable (EN) 00000 R/W 6 to 2 Flag 00000 R/W FPU Exception Cause Field FPU Exception Enable Field FPU Exception Flag Field Each time an FPU operation in struction is ex ecuted, the FPU exception ca[...]

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 3 8 of 1658 REJ09B0261-0100 <Bi g endian> DR (2i) FR (2i) FR (2i+1) 8n+4 8n+7 8n 8n+3 63 0 63 32 31 0 Floatin g -point re g ister Memory area 63 0 <Little endian> Floatin g -point re g ister Memory area DR (2i) FR (2i) FR (2i+1) 4n 4m 4n+3 4m+3 63 0 63 32 31 0 DR (2i) FR (2i+1) FR (2i) 8n[...]

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 3 9 of 1658 REJ09B0261-0100 2.3 Memory-Mapped Registers Some control r egisters are ma pped to the following mem ory areas. Each of the mapped registers has two addresses. H'1C00 0000 to H'1FFF FFFF H'FC00 0000 to H'FFFF FFFF These two areas are use d as follows. • H'1C00 0[...]

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 4 0 of 1658 REJ09B0261-0100 2.4 Data Formats in Registers Register opera nds are always longwords (32 bi ts). When a memory ope rand is only a by te (8 bits) or a word (16 bits), it is sign-extended into a longw ord when loaded into a register. 31 SS S 0 6 7 6 7 0 31 SS S 0 14 15 14 15 0 Figure 2.6 F[...]

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 4 1 of 1658 REJ09B0261-0100 Address A A 70 7 0 70 7 0 31 15 0 15 0 31 0 15 0 31 0 23 15 7 0 A + 1 A + 2 A + 3 Byte 0 Word 0 Lon g word Word 1 Byte 1 Byte 2 Byte 3 A + 11 70 7 0 70 7 0 31 15 0 23 15 7 0 A + 10 A + 9 A + 8 Byte 3 Word 1 Lon g word Word 0 Byte 2 Byte 1 Byte 0 Address A + 4 Address A + 8[...]

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 4 2 of 1658 REJ09B0261-0100 From any state when reset/manual reset input Reset state Instruction execution state Sleep instruction execution Power-down state Interrupt occurence Reset/manual reset clearance Reset/manual reset input Reset/manual reset input Figure 2.8 Pr ocessing State Transitions[...]

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 4 3 of 1658 REJ09B0261-0100 2.7 Usage Notes 2.7.1 Notes on Self-Modifying Code To accelerate the processing speed , the instruction prefetching cap ability of this LSI has been significantl y enhanced from that of t h e SH-4. T h erefore, in the case when a code in memory is rewritten and a ttempted [...]

2. Programming Model Rev.1.00 Jan. 10, 2008 Page 4 4 of 1658 REJ09B0261-0100[...]

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 4 5 of 1658 REJ09B0261-0100 Section 3 Instruction Set This LSI's instruction set is imp lemented with 16-bit fixe d-length instructi ons. This L SI can use byte (8-bit), w ord (16-bit ), longword (3 2-bit), an d quadwor d (64-bit) data sizes for memory access. Single-precision floati ng- point dat[...]

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 4 6 of 1658 REJ09B0261-0100 Table 3.1 Execution Order of Delayed Branch Instructions Instructions Execution Order BRA TARGET (Delayed branc h instruction) BRA ADD (Delay slot) ↓ : ADD : ↓ TARGET target-inst (Branch dest ination instruction) target-inst A slot illegal instructio n exception may occu[...]

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 4 7 of 1658 REJ09B0261-0100 3.2 Addressing Modes Addressing modes and effective address calculation methods are shown in tabl e 3.2. When a location in virtual memory space is accessed (A T in MMUCR = 1), t he effective address is translated into a physical memory addre ss. If multiple virtual memory s[...]

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 4 8 of 1658 REJ09B0261-0100 Addressing Mode Instruction Format Effective Address Calculation Method Calculation Formula Register indirect with pre- decrement @–Rn Effective address is register R n contents, decremented by a constant beforehand: 1 for a byte operand, 2 for a word operand, 4 for a long[...]

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 4 9 of 1658 REJ09B0261-0100 Addressing Mode Instruction Format Effective Address Calculation Method Calculation Formula GBR indirect with displace- ment @(disp:8, GBR) Effective address is register GBR contents with 8-bit displacement disp added . After disp is zero-extended, it is multiplied by 1 (byt[...]

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 5 0 of 1658 REJ09B0261-0100 Addressing Mode Instruction Format Effective Address Calculation Method Calculation Formula PC-relative disp:8 Effective address is PC + 4 with 8-bit displacement disp added after being sign-e xtended and multiplied by 2. 2 + × disp (si g n-extended) 4 + PC PC + 4 + disp ×[...]

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 5 1 of 1658 REJ09B0261-0100 Addressing Mode Instruction Format Effective Address Calculation Method Calculation Formula Immediate #imm:8 8-bit immediate dat a imm of TST, AND, OR, or XOR instruction is zero-extended. — #imm:8 8-bit immediate data i mm of MOV, ADD, or CMP/EQ instruction is sign-extend[...]

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 5 2 of 1658 REJ09B0261-0100 3.3 Instruction Set Table 3.3 sho ws the notat ion used i n the SH i nstruction li sts shown i n tables 3.4 to 3.13. Table 3.3 Notation Used in Instruction List Item Format Description Instruction mnemonic OP.Sz SRC, DEST OP: Operation code Sz: Size SRC: Source operand DEST:[...]

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 5 3 of 1658 REJ09B0261-0100 Item Format Description Privileged mode "Privileged" means the instruction ca n only be executed in privileged mode. T bit Value of T bit after instruction execution —: No change New ⎯ "New" means the instruction which has been newly added in the SH-4[...]

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 5 4 of 1658 REJ09B0261-0100 Instruction Operation Instruction C ode Privileged T Bit New MOV.B @(disp * ,Rm),R0 (disp + Rm) → sign extension → R0 10000100mmmmdddd — — — MOV.W @(disp * ,Rm),R0 (disp × 2 + Rm) → sign extension → R0 10000101mmmmdddd — — — MOV.L @(disp * ,Rm),R n (disp[...]

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 5 5 of 1658 REJ09B0261-0100 Instruction Operation Instructio n Code Privileged T Bit New MOVT Rn T → Rn 0000nnnn00101001 — — — SWAP.B Rm,Rn Rm → swap lower 2 bytes → Rn 0110nnnnmmmm1000 — — — SWAP.W Rm,Rn Rm → swap upper /lower words → Rn 0110nnnnmmmm1001 — — — XTRCT Rm,Rn R[...]

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 5 6 of 1658 REJ09B0261-0100 Instruction Operation Instructio n Code Privileged T Bit New CMP/STR Rm,Rn When any bytes are equal, 1 → T Otherwise, 0 → T 0010nnnnmmmm1100 — Comparison result — DIV1 Rm,Rn 1-step division (Rn ÷ Rm) 0011nnnnmmmm0100 — Calculation result — DIV0S Rm,Rn MSB of Rn [...]

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 5 7 of 1658 REJ09B0261-0100 Instruction Operation Instructio n Code Privileged T Bit New MULU.W Rm,Rn Unsigned, Rn × Rm → MACL 16 × 16 → 32 bits 0010nnnnmmmm1110 — — — NEG Rm,Rn 0 – Rm → Rn 0110nnnnmmmm1011 — — — NEGC Rm,Rn 0 – Rm – T → Rn, borrow → T 0110nnnnmmmm1010 — [...]

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 5 8 of 1658 REJ09B0261-0100 Instruction Operation Instructio n Code Privileged T Bit New XOR #imm,R0 R0 ∧ imm → R0 11001010iiiiiiii — — — XOR.B #imm, @(R0,GBR) (R0 + GBR) ∧ imm → (R0 + GBR) 11001110iiiiiiii — — — Table 3.7 Shift Instructions Instruction Operation Instructio n Code P[...]

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 5 9 of 1658 REJ09B0261-0100 Table 3.8 Branch Instructions Instruction Operation Instruction C ode Privileged T Bit New BF label When T = 0, disp × 2 + PC + 4 → PC When T = 1, nop 10001011dddddddd — — — BF/S label Delayed branch; when T = 0, disp × 2 + PC + 4 → PC When T = 1, nop 10001111ddd[...]

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 6 0 of 1658 REJ09B0261-0100 Instruction Operation Instructio n Code Privileged T Bit New LDC Rm,SSR Rm → SSR 0100mmmm00111110 Privileged — — LDC Rm,SPC Rm → SPC 0100mmmm01001110 Privileged — — LDC Rm,DBR R m → DBR 0100mmmm11111010 Privileged — — LDC Rm,Rn_BANK Rm → Rn_BANK (n = 0 to[...]

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 6 1 of 1658 REJ09B0261-0100 Instruction Operation Instructio n Code Privileged T Bit New SETS 1 → S 0000000001011000 — — — SETT 1 → T 0000000000011000 — 1 — SLEEP Sleep or standby 0000000000011011 Privileged — — STC SR,Rn SR → Rn 0000nnnn00000010 Privileged — — STC GBR,Rn GBR ?[...]

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 6 2 of 1658 REJ09B0261-0100 Instruction Operation Instructio n Code Privileged T Bit New SYNCO Data acce sses invoked by the following instructions are not executed until execution of data accesses which precede this instruction has been completed. 0000000010101011 ⎯ ⎯ New TRAPA #imm PC + 2 → SPC[...]

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 6 3 of 1658 REJ09B0261-0100 Instruction Operation Instruction Cod e Privileged T Bit New FADD FRm,FRn FRn + FRm → FRn 1111nnnnmmmm0000 — — — FCMP/EQ FRm,FRn When FRn = FRm, 1 → T Otherwise, 0 → T 1111nnnnmmmm0100 — Comparis on result — FCMP/GT FRm,F Rn When FRn > FRm, 1 → T Otherwi[...]

3. Instruction Set Rev.1.00 Jan. 10, 2008 Page 6 4 of 1658 REJ09B0261-0100 Table 3.12 Floating-Point Contr ol Instructions Instruction Operation Instructio n Code Privileged T Bit New LDS Rm,FPSCR Rm → FPS CR 0100mmmm01101010 — — — LDS Rm,FPUL Rm → FPUL 0100mmmm01011010 — — — LDS.L @Rm+,FPSCR (Rm) → FPSCR, Rm+4 → Rm 0100mmmm0110[...]

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 6 5 of 1658 REJ09B0261-0100 Section 4 Pipelining This LSI is a 2-ILP (instruction-level-paralle lism) supe rscalar pi pelining mi croprocessor. Instruction e x ecution i s pipelined, a n d two i nstructions can be executed i n parallel . 4.1 Pipelines Figure 4.1 s hows the basic pi pelines. Normally, a pipe[...]

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 6 6 of 1658 REJ09B0261-0100 Figure 4.2 s hows the inst ruction execution p atterns. Repre sentations in figure 4.2 and their descriptions ar e listed in ta ble 4.1. Table 4.1 Representations of Instruction Execution Patterns Representation Description E1 E2 E3 WB CPU EX pipe is occupied S1 S2 S3 WB CPU LS p[...]

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 6 7 of 1658 REJ09B0261-0100 I1 I2 I3 (I1) (ID) ID E1/S1 E2/s2 E3/s3 WB I3 I3 I3 (I2) (I3) I1 I2 ID E1/S1 E2/S2 E3/S3 WB I1 I2 ID E1/S1 E2/S2 E3/S3 WB I1 I2 ID s1 s2 s3 WB E2s2 ID E3s3 ID WB ID I1 I2 I3 ID S1 S2 S3 WB E1s1 E3s3 E2s2 E1s1 E1s1 E1s1 E1s1 E2s2 E2s2 E2s2 E2s2 E3s3 E3s3 E3s3 E3s3 WB WB WB WB E2s2[...]

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 6 8 of 1658 REJ09B0261-0100 I3 I3 I3 I1 I2 ID s1 s2 s3 WB I1 I2 ID WB I1 I2 ID E1/S1 E2/s2 E3/s3 E1/s1 E2/s2 E3/S3 WB I1 I2 I3 ID E1 E2 E3 WB (2-1) 1-step operation (EX type): 1 issue cycle (2-2) 1-step operation (LS type): 1 issue cycle (2-3) 1-step operation (MT type): 1 issue cycle (2-4) MO V (MT type): [...]

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 6 9 of 1658 REJ09B0261-0100 I1 I2 I3 ID S1 S2 S3 WB I3 I3 I3 I3 I1 I2 ID S1 S2 S3 WB I1 I2 ID S1 S2 S3 WB E2S2 E3S3 WB E1S1 I1 I2 ID S1 S2 S3 WB E2S2 E3S3 WB E1S1 E2S2 E3S3 WB E1S1 E2s2 E3s3 E1s1 I1 I2 ID WB I1 I2 I3 ID s1 s2 s3 WB I1 I2 I3 ID S1 S2 S3 WB I3 I3 I1 I2 ID S1 S2 S3 WB I1 I2 ID S1 S2 S3 WB S1 S[...]

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 7 0 of 1658 REJ09B0261-0100 I1 I2 I3 ID s1 s2 s3 WB I3 I3 I3 I3 I3 I3 I3 I1 I2 ID s1 s2 s3 WB I1 I2 ID s1 s2 s3 WB I1 I2 ID S1 S2 S3 WB I1 I2 ID E1s1 E2s2 E3s3 WB I1 I2 ID S1 S2 S3 WB ID ID ID I1 I2 ID E1S1 E2S2 E3S3 WB ID ID ID ID ID I1 I2 ID S1 S2 S3 WB (I1) (ID) (I2) (I3) (I1) (ID) (I2) (I3) ID ID ID ID [...]

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 7 1 of 1658 REJ09B0261-0100 I1 I2 I3 ID s1 s2 s3 WB I3 I3 I3 I3 I3 I3 I3 I1 I2 ID WB I1 I2 ID S1 S2 S3 E1s1 E2s2 E3s3 WB I1 I2 ID WB I1 I2 ID S1 S2 S3 E1S1 E2S2 E3S3 WB I1 I2 ID s1 s2 s3 WB I1 I2 ID s1 s2 s3 WB I1 I2 ID S1 S2 S3 WB (I1) (I2) (I3) (ID) (??1) (??2) (??3) (WB) (4-9) STC from DBR/GBR/Rp_BANK/SS[...]

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 7 2 of 1658 REJ09B0261-0100 I1 I2 I3 ID s1 s2 s3 WB MS I3 I3 I3 I3 I3 I3 I3 I3 I1 I2 ID E1 M2 M3 E1 M2 M3 MS E1 M2 M3 MS M2 M3 MS I1 I2 ID I1 I2 ID S1 S2 S3 WB S1 S2 S3 WB I1 I2 ID I1 I2 ID s1 s2 s3 WB MS I1 I2 ID S1 S2 S3 WB MS I1 I2 ID S1 S2 S3 WB MS M2 M3 MS M2 M3 MS M2 M3 I1 I2 ID S1 S2 S3 WB S1 S2 S3 W[...]

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 7 3 of 1658 REJ09B0261-0100 I1 I2 I3 ID s1 s2 s3 s1 s2 s3 WB s1 s2 s3 WB FS1 FS2 FS3 FS4 FS1 FS2 FS3 FS4 FS FS1 FS2 FS3 FS4 FS1 FS2 FS3 FS4 FS1 FS2 FS3 FS4 FS FS1 FS2 FS3 FS4 FS FS1 FS2 FS3 FS4 FS1 FS2 FS3 FS4 FS FS1 FS2 FS3 FS4 FS I3 I3 I3 I3 I3 I3 I3 I3 I3 I3 I1 I2 ID I1 I2 ID S1 S2 S3 WB S1 S2 S3 S1 S2 S[...]

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 7 4 of 1658 REJ09B0261-0100 I1 I2 I3 ID s1 s2 s3 FS1 FS2 FS3 FS4 FS I1 I2 I3 ID I1 I2 I3 ID s1 s2 s3 FS1 FS2 FS3 FS4 FE1 FE2 FE3 FE4 FE5 FE6 FS I1 I2 I3 ID FE1 FE2 FE3 FE4 FE5 FE6 FS FE1 FE2 FE3 FE4 FE5 FE6 FE1 FE2 FE3 FE4 FE5 FE6 FS FE1 FE2 FE3 FE4 FE5 FE6 FS FE3 FE4 FE5 FE6 FS FE3 FE4 FE5 FE6 FS FE1 FE2 F[...]

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 7 5 of 1658 REJ09B0261-0100 I1 I2 I3 ID FE1 FE2 FE3 FEPL FEPL FE4 FE5 FE6 FS I1 I2 I3 ID FE1 FE2 FE3 FE4 FE5 FE6 FS I1 I2 I3 ID FE1 FE2 FE1 FE2 FE3 FE4 FE5 FE6 FS FE3 FE4 FE5 FE6 FS FE1 FE2 FE3 FE4 FE5 FE6 FS FE1 FE2 FE3 FE4 FE5 FE6 I1 I2 I3 ID FE1 FE2 FE1 FE2 FE3 FE4 FE5 FE6 FS FE3 FE4 FE5 FE6 FS FE1 FE2 F[...]

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 7 6 of 1658 REJ09B0261-0100 4.2 Parallel-Executability Instructions are categorized into six groups according to the inte rnal function bl ocks used, as shown in tabl e 4.2. Table 4.3 shows t he paral lel-executabili ty of pairs o f instructions i n terms of groups. Fo r example, A DD in the EX group and BR[...]

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 7 7 of 1658 REJ09B0261-0100 Instruction Group Instruction FE FADD FSUB FCMP (S/D) FCNVDS FCNVSD FDIV FIPR FLOAT FMAC FMUL FRCHG FSCHG FSQRT FTRC FTRV FSCA FSRRA FPCHG CO AND.B #imm,@(R0,GBR) ICBI LDC Rm,DBR LDC Rm, SGR LDC Rm,SR LDC.L @Rm+,DBR LDC.L @Rm+,SGR LDC.L @Rm+,SR LDTLB MAC.L MAC.W MOVCO MOVLI OR.B [...]

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 7 8 of 1658 REJ09B0261-0100 Table 4.3 Combination of Precedin g and Following Instructions Preceding Instruction (addr) EX MT BR LS FE CO EX No Yes Yes Yes Yes MT Yes Yes Yes Yes Yes Following Instruction (addr + 2) BR Yes Yes No Yes Yes LS Yes Yes Yes No Yes FE Yes Yes Yes Yes No CO No[...]

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 7 9 of 1658 REJ09B0261-0100 4.3 Issue Rates and Execution Cycles Instruction execution cycles a re summarized in table 4. 4. Instruction Gro up in the ta ble 4.4 corresponds to the category in th e table 4.2. Penalt y cycles due t o a pipeli ne stall are not considered in the issue rates a nd ex ecution cyc[...]

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 8 0 of 1658 REJ09B0261-0100 Table 4.4 Issue Rates and Execution Cycles Functional Category No. Instruction Instruction Group Issue Rate Execution Cycles Execution Pattern 1 EXTS.B Rm,Rn EX 1 1 2-1 2 EXTS.W Rm,Rn EX 1 1 2-1 3 EXTU.B Rm,Rn EX 1 1 2-1 4 EXTU.W Rm,Rn EX 1 1 2-1 5 MOV Rm,Rn MT 1 1 2-4 6 MOV #imm[...]

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 8 1 of 1658 REJ09B0261-0100 Functional Category No. Instruction Instruction Group Issue Rate Execution Cycles Execution Pattern 30 MOV.L Rm,@-Rn LS 1 1 3-1 31 MOV.B R0,@(disp,Rn) LS 1 1 3-1 32 MOV.W R0,@(disp,Rn ) LS 1 1 3-1 33 MOV.L Rm,@(disp,Rn) LS 1 1 3-1 34 MOV.B Rm,@(R0,Rn) LS 1 1 3-1 35 MOV.W Rm,@(R0,[...]

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 8 2 of 1658 REJ09B0261-0100 Functional Category No. Instruction Instruction Group Issue Rate Execution Cycles Execution Pattern 60 CMP/GT Rm,Rn EX 1 1 2-1 61 CMP/HI Rm,Rn EX 1 1 2-1 62 CMP/HS Rm,Rn EX 1 1 2-1 63 CMP/PL Rn EX 1 1 2-1 64 CMP/PZ Rn EX 1 1 2-1 65 CMP/STR Rm,Rn EX 1 1 2-1 66 DIV0S Rm,Rn EX 1 1 2[...]

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 8 3 of 1658 REJ09B0261-0100 Functional Category No. Instruction Instruction Group Issue Rate Execution Cycles Execution Pattern 90 TST Rm,Rn EX 1 1 2-1 91 TST #imm,R0 EX 1 1 2-1 92 TST.B #imm,@(R0,GBR) CO 3 3 3-2 93 XOR Rm,Rn EX 1 1 2-1 94 XOR #imm,R0 EX 1 1 2-1 Logical instructions 95 XOR.B #imm,@(R0,GBR) [...]

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 8 4 of 1658 REJ09B0261-0100 Functional Category No. Instruction Instruction Group Issue Rate Execution Cycles Execution Pattern 120 JMP @Rn BR 1+3 1 1-2 121 JSR @Rn BR 1+3 1 1-2 Branch instructions 122 RTS BR 1+0 to 3 1 1-3 123 NOP MT 1 1 2-3 124 CLRMAC EX 1 1 5-7 125 CLRS EX 1 1 2-1 126 CLRT EX 1 1 2-1 127[...]

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 8 5 of 1658 REJ09B0261-0100 Functional Category No. Instruction Instruction Group Issue Rate Execution Cycles Execution Pattern 150 LDC.L @Rm+,SPC LS 1 1 4-5 151 LDC.L @Rm+,VBR LS 1 1 4-5 152 LDS Rm,MACH LS 1 1 5-1 153 LDS Rm,MACL LS 1 1 5-1 154 LDS Rm,PR LS 1 1 4-13 155 LDS.L @Rm+,MACH LS 1 1 5-2 156 LDS.L[...]

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 8 6 of 1658 REJ09B0261-0100 Functional Category No. Instruction Instruction Group Issue Rate Execution Cycles Execution Pattern 180 FLDI0 FRn LS 1 1 6-13 181 FLDI1 FRn LS 1 1 6-13 182 FMOV FRm,FRn LS 1 1 6-9 183 FMOV.S @Rm,FRn LS 1 1 6-9 184 FMOV.S @Rm+,FRn LS 1 1 6-9 185 FMOV.S @(R0,Rm),F Rn LS 1 1 6-9 186[...]

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 8 7 of 1658 REJ09B0261-0100 Functional Category No. Instruction Instruction Group Issue Rate Execution Cycles Execution Pattern 210 FABS DRn LS 1 1 6-12 211 FADD DRm,DRn FE 1 1 6-16 212 FCMP/EQ DRm,DRn FE 1 1 6-16 213 FCMP/GT DRm,DRn FE 1 1 6-16 214 FCNVDS DRm,FPUL FE 1 1 6-16 215 FCNVSD FPUL,DRn FE 1 1 6-1[...]

4. Pipelining Rev.1.00 Jan. 10, 2008 Page 8 8 of 1658 REJ09B0261-0100 Functional Category No. Instruction Instruction Group Issue Rate Execution Cycles Execution Pattern 241 FRCHG FE 1 1 6-14 242 FSCHG FE 1 1 6-14 243 FPCHG FE 1 1 6-14 244 FSRRA FRn FE 1 1 6-21 Graphics acceleration instructions 245 FSCA FPUL,DRn FE 1 3 6-22 246 FTRV XMTRX,FVn FE 1[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 8 9 of 1658 REJ09B0261-0100 Section 5 Exception Handling 5.1 Summary of Exception Handling Exception ha ndling processi ng is handle d by a special routine whic h is executed by a reset, general exception handling, or in terrupt. For example, if the executing in struction ends abnormally, appr opria[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 9 0 of 1658 REJ09B0261-0100 Table 5.2 States of Regist er in Each Operating Mode Register Name Abbr. Power-on Reset Manual Reset Sleep Standby TRAPA exception register TRA Undefined Undefined Retained Retained Exception event register EXPEVT H'0000 0000 H'0000 0 020 Retained Retained Inter[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 9 1 of 1658 REJ09B0261-0100 5.2.2 Excepti on Event Register (E XPEVT) The exception event register (EXP EVT) consists of a 12-bit exce ption code. The exception code set in EXPEVT is that for a reset or general exception event. The ex ception code is set automatically by hardware when an exception o[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 9 2 of 1658 REJ09B0261-0100 5.2.3 Interrupt Event Re gister (INTEVT) The interrupt event register (INTEVT) consi sts of a 14-bit exception code. T h e exception code is set automatically by hardware when an exce p tion occurs. INTEVT can also be modifi ed by software. 31 30 29 28 27 26 25 24 23 22 2[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 9 3 of 1658 REJ09B0261-0100 5.2.4 Non-Sup port Detection Exce ption Registe r (EXPMASK) The non-support de tection exception register (EXPMASK) is u sed to enable or disable the generation of exceptions i n response to the use of a n y of funct ions 1 to 3 l isted below. T h e functions of 1 to 3 ar[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 9 4 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 31 to 5 ⎯ All 0 R Reserved For details on reading/writing these b its, see General Precautions on Handling of Product. 4 MMCAW 1 R/W Memory-Mapped Cac he Associative Write 0: Memory-mapped cache associative wr ite is disabled. [...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 9 5 of 1658 REJ09B0261-0100 5.3 Exception Handling Functions 5.3.1 Excepti on Handling Flow In exceptio n handlin g, the content s of the p rogram cou nter (PC), stat us register (SR), and R15 are saved in the sa ved program cou nter (SPC), saved status register (S SR), and save d general register15[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 9 6 of 1658 REJ09B0261-0100 5.4 Exception Types and Priorities Table 5.3 sho ws the types o f exceptions, with th eir relative priorities, vector addresses, a nd exception/interrup t codes. Table 5.3 Exceptions Exception T ransition Direction * 3 Exception Category Execution Mode Exception Priority [...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 9 7 of 1658 REJ09B0261-0100 Exception T ransition Direction * 3 Exception Category Execution Mode Exception Priority Level * 2 Priority Order * 2 Vector Address Offs et Exception Code * 4 Unconditional trap (TRAPA) 2 4 (VBR) H ' 10 0 H ' 160 General exception Completion type User break aft[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 9 8 of 1658 REJ09B0261-0100 5.5 Exception Flow 5.5.1 Excepti on Flow Figure 5.1 s hows an out line flowchart of the basic operations in i nstruction e xecution and exception ha ndling. For t h e sake of cl arity, the f ollowing de scription assu mes that instru ctions are executed sequen tially, one[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 9 9 of 1658 REJ09B0261-0100 Execute next instruction Is hi g hest- priority exception re-exception type? Cancel instruction execution result Yes Yes Yes No No No No Yes SSR ← SR SPC ← PC SGR ← R15 EXPEVT/INTEVT ← exception code SR.{MD,RB,BL} ← 111 SR.IMASK ← received interuupt level ( * [...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 00 of 1658 REJ09B0261-0100 5.5.2 Excepti on Source Acceptance A priority ranking is provided for all except ions fo r use in dete rmining w hich of tw o or more simultaneously ge nerated exceptions should be accepted. Five of the general exceptions—general illegal instruction ex ception, slot il[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 01 of 1658 REJ09B0261-0100 5.5.3 Exception Requests and BL Bit When the BL bit in SR is 0, genera l exceptions and interrupts are accepted. When the BL b it in SR is 1 and an gene ral exception other than a user break is generated, the CPU's internal registers and the re gisters of the other [...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 02 of 1658 REJ09B0261-0100 5.6 Description of Exceptions The various e xception ha ndling operati ons explaine d here are exception sources , transition address on the occurrence of excep tion, and proces sor operation when a transition is made. 5.6.1 Reset s (1) Power-On Reset • Condition: Powe[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 03 of 1658 REJ09B0261-0100 (4) Instruction TLB Mult iple Hit Exception • Source: Multiple ITLB address matches • Transition a ddress: H'A0 000000 • Transition operations: The virtual a ddress (32 bi ts) at which t his exception occurre d is set in TE A, and the correspondi ng virtual pa[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 04 of 1658 REJ09B0261-0100 5.6.2 General E xceptions (1) Data TLB Miss Exception • Source: Address mismatch in UTLB addre ss comparison • Transition ad dress: VBR + H' 00000400 • Transition operation s: The virtual a ddress (32 bi ts) at which t his exception occurre d is set in TE A, a[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 05 of 1658 REJ09B0261-0100 (2) Instruction TLB Miss E xception • Source: Address mismatch in ITLB address comparison • Transition ad dress: VBR + H' 00000400 • Transition operations: The virtual a ddress (32 bi ts) at which t his excep tion occurred is set in TEA, and the correspondi ng[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 06 of 1658 REJ09B0261-0100 (3) Initial Page Write Exception • Source: TLB is hit in a store access, but di rty bit D = 0 • Transition ad dress: VBR + H' 00000100 • Transition operation s: The virtual a ddress (32 bi ts) at which t his exception occurre d is set in TE A, and the correspo[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 07 of 1658 REJ09B0261-0100 (4) Data TLB Protection Violation Exception • Source: The access does not acco rd with the UTLB protection information (PR bits or EPR bits) sh own in t able 5.4 an d table 5. 5. Table 5.4 UTLB Protection Inform a tion (TLB Compatible Mode) PR Privileged Mo de User Mod[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 08 of 1658 REJ09B0261-0100 The PC and SR contents for the instru ction at which this excep ti on occurred are save d in SPC and SSR. The R15 contents at this time are saved in SGR. Exception code H'0A0 (for a read access) or H' 0C0 (for a write access) is set in E XPEVT. The BL, MD, and [...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 09 of 1658 REJ09B0261-0100 (5) Instruction TLB Protec tion Violation Exception • Source: The access does not accord with the ITLB pr otection inf ormation (PR bits or EPR bits) shown in ta ble 5.6 and table5.7. Table 5.6 ITLB Protection Information (TLB Compat ible Mode) PR Privileged Mo de User[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 10 of 1658 REJ09B0261-0100 ITLB_protection_violation_exception() { TEA = EXCEPTION_ADDRESS; PTEH.VPN = PAGE_NUMBER; SPC = PC; SSR = SR; SGR = R15; EXPEVT = H'0000 00A0; SR.MD = 1; SR.RB = 1; SR.BL = 1; PC = VBR + H'0000 0100; } (6) Data Address Error • Sources: ⎯ Word data access fro[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 11 of 1658 REJ09B0261-0100 • Transition operations: The virtual a ddress (32 bi ts) at which t his exception occurre d is set in TE A, and the correspondi ng virtual pa ge number (22 bit s) is set in PTEH [31:10] . ASID in PTEH indic ates the ASID when this excep tion occurred. The PC and SR con[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 12 of 1658 REJ09B0261-0100 (7) Instruction Address Error • Sources: ⎯ Instructio n fetch from othe r than a word bounda ry (2n +1) ⎯ Instruction fetch from area H'80000000 to H'FFFFFFFF in user mode Area H'E5000000 t o H'E5FFFFFF can be a ccessed in user mode. For deta il[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 13 of 1658 REJ09B0261-0100 (8) Uncondi tional Trap • Source: Execut ion of TRAP A instructio n • Transition ad dress: VBR + H' 00000100 • Transition operations: As this is a processing-c ompletion-t ype excepti on, the PC c ontents fo r the inst ruction following the TRAPA instruction a[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 14 of 1658 REJ09B0261-0100 (9) General Illegal Instruction Exception • Sources: ⎯ Decoding of a n undefined instruct ion not i n a delay sl ot Delayed bra nch instructions: JMP, J SR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefine d instructi on: H'FFF D ⎯ Decoding in user mode of [...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 15 of 1658 REJ09B0261-0100 (10) Slot Illegal Instruc tion Exception • Sources: ⎯ Decoding of a n undefined instruct ion in a d elay slot Delayed bra nch instructions: JMP, J SR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefine d instructi on: H'FFF D ⎯ Decoding of an instruction that[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 16 of 1658 REJ09B0261-0100 (11) General FPU Disable Exception • Source: Decodi ng of an FPU instructi on* not in a delay slot with SR.FD = 1 • Transition ad dress: VBR + H' 00000100 • Transition operation s: The PC and SR contents for the instru ction at which this excep ti on occurred [...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 17 of 1658 REJ09B0261-0100 (12) Slot FP U Disa ble Exception • Source: Decod ing of an F PU instructi on in a del ay slot wi th SR.FD = 1 • Transition ad dress: VBR + H' 00000100 • Transition operations: The PC contents for the preceding delayed bran ch instru ction ar e saved in SP C. [...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 18 of 1658 REJ09B0261-0100 (13) Pre-Execution User Break/Post-Execution User Bre ak • Source: Fulfilling of a break conditio n set in the user break con troller • Transition address: VBR + H'0000 0100, or DBR • Transition operation s: In the case of a post-executi on break, the PC conte[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 19 of 1658 REJ09B0261-0100 (14) FPU Exception • Source: Except ion due to exec ution of a floating-p oint opera tion • Transition ad dress: VBR + H' 00000100 • Transition operation s: The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR . [...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 20 of 1658 REJ09B0261-0100 5.6.3 Interrupts (1) NMI (N onmaskable Interr upt) • Source: NMI p in edge detecti on • Transition ad dress: VBR + H' 00000600 • Transition operation s: The PC and SR contents for the instruction i mmediately after this exception is accepted are saved in SPC a[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 21 of 1658 REJ09B0261-0100 The code corresponding t o the each interrupt source is set in INTEVT . The BL, MD, and RB bits are set to 1 in SR, and a branch is made to VBR + H'0600. When the INTMU bit in CPUOPM is 1, IMASK bit in SR is changed to accepted interrupt level. For details, see sect[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 22 of 1658 REJ09B0261-0100 8. In itial page write exception in second data transfer (2) Indivisible Delayed Branch Instru ction an d Delay Slot Instruction As a delayed branch instruction and its associated del ay slot inst ruction are i ndivisible, t hey are treated as a single instruction . Cons[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 23 of 1658 REJ09B0261-0100 5.7 Usage Notes (1) Return from Exception Handling A. Check the BL bit in SR with software. If SPC and S SR have been saved to memory, set the BL bit in SR to 1 before restor ing them. B. Issue an RTE instruction. When RTE is executed, the SPC contents are saved in PC, t[...]

5. Exception Handling Rev.1.00 Jan. 10, 2008 Page 1 24 of 1658 REJ09B0261-0100 other exceptio ns is determine d depending on the processing mode by SR after restoring or the BL bit. The comple tion type exception is accepted before branching to the destination of RTE instruc tion. However, if t he re-execu tion type e xception i s occurre d, the op[...]

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 25 of 1658 REJ09B0261-0100 Section 6 Floating-Point Unit (FPU) 6.1 Features The FPU has the following features. • Conforms to IEEE754 standard • 32 single-preci sion floatin g-point registers (can also be referenced as 16 double-precision registers) • Two rounding modes: Roun d to Nea[...]

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 26 of 1658 REJ09B0261-0100 6.2 Data Formats 6.2.1 Fl oating-Poin t Format A floatin g-point n umber con sists of t he followi ng three fie lds: • Sign bit (s) • Exponent fi eld (e) • Fraction field (f) This LSI can handle si ngle-precisi on and double-p recision floatin g-point nu mbe[...]

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 27 of 1658 REJ09B0261-0100 Table 6.1 Floating-Poin t Number Formats and Parameters Parameter Single-Preci sion Double-Precision Total bit width 32 bits 64 bits Sign bit 1 bit 1 bit Exponent field 8 bits 11 bits Fraction field 23 bits 52 bits Precision 24 bits 53 bits Bias +127 +1023 E max +[...]

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 28 of 1658 REJ09B0261-0100 Table 6.2 Floating-Poi nt Ranges Type Single-Precision Double-Precision Signaling non- number H'7FFF FFFF to H'7FC0 0000 H'7FFF FFFF FFFF FFFF to H'7FF8 0000 0000 0000 Quiet non-number H'7FBF FFFF to H'7F 80 0001 H'7FF7 FFF F FFF[...]

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 29 of 1658 REJ09B0261-0100 6.2.2 No n-Numbers (Na N) Figure 6.3 shows the bit p attern of a non-number (NaN). A value is NaN in th e following case: • Sign bit: Don't care • Exponent fi eld: All bi ts are 1 • Fraction field: At least one bit is 1 The NaN is a signaling NaN (sNaN)[...]

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 30 of 1658 REJ09B0261-0100 See section 10, Instruction De scriptions of the SH-4A Extended Functions Softw are Manual for details of floating- point operat ions when a non-n umber (Na N) is input . 6.2.3 Denorm alized Numbers For a denormal ized number floating-poi nt value, the exponent fi[...]

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 31 of 1658 REJ09B0261-0100 6.3 Register Descriptions 6.3.1 Fl oating-Poin t Registers Figure 6.4 s hows the fl oating-point regi ster conf iguration. There are thirty-two 32-bit floating- point regi sters comprise d with two banks: FPR0_BA NK0 to FPR1 5_BANK0, a nd FPR0_BANK1 to FPR15_BANK1[...]

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 32 of 1658 REJ09B0261-0100 7. Single-precision float ing-poin t extended regi ster matrix, XMTRX: XMT RX comprises all 16 XF registers. XMTRX = XF0 XF4 XF8 XF12 XF1 XF5 XF 9 XF13 XF2 XF6 XF10 XF14 XF3 XF7 XF11 XF15 FPR0 BANK0 FPR1 BANK0 FPR2 BANK0 FPR3 BANK0 FPR4 BANK0 FPR5 BANK0 FPR6 BANK0[...]

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 33 of 1658 REJ09B0261-0100 6.3.2 Floa ting-Point Status/ Control Register (FPSCR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit: 0000000000000100 Initial value: RRRRRRRRRR R / W R / W R / W R / W R / W R / W R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit: 0000000000000001 Initial valu[...]

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 34 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 17 to 12 Cause All 0 R/W 11 to 7 Enable All 0 R/W 6 to 2 Flag All 0 R/W FPU Exception Cause Field FPU Exception Enable Field FPU Exception Flag Field Each time an FPU operation in struction is ex ecuted, the FPU exception[...]

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 35 of 1658 REJ09B0261-0100 <Bi g endian> DR (2i) FR (2i) FR (2i+1) 8n+4 8n+7 8n 8n+3 63 0 63 32 31 0 Floatin g -point re g ister Memory area 63 0 <Little endian> Floatin g -point re g ister Memory area DR (2i) FR (2i) FR (2i+1) 4n 4m 4n+3 4m+3 63 0 63 32 31 0 DR (2i) FR (2i+1) F[...]

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 36 of 1658 REJ09B0261-0100 Table 6.3 Bit Allocation for FPU E xception Handling Field Name FPU Error (E) Invalid Operation (V) Division by Zero (Z) Overflow (O) Underflo w (U) Inexact (I) Cause FPU exception cause field Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Enable FPU exception enable f[...]

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 37 of 1658 REJ09B0261-0100 6.4 Rounding In a floating-point instr uction, rounding is performed when g enerating the final operation r esult from the intermediate result. Therefor e, the result of combination instructions su ch as FMAC, FTRV, and FIPR will differ from the result wh en using[...]

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 38 of 1658 REJ09B0261-0100 6.5 Floating-Point Exceptions 6.5.1 General FPU Disable Exceptions a nd Slot FPU Disable Exceptions FPU-related exceptions are occurred when an FPU instruction is executed with SR.FD set to 1. When the FPU instruction is in othe r than delayed slot, t he general F[...]

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 39 of 1658 REJ09B0261-0100 6.5.3 FPU E xception Handling FPU exception handling is initiated in the following cases: • FPU error (E): FPSCR.DN = 0 and a denormalized numb er is input • Invalid operation (V): FPSCR.En able.V = 1 and (instruction = FTRV or invalid operation) • Division [...]

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 40 of 1658 REJ09B0261-0100 6.6 Graphics Support Functions This LSI supports two kinds of graphics functio ns: new instr uctions for geometric op erations, and pair single -precision t ransfer instructions that enable high-speed data transfer. 6.6.1 Geome tric Operation Instructions Geometri[...]

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 41 of 1658 REJ09B0261-0100 (2) FTRV XMTRX, FVn (n: 0, 4, 8, 12) This instruction is basically used for the following purposes: • Matrix (4 × 4) ⋅ vector (4): This operati on is general ly used fo r viewpoint changes, angl e changes, or movements cal led vector transformations (4-d imen[...]

6. Floating-Point Unit (FPU) Rev.1.00 Jan. 10, 2008 Page 1 42 of 1658 REJ09B0261-0100 This instruction chang es the value of the SZ bit in FPSCR, enabling fast switching between use and non-use of pair single-p recision data transfer.[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 43 of 1658 REJ09B0261-0100 Section 7 Memory Management Unit (MMU) This LSI supports an 8-b it address space identifier, a 32-bit virt ual addres s space, and a 29-bit or 32-bit physical address space. Addr ess translation from virtual addr esses to physical addresses is enabled by t he m[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 44 of 1658 REJ09B0261-0100 7.1 Overview of MMU The MMU was conceived as a means of making ef ficient use of physical memory. As shown in (0) in figu re 7.1, when a process is smaller in size t han the physical memory, the entire process can be mapped onto physical memory, but if th e pro[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 45 of 1658 REJ09B0261-0100 There are tw o methods by which the MM U can perform mappi ng from vi rtual memo ry to physical memory: the paging method, using fixed- length address translation, an d the segment method, using variable-len gth address translation. With the paging method, the [...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 46 of 1658 REJ09B0261-0100 7.1.1 Addre ss Spaces (1) Virtual Address Space This LSI supports a 32-bit virtua l address space, and can access a 4-Gbyte address space. The virtual address space is divi ded into a number of areas, as shown in figures 7.2 and 7.3. In privileged mode, the 4-G[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 47 of 1658 REJ09B0261-0100 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 Physical address space 256 256 U0 area Cacheable Address translation possible Address error Address error On-chip memory area Address error Store queue area P0 area Cacheable Address translation possible U[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 48 of 1658 REJ09B0261-0100 (b) P1 Area The P1 area does not allow address tra nslation using t he TLB but can be accessed using t he cache. Regardless of whether the M MU is enabled or disa bled, clearing t he upper 3 bi ts of an ad dress to 0 gives the corr esponding phys ical address. [...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 49 of 1658 REJ09B0261-0100 The area from H'E000 0000 to H'E3FF FFFF comp rises addresses for accessing the store queue s (SQs). In user mode, t he access right is specified by the SQMD bit in MM UCR. For details, see section 8.7, Store Que ues. The area fro m H'E500 0000 t[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 50 of 1658 REJ09B0261-0100 (2) Physical Address Sp ace This LSI supports a 29-bit physical address space. The physical addr ess space is divided into eight areas as shown in figure 7.5. Area 7 is a reserv ed area. For details, see section 11, Local Bus State Controller (LB SC) section of[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 51 of 1658 REJ09B0261-0100 the return from the exception handling routine, the instruction which caused the TLB miss exception is re-execu ted. (4) Single Virtual Memor y Mode and Multiple Virtual Memory Mode There are tw o virtual mem ory systems, sin gle virtual memory and m ultiple vi[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 52 of 1658 REJ09B0261-0100 7.2 Register Descriptions The following registers are related to MMU processing. Table 7.1 Register Configuration Register Name Abbreviation R/W P4 Addres s * Area 7 Address * Size Page table entry high register PTEH R/W H'FF00 0000 H'1F00 0000 32 Pag[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 53 of 1658 REJ09B0261-0100 Register Name Abbreviation Power-on Reset Manual Reset Sleep Standby Instruction re-fetch inhibit control register IRMCR H'0000 0000 H'0000 0000 Retained Retained 7.2.1 Pa ge Table Entr y High Reg ister (PTEH) PTEH consists of the virtual page number [...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 54 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 31 to 10 VPN Undefined R/W Virtual Page Number 9, 8 ⎯ All 0 R Reserve d For details on reading from or writing to these bits, see description in General Precautions on Hand ling of Product. 7 to 0 ASID Undefined R/W [...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 55 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 8 V Undefi ned R/W 7 SZ1 Undefined R/W 6 PR1 Undefi ned R/W 5 PR0 Undefi ned R/W 4 SZ0 Undefined R/W 3 C Undefined R/W 2 D Undefined R/W 1 SH Undefined R/W Page Management Information The meaning of each bit is same as[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 56 of 1658 REJ09B0261-0100 7.2.4 TLB Excepti on Address Register (TEA) After an MMU exception or addr ess error exception occurs, the virtual address at which the exception occ urred is st ored. The contents of this re gister can be changed by softwa re. 31 30 29 28 27 26 25 24 Virtual a[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 57 of 1658 REJ09B0261-0100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit: 0000000000000000 Initial value: R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R R R/W R R TI URB LRUI URC SQMD SV AT R R R/W R R/W R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 58 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 25, 24 ⎯ All 0 R Reserved For details on reading from or writing to these bits, see description in General Precautions on Hand ling of Product. 23 to 18 URB 000 000 R/W UTLB Repl ace Boundary These bits indicate the [...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 59 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 7 ME 0 R/W TLB Extended Mode Switching 0: TLB compatible mode 1: TLB extended mode For modifying the ME bit value, always set the TI bit to 1 to invalidate the contents of ITLB and UTLB. The selection of TLB operating [...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 60 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 31 to 14 ⎯ All 0 R Reserve d For details on reading/writing these b its, see General Precautions on Handling of Product. 13 to 8 EPR Undefined R/W 7 to 4 ESZ Undefined R/W Page Control Information Each bit has the sa[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 61 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 31 to 8 ⎯ All 0 R Reserve d For details on reading from or writing to these bits, see description in General Precautions on Hand ling of Product. 7 to 0 UB H'00 R/W Buffered Write Control for Each Area (64 Mbyte[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 62 of 1658 REJ09B0261-0100 7.2.8 Instr uction Re-Fetch Inhibit Control Register (IRMCR) When the specific resource is change d, IRMCR controls whether the instruction fet ch is performed agai n for the next instr uction. The speci fic resource means the part of cont rol registers, TLB, a[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 63 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 3 R1 0 R/W Re-Fetch Inhi bit 1 after Register Change When a register allocated in a ddresses H'FF200000 to H'FF2FFFFF is changed, this bit controls whether re- fetch is performed for the next instruction. 0: [...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 64 of 1658 REJ09B0261-0100 7.3 TLB Functions (TLB Compatible Mode; MMUCR.ME = 0) 7.3.1 Unified TLB (UTLB) Configuration The UTLB is used for the following two purposes: 1. To translate a virtual address to a physical address in a data access 2. A s a table of address translation informat[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 65 of 1658 REJ09B0261-0100 • SH: Share status bit When 0, pa ges are not sha red by processes. When 1, pa ges are shared b y processes. • SZ[1:0]: Page size bits Specify the page size. 00: 1-Kbyt e page 01: 4-Kbyt e page 10: 64-Kbyte p age 11: 1-Mbyte page • V: Validity bit Indicat[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 66 of 1658 REJ09B0261-0100 1: Cacheable When the cont rol register area is ma pped, thi s bit must be cleared to 0. • D: Dirty bit Indicates whet her a write ha s been perfo rmed to a page . 0: Write has not been pe rformed 1: Write has been perfo rmed • WT: Write-through bit Specifi[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 67 of 1658 REJ09B0261-0100 7.3.2 Instruction T LB (ITLB) Configuration The ITLB is used to translate a virtual addre ss to a physical ad dress in an instruction access. Information in the address translation table located in the UTLB is cache d into the ITLB. Figure 7.8 shows t he ITLB c[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 68 of 1658 REJ09B0261-0100 SR.MD? R/W? R/W? Yes Yes No No No Yes Yes Yes No PR? PR? D? R/W? W W W R R R R W R/W? WT? 1 1 0 0 00 or 01 10 11 01 or 11 00 or 10 Yes No Internal resource access 1 0 CCR.OCE? 1 0 CCR.CB? 0 1 CCR.WT? 1 0 CCR.OCE? No Data access to virtual address (VA) VA is in [...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 69 of 1658 REJ09B0261-0100 Figure 7.10 shows a flowchart of a me mory access using the ITLB. Yes Yes No No No Yes Yes Yes No Internal resource access 1 0 1 0 CCR.ICE? Yes No No Yes No Instruction access to virtual address (VA) VA is in P4 area VA is in P2 area VA is in P1 area VA is in P[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 70 of 1658 REJ09B0261-0100 7.4 TLB Functions (TLB Extended Mode; MMUCR.ME = 1) 7.4.1 Unified TLB (UTLB) Configuration Figure 7.11 s hows the co nfiguration of the UTLB in TLB extended m ode. Figure 7.12 shows the relationshi p between t he page size and a ddress format. PPN[28:10] PPN[28[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 71 of 1658 REJ09B0261-0100 0001: 4-Kb yte page 0010: 8-Kb yte page 0100: 64-K byte page 0101: 256- Kbyte page 0111: 1-Mb yte pa ge 1000: 4-Mb yte pa ge 1100: 64-M byte page Note: When a value othe r than those listed ab ov e is reco rded, opera tion is not guar anteed. • V: Validity bi[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 72 of 1658 REJ09B0261-0100 EPR[1]: Writing in user mode EPR[0]: Exec ution in u ser mode (inst ruction fet ch) • C: Cacheability bit Indicates whether a page is c acheable. 0: Not cacheable 1: Cacheable When the cont rol register area is ma pped, thi s bit must be cleared to 0. • D: [...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 73 of 1658 REJ09B0261-0100 Virtual address Physical address 31 1-Kbyte pa g e 10 9 0 VPN Offset 28 10 9 0 PPN Offset 31 4-Kbyte pa g e 12 11 0 VPN Offset 28 12 11 0 PPN Offset 31 64-Kbyte pa g e 16 15 0 VPN Offset 28 16 15 0 PPN Offset 31 8-Kbyte pa g e 13 12 0 VPN Offset 28 13 12 0 PPN [...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 74 of 1658 REJ09B0261-0100 7.4.3 Addre ss Translation Method Figure 7.14 is a flowchart of memory access using the UTLB in TLB extended mode.[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 75 of 1658 REJ09B0261-0100 SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) VPNs match, ASIDs match, and V = 1 Only one entry matches SR.MD? Cache access in write-throu g h mode Data TLB protection violation exception Initial pa g e write exception Data TLB protection violation exception Cache acc[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 76 of 1658 REJ09B0261-0100 Figure 7.15 is a flowchart of memory acces s using the ITLB in TLB extended mode. SH = 0 and (MMUCR.SV = 0 or SR.MD = 0) VPNs match, ASIDs match, and V = 1 Only one entry matches SR.MD? Instruction TLB protection violation exception Instruction TLB multiple hit[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 77 of 1658 REJ09B0261-0100 7.5 MMU Functions 7.5.1 MM U Hardware Managem ent This LSI supports the following MMU functions. 1. The MMU decodes the virtua l address to be accessed by software, and performs address translation by controlling the UTLB/ITLB in accordance wi th the MMUCR sett[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 78 of 1658 REJ09B0261-0100 7.5.3 MMU Instruction (LDTLB) A TLB load instruction (LDTLB) is provide d for recording UTLB entries. When an LDTLB instruction is issued, this LSI copies the con tents of PTE H and PTEL (als o the contents of PTEA in TLB extend ed mode) to t he UTLB entry i nd[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 79 of 1658 REJ09B0261-0100 The operation of the LDTLB instructio n is show n in figure s 7.16 and 7.17. PPN [28:10] PPN [28:10] PPN [28:10] SZ [1:0] SZ [1:0] SZ [1:0] SH SH SH C C C PR [1:0] PR [1:0] PR [1:0] ASID [7:0] ASID [7:0] ASID [7:0] VPN [31:10] VPN [31:10] VPN [31:10] V V V Entr[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 80 of 1658 REJ09B0261-0100 PPN[28:10] PPN[28:10] PPN[28:10] ESZ [ 3:0 ] ESZ [ 3:0 ] ESZ [ 3:0 ] SH SH SH C C C EPR [ 5:0 ] EPR [ 5:0 ] EPR [ 5:0 ] ASID[7:0] ASID[7:0] ASID[7:0] VPN [ 31:10 ] VPN [ 31:10 ] VPN [ 31:10 ] V V V Entry 0 Entry 1 Entry 2 D D D WT WT WT PPN[28:10] ESZ [ 3:0] SH[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 81 of 1658 REJ09B0261-0100 7.5.5 Avoiding Synony m Problems When information on 1- or 4-Kbyte pages is written as TLB entries, a synonym problem may arise. The problem is that, when a number of virtual addresses ar e mapped onto a single physical address, the same physical addres s data [...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 82 of 1658 REJ09B0261-0100 7.6 MMU Exceptions There are seven M MU except ions: instr uction TLB m ultiple hit exce ption, inst ruction TLB mi ss exception, instruction TLB pro tection violation exception, data TLB multiple hit exception, data TLB miss except ion, data TLB protection vi [...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 83 of 1658 REJ09B0261-0100 7.6.2 Instr uction TLB Miss Exception An instruction TLB miss exceptio n occurs when address translation information for the virtual address to which an instruction access is made is not found in th e UTLB entries by the hardware ITLB miss handling routine. The[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 84 of 1658 REJ09B0261-0100 3. In TLB co mpatible mode, execute th e LDTLB instruction and write the con tents of PTEH and PTEL to the TLB. In TLB extend ed mode, exec ute the LDTL B inst ruction and write the contents of PTE H, PTEL, PTEA to the UTLB. 4. Finally, execute the except ion h[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 85 of 1658 REJ09B0261-0100 (2) Software Processing (Instruction TLB Protection Vi olation Exception Handling Routine) Resolve the ins truction TLB protection violation, exec ute the exception handlin g return instr uction (RTE), terminate the exception handling routine, an d return cont [...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 86 of 1658 REJ09B0261-0100 3. Sets exception code H'040 in the case of a re ad, or H'060 in the case of a write in EXPEVT (OCBP, OCBWB: read; OCBI, MOVC A.L: write). 4. Sets th e PC value indicating the address of th e instruction at which th e exception occurred in SPC. If the[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 87 of 1658 REJ09B0261-0100 7.6.6 Data TLB Protection Violati on Exception A data TLB pr otection viol ation excepti on occurs whe n , even tho ugh a UTLB entr y contains address translation information ma tching the virtual addre ss to which a data access is made, the actual access type [...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 88 of 1658 REJ09B0261-0100 7.6.7 Initial Page Write Exception An initial page write excep tion occurs when the D bit is 0 even though a UTLB entry contains address translation information matching the virtual addre ss to which a dat a access (write) is made, and the access is permi tted.[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 89 of 1658 REJ09B0261-0100 5. In TLB co mpatible mode , execute th e LDTLB instru ction and write th e contents o f PTEH and PTEL to the TLB. In TLB extended mode, execu te the LDTLB instruction and write the con tents of PTEH, PTEL, PTEA to the UTLB. 6. Fin ally, execute the excep tion [...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 90 of 1658 REJ09B0261-0100 7.7 Memory-Mapped TLB Configuration To enable the ITLB and UTL B to be mana ged by s oftware, their contents are allowed to be read from and written to by a program in the P1/P2 area with a MOV instru ction in privileged mode. Operation is not guaranteed if acc[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 91 of 1658 REJ09B0261-0100 7.7.1 ITLB Address Array The ITLB address array is allocated to a ddresses H'F200 0000 to H'F2FF FFFF in t he P4 area. An address array access requires a 32 -bit addre ss field specificati on (when re ading or w riting) and a 32-bit data fi eld specif[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 92 of 1658 REJ09B0261-0100 7.7.2 ITLB Data Array (TLB Compatible Mode) The ITLB data array is allocated to addresses H'F3 00 0000 to H' F37F FFFF in the P4 area. A d ata array access requires a 32-bit address field specifi cation (when reading or writing) and a 32-bit data fiel[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 93 of 1658 REJ09B0261-0100 7.7.3 ITLB Data Array (TLB E xtended Mode) In TLB exten ded mode t he names of t he data arrays have be en changed from ITLB data array t o ITLB data array 1, ITLB data array 2 is added, and the EPR and ESZ bits a re accessible. In TLB extended mode , the PR an[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 94 of 1658 REJ09B0261-0100 (2) ITLB Data Array 2 The ITLB data arra y is allocated to addresses H' F380 0000 to H'F3 FF FFFF in th e P4 area. Acces s to data array 2 requires a 32-bit address fi eld specificati on (when rea ding or wri ting) and a 3 2-bit data field specificati[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 95 of 1658 REJ09B0261-0100 7.7.4 UTLB Address Array The UTLB address arra y is allocated to addresses H'F600 0000 to H'F60F FFFF in the P4 area. An address array access requires a 32 -bit addre ss field specificati on (when re ading or w riting) and a 32-bit data fi eld specifi[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 96 of 1658 REJ09B0261-0100 Address field Data field VPN: V: E: D: * : Virtual pa g e number Validity bit Entry Dirty bit Don't care ASID: A: : Address space identifier Association bit Reserved bits (write value should be 0 and read value is undefined ) 31 0 V D 10 98 7 ASID VPN A 87[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 97 of 1658 REJ09B0261-0100 Address field Data field PPN: V: E: SZ: D: * : Physical pa g e number Validity bit Entry Pa g e size bits Dirty bit Don't care PR: C: SH: WT: : Protection key data Cacheability bit Share status bit Write-throu g h bit Reserved bits (write value should be 0[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 98 of 1658 REJ09B0261-0100 (2) UTLB Data Array 2 The UTLB data arra y is allocated to ad dresses H' F780 0000 to H'F78F F FFF in the P4 area. Access to data array 2 requi res a 32-bit a ddress field specification ( when reading or writing ) and a 32-bit data field specification[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 1 99 of 1658 REJ09B0261-0100 7.8 32-Bit Address Extended Mode Setting the SE bit in PASCR to 1 c hanges mode from 29 -bit address m ode which handles t he 29- bit physical address space to 32-b it address extended mode whic h handles the 32-bit physical address space. P1 (0.5 Gbyte) P1/P2 [...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 2 00 of 1658 REJ09B0261-0100 7.8.2 Transiti on to 32-Bit Address Extended Mode This LSI enters 29-bit address mo de after a power-on reset. Transition is made to 32-bit address extended mode by setting the SE bit in PASCR to 1. In 32-bit address exten ded mode, the MMU operates as f ollows[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 2 01 of 1658 REJ09B0261-0100 Legend: • VPN: Virtual page number For 16-Mbyte page: Upper 8 bit s of virtual add ress For 64-Mbyte page: Upper 6 bit s of virtual add ress For 128-M byte page: U pper 5 bits of virtual address For 512-M byte page: U pper 3 bits of virtual address Note: B&ap[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 2 02 of 1658 REJ09B0261-0100 • WT: Write-through bit Specifies the cache write mode. 0: Copy-back mode 1: Write-throug h mode • UB: Buffered write b it Specifies whether a buffered write is performed. 0: Buffered write (Data access of subsequent processi ng proceed s without waiting fo[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 2 03 of 1658 REJ09B0261-0100 7.8.5 Mem ory-Mapped PMB Configurati on To enable the PMB to be manage d by software, its cont ents are allowe d to be read from and written to by a P1 or P2 area program with a MOV instruction in privileged mode. The PMB address array is allocated to ad dresse[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 2 04 of 1658 REJ09B0261-0100 Address field Data field VPN: V: E: Physical pa g e number Validity bit Entry : Reserved bits (write value should be 0 and read value is undefined ) 31 0 V 8 8 7 VPN 31 19 20 0 11110 000 11 01 0 0 E 23 24 12 11 00000 00000 00 0 0 Figure 7.28 Memory-Map ped PMB [...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 2 05 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 30 to 8 ⎯ All 0 R Reserve d For details on reading from or writing to these bits, see description in General Precautions on Hand ling of Product. 7 to 0 UB All 0 R/W Buffered Write Control for Each Area (64 Mbytes) W[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 2 06 of 1658 REJ09B0261-0100 (5) CCR.CB The CB bit in CCR is invalid. Whether a cacheab le write for the P1 area is performed in copy- back mode or write-though mode is determined by the WT bit in the PMB. (6) IRMCR. MT The MT bit in IRMCR is valid for a memory-mapped PMB write. (7) QACR0,[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 2 07 of 1658 REJ09B0261-0100 7.9 32-Bit Boot Function The address m ode of this LS I after a p ower-on reset o r manual reset ca n be switche d between 2 9- bit address m ode and 32 -bit address extended m ode by s pecifying e xternal pins. The fol lowing changes apply when this LSI is boo[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 2 08 of 1658 REJ09B0261-0100 C. If the MT bit in IRMCR is set to 0 (initia l value) before accessin g the memory-mapped PMB, no specific sequence is require d . However, c orrect operati on with met hod C may no lon ger be guara nteed in future S uperH- family products. Selection of step A[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 2 09 of 1658 REJ09B0261-0100 7.10 Usage Notes 7.10.1 Note on Using LDTLB Instruction When using an LDTLB instruction instead of soft ware to a value t o the MMUCR. URC, execute 1 or 2 below . 1. In 29-bit addre ss mode, follow A. a nd B. be low. In 3 2-bit address mode, fol low A. t hrough[...]

7. Memory Management Unit (MMU) Rev.1.00 Jan. 10, 2008 Page 2 10 of 1658 REJ09B0261-0100 Notes: 1. An exception handling routine is an entir e set of instructions that are executed from the address (VBR + offset) upon occurrence of an exception to the RTE for retu rning to the original pr ogram or t o the RTE del ay slot. 2. MMU-related exceptions [...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 11 of 1658 REJ09B0261-0100 Section 8 Caches This LSI has an on-chi p 32-Kbyte i nstruction cache (IC) fo r instructions a nd an on-chip 32-Kbyte operand cache (OC) for data. 8.1 Features The features of the cache are given in t able 8.1. This LSI supports two 32-byte stor e queues (SQs) to perform high- speed[...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 12 of 1658 REJ09B0261-0100 This LSI has an IC way prediction scheme to reduce power con sumption. In addition, memory- mapped associative writing , which is detectable as an e xception, can be enabled by using the non- support detection exception regist er (EXPMASK) . For details, see section 5, Except ion Ha[...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 13 of 1658 REJ09B0261-0100 31 54 2 LW0 32 bits LW1 32 bits LW2 32 bits LW3 32 bits LW4 32 bits LW5 32 bits LW6 32 bits LW7 32 bits MMU [12:5] 255 19 bits 1 bit Ta g V Address array (way 0 to way 3) Data array (way 0 to way3) Entry selection Lon g word (LW) selection Virtual address 3 8 22 19 0 Read data 13 12[...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 14 of 1658 REJ09B0261-0100 • Data array The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized by a power-on or manual reset. • LRU In a 4-way set-associative method, up to 4 items of data can be registered i n the cache at each entry address. When an en try is [...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 15 of 1658 REJ09B0261-0100 8.2 Register Descriptions The following registers are related to cach e. Table 8.3 Register Configuration Register Name Abbreviation R/W P4 Address * Area 7 Ad dress * Size Cache control register CCR R/W H ' FF00 001C H ' 1F00 001C 32 Queue address control register 0 QACR0[...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 16 of 1658 REJ09B0261-0100 8.2.1 Cac he Control Regis ter (CCR) CCR controls the cache ope rating mode, the cach e write mode, a nd invalidation of all cache entries. CCR modifications must only be mad e by a progra m in the non-cacheable P2 area or IL memory. After CCR has been updated, execute one of the fo[...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 17 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 10, 9 ⎯ All 0 R Reserve d For details on reading from or writing to these bits, see description in General Precautions on Hand ling of Product. 8 ICE 0 R/W IC Enable Bit Selects whether the IC is used. Note however when address translatio[...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 18 of 1658 REJ09B0261-0100 8.2.2 Queue Address Contro l Register 0 (QACR0) QACR0 specifies the area onto whi ch store q ueue 0 (SQ 0) is mappe d when the MMU is disabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit: Initial value: RRRRRRRRRRRRRRRR 0000000000000000 00000000000 00 R R R R R R R R R R R [...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 19 of 1658 REJ09B0261-0100 8.2.3 Queue Address Contro l Register 1 (QACR1) QACR1 specifies the area onto whi ch store q ueue 1 (SQ 1) is mappe d when the MMU is disabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit: Initial value: RRRRRRRRRRRRRRRR 0000000000000000 00000000000 00 R R R R R R R R R R R [...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 20 of 1658 REJ09B0261-0100 8.2.4 On-Chip Memory Control R egister (RAMCR) RAMCR controls the nu mber of ways in the IC and OC a nd prediction of t he IC way. RAMCR modi fications must only be ma de by a progra m in the no n-cacheable P2 a rea. After RAMCR has been updated, execute one of th e following three [...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 21 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 8 RP 0 R/W On-Chip Mem ory Protection Enable Bit For details, see section 9.4, On-Chip Memory Protective Functions. 7 IC2W 0 R/W IC Two-Way Mode bit 0: IC is a four-way operation 1: IC is a two-way operation For details, see section 8.4.3, [...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 22 of 1658 REJ09B0261-0100 8.3 Operand Cache Operation 8.3.1 Read Operati on When the Oper and Cache (OC) is enable d (OCE = 1 in C CR) and data is read fr om a cacheable area, the cache operates a s follows: 1. The tag, V bit, U bit, and LRU bits on each way are read fr om the cache li ne indexed by virtual [...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 23 of 1658 REJ09B0261-0100 write-back buffer is then wr itten back to external memory. 8.3.2 Prefetc h Operation When the Oper and Cache (OC) is enabled (OCE = 1 in CCR) and data i s prefetched from a cacheable area, the cache operates as follows: 1. The tag, V bit, U bit, and LRU bits on each way are read fr[...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 24 of 1658 REJ09B0261-0100 8.3.3 Write Operation When the Oper and Cache (OC) is enable d (OCE = 1 i n CCR) and dat a is writ ten to a cacheabl e area, the cache operates a s follows: 1. The tag, V bit, U bit, and LRU bits on each way are read fr om the cache li ne indexed by virtual address bits [12:5]. 2. T[...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 25 of 1658 REJ09B0261-0100 6. Cache miss (copy- back, with write-back) The tag and data field of t he cache line on the wa y which is selected to replace are saved in the write-back buffer. Then a data write in accor da nce with the access size is pe rformed for the data field o n the hit wa y which is indexe[...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 26 of 1658 REJ09B0261-0100 8.3.6 OC Tw o-Way Mode When the OC2W bit in RAMCR is set to 1, OC two-wa y mode which only uses way 0 and way 1 in the OC is e ntered. Thus, power co nsumption can be red uced. In this mode, only way 0 and wa y 1 are used even if a memory-mapped OC access is made. The OC2W bit shoul[...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 27 of 1658 REJ09B0261-0100 8.4 Instruction Cache Operation 8.4.1 Read Operati on When the IC is enabled (ICE = 1 in CCR) and in struction fetches are performed from a cach eable area, the instruction cache operates as follows: 1. The tag, V bit, U bit and LRU bits on each way a re read from the cache line ind[...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 28 of 1658 REJ09B0261-0100 3. Cache hit The LRU bits is updated to indicate the way is the latest one. 4. Cache miss Data is read into the cache line on a way whi ch selected using the LRU bits to replace from the physical address space correspondin g to the virtual a ddress. Data reading is performed, using [...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 29 of 1658 REJ09B0261-0100 8.5 Cache Operation Instruction 8.5.1 Coherenc y between Cache and External Memory (1) Cache Operation Instruction Coherency bet ween cache and external memory should be assured by software. In this LSI, the following six instructions are suppor ted for cach e operations. Details of[...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 30 of 1658 REJ09B0261-0100 • FLUSH transaction When the operand cache is enabled, the FLUSH transaction checks t he operand cache and if the hit line is dirty, then th e data is written back to the external memory. If the tran saction is not hit to t he cache or the hit entr y is not di rty, it is no-oper a[...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 31 of 1658 REJ09B0261-0100 the dirty bit to 0. This o peration is onl y execut able in privileged mode , and an address error exception occurs in user mode . TLB-r elated exceptions do not occur. Do not execute this in struction to invalidat e the memory -mapped arra y areas and c ontrol register areas for wh[...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 32 of 1658 REJ09B0261-0100 8.6 Memory-Mapped Cache Configuration The IC and OC can be managed by softwa re. The content s of IC data array can be read from or written to by a program in the P2 area by means of a MOV instru ction in privileged mode. The contents of IC address ar ray can also be read from o r w[...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 33 of 1658 REJ09B0261-0100 In the data field, the tag is indicated by bits [ 31:10], an d the V bit by bit [0]. As the IC address array tag is 19 bits in length, data field bits [ 31:29] are not used in the case of a writ e in whic h association is not performed. Data field bits [3 1:29] are used for the virt[...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 34 of 1658 REJ09B0261-0100 8.6.2 IC Data Array The IC data array is allocated to addresses H'F1 00 0000 to H'F1FF FFFF i n the P4 area. A data array access requires a 32-bit address field specifi cation (when reading or writing) and a 32-bit data field specification. The way and ent ry to be accesse[...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 35 of 1658 REJ09B0261-0100 32-bit data field specification. Th e wa y and entry to be accessed are specified in the address field, and the write tag , U bit, and V bit are specified in the data field. In the address field, bits [31:24] have t he value H'F4 indicating the OC address arra y, and the wa y i[...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 36 of 1658 REJ09B0261-0100 Address field 3 1 2 3 543210 1 1 1 1 0 1 0 0 Entry A Data field 31 10 9 1 0 V Ta g 24 13 12 14 15 2 U V U A : Validity bit : Dirty bit : Association bit : Reserved bits (write value should be 0 and read value is undefined ) : Don't care Way 0 00 0 ******** * * Figure 8.7 Memor [...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 37 of 1658 REJ09B0261-0100 Address field 3 1 2 3 543210 11110101 E n t r y Data field 31 0 Lon g word data 24 13 12 14 15 L * : Lon g word specification bits : Don't care Way 0 L0 ******** * Figure 8.8 Memory-Mappe d OC Data Array (Cache siz e = 32 Kbytes) 8.6.5 Mem ory-Mapped Cache Asso ciative Write Op[...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 38 of 1658 REJ09B0261-0100 8.7 Store Queues This LSI supports two 32-byte stor e queues (SQs) to perform high- speed writes to external memory. 8.7.1 SQ Confi g uration There are tw o 32-byte st ore queues, SQ0 and S Q1, as shown in figure 8.9. These two store queues can be set inde pendently. SQ0 SQ0[0] SQ0[[...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 39 of 1658 REJ09B0261-0100 8.7.3 Transfer to E xternal Memory Transfer from the SQs to external memory can be perf ormed with a prefet ch instruction (PREF). Issuing a PRE F instruction for addresses H'E000 0000 to H'E 3FF FFFC in the P4 area starts a transfer from the SQ s to external memory. The t[...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 40 of 1658 REJ09B0261-0100 Physical address bits [4:0] are always fixed at 0 since burst t ransfer starts at a 32-byte boundar y. 8.7.4 Determination of SQ Access Exception Determination of an exception in a write to an SQ or transfer to external memory (PREF instruction) i s performed as follows accor ding t[...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 41 of 1658 REJ09B0261-0100 8.8 Notes on Using 32-Bit Address Extended Mode In 32-bit ad dress extende d mode, the items descri bed in this section are extended as follows. 1. Th e tag bits [28:10] (19 bits) in th e IC and OC are extended to bits [31:10] (22 b its). 2. An instruction which operates the IC (a m[...]

8. Caches Rev.1.00 Jan. 10, 2008 Page 2 42 of 1658 REJ09B0261-0100[...]

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 43 of 1658 REJ09B0261-0100 Section 9 On-Chip Memor y This LSI includes three type s of memory modu les for storage of instructions and d ata: OL memory, IL memory, and U memory. The OL memory is suitable for data sto rage while the IL memory is suit able for instruc tion stora ge. The U memo ry can st[...]

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 44 of 1658 REJ09B0261-0100 (2) IL Memory • Capacity The IL memory in this LSI is 8 Kbytes. • Page The IL memory is divided into two pages (pages 0 a nd 1). • Memory map The IL memory is allocated to t he addresses sho wn in table 9. 2 in both t he virtual address space and the physical address s[...]

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 45 of 1658 REJ09B0261-0100 The CPU can access the P4 area in th e virtual address space ( when SR.MD = 1) or on-chi p memory area (when SR.MD = 0 an d RAMCR.RMD = 1). Access operatio ns involving these addresses are alwa ys non-cacheable. Table 9.3 U Memory Addresses Address Space Memory Address Virtu[...]

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 46 of 1658 REJ09B0261-0100 9.2 Register Descriptions The following registers are related to th e on-chip memory. Table 9.4 Register Configuration Name Abbreviation R/W P4 Address * Area 7 Address * Access Size On-chip memory control register RAMCR R/W H'FF00 0074 H'1F00 00 74 32 OL memory tr[...]

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 47 of 1658 REJ09B0261-0100 9.2.1 On-Chip Memory Control R egister (RAMCR) RAMCR contr ols the protect ive functions i n the on-chi p memory. When updatin g RAMCR, please follow li mitation descri bed at section 8.2.4, On-C hip Memory Control Register (RAMCR). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 [...]

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 48 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 OC2W 0 R/W OC Two-Way Mode For further details, refer to section 8.3.6, OC Two-Way Mode. 5 ICWP D 0 R/W IC Way Prediction Disable For further details, refer to section 8.4.4, Instruction Cache Way Prediction Operation. 4 to 0 — [...]

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 49 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 to 0 L0SSZ Undefine d R/W OL memory Page 0 Block Transfer Source A ddress Select When MMUCR.AT = 0 or RAMCR.RP = 0, these bits select whether the operand ad dresses or L0SADR values are used as bits 15 to 10 of the transfer source[...]

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 50 of 1658 REJ09B0261-0100 9.2.3 OL memory Transfer Source Address Register 1 (LSA1) When MMUCR.AT = 0 or RAMCR.RP = 0, the LS A1 specifies the tran sfer source physical address for bl ock transfer to page 1A or 1B i n the OL memory. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit : 000 Initial va[...]

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 51 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 to 0 L1SSZ Undefined R/W OL memory Pa ge 1 Block Transfer Source Address Select When MMUCR.AT = 0 or RAMCR.RP = 0, these bits select whether the operand ad dresses or L1SADR values are used as bits 15 to 10 of the transfer source [...]

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 52 of 1658 REJ09B0261-0100 9.2.4 OL mem ory Transfer Dest ination Addre ss Register 0 (LDA0) When MMUCR.AT = 0 or RAMCR.RP = 0, LDA0 specifi es the transfer destination physical address for bl ock transfer to pa ge 0A or 0B of the OL memory. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit : 000 In[...]

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 53 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 to 0 L0DSZ Undefined R/W OL memory Pa ge 0 Block Transfer Destinati on Address Select When MMUCR.AT = 0 or RAMCR.RP = 0, these bits select whether the operand ad dresses or L0DADR values are used as bits 15 to 10 of the transfer d[...]

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 54 of 1658 REJ09B0261-0100 9.2.5 OL mem ory Transfer Dest ination Addre ss Register 1 (LDA1) When MMUCR.AT = 0 or RAMCR.RP = 0, LDA1 specifi es the transfer destination physical address for bl ock transfer to page 1A or 1B i n the OL memory. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit : 000 In[...]

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 55 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 to 0 L1DSZ Undefi ned R/W OL memory Pa ge 1 Block Transfer Destinati on Address Select When MMUCR.AT = 0 or RAMCR.RP = 0, these bits select whether the operand ad dresses or L1DADR values are used as bits 15 to 10 of the transfer [...]

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 56 of 1658 REJ09B0261-0100 9.3 Operation 9.3.1 Instr uction Fetch Access from the CPU (1) OL Memory Instruction fetch access from the CPU is perfor med via the cache/RAM inte rnal bus. This access takes more than one cycle. (2) IL Memory Instruction fetch access from the CPU is performed directly via [...]

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 57 of 1658 REJ09B0261-0100 (3) U Memory Operand access from the CPU and read access from the FPU are performed via the read buffer. The read buffe r is configured with t wo sets of one-line 32 -byte buffe rs, and holds up to two lines which have be en accessed through operand acce ss by the CPU and ac[...]

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 58 of 1658 REJ09B0261-0100 (1) When MMU is Enabled (MMUCR.AT = 1) and RAMCR.RP = 1 An address of the OL memory area is specifi ed to the UTLB VPN field, and to the physical address of the tr ansfer source (in the case of the PREF instruction) or th e transfer destination (in the case of the OCBWB inst[...]

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 59 of 1658 REJ09B0261-0100 When the PREF instruction is issu ed to the OL me mory area, the physical address bits [28:10] a re generated in accordance with the LSA0 or LSA1 specificat ion. The physical address bits [9:5] a re generated fro m the virtual address. The physical add ress bits [4: 0] are f[...]

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 60 of 1658 REJ09B0261-0100 9.4 On-Chip Memory Protective Functions This LSI im plements t he following protective f unctions t o the on-c hip memory by using t he on- chip memory access m ode bit (RMD) and the on-chip memory protectio n enable bit (RP) in the on-chip mem ory control regi ster (RAMC R)[...]

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 61 of 1658 REJ09B0261-0100 9.5 Usage Notes 9.5.1 Page Conflict In the event o f simultane ous access to t he same page from different buses, page c onflict occurs. Although each access is completed co rrectly, this kind of conflict tends to lower OL memory accessibility. Therefore it is advisabl e to [...]

9. On-Chip Memory Rev.1.00 Jan. 10, 2008 Page 2 62 of 1658 REJ09B0261-0100 (2) IL Memory In order to allocate instructions in the IL memory , write an instruction to the IL me mory, execute the following seq uence, then bran ch to the rewritten instructio n. • SYNCO • ICBI @Rn In this case, the target for t he ICBI instructio n can be any addre[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 63 of 1658 REJ09B0261-0100 Section 10 Interrupt Controller (INTC) The interrupt controller (INTC) determines the prio rity of interrupt so urces and controls the flow of interrupt requests to the CPU (SH-4A). The IN TC has registers for setting the priority of each of the interr upts and[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 64 of 1658 REJ09B0261-0100 Figure 10.1 show s a block diagra m of the INTC. Input control Priority determination for e xter nal interrupts (lev els 1 to 15) Priority determination for on-chip peripheral module interrupts (lev els 2 to 31) Bus interface WDT H-UDI DMAC PCIC DU GDT A GPIO i[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 65 of 1658 REJ09B0261-0100 The details of the input control circu it of figure 10.1 are shown in figure 10.2. NMI IRQ/ IRL7 to IRQ/ IRL0 NMI detector * 4 Input control NMI interrupt request INTC IRL mask controller Noise canceller Noise canceller for le vel detection IRL detector * 2 Pri[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 66 of 1658 REJ09B0261-0100 10.1.1 Interrupt Method The basic flo w of exceptio n handlin g for inte rrupts is as follows. In interrupt exceptio n handling, the contents of the pro gram counter (PC), status register (SR), and general regist er 15 (R 15) are save d in the saved p rogram co[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 67 of 1658 REJ09B0261-0100 10.1.2 Interrupt Sources Table 10.1 shows an examp le of the interrupt ty pes. The INTC supports both ex ternal interrupts and on-chip peripheral module interrupts. External interrupts refer to the interrupts inpu t through the external NMI, IRL, and IRQ pins. [...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 68 of 1658 REJ09B0261-0100 Source Number of Sources (Max.) Priority INTEVT Remarks H'320 IRL[3:0] pin = HLLH (H'9) H'C20 IRL[7:4] pin = HLLH (H'9) H'340 IRL[3:0] pin = HLHL (H'A) External interrupts IRL 2 H'C40 IRL[7:4] pin = HLHL (H'A) High H&apos[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 69 of 1658 REJ09B0261-0100 Source Number of Sources (Max.) Priority INTEVT Remarks DMAC(0) 7 H'680 DMINT3 * H'6A0 DMINT4 * On-chip module interrupts * Values set in INT2PRI0 to INT2PRI9 H'6C0 DMINT5 * H'6E0 DMAE0 (channels 0 to 5) * SCIF-ch0 4 H'700 ERI0 * H&apos[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 70 of 1658 REJ09B0261-0100 Source Number of Sources (Max.) Priority INTEVT Remarks SIOF 1 H'CE0 SIOFI MMCIF 4 H'D00 FSTAT Values set in INT2PRI0 to INT2PRI9 H'D20 TRAN On-chip module interrupts * H'D40 ERR H'D60 FRDY DU 1 H'D80 DUI GDTA 3 H'DA0 GACLI H&[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 71 of 1658 REJ09B0261-0100 BRI0, BRI1, BRI2, BRI3, BRI4, BRI5: SCIF channels 0 to 5 break interrupt TXI0, TXI1, TXI2, TXI3, TXI4, TXI5: SCIF channels 0 to 5 transmission data empty interrupt FLSTE: FLCTL error int errupt FLTEND: FLCTL error interrupt FLTRQ0: FLCTL data FIFO transfer requ[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 72 of 1658 REJ09B0261-0100 10.2 Input/Output Pins Table 10.2 sho ws the pin co nfiguration. Table 10.2 INTC Pin Configuration Pin Name Function I/O Description NMI Nonmaskable interrupt input pin Input Nonmaskable interrupt request signal input IRQ/ IRL7 to IRQ/ IRL0 External interrupt i[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 73 of 1658 REJ09B0261-0100 10.3 Register Descriptions Table 10.3 shows the INTC register configur ation. Table 10.4 shows the register states in each operating mode. Table 10.3 INTC Register C onfigurati on Name Abbreviatio n R/W P4 Addres s Area 7 Address Access Size Sync. Clock Interru[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 74 of 1658 REJ09B0261-0100 Name Abbreviatio n R/W P4 Addres s Area 7 Address Access Size Sync. Clock Interrupt source register (affected by the mask state) INT2A1 R H'FFD4 0034 H'1F D4 0034 32 Pck Interrupt mask register INT2MSKR R/W H'FFD4 0038 H'1FD4 0038 32 Pck Int[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 75 of 1658 REJ09B0261-0100 Table 10.4 Register States in Eac h Operating Mode Name Abbreviation Power-on Reset by PRESET Pin/WDT/H-UDI Manual Reset by WDT/Multiple Exception Sleep by SLEEP Instruction Deep Sleep by SLEEP Instruction (DSLP = 1) Interrupt control register 0 ICR0 H'x00[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 76 of 1658 REJ09B0261-0100 Name Abbreviation Power-on Reset by PRESET Pin/WDT/H-UDI Manual Reset by WDT/Multiple Exception Sleep by SLEEP Instruction Deep Sleep by SLEEP Instruction (DSLP = 1) INT2PRI7 H'0000 0000 H'0000 0000 Retained Retained INT2PRI8 H'0000 0000 H'0[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 77 of 1658 REJ09B0261-0100 10.3.1 External Interrupt Re quest Registers (1) Interrupt Control Register 0 (ICR0) ICR0 is a 32-bit readable and partially writable register that sets the input signa l detection mode for the exte rnal interrupt input pins and NMI pin, and indica tes the leve[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 78 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 25 NMIB 0 R/W NMI Block Mode Selects whether an NMI interrupt is held until the BL bit in SR is cleared to 0 or detected immediate ly when the BL bit in SR of the CPU is set to 1. 0: An NMI interrupt is held wh en the BL b[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 79 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 21 LVLMODE 0 R/W Level-sense IRQ/ IRL with holding function Selects whether or not to use the holding func tion for level-sense IRQ and IRL interrupts. 0: Level-sense IRQ and IRL interrupt requests are hel d (initial value[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 80 of 1658 REJ09B0261-0100 (2) Interrupt Control Register 1 (ICR1) ICR1 is a 32-bit readable/writ able register that specifies the individual input signal detection modes for the respective external interrupt inpu t pins IRQ/ IRL7 to IRQ/ IR L0 . These settings are only valid whe n IRLM0[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 81 of 1658 REJ09B0261-0100 IRQ and IRL Interrupt Requests). 2. When the IRQnS setting is changed from edge sens e (IRQnS is 00 or 01) to level sense (IRQnS is 10 or 11), the IRQ interr upt source that has been edge sensed is cleared. When the IRQnS setting is changed from level se nse (I[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 82 of 1658 REJ09B0261-0100 (3) Interrupt Priority Register (INTPRI) INTPRI is a 32-bit readable/writable reg ister used to set the priori ties of IRQ[ 7:0] (as leve ls from 15 to 0). These settings are only valid f or IRQ/ IRL 7 to IRQ/ IRL4 or IRQ/ IRL3 to IRQ/ IRL0 when set up as indi [...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 83 of 1658 REJ09B0261-0100 (4) Interrupt Source Re gister (INTREQ) INTREQ is a 32-bit readable and cond itionally writable register that indicates which of the IRQ [n] (n = 0 to 7) interrupts is currently asserting a request for the INTC. Even if an interrupt is mask ed by the settin g i[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 84 of 1658 REJ09B0261-0100 (5) Interrupt Mask Register 0 (INTMSK0) INTMSK0 is a 32-bit readable and co nditionally writable register that sets masking for each of the interrupt requests IRQn (n = 0 to 7). To clear the mask setting for an interrupt, write 1 to the corresponding bit in INT[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 85 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 26 IM05 1 R/W Sets masking of individual pin interrupt source on IRQ5. 25 IM06 1 R/W Sets masking of individual pin interrupt source on IRQ6. 24 IM07 1 R/W Sets masking of individual pin interrupt source on IRQ7. [When rea[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 86 of 1658 REJ09B0261-0100 (6) Interrupt Mask Register 1 (INTMSK1) INTMSK1 is a 32-bit readable and co nditionally writable register that sets masking for IRL interrupt requests. To clear the mask setting for the interrupt, write 1 to th e corresponding bit in INTMSKCLR 1. Writing 0 to t[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 87 of 1658 REJ09B0261-0100 (7) Interrupt Mask Register 2 (INTMSK2) INTMSK2 is a 32-bit readable and co nditionally writable register that sets masking for IRL interrupt requests for input lev el pattern on the IRL pins. To clear the mask setting for the interrupt, write 1 to the corresp [...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 88 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 26 IM010 0 R/W Masks the interr upt source of IRL3 to IRL0 = LHLH (H'5). 25 IM009 0 R/W Masks the interr upt source of IRL3 to IRL0 = LHHL (H'6). 24 IM008 0 R/W Masks the interr upt source of IRL3 to IRL0 = LHHH [...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 89 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 15 IM115 0 R/W Masks the interr upt source of IRL7 to IRL4 = LLLL (H'0). 14 IM114 0 R/W Masks the interr upt source of IRL7 to IRL4 = LLLH (H'1). 13 IM113 0 R/W Masks the interr upt source of IRL7 to IRL4 = LLHL [...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 90 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 2 IM102 0 R/W Masks the interrupt source of IRL7 to IRL4 = HHLH (H'D). 1 IM101 0 R/W Masks the interrupt source of IRL7 to IRL4 = HHHL (H'E). [When read] 0: The interrupt is accepted. 1: The interrupt is masked. [...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 91 of 1658 REJ09B0261-0100 (8) Interrupt Mask Clear Re gister 0 (INTMSKCLR0) INTMSKCLR0 is a 32-bit write-only register that clears the mask settings fo r each of the interrupt requests IRQn (n = 0 to 7 ). Undefine d values are read from t his register. 16 17 18 19 20 21 22 23 24 25 26 2[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 92 of 1658 REJ09B0261-0100 (9) Interrupt Mask Clear Re gister 1 (INTMSKCLR1) INTMSKCLR1 is a 32-bit write-only register th at clears the mask settings for the IRL interrupt requests. Unde fined values are read from t his register. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 93 of 1658 REJ09B0261-0100 (10) Interrupt Mask Clear Re gister 2 (INTMSKCLR2) INTMSKCLR2 is a 32-bit write-only register th at clears the mask settings for the IRL interrupt requests for each input level pattern on the IRL pins. Undefine d values ar e read from t his register. 16 17 18 1[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 94 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 23 IC007 0 R/W Clears masking of the interrupt source of IRL3 to IRL0 = HLLL (H'8). 22 IC006 0 R/W Clears masking of the interrupt source of IRL3 to IRL0 = HLLH (H'9). 21 IC005 0 R/W Clears masking of the interru[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 95 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 11 IC111 0 R/W Clears masking of the interrupt source of IRL7 to IRL4 = LHLL (H'4). 10 IC110 0 R/W Clears masking of the interrupt source of IRL7 to IRL4 = LHLH (H'5). 9 IC109 0 R/W Clears mask ing of the interru[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 96 of 1658 REJ09B0261-0100 (11) NMI Flag Control Re gister (NMIFC R) NMIFCR is a 32-bit readable and co nditionally writa ble reg ister that has an NMI flag (N MIFL bit). The NMIFL bit is automatically set to 1 when an NMI interrupt is detected by the INTC. Writing 0 to the NMIFL bit cle[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 97 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 16 NMIFL 0 R/(W) NMI Flag (NMI Interrupt Request Detection) Indicates whether an NMI interrupt req uest signal has been detected. This bit is automatically set to 1 when the INTC detects an NMI interrupt request. Write 0 t[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 98 of 1658 REJ09B0261-0100 10.3.2 User Mode Interrupt Disable Function (1) User Interrupt Mask Le vel Se tting Register (USERIMASK) USERIMASK is a 32-bit readable and c onditionally writable register that sets the acceptable interrupt level. This register is allocated to the 64-Kbyte pag[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 2 99 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Description 31 to 24 (Code for writing) H'00 R/W Code for writing (H'A5) These bits are always read as 0. Set these bits to H'A5 when writing to the UIMASK bits (Write to the UIMASK bits with these bits set to H'A5[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 00 of 1658 REJ09B0261-0100 3. Branch to the device driver. 4. In the device driver operat ing in user mode, set the UIM ASK bits to mask the B-type interrupts. 5. Process more urgent i nterrupts i n the device driver. 6. Clear the UIMASK bit to 0 and ret urn from the processing by t he d[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 01 of 1658 REJ09B0261-0100 Table 10.5 Interrupt Request Sou rces and INT2PRI0 to INT2PRI9 Bits Register 28 to 24 20 to 16 12 to 8 4 to 0 INT2PRI0 TMU channel 0 TMU channel 1 TMU chann el 2 TMU channel 2 input capture INT2PRI1 TMU channel 3 TMU channel 4 TMU chann el 5 Reserved * INT2PRI2[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 02 of 1658 REJ09B0261-0100 (2) Interrupt Source Register (Not affect ed by Mask Setting) (INT2A0) INT2A0 is a 32-bit read-o nly register t hat indicat es the interrupt sources of on-chip peri pheral modules. Even if an interr upt is masked by the interr upt mask regi ster, the correspond[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 03 of 1658 REJ09B0261-0100 Bit Initial Value R/W Source Function Description 21 Undefined R HSPI HSPI interrupt source indication 20 Undefi ned R SIOF SIOF interrupt source indication 19 Undefi ned R PCIC (5) PCIERR and PCIPWD3 to PCIPWD0 interrupt source indication 18 Undefi ned R PCIC [...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 04 of 1658 REJ09B0261-0100 Bit Initial Value R/W Source Function Description 5 Undefined R SCIF channel 3 SCIF channel 3 interrupt source indication 4 Undefined R SCIF channel 2 SCIF channel 2 interrupt source indication 3 Undefined R SCIF channel 1 SCIF channel 1 interrupt source indica[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 05 of 1658 REJ09B0261-0100 Table 10.7 Reflection time for INT2A0 an d INT2A1 when Interrupt Source Bit in Peripheral Module Is Set/Cleared Module Relation between Setting/Clear ing Interrupt Source of Module and Indication by IN T2A0 and INT2A1 WDT, TMU, SCIF, HSPI, S IOF, MMCIF, DU, SSI[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 06 of 1658 REJ09B0261-0100 Module Relation between Setting/Clear ing Interrupt Source of Module and Indication by IN T2A0 and INT2A1 DMAC Interrupt sources DMAE0, DMAE1 When the DMAE0 or DMAE1 interrupt source bit (i.e. the AE bit in DMAOR0 or DMAOR1) is set, the same interrupt status in[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 07 of 1658 REJ09B0261-0100 (3) Interrupt Source Register (Affecte d by Mask States) (INT2A1) INT2A1 is a 32-bit read-o nly register t hat indicat es the interrupt sources of on-chip peri pheral modules. If a n interrupt is maske d by the int errupt mas k register, the c orresponding bit [...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 08 of 1658 REJ09B0261-0100 Bit Initial Value R/W Source Function Description 20 0 R SIOF SIOF interrupt source indication 19 0 R PCIC (5) PCIERR an d PCIPWD3 to PCIPWD0 interrupt source indication 18 0 R PCIC (4) PCIINTD interrupt source indication 17 0 R PCIC (3) PCIINTC interrupt sourc[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 09 of 1658 REJ09B0261-0100 Bit Initial Value R/W Source Function Description 3 0 R SCIF channel 1 SCIF channel 1 interrupt source indication 2 0 R SCIF channel 0 SCIF channel 0 interrupt source indication 1 0 R TMU channels 3 to 5 TMU channel 3 to 5 interrupt source indication 0 0 R TMU [...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 10 of 1658 REJ09B0261-0100 (4) Interrupt Mask Regi ster (INT2MSKR) INT2MSKR is a 32-bit read able/writable register th at can mask interrupts for sources indicated in the interrupt source reg ister. When a bit in this register is set to 1, the in terrupt in the corresponding bit is not n[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 11 of 1658 REJ09B0261-0100 Bit Initial Value R/W Source Function Description 18 1 R/W PCIC (4) Masks the PCIINTD interrupt 17 1 R/W PCIC (3) Masks the PCIINTC interrupt 16 1 R/W PCIC (2) Masks the PCIINTB interrupt 15 1 R/W PCIC (1) Masks the PCIINTA interrupt 14 1 R/W PCIC (0) Masks the[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 12 of 1658 REJ09B0261-0100 (5) Interrupt Mask Clear Register (INT2MSKCR) INT2MSKCR is a 32-bit write-only reg ister that clears the masking set in the interrupt mask register. When the corresponding bit in this register is set to 1, the interrupt source masking is cleared. These bits are[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 13 of 1658 REJ09B0261-0100 Bit Initial Value R/W Source Function Description 18 0 R/W PCIC (4) Clears the PCIINTD interrupt masking 17 0 R/W PCIC (3) Clears the PCIINTC interrupt masking 16 0 R/W PCIC (2) Clears the PCIINTB interrupt masking 15 0 R/W PCIC (1) Clears the PCIINTA interrupt[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 14 of 1658 REJ09B0261-0100 10.3.4 Individual On-Chip Modul e Interrupt Source Re gist ers (INT2B0 to INT2B 7) INT2B0 to INT2B7 are registers th at indica te more details on each interrupt source, in a ddition to the interrupt source that is corresponding to each module a n d is indicated[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 15 of 1658 REJ09B0261-0100 (2) INT2B1: Detailed Interrupt Sources for the SCIF Module Bit Name Detailed Source Description SCIF 31 to 24 ⎯ Reserved These bits are read as 0 and cannot be modified. 23 TXI5 SCIF channe l 5 transmit FIFO data empty interrupt 22 BRI5 SCIF channel 5 break i[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 16 of 1658 REJ09B0261-0100 Module Bit Name Detailed Source Description SCIF 11 TXI2 SCIF channel 2 transmit FIFO data empty interrupt 10 BRI2 SCIF channel 2 break interrupt or overrun error interrupt 9 RXI2 SCIF channel 2 receiv e FIFO data full interrupt or receive data ready interrupt [...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 17 of 1658 REJ09B0261-0100 (3) INT2B2: Detailed Interrupt Sources for the DMAC Module Bit Name Detailed Source Description DMAC 31 to 14 ⎯ Reserved These bits are read as 0 and cannot be modified. 13 DMAE1 Channe ls 6 to 11 DMA address error interrupt 12 DMINT11 Channel 11 D MA transfe[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 18 of 1658 REJ09B0261-0100 (4) INT2B3: Detailed Interrupt Sources for the PCIC Module Bit Name Detailed Source Description PCIC 31 to 10 ⎯ Reserved These bits are read as 0 and cannot be modified. 9 PCIPWD0 PCIC power state D0 state interrupt 8 PCIPWD1 PCIC power state D1 state interru[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 19 of 1658 REJ09B0261-0100 (5) INT2B4: Detailed Interrupt Sources for the MMCIF Module Bit Name Detailed Source Description MMCIF 31 to 4 ⎯ Reserved These bits are read as 0 and cannot be modified. 3 FRDY FIFO ready end interrupt 2 ERR CRC error inter rupt, data timeout error interrupt[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 20 of 1658 REJ09B0261-0100 (7) INT2B6: Detailed Interrupt Sources for the GPIO Module Bit Name Detailed Source Description GPIO 31 to 26 ⎯ Reserved These bits are read as 0 and cannot be modified. 25 PORTL7I GPIO interrupt from port L pin 7 24 PORTL6I GPIO interrupt from port L pin 6 G[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 21 of 1658 REJ09B0261-0100 (8) INT2B7: Detailed Interrupt Sources for the GDTA Module Bit Name Detailed Source Description GDTA 31 to 3 ⎯ Reserved These bits are read as 0 and cannot be modified. 2 GAERI GDTA error interrupt 1 GAMCI MC transfer end interrupt GDTA interrupt sources are [...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 22 of 1658 REJ09B0261-0100 10.3.5 GPIO Interrupt Set Re gister (INT2GPIC) INT2GPIC enables inte rrupt r equests in put from the pins 0 to 5 of port E, pi ns 1 to 4 of port H, pins 6 and 7 of port L , as GPIO interrupt s. A GPIO interrupt is a low-active interrup t. Enab le interrupt requ[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 23 of 1658 REJ09B0261-0100 Bit Name Initial Value R/W Function Description 18 PORTH3E 0 R/W Enables interrupt request from pin 3 of port H. 17 PORTH2E 0 R/W Enables interrupt request from pin 2 of port H. 16 PORTH1E 0 R/W Enables interrupt request from pin 1 of port H. 15 to 11 ⎯ All 0[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 24 of 1658 REJ09B0261-0100 10.4 Interrupt Sources There are four types of interrup t sources, NMI, IRQ, IRL, and on -chip mo dule inter rupts. Each interrupt has a priority level (16 to 0). Level 16 i s the highe st and level 1 is the lowest. When the level is set to 0, the interrupt is [...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 25 of 1658 REJ09B0261-0100 (2) Dependence o n ICR0.LVL MODE Setting For the IRQ i nterrupt at l evel detect ion, ther e are the followin g features a ccording to the setting of ICR0.LVLMODE. The initial v alue of the ICR0 bit in LVLMODE is 0. It is recommended to set the bit to 1 be fore[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 26 of 1658 REJ09B0261-0100 Priority encoder Interrupt requests SH7785 IRQ/ I R L3 to IRQ/ I R L 0 IRQ/ I R L 7 to IRQ/ I R L4 I R L 7 to I R L4 I R L3 to I R L 0 Interrupt requests Priority encoder Figure 10.3 Example of IRL Interrupt Connection Table 10.12 IRL Interrupt Pins (IRL[3 :0],[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 27 of 1658 REJ09B0261-0100 The priority of IRL interrupts should be retained from when an i n terr upt is accepted to when interrupt handling starts. The l evel can be ch anged to a hi gher level . When the INTMU bit in CPUOPM is set to 1, the interru pt mask level (IMASK) bit in SR is a[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 28 of 1658 REJ09B0261-0100 An on-chi p peripheral module interrupt source fl ag or an int errupt enable fl ag should be update d when the BL bit in SR i s set to 1 or when th e correspondi ng interrupt is not ge nerated b y the setting of interrupt masking occurs. To preven t the accepta[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 29 of 1658 REJ09B0261-0100 An interrupt request is masked if priority level H'01 is set. INTC distin g uishes between priority levels H'1A and H'1B, althou g h both become the same level after truncatin g the least si g nificant bit for the CPU. INTC Priority level: hi g h[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 30 of 1658 REJ09B0261-0100 Table 10.13 Interrupt Except ion Handling and Priority Interrupt Source INTEVT Code Interrupt Priority Mask/Clear Register & Bit Interrupt Source Register Detail Source Register Priority within Sets of Sources Default Priority NMI ⎯ H'1C0 16 ⎯ ⎯ [...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 31 of 1658 REJ09B0261-0100 Interrupt Source INTEVT Code Interrupt Priority Mask/Clear Register & Bit Interrupt Source Register Detail Source Register Priority within Sets of Sources Default Priority IRL[3:0] = HL LL (H'8) H'300 7 INTMSK2[7] INTMSKCLR 2[7] ⎯ ⎯ High High [...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 32 of 1658 REJ09B0261-0100 Interrupt Source INTEVT Code Interrupt Priority Mask/Clear Register & Bit Interrupt Source Register Detail Source Register Priority within Sets of Sources Default Priority IRQ IRQ[0] H'240 INTPRI [31:28] INTMSK0[31] INTMSKCLR0 [31] INTREQ [31] ⎯ High[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 33 of 1658 REJ09B0261-0100 Interrupt Source INTEVT Code Interrupt Priority Mask/Clear Register & Bit Interrupt Source Register Detail Source Register Priority within Sets of Sources Default Priority DMAC(0) DMINT0 * H'620 INT2B3[0] High High DMINT1 * H'640 INT2B3[1] DMINT2 [...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 34 of 1658 REJ09B0261-0100 Interrupt Source INTEVT Code Interrupt Priority Mask/Clear Register & Bit Interrupt Source Register Detail Source Register Priority within Sets of Sources Default Priority SCIF-ch2 ERI2 * INT2B1[8] High RXI2 * H'980 INT2PRI2 [12:8] INT2MSKR[4] INT2MSKC[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 35 of 1658 REJ09B0261-0100 Interrupt Source INTEVT Code Interrupt Priority Mask/Clear Register & Bit Interrupt Source Register Detail Source Register Priority within Sets of Sources Default Priority PCIC(5) PCIERR H'AA0 INT2B4[5] High High PCIPWD3 H'AC0 INT2B4[6] PCIPWD2 H&[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 36 of 1658 REJ09B0261-0100 Interrupt Source INTEVT Code Interrupt Priority Mask/Clear Register & Bit Interrupt Source Register Detail Source Register Priority within Sets of Sources Default Priority HAC-ch1 HAC I1 H'EE0 INT2PRI6 [20:16] INT2MSKR[13] INT2MSKCLR [13] INT2A0[13] IN[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 37 of 1658 REJ09B0261-0100 10.5 Operation 10.5.1 Interrupt Sequence The sequence of interrupt operations is described below. Figure 10.4 shows a fl owchart of the operations. 1. Interrupt request sources send i nterrupt req uest signals t o the INTC. 2. Th e INTC selects the interrupt wi[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 38 of 1658 REJ09B0261-0100 Pro g ram execution state Interrupt g enerated? ICR0.MAI = 1? SR.BL = 0 or sleep mode? Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No NMI? No Yes No No Yes Is NMI input low? Level 15 interrupt? No No No Set interrupt source code in INTE[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 39 of 1658 REJ09B0261-0100 10.5.2 Multiple Interrupts To handle multiple i nterrupts, the procedure for the inte rrupt handl ing routi ne should be as follows. 1. To ide ntify the in terrupt sour ce, set th e value of IN TEVT to an off set and bran ch it to the interrupt handling routine[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 40 of 1658 REJ09B0261-0100 10.6 Interrupt Response Time Table 10.14 s hows response t ime. The response time is the interval from generation of an interrupt request until the start of interrupt excep tion handling and until fetching of the first instruction of the exception h andling rou[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 41 of 1658 REJ09B0261-0100 Table 10.15 s hows response t ime. The response tim e is from the interrupt exception handling to the start of fetching th e first instruction in exception h andling routine. In this case, suppose that the setting values of the following registers th at enable [...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 42 of 1658 REJ09B0261-0100 Table 10.16 s hows response t ime. The response tim e is the time until when the interrupt request signal from the INTC to the CPU is n egated. In this case, suppose that the setting valu es of the following regi sters, INTMSK 0, INTMSK1, INTM SK2, INT2MSKR, an[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 43 of 1658 REJ09B0261-0100 10.7 Usage Notes 10.7.1 Example of Handing Routine of IRL Interrupts and Level Detection IRQ Interrupts when ICR0.LVLMODE = 0 When ICR0.LVLMODE is 0, IRL interrupt reques ts and level detect ion IRQ i nterrupt requests that the INTC retains should be cleared in[...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 44 of 1658 REJ09B0261-0100 10.7.2 Notes on Setti ng IRQ/ IR L[7 :0] Pin F unction When the IRQ/ IRL[7:0] pin f unctions are switched, the INTC may ret ain an incorrect ly detected interrupt re quest. Therefore, mask the IRL a nd IRQ interrupt requests before sw itching the IRQ/ IRL[7: 0][...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 45 of 1658 REJ09B0261-0100 10.7.3 Clearing IR Q and IRL Interru pt Requests To clear the interrupt request retained in the INTC, follow th e procedure bel ow. (1) Clearing Inter rupt Request Indepe ndent from ICR0.LVLMODE Setting ⎯ Clearing IRQ interrupt requ ests at edge detection To [...]

10. Interrupt Controller (INTC) Rev.1.00 Jan. 10, 2008 Page 3 46 of 1658 REJ09B0261-0100[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 47 of 1658 REJ09B0261-0100 Section 11 Local Bus State Controller (LBSC) The local bus state controller (LBSC) di vides the external memory sp ace and outputs control signals according to t he specification of each memor y and bus interface . The LBSC function enables connection of [...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 48 of 1658 REJ09B0261-0100 • MPX interface ⎯ Address/data multiplex ing Connectable area: 0 to 6 Settable bus widt h: 64 and 32 bits • Byte control SRAM interface ⎯ SRAM interface with byte control Connectable area: 1 and 4 Settable bus widt h: 64, 32 and 16 bits • PCMCIA[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 49 of 1658 REJ09B0261-0100 Figure 11.1 show s a block diagra m of the LBSC. Bus interface CSnWCR CSnBCR BCR CSnPCR Memory controller Area controller Wait controller LBSC SuperHyway bus Module bus RDY CS0 to CS6 CE2A to CE2B BS RD R/ W WE7 to WE0 IORD , IOWR REG IOIS16 Le g end: CSn[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 50 of 1658 REJ09B0261-0100 11.2 Input/Output Pins Table 11.1 sho ws the LBSC pi n configuratio n. Table 11.1 Pin Configuration Pin Name Function I/O Description A25 to A0 Address Bus O Address o utput D63 to D0 Data Bus I/O Data input/output These pins are multiplexed as follows: D[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 51 of 1658 REJ09B0261-0100 Pin Name Function I/O Description WE0 / REG Data Enable 0 O Write strobe signal for D7 to D0 in SRAM interface setting REG signal in PCMCIA interface setting WE1 Data Ena ble 1 O Write strobe signal for D15 to D8 in SRAM interface setting Write strobe sig[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 52 of 1658 REJ09B0261-0100 Pin Name Function I/O Description BACK Bus Request Acknowledge O Bus request acknowl edge signal Multiplexed with Port M0 (GPIO input/output). CE2A * 1 , CE2B * 2 PCMCIA Card Select O CE2A , CE2B in PCMCIA interface setting Only valid in little endian mod[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 53 of 1658 REJ09B0261-0100 Pin Name Function I/O Description MODE11, MODE12 Bus Mode Switching I Signals for switching buses: lo cal bus, PCI bus or DU bus Bus modes for D63 to D32 and WE7 to WE4 are switched at a power-on reset by the PRESET pin MODE11: Multiplexed with SCIF4_SCK [...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 54 of 1658 REJ09B0261-0100 11.3 Overview of Areas 11.3.1 Space Divisions The LSI has a 32-bit virtual addres s space as the architecture. The vi rtual address space is divided into five areas according t o the upper address valu e. Also, the memory space of the local bus has a 29-b[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 55 of 1658 REJ09B0261-0100 Table 11.2 LBSC Extern al Memory Space Map Area External addresses Size Connectable Memory Specifiable Bus Width (bits) Access Size * 7 SRAM 8, 16, 32, 64 * 1 Burst ROM 8, 16, 32, 64 * 1 0 H'0000 0000 to H'03FF FFFF 64 Mbytes MPX 32, 64 * 1 8/16[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 56 of 1658 REJ09B0261-0100 Area External addresses Size Connectable Memory Specifiable Bus Width (bits) Access Size * 7 SRAM 8, 16, 32, 64 * 2 MPX 32, 64 * 2 Burst ROM 8, 16, 32, 64 * 2 6 H'1800 0000 to H'1BFF FFFF 64 Mbytes PCMCIA 8, 16 * 2, 5 8/16/32 bits, 32 bytes 7 * [...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 57 of 1658 REJ09B0261-0100 11.3.2 Memory Bus Width The memory b us width of the LBSC ca n be set independen tly for each a rea. In area 0, a bus width of 8, 16, 32, or 64 bits is selec ted according to th e external pin settings at a powe r-on reset by the PRESET pin. The relation [...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 58 of 1658 REJ09B0261-0100 11.3.3 PCMCIA Support This LSI supports the PCMCIA interface specificati ons for areas 5 and 6 in the external memory space. The IC memory card interfac e and I/O card inte rface specified in JEIDA sp ecifications version 4.2 (PCMCIA2.1) are supporte d. B[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 59 of 1658 REJ09B0261-0100 Table 11.4 PCMCIA Support Interface IC Memory Card Interface I/O Card Interface Pin Signal Name I/O Function Signal Name I/O Function Corresponding Pin of SH7785 1 GND Ground GND Ground ⎯ 2 D3 I/O Data D3 I/O Data D3 3 D4 I/O Data D4 I/O Data D4 4 D5 I/[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 60 of 1658 REJ09B0261-0100 IC Memory Card Interface I/O Card Interface Pin Signal Name I/O Function Signal Name I/O Function Corresponding Pin of SH7785 30 D0 I/O Data D0 I/O Data D0 31 D1 I/O Data D1 I/O Data D1 32 D2 I/O Data D2 I/O Data D2 33 WP * 1 O Write protect IOIS16 O 16-b[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 61 of 1658 REJ09B0261-0100 IC Memory Card Interface I/O Card Interface Pin Signal Name I/O Function Signal Name I/O Function Corresponding Pin of SH7785 60 RSRVD Reserved INPACK O Input acknowledge ⎯ 61 REG I Attribute memory space select REG I Attribute memory space select REG 6[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 62 of 1658 REJ09B0261-0100 11.4 Register Descriptions Table 11.5 shows registers for the LBSC. These registers contro l the interface with each memory, wait state, etc. Table 11.5 Register Configuration (1) Register Name Abbrev. R/W P4 Address Area 7 Address Access Size * Sync Cloc[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 63 of 1658 REJ09B0261-0100 Table 11.5 Register Configuration (2) Register Name Abbrev. Power-on Reset by PRESET Pin/WDT/H-UDI Manual Reset by WDT/Multiple Exception Sleep by SLEEP Command Deep Sleep by SLEEP Command (DSLP = 1) Memory Address Map Select Register MMSELR H'0000 0[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 64 of 1658 REJ09B0261-0100 11.4.1 Memory Address Map Select Register (MMSELR) MMSELR is a 32-bit register that selects memory address maps for areas 2 to 5. This register should be accessed at t h e address H'FC 40 0020 in longword. To preve nt incorrect writing, writing is ac[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 65 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 to 0 AREASEL 000 R/W DDR2-S DRAM/PCI Memory Space Select 000: Sets area 3 (H'0C00 0000 to H'0FFF FFFF) as the DDR2-SDRAM space and the other areas as the local bus space 001: Sets area 3 (H'0C00 [...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 66 of 1658 REJ09B0261-0100 Example: ----------------------------------------------------------------------- MOV.L #H'FC400020, R0 ; MOV.L #MMSELR_DATA, R1 ; MMSELR_DATA=Writing value of MMSELR SYNCO ; (upper word=H'A5A5) MOV.L R1, @R0 ; Writing to MMSELR MOV.L @R0, R2 MOV[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 67 of 1658 REJ09B0261-0100 11.4.2 Bus Control Re gister (BCR) BCR is a 32-bit readable/writable register that sp ecifies the function, bus cycle state, etc for each area. BCR is initialized to H'0000 0000 in big endian mode and to H'8000 0000 in little endian mode by a po[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 68 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 26 DPUP 0 R/W Data Pin Pu ll-Up Resistor Control Specifies the pull-up resistor state of the data pins (D63 to D0). This bit is initialized at a power-on reset. The pins are not pulled up when access is perfor me[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 69 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 19, 18 ⎯ All 0 R Reserved These bits are always read as 0. The write value shou ld always be 0. 17 BREQEN 0 R/W BREQ Enable Specifies whether an external request can be accepted or not. In the initialized state[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 70 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 to 0 ASYNC[6:0] All 0 R/W Asynchronous Input These bits enable asynchronous inp uts of the corresponding pins. 0: CLKOUT-synchronous inputs to the corresponding pins 1: CLKOUT-asynchronous inputs to the corresp[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 71 of 1658 REJ09B0261-0100 11.4.3 CSn Bus Control Reg ister (CSnBCR) CSnBCR are 32-bit readable/writable registers that specify the bus width for area n (n = 0 to 6), idle mode between cycles, burst ROM setting and memory typ es. Some types of memory continue to driv e the data bus[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 72 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 30 to 28 IWW 111 R/W Idle Cycles between Write-Read/Wr ite-Write These bits specify the number of idle cycles to be inserted after the access of the memory connected to the space. The target cycles are write-read[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 73 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 23 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 22 to 20 IWRWS 111 R/W Idle Cycles bet ween Read-Write in Same Space These bits specify the number of idle cycles to be insert[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 74 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 15 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 14 to 12 IWRRS 111 R/W Idle Cycles bet ween Read-Read in Same Space These bits specify the number of idle cycles to be inserte[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 75 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 9, 8 SZ 11 R/W * Bus Width In CS0BCR, the external pins (MODE5 and MODE6) to specify the bus size are sampled at a power- on reset. When using the MPX interface, set these bit s to 00 or 11. When using the byte c[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 76 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 to 4 BW 111 R/W Burst Pitch When the burst ROM interfac e is used, these bits specify the number of wait cycles to be insert ed after the second data access in a burst transfer. 000: No idle cycle inserted, RDY[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 77 of 1658 REJ09B0261-0100 11.4.4 CSn Wait Control Register (CSnWCR ) CSnWCR (n = 0 to 6) are 32-bit readable/writable re gisters that specify the number of wait cycles to be inserted for areas 0 to 6, the number of wait cycles to be inserted preceding the first data in burst memor[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 78 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 27 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 26 to 24 ADH 111 R/W Address Hold Cycle These bits specify the numbe r of cycles to be inserted as the address hold time with [...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 79 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 19 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 18 to 16 RDH 111 R/W RD Hold Cycle ( RD Negation– CSn Negation Delay Cycle) These bits specify the numbe r of cycles to be i[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 80 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 11 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 10 to 8 WTH 111 R/W WE Hold Cycle ( WE Negation– CSn Negation Delay Cycle) These bits specify the numbe r of cycles to be in[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 81 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 3 to 0 IW[3:0] 1111 R/W Insert Wait Cycle These bits specify the num ber of wait cycles to be inserted. The wait cycles are as follows when the SRAM interface, byte control SRAM interface, burst ROM interface (fi[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 82 of 1658 REJ09B0261-0100 11.4.5 CSn PCMCIA Co ntrol Register ( CSnPCR) CSnPCR is a 32-bit readab le/writable register that specifies the timing for the PCMCIA interface connected to area n (CSnPCR, n = 5 or 6), the sp ace property, an d the assert/negate timing for the OE and WE [...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 83 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 27 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 26 to 24 SAB 111 R/W Space Propert y B These bits specify the space property of PCMCIA connected to the seco nd half of the ar[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 84 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 19 to 16 PCIW 0000 R/W PCMCIA Insert Wait Cycle B These bits specify the num ber of wait cycles to be inserted. The bit settings are selected when the access area of PCMCIA interface is the second half. When the [...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 85 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 14 to 12 TEDA 000 R/W OE / WE Assert Delay A These bits set the delay time from address output to OE / WE assertion when the first half area is accessed with the connected PCMCIA interface. 000: No wait cycle ins[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 86 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 to 4 TEHA 000 R/W OE / WE Negation-Address Delay A These bits set the delay time from OE / WE negation to address hold when the first half area is acces sed with the connected PCMCIA interface. 000: No wait cyc[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 87 of 1658 REJ09B0261-0100 11.5 Operation 11.5.1 Endian/Access Size and Data Alignme nt This LSI supports both big and little end ian modes. In big endian mode, the most sign ificant byte (MSByte) in a string of byte data is stored at address 0, and in little endian mode, the least[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 88 of 1658 REJ09B0261-0100 Table 11.6 64-Bit Extern al Device/Big Endi an Access and Data Alignment (1) Operation Data Bus Access Size Address No. D63 to D56 D55 to D48 D47 to D40 D39 to D32 D31 to D24 D23 to D16 D15 to D8 D7 to D0 8n 1 Data 7 to 0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8n + [...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 89 of 1658 REJ09B0261-0100 Table 11.7 64-Bit Extern al Device/Big Endi an Access and Data Alignment (2) Operation Strobe Signal Access Size Address No. WE7 WE6 WE5 WE4 WE3 WE2 WE1 WE0 8n 1 Asserted ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8n + 1 1 ⎯ Asserted ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8n + 2 1 ?[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 90 of 1658 REJ09B0261-0100 Table 11.8 32-Bit Extern al Device/Big-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No. D31 to D24 D23 to D16 D15 to D8 D7 to D0 WE3 WE2 WE1 WE0 4n 1 Data 7 to 0 ⎯ ⎯ ⎯ Asserted 4n + 1 1 ⎯ Data 7 to 0 ⎯ ?[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 91 of 1658 REJ09B0261-0100 Table 11.9 16-Bit Extern al Device/Big-E ndian Access and Data Alignment Operation Data B us Strobe Signals Access Size Address No. D31 to D24 D23 to D16 D15 to D8 D7 to D0 WE3 WE2 WE1 WE0 2n 1 ⎯ ⎯ Data 7 to 0 ⎯ Asse rted Byte 2n + 1 1 ⎯ ⎯ ⎯ D[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 92 of 1658 REJ09B0261-0100 Table 11.10 8-Bit External Device/Big-E ndian Access and Data Ali gnment Operation Data Bus Strobe Si gnals Access Size Address No. D31 to D24 D23 to D16 D15 to D8 D7 to D0 WE3 WE2 WE1 WE0 Byte n 1 ⎯ ⎯ ⎯ Data 7 to 0 Asserted 2n 1 ⎯ ⎯ ⎯ Data 15[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 93 of 1658 REJ09B0261-0100 Table 11.11 64-Bit Exter nal Device/ Littl e Endian Access and Data Alignment (1) Operation Data Bus Access Size Address No. D63 to D56 D55 to D48 D47 to D40 D39 to D32 D31 to D24 D23 to D16 D15 to D8 D7 to D0 8n 1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Data 7 to 0 [...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 94 of 1658 REJ09B0261-0100 Table 11.12 64-Bit Exter nal Device/ Littl e Endian Access and Data Alignment (2) Operation Strobe Signal Access Size Address No. WE7 WE6 WE5 WE4 WE3 WE2 WE1 WE0 8n 1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Asserted 8n + 1 1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Asse rted ⎯ 8n +[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 95 of 1658 REJ09B0261-0100 Table 11.13 32-Bit Exter nal Device/ Li ttle-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No. D31 to D24 D23 to D16 D15 to D8 D7 to D0 WE3 WE2 WE1 WE0 4n 1 ⎯ ⎯ ⎯ Data 7 to 0 Asserted 4n + 1 1 ⎯ ⎯ Data 7 [...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 96 of 1658 REJ09B0261-0100 Table 11.14 16-Bit Exter nal Device/ Li ttle-Endian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No. D31 to D24 D23 to D16 D15 to D8 D7 to D0 WE3 WE2 WE1 WE0 2n 1 ⎯ ⎯ ⎯ Data 7 to 0 Asserted Byte 2n + 1 1 ⎯ ⎯ Da[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 97 of 1658 REJ09B0261-0100 Table 11.15 8-Bit External Device/Little-E ndian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No. D31 to D24 D23 to D16 D15 to D8 D7 to D0 WE3 WE2 WE1 WE0 Byte n 1 ⎯ ⎯ ⎯ Data 7 to 0 Asserted 2n 1 ⎯ ⎯ ⎯ Data 7[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 98 of 1658 REJ09B0261-0100 11.5.2 Areas (1) Area 0 Area 0 is an area where bits 28 to 26 in the local bu s address are 000. The interface that can be set for this a r ea is the SRAM, burst ROM or MPX interface. A bus width of 8, 16, 32, or 64 bits is selectable by external pins MOD[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 3 99 of 1658 REJ09B0261-0100 For the nu mber of bu s cycles, 0 to 25 wait cy cles to be inserted can be selected by C S1WCR. When the burst ROM interface is used, th e number of a burst pitch is selectable in the range from 0 to 7 with the BW bits in CS1BCR. Any number of wait cycles[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 00 of 1658 REJ09B0261-0100 (4) Area 3 Area 3 is an area where bits 28 to 26 in the local bu s address are 011. The interface that can be set for this area is the SRAM, MPX, or burst ROM interface. A bus width of 8, 16, 32, or 64 bits is selectable by bits SZ in CS3BCR. When th e MP[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 01 of 1658 REJ09B0261-0100 For the nu mber of bu s cycles, 0 to 25 wait cy cles inserted can be selected by CS4WCR. When the burst ROM interface is used, th e number of a burst pitch is selectable in the range from 0 to 7 with the BW bits in CS4BCR. Any number of wait cycles can be[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 02 of 1658 REJ09B0261-0100 CS5PCR. In a ddition, t he number of wait cyc les can be specified in the range from 0 to 50 cycles by the PCWA/ B bit. The number of wai t cycles specifie d by CS5PC R is added t o the value specified by bi ts IW3 to IW0 in CS 5WCR or bits PCIW3 t o PCIW[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 03 of 1658 REJ09B0261-0100 11.5.3 SRAM interface (1) Basic Timing The strobe signals for the SR AM interface in th is LSI are output primar ily based on the SRAM connection. Figure 11.5 shows the basic timin g of the SRAM interface. Normal access without wait cycles is completed in[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 04 of 1658 REJ09B0261-0100 T1 CLKOUT A25 to A0 CS n R/ W RD D31 to D0 (In readin g ) W En D31 to D0 (In writin g ) BS T2 RDY DACKn In this example, DACKn is hi g h-active. Figure 11.5 Basic Timi ng of SRAM Interface[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 05 of 1658 REJ09B0261-0100 Figures 11. 6 to 11.8 sh ow examples of connec tions to SR AM with 3 2-, 16- and 8-bit data width, respectively. •••• •••• •••• •••• •••• A16 A0 CS OE I/O7 I/O0 WE •••• •••• •••• ••••[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 06 of 1658 REJ09B0261-0100 A16 A0 CS O E I/O7 I/O0 W E A17 A1 CS n RD D15 D8 W E1 D7 D0 W E 0 SH7785 128K × 8 bits SRAM A16 A0 CS O E I/O7 I/O0 W E •••• •••• •••• •••• •••• •••• •••• •••• •••• •••• •[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 07 of 1658 REJ09B0261-0100 A16 A0 CS n RD D7 D0 W E 0 SH7785 128K × 8 bits SRAM A16 A0 CS O E I/O7 I/O0 W E •••• •••• •••• •••• •••• •••• •••• •••• Figure 11.8 Example of 8-Bi t Data Width SRAM Connection (2) Wait Cyc[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 08 of 1658 REJ09B0261-0100 T1 CLKOUT A25 to A0 CS n R/ W RD D31 to D0 (In readin g ) WE n D31 to D0 (In writin g ) BS Tw T2 RDY DACKn In this example, DACKn is active-hi g h. (The circle indicates the samplin g timin g .) : Samplin g Timin g Figure 11.9 SRAM Interface Wa it Timing [...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 09 of 1658 REJ09B0261-0100 When software wait insertion is specified by CSnWCR, the extern al wait input signal, RDY , is also sampled. The RDY signal sampling ti ming is shown in figu re 11.10, whe re a single wai t cycle is specified as a software wait. T he RDY signal is sampled[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 10 of 1658 REJ09B0261-0100 (3) Read-Strobe/ Write-Strobe Timing When the SRAM interface is used, the strobe sign al negati on timing i n reading ca n be specified with the RDSPL bit in CSnBCR. For details of settings, see sectio n 11.4.3, CSn Bus Control Register (CSnBCR). The RDSP[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 11 of 1658 REJ09B0261-0100 TAS1 CLKOUT A25-A0 CS n R/ W RD D31-D0 T1 TS1 Tw Tw Tw T2 Tw TH1 TH2 TAH1 * 1 * 2 TS1: CS n assertion - RD assertion delay cycle CSnWCR RDS = 001 TAS1: Address setup wait CSnWCR ADS=001 TAH1: Address hold wait CSnWCR AHS = 001 Tw: Access wait CSnWCR IW = [...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 12 of 1658 REJ09B0261-0100 11.5.4 Burst ROM Interface When the TYPE bit in CSnBCR is set to 010 , a bur st ROM can be connected to areas 0 to 6. The burst ROM interface provides hi gh-spee d access to ROM that ha s a burst access function. The burst access timing of burst ROM is sh[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 13 of 1658 REJ09B0261-0100 T1 TB1 TB2 TB1 TB2 TB1 TB2 T2 CLKOUT A25 to A5 A4 to A0 CS n R/ W RD D31 to D0 (In readin g ) BS RDY Figure 11.12 Burst ROM B asic Timing[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 14 of 1658 REJ09B0261-0100 T1 Twe TB2 TB1 Tw TB2 Tw Tw TB1 TB2 Tw T2 TB1 CLKOUT A25 to A5 A4 to A0 CS n R/ W RD D31 to D0 (In readin g ) BS RDY Figure 11.13 Burst ROM Wait Timing[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 15 of 1658 REJ09B0261-0100 * 2 TAS1 TS1 TB2 TB1 TB2 TB1 TB1 T1 TB2 T2 TAH1 TH1 CLKOUT A25 to A5 A4 to A0 CS n R/ W RD D31 to D0 (In readin g ) BS RDY DACKn * 1 Notes: 1. In this example, DACKn is active-hi g h. 2. When RDSPL in CSnBCR is set to 1. Figure 11.14 Burst ROM Wait Timing[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 16 of 1658 REJ09B0261-0100 11.5.5 PCMCIA Interface By setting the TYPE bits in CS 5BCR a nd CS6BCR, the bus interface for the external space areas 5 and 6 can be set to the IC memory card interface or I/O c ard interface, which is stipulated in JEIDA specification v ersion 4.2 (PCM[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 17 of 1658 REJ09B0261-0100 complement mode. To access the De vice Control Re gister and Alternate Status Register, use a CPU byte access (do not use a DMA transfer), and to access the Data Register, use the CPU word access (do not use a DM A transfer). To access the Data Port use a[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 18 of 1658 REJ09B0261-0100 Table 11.16 Relationship between Addre ss and CE when Usin g PC MCIA Interface Bus (Bits) Read/ Write Access (bits) * 1 Odd/ Even IOIS16 Access CE2 CE1 A0 D15 to D8 D7 to D0 8 Read 8 Even × ⎯ H L L Invalid Read data Odd × ⎯ H L H I nvalid Read data [...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 19 of 1658 REJ09B0261-0100 Bus (Bits) Read/ Write Access (bits) * 1 Odd/ Even IOIS16 Access CE2 CE1 A0 D15 to D8 D7 to D0 Write 8 Even H ⎯ H L L Invalid Write data Odd H First L H H Invalid Write data Dynamic Bus Sizing * 2 Odd H Second H L H Invalid Write data 16 Even H First L [...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 20 of 1658 REJ09B0261-0100 G A25 to A0 D15 to D0 PC card (memory I/O) CD1, CD2 C E1 G C E 2 O E W E / P G M ( I ORD ) ( I OWR ) ( I O I S6 ) W AIT A25 to A0 D15 to D0 PC card (memory I/O) CD1, CD2 C E1 C E 2 O E W E / P G M W AIT A25 to A0 SH7785 D15 to D0 R/ W C E 2B C E 2 A RD W [...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 21 of 1658 REJ09B0261-0100 (1) Memory Card Interface Basic Timing Figure 11.17 shows the basic timing for the PCMCIA memory card interface, and figure 11.18 shows the wait timing for the PC MCIA memory card interface. CLKOUT Tpcm1 Tpcm2 A25 to A0 C Exx R/ W D15 to D0 (In readin g )[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 22 of 1658 REJ09B0261-0100 CLKOUT Tpcm0 A25 to A0 R/ W C Exx R E G RD (In readin g ) D15 to D0 (In readin g ) D15 to D0 (In writin g ) W E1 (In writin g ) BS RDY Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w DACKn In this example, DACKn is active-hi g h. Figure 11.18 Wait Timing for PCMC[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 23 of 1658 REJ09B0261-0100 (2) I/O Card Inte rface Timing Figures 11.19 and 11.20 s how the timing for the PCMC IA I/O card interface. When a PCMCIA card is acce ssed as the I/O card in terface, dynamic sizing with the I/O bus width can be performed using t he IOIS16 pin. With the [...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 24 of 1658 REJ09B0261-0100 CLKOUT Tpci1 Tpci2 A25 to A0 R/ W C Exx I C I ORD (In readin g ) D15 to D0 (In readin g ) I C I OWR (In writin g ) D15 to D0 (In writin g ) BS R E G DACKn In this example, DACKn is active-hi g h. Figure 11.19 Basic Timing for PCMCIA I/O Card Inte rface[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 25 of 1658 REJ09B0261-0100 CLKOUT A25 to A0 R/ W C Exx I C I ORD (In readin g ) I C I OWR (In writin g ) D15 to D0 (In readin g ) D15 to D0 (In writin g ) BS RDY I O I S 1 6 Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w R E G DACKn In this example, DACKn is active-hi g h. Figure 11[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 26 of 1658 REJ09B0261-0100 Tpci Tpci0 Tpci1w Tpci2 Tpci2w Tpci0 Tpci Tpci2 Tpci1w Tpci2w CLKOUT A25 to A1 A0 R/ W I ORD ( W E 2 ) (In readin g ) I OWR ( W E3 ) (In writin g ) D15 to D0 (In writin g ) D15 to D0 (In readin g ) BS I O I S 1 6 DACKn C Exx R E G RDY In this example, DAC[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 27 of 1658 REJ09B0261-0100 11.5.6 MPX Interface When both the MODE 7 pin is set to 0 at a pow er-on reset by the PRESET pin, the MPX interface is selected for area 0. The MPX interface is sel ected for areas 1 to 6 by the MPX bit in CS1BCR, CS2BCR, and CS4BCR to CS6BCR. The MPX int[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 28 of 1658 REJ09B0261-0100 CLKOUT CS n BS RD R/ W D31 to D0 RDY SH7785 MPX device CLK CS BS F R AME W E I/O31 to I/O0 RDY Figure 11.22 Example of 32-Bit D ata Width MPX Connection CLKOUT CS n BS RD RD/ WR D63 to D0 RDY SH7785 MPX device CLK CS BS F R AME W E I/O63 to I/O0 RDY Figur[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 29 of 1658 REJ09B0261-0100 Tm1 Tm1 CLKOUT RD / F R AME CS n R/ W D63 to D0 BS Tmd1w Tmd1 RDY D A C K A D0 A Figure 11.24 MPX Interfac e Timing 1 (Single Read Cycle, IW = 0000, No External Wait, 64-Bit Bus Width)[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 30 of 1658 REJ09B0261-0100 Tm1 CLKOUT A RD / F R AME CS n R/ W D63 to D0 BS Tmd1w Tmd1w Tmd1 RDY DACKn D0 In this example, DACKn is active-hi g h. The circles indicate the samplin g timin g . Figure 11.25 MPX Interfac e Timing 2 (Single Read , IW = 0000, One External Wait Insert ed[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 31 of 1658 REJ09B0261-0100 Tm1 CLKOUT A RD / F R AME CS n R/ W D63 to D0 BS Tmd1 RDY DACKn D0 In this example, DACKn is active-hi g h. The circle indicates the samplin g timin g . Figure 11.26 MPX Interfac e Timing 3 (Single Write Cycle, IW = 0000, No External Wait, 64-Bit Bus Widt[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 32 of 1658 REJ09B0261-0100 Tm1 CLKOUT A RD / F R AME CS n R/ W D63 to D0 BS Tmd1w Tmd1w Tmd1 RDY DACKn D0 In this example, DACKn is active-hi g h. Figure 11.27 MPX Interfac e Timing 4 (Single Write Cycle, IW = 0001, One External Wait In serted, 64-Bit Bus Width)[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 33 of 1658 REJ09B0261-0100 Tm1 CLKOUT RD / F R AME CS n R/ W D63 to D0 BS Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 RDY DACKn D1 D2 D3 D0 A In this example, DACKn is active-hi g h. Figure 11.28 MPX Interfac e Timing 5 (Burst Read Cycle, IW = 0000, No Externa l Wait, 64-Bit Bus Width, 32-Byte Data [...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 34 of 1658 REJ09B0261-0100 Tm1 CLKOUT A RD / F R AME CS n R/ W D63 to D0 BS Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4 RDY DACKn D3 D1 D2 D0 In this example, DACKn is active-hi g h. Figure 11.29 MPX Interfac e Timi ng 6 (Burst Read Cycle, IW = 0000, External Wait Control, 64-Bit Bu s Wi[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 35 of 1658 REJ09B0261-0100 Tm1 CLKOUT A RD / F R AME CS n R/ W D63 to D0 BS Tmd1 Tmd2 Tmd3 Tmd4 RDY DACKn D0 D1 D2 D3 In this example, DACKn is active-hi g h. Figure 11.30 MPX Interfac e Timing 7 (Burst Write Cycle, IW = 0000, No External Wait, 64-Bit Width, 32-Byte Data Transfer)[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 36 of 1658 REJ09B0261-0100 D2 D1 Tm1 CLKOUT A RD / F R AME CS n R/ W D63 to D0 BS Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4 RDY DACKn D0 D3 In this example, DACKn is active-hi g h. Figure 11.31 MPX Interfac e Timi ng 8 (Burst Write Cycle, IW = 0001, External Wait Control, 32-Bit Bu s W[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 37 of 1658 REJ09B0261-0100 Tm1 CLKOUT RD / F R AME CS n R/ W D31 to D0 BS Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8 RDY DACKn A In this example, DACKn is active-hi g h. D2 D3 D1 D4 D6 D7 D8 D5 Figure 11.32 MPX Interfac e Timi ng 9 (Burst Read Cycle, IW = 0000, No External Wait,[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 38 of 1658 REJ09B0261-0100 Tm1 CLKOUT A RD / F R AME CS n R/ W D31 to D0 BS Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd7 Tmd8w Tmd8 RDY DACKn D7 D8 D2 D3 D1 In this example, DACKn is active-hi g h. Figure 11.33 MPX Interfac e Timi ng 10 (Burst Read Cycle, IW = 0000, External Wait Control, 32-Bi[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 39 of 1658 REJ09B0261-0100 Tm1 CLKOUT A RD / F R AME CS n R/ W D31 to D0 BS Tmd1 Tmd2 Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8 RDY DACKn D1 D2 D3 D4 D5 D6 D7 D8 In this example, DACKn is active-hi g h. Figure 11.34 MPX Interfac e Timi ng 11 (Burst Write Cycle, IW = 0000, No External Wait, 32-[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 40 of 1658 REJ09B0261-0100 D3 D2 Tm1 CLKOUT A RD / F R AME CS n R/ W D31 to D0 BS Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd7 Tmd8w Tmd8 RDY DACKn D1 D7 D8 In this example, DACKn is active-hi g h. Figure 11.35 MPX Interfac e Timi ng 12 (Burst Write Cycle, IW = 0001, External Wait Control, 32-B[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 41 of 1658 REJ09B0261-0100 11.5.7 Byte Control SR AM Interface The byte control SRAM interface is a memory interface that outputs a byte -select strobe ( WEn ) in both read and write bus cycles. This interface has 16-bit data pins and can be connected to SRAM having an up per byte [...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 42 of 1658 REJ09B0261-0100 A18 to A3 CS n RD R/ W SH7785 64K × 16 bits SRAM D47 to D32 W E5 W E4 D31 to D16 W E3 W E 2 D15 to D0 W E1 W E 0 A15 to A0 CS O E W E I/O15 to I/O0 UB L B A15 to A0 CS O E W E I/O15 to I/O0 UB L B A15 to A0 CS O E W E I/O15 to /O0 UB L B A15 to A0 CS O E[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 43 of 1658 REJ09B0261-0100 T1 T2 CLKOUT A25 to A0 CS n R/ W RD D31 to D0 (In readin g ) BS DACKn RDY W En In this example, DACKn is active-hi g h. Figure 11.38 Basic Read Cycle of Byte Control SRAM (No Wait)[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 44 of 1658 REJ09B0261-0100 TAS1 CLKOUT A25-A0 CS n R/ W W En (In readin g ) (In writin g ) D63-D0 T1 TS1 Tw Tw Tw T2 Tw TH1 TH2 TAH1 * 1 * 2 TS1: CS n assertion - RD assertion delay cycle CSnWCR RDS = 001 TAS1: Address setup wait CSnWCR ADS=001 TAH1: Address hold wait CSnWCR AHS = [...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 45 of 1658 REJ09B0261-0100 T1 Tw Twe T2 CLKOUT A25 to A0 CS n R/ W RD D31 to D0 (In readin g ) BS DACKn RDY W En In this example, DACKn is active-hi g h. Figure 11.40 Wait State Timing of Byte Contro l SRAM (One Internal Wait + One External Wait)[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 46 of 1658 REJ09B0261-0100 11.5.8 Wait Cycles betw een Access Cycles When the ext ernal memory bus operatin g frequenc y is high, the turn-of f of the data b uffer performed o n completion of reading fr om a low-speed de vice may not be made in time. This cause a collision with the[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 47 of 1658 REJ09B0261-0100 T1 CLKOUT CSm CS n A25 to A0 BS R/ W RD D31 to D0 T2 Twait T1 T2 Twait T1 T2 Reading area m space CSnBCR.IWRRD=001 CSnBCR.IWRWS=001 Reading area n space Writing area n space Figure 11.41 Wait Cycles between Access Cycles (Access Size Is 4 Bytes)[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 48 of 1658 REJ09B0261-0100 11.5.9 Bus Arbitrati o n This LSI is provided with a bus arb itration functio n that gi ves the bus to an external de vice when a request is issued from the devi ce. This bus arbit ration su pports master m ode and slave mode. I n master mode the bus is h[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 49 of 1658 REJ09B0261-0100 Asserted for 2 cycles or more Master-mode device access CLKOUT BR EQ B A C K A25 to A0 CS n R/ W RD W En D31 to D0 (write) BR EQ B A C K BS A25 to A0 CS n R/ W RD W En BS D31 to D0 (write) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z H[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 50 of 1658 REJ09B0261-0100 11.5.10 Master Mode The processor in master mo de holds the bus itself until it receives a bus request. On receiving an assertion (l ow level) of the bus request signal ( BREQ ) from the outside , the master mode processor releases the bus and asse rts (d[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 51 of 1658 REJ09B0261-0100 11.5.11 Slave Mode In slave mode, usually, the bus is released. Unless the bus control i s hold by performing bus arbitration, the external device cannot be accessed. T he bus is released at a reset, and the bus arbitration sequence starts from the fetch [...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 52 of 1658 REJ09B0261-0100 11.5.14 Mode Pin Settings and Ge neral Input Output Port Settings about Data Bus Width Table 11.18 s hows the exa mples of MODE pin setti ngs and port settings (GP IO port co ntrol register) related to the selection of the data bus width used in the local[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 53 of 1658 REJ09B0261-0100 Table 11.19 Register Settings for Divided-Up DACKn Out put in DMA1 Transfer Usin g the SRAM/Burst ROM/Byte Contr o l SRAM Interfaces Not Divided Divided Bus Width [Bit] Access Size in DMA Transfer Bus Cycle Number IWRRD, IWRRS, or IWW in CSnBCR ADS and AD[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 54 of 1658 REJ09B0261-0100 Table 11.20 Register Settings for Divided-Up DACKn Output in DMA1 Transfer Using the PCMCIA Interface Not Divided Divided Bus Width [Bit] Access Size Bus Cycle Nu mber IWRRD, IWRRS, or IWW in CSnBCR IWRRD, IWRRS, or IWW in CSnBCR Byte 1 ⎯ Undividable Wo[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 55 of 1658 REJ09B0261-0100 Table 11.21 Register Settings for Divided-Up DACKn Output in DM A1 Transfer in Re ad Access Using the MPX Interface Not Divided Divided Bus Width [Bit] Access Size Bus Cycle Nu mber IWRRD or IWRRS, in CSnBCR IWRRD or IWRRS, in CSnBCR Byte 1 ⎯ Undiv idab[...]

11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 4 56 of 1658 REJ09B0261-0100 Table 11.22 Register Settings for Divided-Up DACKn Out put in DMA1 Transfer in Write Access Using the MPX Interface Not Divided Divided Bus Width [Bit] Access Size Bus Cycle Number IWW in CSnBCR IW1 and IW0 in CSnWCR IWW in CSnBCR Byte 1 ⎯ ⎯ Undividab[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 57 of 1658 REJ09B0261-0100 Section 12 DDR2-SDRAM Interface (DBSC2) The DDR2-SDRAM interface (DBS C2) c ontrols the DDR 2-SDRAM. 12.1 Features • Supports 32-bit and 16-b it external data bus widths • Supports from DDR2-60 0 (controller operatio n at 300 MHz) to DDR2-400 (co ntroller [...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 58 of 1658 REJ09B0261-0100 ⎯ DDR2-SDR AM data bus width: 16 bits • One 256 Mbits (16 M × 16 bits) connected in parallel (total capacity = 256 Mbits) • Two 256 M bits (32M × 8 bits) connected in parallel (total capacity = 512 Mbits) • One 512 Mbits (32 M × 16 bits) connected i[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 59 of 1658 REJ09B0261-0100 Figure 12.1 show s a block diagra m of the DBSC2. BUS IF Request queue Control unit Re g isters DDRPAD DLL IO cells MDQS3 to MDQS0, MDQS3 to MDQS0 , MDM3 to MDM0, MDQ31 to MDQ0 MCKE, MA14 to MA0, MBA2 to MBA0, MCS , MRAS , MCAS , MWE , MODT Write data queue Re[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 60 of 1658 REJ09B0261-0100 12.2 Input/Output Pins Table 12.1 sho ws the pin co nfiguration o f the DBSC2. Table 12.1 Pin Configuration of the DBSC2 Pin Name Function I/O Description MCK0 DDR2-SDRAM clock 0 Output Clock output for the DDR2-SDRAM MCK0 DDR2-SDRAM clock 0 Output Clock outpu[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 61 of 1658 REJ09B0261-0100 The frequency of the SDRAM operation cl ocks MCK0, MCK0 , MCK1, and MCK1 is the same as the frequency of the DDR clock. MDQ7 to MDQ0 correspond to MDQS0 and MDM0, MDQ15 to MDQ8 correspond to MDQS1 and MDM1, MDQ23 to MDQ16 corr espond to MDQS2 and MDM2, and MDQ[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 62 of 1658 REJ09B0261-0100 Table 12.2 An Exa mple of DDR2-SDRAM Co nnection (When Four 2- Gb DDR2-SDRAM U nits (256 M × 8 Bits) Are Used) Memory MCK1, MCK1 MCK0, MCK0 MODT, MCKE, MCS, MRAS , MCAS , MWE , MA14 to MA0, MBA2 to MBA0 MDQ31 to MDQ24, MDQS3, MDQS3 , MDM3 MDQ23 to MDQ16, MDQS[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 63 of 1658 REJ09B0261-0100 3. SDRAM pins should be connected as sho wn below. Memory #1 Pins SH7785 Pins DQS MDQS3 DQS MDQS3 DM MDM3 DQ7 MDQ31 DQ6 MDQ30 DQ5 MDQ29 DQ4 MDQ28 DQ3 MDQ27 DQ2 MDQ26 DQ1 MDQ25 DQ0 MDQ24 4. SDRAM pins should be conn ected as shown below. Memory #2 Pins SH7785 P[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 64 of 1658 REJ09B0261-0100 5. SDRAM pins should be conn ected as shown below. Memory #3 Pins SH7785 Pins DQS MDQS1 DQS MDQS1 DM MDM1 DQ7 MDQ15 DQ6 MDQ14 DQ5 MDQ13 DQ4 MDQ12 DQ3 MDQ11 DQ2 MDQ10 DQ1 MDQ9 DQ0 MDQ8 6. SDRAM pins should be conn ected as shown below. Memory #4 Pins SH7785 Pin[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 65 of 1658 REJ09B0261-0100 12.3 Data Alignment The DBSC2 ac cesses DDR2-SDR AM with a fixed burst length of 4 (figur e 12.2). As s hown in table 12.3 and table 12.4, i n valid rea d data is disca rded during reading, an d data mask si gnals are used to mask invalid data during writing, [...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 66 of 1658 REJ09B0261-0100 MCK0, MCK1 MA[14:11] MA[9:0] MBA[2:0] MCKE M CS M R A S M C A S M W E MA[10] Invalid 32-bit width: MDQS[3:0] 16-bit width: MDQS[1:0] 32-bit width: MDQ[31:0] 16-bit width: MDQ[15:0] 32-bit width: MDM[3:0] 16-bit width: MDM[1:0] Invalid Invalid Invalid Invalid R[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 67 of 1658 REJ09B0261-0100 Table 12.3 Positions of Valid Data for Access with Burst Length of 4, when the External Data Bus Width I s Set to 32 Bits (1) Little Endian First Access S econd Access Third Access Fourth Access Byte access (address 8n + 0,1,2,3) Invalid Valid Invalid Invalid [...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 68 of 1658 REJ09B0261-0100 Table 12.4 Positions of Valid Data for Access with Burst Length of 4, when the External Data Bus Width I s Set to 16 Bits (1) Little Endian First Access S econd Access Third Access Fourth Access Byte access (address 8n + 0,1) Invalid Invalid Invalid Valid Byte[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 69 of 1658 REJ09B0261-0100 (2) Big Endian First Access Sec ond Access Third Access Fourth Access Byte access (address 8n + 0,1) Valid Invalid Invalid Invalid Byte access (address 8n + 2,3) Invalid Valid Invalid Invalid Byte access (address 8n + 4,5) Invalid Invalid Valid Invalid Byte ac[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 70 of 1658 REJ09B0261-0100 Table 12.5 Data Alignment for Access in Little Endia n when External Da ta Bus Width I s Set to 32 Bits Access Size Address MDQ31 to MDQ24 MDQ23 to MDQ16 MDQ15 to MDQ8 MDQ7 to MDQ0 Address 0 Data 7 to 0 Address 1 Data 7 to 0 Address 2 Data 7 to 0 Address 3 Dat[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 71 of 1658 REJ09B0261-0100 Access Size Address MDQ31 to MDQ24 MDQ23 to MDQ16 MDQ15 to MDQ8 MDQ7 to MDQ0 Quadword Address 0 (First access: address 4) Data 63 to 56 Data 55 to 48 Data 47 to 40 Data 39 to 32 Address 0 (Second access: Address 0) Data 31 to 24 Data 23 to 16 Data 15 to 8 Data[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 72 of 1658 REJ09B0261-0100 Access Size Address MDQ31 to MDQ24 MDQ23 to MDQ16 MDQ15 to MDQ8 MDQ7 to MDQ0 Word Address 0 Data 15 to 8 Data 7 to 0 Address 2 Data 15 to 8 Data 7 to 0 Address 4 Data 15 to 8 Data 7 to 0 Address 6 Data 15 to 8 Data 7 to 0 Longword Address 0 Data 31 to 24 Data [...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 73 of 1658 REJ09B0261-0100 Table 12.7 Data Alignment for Access in Littl e Endian when External Data Bus Width Is Set to 16 Bits Access Size Address MDQ15 to MDQ8 MDQ7 to MDQ0 Byte Address 0 Data 7 to 0 Address 1 Data 7 to 0 Address 2 Data 7 to 0 Address 3 Data 7 to 0 Address 4 Data 7 t[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 74 of 1658 REJ09B0261-0100 Access Size Address MDQ15 to MDQ8 MDQ7 to MDQ0 Longword Address 0 (First access: Address 2) Data 31 to 24 Data 23 to 16 Address 0 (Second access: Address 0) Data 15 to 8 Data 7 to 0 Address 4 (First access: Address 6) Data 31 to 24 Data 23 to 16 Address 4 (Sec[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 75 of 1658 REJ09B0261-0100 Table 12.8 Data Alignment for Access in Big Endian when External Data Bus Width Is Set to 16 Bits Access Size Address MDQ15 to MDQ8 MDQ7 to MDQ0 Byte Address 0 Data 7 to 0 Address 1 Data 7 to 0 Address 2 Data 7 to 0 Address 3 Data 7 to 0 Address 4 Data 7 to 0 [...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 76 of 1658 REJ09B0261-0100 Access Size Address MDQ15 to MDQ8 MDQ7 to MDQ0 Longword Address 0 (First access: Address 0) Data 31 to 24 Data 23 to 16 Address 0 (Second access: Address 2) Data 15 to 8 Data 7 to 0 Address 4 (First access: Address 4) Data 31 to 24 Data 23 to 16 Address 4 (Sec[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 77 of 1658 REJ09B0261-0100 When the external bus width is set to 16 bits Address 16n + 0 Address 16n + 8 1st access 2nd access 16n + 0 16n + 8 16n + 8 16n + 0 16-byte read/write access (a total of two commands are issued) Address 32n + 0 Address 32n + 8 Address 32n + 16 Address 32n + 24[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 78 of 1658 REJ09B0261-0100 When the external bus width is set to 32 bits Address 16n + 0 Address 16n + 8 1st access 16-byte read/write access (a total of one command is issued) 1st access 2nd access 32-byte read access (a total of two commands are issued) 1st access 2nd access 32-byte w[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 79 of 1658 REJ09B0261-0100 12.4 Register Descriptions Table 12.9 sho ws the DBSC2 re gister configuration; Tabl e 12.10 sh ows register st ates in the different processing modes. The register bit width is 32 bits, and the longwor d size (32 bits) should be used for re gister access. If [...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 80 of 1658 REJ09B0261-0100 Table 12.9 DBSC2 Register Confi guration Register Name Abbreviation R/W P4 Area Address Area 7 Address Access Size (Bits) Synchroni- zation Clock DBSC2 status register DBSTATE R H'FE80 000 C H'1E80 000C 32 DDRck SDRAM operation enable register DBEN R[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 81 of 1658 REJ09B0261-0100 Table 12.10 Register Status i n each Processing Mode Power-On Reset Manual Reset Sleep/Deep Sleep Register Name Abbreviation By PRESET pin/ WDT/H-UDI By WDT/Multiple Exception By SLEEP Instruction DBSC2 status register DBSTATE H'0000 0x00 * Retained Retai[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 82 of 1658 REJ09B0261-0100 12.4.1 DBSC2 Status Re gister (DBSTATE) The DBSC2 st atus register (DBSTATE) i s a read-onl y register. Writing is invalid. It is initialized only upon po wer-on reset. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ⎯ ⎯ ⎯ [...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 83 of 1658 REJ09B0261-0100 12.4.2 SDRAM Operati on Enable Regis ter (DBEN) The SDRAM operation ena ble register (DBEN) is a r eada b le/writable regi ster. It is initialized only upon power- on reset. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ⎯ ⎯[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 84 of 1658 REJ09B0261-0100 12.4.3 SDRAM Com mand Control Register (DBCMDCNT ) The SDRAM c ommand cont rol regist er (DBCMDC NT) is a readable/writable register. It is initialized only upon power-on reset. The CMD2 to CMD0 bits in DBCMDCNT are always read as 000. 16 17 18 19 20 21 22 23 [...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 85 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 to 0 CMD2 to CMD0 000 R/W SDRAM Command Issue Bit These bits are used to issue commands necessary to execute the DDR2-SDRAM initialization se quence and self-refresh transition/cancellation. When th ese bits are wri[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 86 of 1658 REJ09B0261-0100 12.4.4 SDRAM Configuration Setting Re gister (DBCONF) The SDRAM config uration set ting register (DB CONF ) is a rea dable/writable register. It is initialized only up on power-on reset. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 1 0 1 1 0 0 1 0 0 0 0 0[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 87 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 15 to 10 ⎯ All 0 R Reserved These bits are always read as 0. The write value shou ld always be 0. Operation when a value other than 0 is writte n is not guaranteed. 9, 8 BASFT1 and BASFT0 00 R/W Bank Address Shift B[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 88 of 1658 REJ09B0261-0100 12.4.5 SDRAM Timing Register 0 (DBTR0) The SDRAM timing register 0 (DBTR0) is a readable/w ritable register. It is initialized only upon power-on reset. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 1 1 0 0 0 0 0 0 0 1 0 0 0 0 00 TRAS0 TRAS1 TRAS2 TRAS3 ⎯ [...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 89 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 23 to 20 ⎯ All 0 R Reserved These bits are always read as 0. The write value shou ld always be 0. Operation when a value other than 0 is writte n is not guaranteed. 19 to 16 TRAS3 to TRAS0 0011 R/W tRAS (ACT-PRE per[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 90 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 14 to 8 TRFC6 to TRFC0 000 0101 R/W tRFC (REF-ACT/REF period) Setting Bits These bits set the REF-ACT/REF minimum period constraint These bits should be set accordin g to the DDR2-SDRAM specifications. The number of c[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 91 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 to 0 TRCD2 to TRCD0 001 R/W tRCD (ACT-READ/WRITE period) Setting Bits These bits set the ACT-READ/WRITE minimum period. These bits should be set according to the DDR2- SDRAM specifications. The number of cycles is t[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 92 of 1658 REJ09B0261-0100 12.4.6 SDRAM Timing Register 1 (DBTR1) The SDRAM timing register 1 (DBTR1) is a readable/writable register. It is initialized only upon power-on reset. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 1 0 0 0 0 0 0 0 0 0 0 0 0 0 00 TRP0 TRP1 TRP2 ⎯ ⎯ ⎯ ?[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 93 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 15 to 11 ⎯ All 0 R Reserved These bits are always read as 0. The write value shou ld always be 0. Operation when a value other than 0 is writte n is not guaranteed. 10 to 8 TRRD2 to TRRD0 000 R/W tRRD (ACT(A)-ACT(B)[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 94 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 to 0 TWR2 to TWR0 001 R/W tWR (write recovery period) S etting Bits These bits set the write recovery minimum period constraint. These bits should be set accordin g to the DDR2-SDRAM specifications. The number of cy[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 95 of 1658 REJ09B0261-0100 12.4.7 SDRAM Timing Re gister 2 (DBTR2) The SDRAM timing register 2 (DBTR2) is a readable/w ritable register. It is initialized only upon power-on reset. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 1 0 0 0 0 0 1 0 0 0 0 0 00 TRC0 TRC1 TRC2 TRC3 TRC4 ?[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 96 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 20 to 16 TRC4 to TRC0 0 0100 R/W tRC (ACT-ACT/REF period) Setting Bits These bits set the constraint for the minimum time from ACT command to ACT command (in the same bank)/ REF command. These bits should be set accor[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 97 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 11 to 8 RDWR3 to RDWR0 0011 R/W READ-WRITE Command Mi nimum Interval Setting Bits These bits set the READ-WRITE command minimum interval constraint. These bits should be set accordin g to the SDRAM specifications . Th[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 98 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 3 to 0 WRRD3 to WRRD0 0011 R/W WRITE-READ Command Mi nimum Interval Setting Bits These bits set the WRITE-READ command minimum interval constraint. These bits should be set accordin g to the SDRAM specifications . The[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 4 99 of 1658 REJ09B0261-0100 12.4.8 SDRAM Refr esh Control Register 0 (DBRFCNT0) The SDRAM refresh control re gister 0 (DBRFCNT 0) is a readable/writabl e register. It is initialized only upon power-on reset. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 A[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 00 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 0 SRFEN 0 R/W Self-Refresh Mode Bit Performs transition to or cancellation of self-r efresh mode. By writing 1, a transiti on is made to self-refresh. By writing 0, self-refresh mo de is cancelled. For details on tran[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 01 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 12 to 0 TREFI12 to TREFI0 0 0010 0000 0000 R/W Averag e Refresh Interval Setting Bits These bits set the average interval for auto-refresh operation. Upon refresh execution, this val ue is added to the refresh interva[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 02 of 1658 REJ09B0261-0100 12.4.10 SDRAM Refr esh Control Register 2 (DBRFCNT2) The SDRAM refresh control re gister 2 (DBRFCNT 2) is a readable/writabl e register. It is initialized only up on power-on reset. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 1 0 00[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 03 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 15 to 8 ⎯ All 0 R Reserved These bits are always read as 0. The write value shou ld always be 0. Operation when a value other than 0 is writte n is not guaranteed. 7 to 0 LV0TH7 to LV0TH0 1000 0000 R/W Level 0 Thres[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 04 of 1658 REJ09B0261-0100 12.4.11 SDRAM Refresh S t atus Register (DBRF STS) The SDRAM refres h status register (DBRFSTS) is a read able/writable register. It is initialized only upon po wer-on reset. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ⎯ ?[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 05 of 1658 REJ09B0261-0100 12.4.12 DDRPAD Frequenc y Setti ng Register (DBFREQ) The DDRPAD frequen cy setting register (DBFREQ) is a readable/writable register. It is initialized only upon po wer-on reset. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ?[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 06 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 to 0 FREQ2 to FREQ0 000 R/W Frequency Setting Bits These bits set the operatin g frequency of the data bus in the DDR2-SDRAM. 000: up to 300 MHz (DDR2-600) 001: Reserved 010: 200 MHz (DDR2-400) 100 to 111: Setting p[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 07 of 1658 REJ09B0261-0100 12.4.13 DDRPAD DIC, ODT, O CD Setting Re gister (DBDICODTOCD) The SDRAM refres h status register (DBRFSTS) is a read able/writable register. It is initialized only upon po wer-on reset. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 [...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 08 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 18 DIC_DQ 0 R/W Data Pin Impedanc e value This bit should be set to the same value as the value set for DIC of EMRS(1) in the DDR2-SDRAM. 0: Normal 1: Weak 17 DIC_CK 0 R/W Clock Pin Impedance value This bit should be [...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 09 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 10 ODT_ EARLY 0 R/W ODT Assertion Period Settin g Sets the ODT assertion perio d. The number of cycles is the number of DDR clock cycles. This setting is valid only wh en ODTEN is set to 01. In order to extend ODT by [...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 10 of 1658 REJ09B0261-0100 12.4.14 SDRAM Mode Setting Regi ster (DBMRCNT) The SDRAM mode setting register (DBMRCNT) is a write-only register. If it is read, correct operation ca nnot be guarantee d. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ [...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 11 of 1658 REJ09B0261-0100 By writing to this register, th e DDR2-SDRAM ad dress and bank address pin s can be directly manipulated t o set the mode and exte nded mode registers. When thi s register i s written, the mode register setting (MRS)/extended mode register setting (EMRS) comma[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 12 of 1658 REJ09B0261-0100 12.5 DBSC2 Operation 12.5.1 Supported SDRAM Commands Table 12.11 lists the SDRAM comm ands issued by the DBSC2. Th ese commands are issued to the DDR2-SDRAM in synchronously with MCK0, MCK0 , MCK1, and MCK 1 . In the table, n-1 indicates the state of the signa[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 13 of 1658 REJ09B0261-0100 12.5.2 SDRAM Command Issue (1) Basic Access The DBSC2 st ores in a que ue the requests received via t he SuperHywa y bus. Request processing is begun around the time of preceding precharge/ac tivate processing, but pr ocessing completion is in the order receiv[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 14 of 1658 REJ09B0261-0100 16-bit external bus Read (16 bytes) Read (1, 2, 4, 8, or 16 bytes) Read (32 bytes) Write (1, 2, 4, 8, or 16 bytes) Write (32 bytes) Read (1, 2, 4, or 8 bytes) Read (32 bytes) Write (1, 2, 4, or 8 bytes) Write (16 bytes) Read Write (32 bytes) Write Read Read Wr[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 15 of 1658 REJ09B0261-0100 command to be issued at time 2 from the following request que ue. From the search results it is seen that advance prec harge processing can be exec uted for the third read (8-byte ) request and the fourth read (16-byte) request. Because the DBSC2 gi ves priori[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 16 of 1658 REJ09B0261-0100 12.5.3 Initialization Sequence The following shows an examp le of the initialization sequence. For detailed information such as the power supply and timing parameter s, please refer to the datasheet for the DDR2-SDRAM being used. 1. Fo llowing the instructio n[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 17 of 1658 REJ09B0261-0100 10. Writing to DBMRCNT issues the MRS command to the SDRAM and sets the variou s parameters. At this point, the op erating mode is set to normal mode, the DLL reset is set to reset, the burst length is set to 4, and the burs t type is set t o sequential. The a[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 18 of 1658 REJ09B0261-0100 Because access is disabled in self-refresh mode, any attempt to access data in the DDR2-SDRAM will be ignored. The following procedure is used to mak e a transition to self-refresh mode. 1. Check to make sure the DBSC2 is not being accessed. T he time required[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 19 of 1658 REJ09B0261-0100 1. Check to make sure the DBSC2 is not being acce ssed. The time required for transition to self- refresh must not exceed t h e auto-refresh i nterv al requested by the SDRA M by interr upts or some other ca uses. 2. Set the ACEN bit in the SDRA M operation en[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 20 of 1658 REJ09B0261-0100 12.5.5 Auto-Refresh Operation When the auto-refresh enab le bit (ARFEN) in the SD RAM refresh control register 0 (DBRFCNT0) is 1, the a u to-refresh com mand is issued periodically. I f accessing data i n the SDRAM, always make sure this is set. The average re[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 21 of 1658 REJ09B0261-0100 LV1TH LV0TH 0 Time Refresh counter value Max. value (Avera g e refresh interval + LV1TH) Level 1 (Refreshin g durin g request empty cycles) Level 0 (Refreshin g in vacant periods between SHwy commands) Level 2 (Refreshin g not done) Refreshin g is done immedia[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 22 of 1658 REJ09B0261-0100 Table 12.12 Relation between SDRAM Address Pins and Logical Addresses when the External Data Bus Wid t h Is Set to 16 Bits (BASFT = 00 ) (When Using a 16-Bit Product, One Is Connected; for 8-Bit Produc ts, Two Are Connected) Memory Type MBA 2 MBA 1 MBA 0 MA14 [...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 23 of 1658 REJ09B0261-0100 Table 12.13 Relation between SDRAM Address Pins and Logical Addresses when the External Data Bus Wid t h Is Set to 32 Bits (BASFT = 00 ) (When Using 16-Bit Products, Tw o Are Connected; for 8-Bit Products, Four Are C onnect ed) Memory Type MBA 2 MBA 1 MBA 0 MA[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 24 of 1658 REJ09B0261-0100 Table 12.14 Relation between SDRAM Address Pins and Logical Addresses when the External Data Bus Wid t h Is Set to 16 Bits (BASFT = 01 ) (When Using a 16-Bit Product, One Is Connected; for 8-Bit Produc ts, Two Are Connected) Memory Type MBA 2 MBA 1 MBA 0 MA14 [...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 25 of 1658 REJ09B0261-0100 Table 12.15 Relation between SDRAM Address Pins and Logical Addresses when the External Data Bus Wid t h Is Set to 32 Bits (BASFT = 01 ) (When Using 16-Bit Products, Tw o Are Connected; for 8-Bit Products, Four Are C onnect ed) Memory Type MBA 2 MBA 1 MBA 0 MA[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 26 of 1658 REJ09B0261-0100 Table 12.16 Relation between SDRAM Address Pins and Logical Addresses when the External Data Bus Wid t h Is Set to 16 Bits (BASFT = 10 ) (When Using a 16-Bit Product, One Is Connected; for 8-Bit Produc ts, Two Are Connected) Memory Type MBA 2 MBA 1 MBA 0 MA14 [...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 27 of 1658 REJ09B0261-0100 Table 12.17 Relation between SDRAM Address Pins and Logical Addresses when the External Data Bus Wid t h Is Set to 32 Bits (BASFT = 10 ) (When Using 16-Bit Products, Tw o Are Connected; for 8-Bit Products, Four Are C onnect ed) Memory Type MBA 2 MBA 1 MBA 0 MA[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 28 of 1658 REJ09B0261-0100 Table 12.18 Relation between SDRAM Address Pins and Logical Addresses when the External Data Bus Wid t h Is Set to 16 Bits (BASFT = 11 ) (When Using a 16-Bit Product, One Is Connected; for 8-Bit Produc ts, Two Are Connected) Memory Type MBA 2 MBA 1 MBA 0 MA14 [...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 29 of 1658 REJ09B0261-0100 Table 12.19 Relation between SDRAM Address Pins and Logical Addresses when the External Data Bus Wid t h Is Set to 32 Bits (BASFT = 11 ) (When Using 16-bit Products, Two Are Connec ted; for 8-Bit Products, Four Are C onnect ed) Memory Type MBA 2 MBA 1 MBA 0 MA[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 30 of 1658 REJ09B0261-0100 12.5.7 Regarding SDRAM Access an d Timing Constraints In this section, waveforms at t he various pins du ri ng basic DDR2-SDRAM access are explained first and then the relation between DDR2-SDRAM access and the CAS latency (CL), tRAS, tRFC, tRCD, tRP, tRRD, tW[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 31 of 1658 REJ09B0261-0100 MCK0, MCK1 MA[14:11] MA[9:0] MBA[2:0] MCKE M CS M R A S M C A S M W E MA[10] ACT bank A bank A Invalid Invalid Invalid Invalid MDQS[3:0] MDQ[31:0] MDM[3:0] Invalid Invalid Invalid SDRAM command Invalid Invalid Example of CL = 3 Valid Valid Valid Valid Valid Va[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 32 of 1658 REJ09B0261-0100 MCK0, MCK1 MA[14:11 ] MA[9:0] MBA[2:0] MCKE M CS M R A S M C A S M W E MA[10] ACT bank A READ bank A Invalid Invalid MDQS[3:0] MDQ[31:0] MDM[3:0] Invalid Invalid Invalid SDRAM command Valid Invalid READ bank A Invalid Invalid Valid Invalid Invalid Invalid Vali[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 33 of 1658 REJ09B0261-0100 MCK0, MCK1 MA[14:11] MA[9:0] MBA[2:0] MCKE M CS M R A S M C A S M W E MA[10] ACT bank A bank A Invalid Invalid Invalid Invalid MDQS[3:0] MDQ[31:0] MDM[3:0] Invalid Invalid SDRAM command Invalid Invalid Invalid Invalid Valid Valid Valid Valid Valid Valid Hi g h[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 34 of 1658 REJ09B0261-0100 MCK0, MCK1 MA[14:11] MA[9:0] MBA[2:0] MCKE M CS M R A S M C A S M W E MA[10] ACT bank A bank A Invalid Invalid MDQS[3:0] MDQ[31:0] MDM[3:0] Invalid Invalid SDRAM command Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Example of CL = 3 [...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 35 of 1658 REJ09B0261-0100 MCK0, MCK1 MA[14:11] MA[9:0] MBA[2:0] MCKE M CS M R A S M C A S M W E MA[10] Invalid MDQS[3:0] MDQ[31:0] MDM[3:0] Invalid Invalid Invalid Invalid PALL Invalid REF SDRAM command Hi g h level Figure 12.12 Auto-Refresh Operation Figure 12.13 sh ows the self-refre[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 36 of 1658 REJ09B0261-0100 example is shown in section 12.5.11, Method for Securing Time Requir ed for Initialization, Self- Refresh Cancellation, etc. RSHX MCK0, MCK1 MA[14:11] MA[9:0] MBA[2:0] MCKE M CS M R A S M C A S M W E MA[10] Invalid MDQS[3:0] MDQ[31:0] MDM[3:0] Invalid Invalid [...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 37 of 1658 REJ09B0261-0100 command, the constraint tRCD betwee n th e ACT comm and and READ co mmand, and the constraint tRAS between the ACT command a n d the PRE command a re involved. The DBSC2 waits to issue commands until each of the constraints is satisfied. MCK0, MCK1 MA[14:11] M[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 38 of 1658 REJ09B0261-0100 MCK0, MCK1 MA[14:11] MA[9:0] MBA[2:0] MCKE M CS M R A S M C A S M W E MA[10] ACT bank A READ bank A Invalid Invalid Invalid Invalid Invalid Invalid MDQS[3:0] MDQ[31:0] MDM[3:0] I nvalid Invalid Invalid Valid PRE bank C Valid Valid Valid ACT bank B READ bank B [...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 39 of 1658 REJ09B0261-0100 MCK0, MCK1 MA[14:11] MA[9:0] MBA[2:0] MCKE M CS M R A S M C A S M W E MA[10] bank A Invalid MDQS[3:0] MDQ[31:0] MDM[3:0] Invalid Invalid Invalid Invalid PRE bank A Invalid Invalid Invalid Invalid SDRAM command ACT bank A Valid Valid Valid Invalid Invalid Inval[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 40 of 1658 REJ09B0261-0100 MCK0, MCK1 MA[14:11] MA[9:0] MBA[2:0] MCKE M CS M R A S M C A S M W E MA[10] ACT bank A READ bank A Invalid Invalid Invalid Invalid MDQS[3:0] MDQ[31:0] MDM[3:0] Invalid Invalid Invalid Invalid PALL Invalid Invalid REF SDRAM command tRAS = 9 cycles Read data tR[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 41 of 1658 REJ09B0261-0100 MCK0, MCK1 MA[14:11] MA[9:0] MBA[2:0] MCKE M CS M R A S M C A S M W E MA[10] WRITE any bank Invalid MDQS[3:0] MDQ[31:0] MDM[3:0] Invalid Invalid Invalid Invalid Invalid READ any bank Invalid Invalid Invalid SDRAM command Invalid Invalid Write data Read data Va[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 42 of 1658 REJ09B0261-0100 MCK0, MCK1 MA[14:11] MA[9:0] MBA[2:0] MCKE M CS M R A S M C A S M W E MA[10] Invalid MDQS[3:0] MDQ[31:0] MDM[3:0] Invalid Invalid Invalid Invalid READ any bank Invalid Invalid Invalid SDRAM command Invalid Invalid WRITE any bank Write data Read data WRRD = 7 c[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 43 of 1658 REJ09B0261-0100 MCK0, MCK1 MA[14:11] MA[9:0] MBA[2:0] MCKE M CS M R A S M C A S M W E MA[10] ACT any bank tRFC Invalid Invalid Invalid Invalid MDQS[3:0] MDQ[31:0] MDM[3:0] Invalid Invalid Invalid Invalid REF SDRAM command READ any bank Invalid Invalid Invalid = 6 cycles Valid[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 44 of 1658 REJ09B0261-0100 12.5.8 Important Inf ormation Regardin g Use of 8-Bank DDR2-S DRAM Products The DDR2-SD RAM specificat ions limit the number of ba nks in an 8-bank product w hich can be activated simultaneously. Control must be ex ecuted so that t he number of activated ba nk[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 45 of 1658 REJ09B0261-0100 write MCK Command Data MCKE MODT Terminatin g resistor in SDRAM As shown in the above fi g ure, when CL is 4, the effective ODT control si g nal (MODT) to the SDRAM can be asserted at the same timin g as the issue of the WRITE command. If CL is 5 or g reater, [...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 46 of 1658 REJ09B0261-0100 write MCK Command Data MCKE MODT Terminatin g resistor in SDRAM read The above fi g ure shows an example when a product with CL = 5 is used. As the ODT control si g nal (MODT) is extended for one cycle, the product with CL = 5 or g reater is required. If a pro[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 47 of 1658 REJ09B0261-0100 This LSI MCKE M BKPRS T IO cell Internal CKE DBSC2 External device SDRAM This LSI MCKE M BKPRS T IO cell Internal CKE DBSC2 Low level input Low level output Hi g h level input 1.8-V power on 1.8-V power on 1.0-V power on 1.0-V power off Normal operation When S[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 48 of 1658 REJ09B0261-0100 MCKE to high level, upon power-on reset the data within the SDRAM is destroyed. Hence if the state signal is not set in advance to a state ot he r than power supp ly back up state, there is the danger that the destroyed data may be treated as the correct data.[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 49 of 1658 REJ09B0261-0100 5. The SDRAM configuration se tting register ( DBCONF), S DRAM timing register 0 (DBTR0), SDRAM timing register 1 (DBTR1), and SDRAM timing register 2 (DBTR2) shou ld be set. 6. By writing to the DDRPAD frequency setting register DBFREQ, DLL setting s are made[...]

12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 5 50 of 1658 REJ09B0261-0100 12.5.13 Regarding MCKE Si gnal Operation The MCKE signal operation is explaine d using fi gure 12.24. Here, the ex planation assume s that MBKPRST is high-le vel input. Pri or to power-on reset t he MCKE signal is indefini te, but upon power-on reset is output[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 51 of 1658 REJ09B0261-0100 Section 13 PCI Controller (PCIC) The PCI cont roller (PCIC) controls t he PCI bus and enables dat a transfers bet w een memory connected to an external bus and a PCI device conn ected to the P CI bus. Th e PCIC facilitates the system design using the PCI bus and ena [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 52 of 1658 REJ09B0261-0100 • Cache snoop functions are sup ported when the PCIC is a ta rget (cache coherency can be supported by sacrific ing perfor mance). • Supports four external interrup t inputs ( INTA , INTB , INTC , and INTD ) i n host mode • Supports one external in terrupt outp[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 53 of 1658 REJ09B0261-0100 Figure 13.1 sh ows a block diagra m of the PCIC. PCI bus PCIC module Internal bus (SHwybus) SHwy bus interface Data FIFO read 32 bytes x 2 PCIECR Data FIFO write 32 bytes x 2 SHwy clock input Interrupt control Interrupt Ta r g et control Re g ister control Confi g ur[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 54 of 1658 REJ09B0261-0100 13.2 Input/Output Pins Table 13.1 sho ws the pin co nfiguration o f the PCIC. Table 13.1 Sign al Descriptions Signal Name PCI Standard Signal I/O Description D32/AD0/DR0 to D37/AD5/DR5, D38/AD6/DG0 to D43/AD11/DG5, D44/AD12/DB0 to D49/AD17/DB5, D50/AD18 to D63/AD31 A[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 55 of 1658 REJ09B0261-0100 Signal Name PCI Standard Signal I/O Description LOCK / ODDF LOCK STRI PCI Lock Exclusive access (the target resource is locked) is accepted when the PCIC is a target IDSEL IDSEL IN PCI Config uration Device Select This signal is input to select the PCIC in con figura[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 56 of 1658 REJ09B0261-0100 Signal Name PCI Standard Signal I/O Description MODE12 MODE11 — IN PCI Operating Mode Select 00: PCI host mode, or PCI host bridge operation by PCICLK 01: PCI normal mode, or non-PCI host bridge operation by PCICLK 10: Local bus 64-bit mode (the PCI disabled) 11: D[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 57 of 1658 REJ09B0261-0100 13.3 Register Descriptions Table 13.2 sho ws a list of PC IC registers. The addresses and offset s of PC I configuratio n registers are the values used when the PCIC is in little endian mode. The access size is the maximum access size in each register. The registers [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 58 of 1658 REJ09B0261-0100 Name Abbreviation SH * 1 R/W PCI * 2 R/W P4 address Area 7 address Sync Clock Access Size * 3 PCI interrupt line re gister PCIINTLINE R/W R/W H'FE04 003C H'1E04 003C PCIclk (32)/(16)/8 PCI interrupt pin re gister PCIINTPIN R/W R H'FE04 003D H'1E04[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 59 of 1658 REJ09B0261-0100 Name Abbreviation SH * 1 R/W PCI * 2 R/W P4 address Area 7 address Sync Clock Access Size * 3 PCI power management interrupt register PCIPINT R/WC — H'FE04 01CC H'1E04 01CC PCIclk 32/16/8 PCI power management interrupt mask register PCIPINTM R/W — H&apo[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 60 of 1658 REJ09B0261-0100 Table 13.3 Register States in Eac h Processing Mode Name Abbreviation Power-On R eset Manual Reset Sleep Mode Control register space (physical a ddress: H'FE00 0000 to H'FE03 FFFF) PCIC enable control register PCIECR H'0000 0000 Retained Retained PCI c[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 61 of 1658 REJ09B0261-0100 Name Abbreviation Power-On R eset Manual Reset Sleep Mode PCI power consumption/dissipation data register PCIPCDD H'00 Retained Retained PCI local register space (physical addre ss: H'FE04 0100 to H'FE04 03FF) PCI control register PCICR H'0000 00x[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 62 of 1658 REJ09B0261-0100 13.3.1 PCIC Enable Contr ol Register (PCIEC R) PCIECR is a register that specifies wh ethe r the PCIC is valid or invalid. SH R/W: PCI R/W: SH R/W: PCI R/W: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit: Initial value: R R R R R R R R R R R R R R RR — — —[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 63 of 1658 REJ09B0261-0100 13.3.2 Configuration Registers The configurat ion regist ers define t he programmi ng model and usage rules of t he configurat ion register space in a PCI compliant device. For de tails, see section 6, Configuration Space, in the PCI Local Bus Specifica tio n Revisio[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 64 of 1658 REJ09B0261-0100 (3) PCI Comm and Register (PCICMD) PCICMD cont rols the basic functions of the PCIC t o generate and respond to PC I cycles. Whe n 0 is written to this register, t his register ig nores access c ommands from the external PCI device, other than configuration access. 0[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 65 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 PER 0 SH: R/W PCI: R/W Parity Error Response Controls the response of the device when the PCIC detects a parity error or receives a parity error. When this bit is set to 1, the PERR signal is asserted. 0: Ignores parity er[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 66 of 1658 REJ09B0261-0100 (4) PCI Status Register (P CISTATUS) PCISTATUS is use d to record status in formation fo r events related to the PCI bus. The reserved bits are read-only bits that ar e read as 0. Reading from this register is normally performed. During writing, the w rite clear bit [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 67 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Desc ription 12 RTA 0 SH: R/WC PCI: R/WC Target Abort Receive Status This bit indicates that a transaction was completed by target abort when the PCIC is a master. 0: Transaction is not completed with target abort 1: The bus master dete[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 68 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Desc ription 6 ⎯ 0 SH: R/W PCI: R Reserved These bits are always read as 0. The write value should always be 0. 5 66C 0 SH: R/W PCI: R 66MHz-Operation Capable Status Indicates whether the PCIC can op erate at 66MHz. 0: PCIC operates a[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 69 of 1658 REJ09B0261-0100 (6) PCI Progra m Int erface R egister ( PCIPIF) This field is the programming interface for the cla ss code of the IDE cont roller. For details of the code value, see appendix D in PCI Local Bus Specification Revision 2.2. R R R R R R R R PCI R/W: 0 1 2 3 4 5 6 7 0 0[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 70 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Desc ription 0 OMP 0 SH: R/W PCI: R PCI Operating Mode (Primary) If this bit is written during register initialization (PCICR.CFINT = 0) in the PCIC, the value of this bit is updated. The value is not u pdated after initi alization (PCI[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 71 of 1658 REJ09B0261-0100 (8) PCI Base Clas s Code Register (PCIBCC) This field defi nes the base class code. For deta il s of the class code, see appendix D in PCI L ocal Bus Specification R evision 2.2. 0 1 2 3 4 5 6 7 x x x x x x x x BCC R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 72 of 1658 REJ09B0261-0100 (10) PCI Latency Timer Register (P CILTM) 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 LTM R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: SH R/W: R/W R/W R/W R/W R/W R/W R/W R/W PCI R/W: Bit Bit Name Initial Value R/W Desc ription 7 to 0 LTM H'00 SH: R/W PCI: R/W Latenc[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 73 of 1658 REJ09B0261-0100 (12) PCI BIST Register (PCIBI ST) R R R R R R R R PCI R/W: 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 — — — — — — — BISTC R R R R R R R R Bit: Initial value: SH R/W: Bit Bit Name Initial Value R/W Desc ription 7 BISTC 0 SH: R PCI: R This bit is used for the BIST f[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 74 of 1658 REJ09B0261-0100 (13) PCI I/O Base Address Register (PCIIBAR) This register is the I/O space base a ddress register of the PCI configuratio n register space header that is defined in PCI local bus specification. This register specifi es the base address in the I/O space of the PCIC. [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 75 of 1658 REJ09B0261-0100 (14) PCI Memory Base Addre ss Register 0 (PCIMBAR0) This register is the memory base address register of the PCI configuratio n register space header that is define d in PCI local bus specificat ion. PCIMBAR0 specifies the me mory space 0 (local address space 0) in t[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 76 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Desc ription 19 to 4 MBA2 H'0000 SH: R PCI: R Memory Space 0 Base Address (lower 16 bit s) These bits are fixed to H'0000 by hardware. 3 LAP 0 SH: R PCI: R Prefetch Control Indicates whether prefetch can be perform ed in local[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 77 of 1658 REJ09B0261-0100 (15) PCI Memory Base Addre ss Register 1 (PCIMBAR1) This register is the memory base address register of the PCI configuratio n register space header that is define d in PCI local bus specificat ion. PCIMBAR1 specifies the me mory space 1 (local address space 1) in t[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 78 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Desc ription 19 to 4 MBA2 H'0000 SH: R PCI: R Memory Space 1 Base Address (lower 16 bit s) These bits are fixed to H'0000 by hardware. 3 LAP 0 SH: R PCI: R Prefetch Control Indicates whether prefetch can be perform ed in local[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 79 of 1658 REJ09B0261-0100 (16) PCI Subsyst em Vender ID Regist er (PCISVID ) See the description of each register in PCI Local Bus Specification Revision 2.2. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 SVID 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 80 of 1658 REJ09B0261-0100 (18) PCI Capability Pointer Register (PCICP) This register i s the extensi on function p ointer regist er of the PC I configurat ion register t hat is defined in t he PCI Power M anagement Spec ification. 0 1 2 3 4 5 6 7 0 0 0 0 0 0 1 0 CP R R R R R R R R Bit: Initia[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 81 of 1658 REJ09B0261-0100 (20) PCI Interrupt Pin Register (PCIINTPIN) 0 1 2 3 4 5 6 7 1 0 0 0 0 0 0 0 INTPIN R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: SH R/W: R R R R R R R R PCI R/W: Bit Bit Name Initial Value R/W Desc ription 7 to 0 INTPIN H'01 SH: R/W PCI: R Interrupt Pin Se[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 82 of 1658 REJ09B0261-0100 (22) Maximum Latency Register (P CIMAXLAT ) This register is not programmable. 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 MAXLAT R R R R R R R R Bit: Initial value: SH R/W: R R R R R R R R PCI R/W: Bit Bit Name Initial Value R/W Desc ription 7 to 0 MAXLAT H'00 SH: R PCI: R[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 83 of 1658 REJ09B0261-0100 (24) PCI Next Item Pointer Re gister (PCINIP) PCINIP indicates the locatio n of the next item i n the list o f extension f unction. 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 NIP R R R R R R R R Bit: Initial value: SH R/W: R R R R R R R R PCI R/W: Bit Bit Name Initial Value R/W[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 84 of 1658 REJ09B0261-0100 (25) PCI Power Management Register (P CIPMC) PCIPMC is a 16-bit regi ster that pr ovides info rmation on t he functions related t o power management. For details, see section 3, PCI Power Mana gement Interface in PCI Bus Power Management Int erface Specificati on Rev[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 85 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Desc ription 8 to 6 ⎯ All 0 SH: R PCI: R Reserved These bits are always read as 0. The write value should always be 0. 5 DSI 0 SH: R PCI: R DSI The write value should always be 0. 0: Indicates that the proper initialization is not req[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 86 of 1658 REJ09B0261-0100 (26) PCI Power Management Control/ Status Register (PCIPMCSR) This register m anages power management events (PME ) of the PC I function. For details, see section 3, PCI Power Management Interf ace in PCI Bus Power Management Interface Specification Re vision 1.1. 0 [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 87 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 1, 0 PS 00 SH: R/W PCI: R/W Power State These bits specify the power state. If an unsupported state is spec ified, a state transition is not made. However, the register is written normally and no error is indicated. 00: D0 s[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 88 of 1658 REJ09B0261-0100 (27) PCIPMCSR Bridge Support Extensi on Register (PCIPMCSRBSE) This register supports the function s specific to the PCI bridge and is required for all PCI-to -PCI bridges. 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 — — — — — — B2B3N BPC CEN R R R R R R R R Bit: Ini[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 89 of 1658 REJ09B0261-0100 (28) PCI Power Consumption/ Radiation Register (PCIPCDD) The data regist er is an 8-bit optional register (rea d-only from the PCI bus) that notifies operation data such as po wer consumpt ion dependi ng on the state and heat dissi pation. For details, see section 3,[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 90 of 1658 REJ09B0261-0100 13.3.3 PCI Local Registers (1) PCI Control Register (PCICR) PCICR is a 3 2-bit regi ster which c ontrols the operatio n of the PC IC in this LSI. Writing to this register is valid only when the valu e of bits 31 to 24 are H'A5. R/W R/W R/W R R R/W R R/W R/W R/W [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 91 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 10 FTO 0 SH: R/W PCI: R PCI TRDY /Control Enable Specifies the function that negates TRDY within 5 cycles before disconnection in a target access. 0: Disabled 1: Enabled 9 PFE 0 SH: R/W PCI: R PCI Pre-Fetch Enable Specifies [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 92 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 IOCS 0 SH: R/W PCI: R INTA Output Controls the INTA output by software. This bit is valid only when the PCIC operates in normal mode. 0: The INTA pin is in the high-impedance state (driven high by an on-chip pull-up res is[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 93 of 1658 REJ09B0261-0100 (2) PCI Local Space Register 0 (PCILSR0) See section 13.4.4 (1), Accessi ng Memory Space in This LSI. SH R/W: PCI R/W: R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R RR R R R R R R R R R R R R R R RR SH R/W: PCI R/W: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 94 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Desc ription 19 to 1 ⎯ All 0 SH: R PCI: R Reserved These bits are always read as 0. The write value should always be 0. 0 MBARE 0 SH: R/W PCI: R PCI Memory Base Address Register 0 Enable Enables accesses to the local address space 0 b[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 95 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Desc ription 28 to 20 LSR 0 0000 0000 SH: R/W PCI: R Capacity of Local Address Spaces 1 (9 bits) These bits specify the size of the local address space 1 (address space for this LSI internal bus) in byte units. (Specified size (Mbytes) [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 96 of 1658 REJ09B0261-0100 (4) PCI Local Address Register 0 (PCILAR0) See section 13.4.3 (2), Accessing PCI Memory Space. SH R/W: PCI R/W: R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R R R R R R RR SH R/W: PCI R/W: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 97 of 1658 REJ09B0261-0100 (5) PCI Local Address Register 1 (PCILAR1) See section 13.4.3 (2), Accessing PCI Memory Space. SH R/W: PCI R/W: R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R R R R R R RR SH R/W: PCI R/W: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 98 of 1658 REJ09B0261-0100 (6) PCI Interrupt Re gister (PCIIR) PCIIR records interrupt sourc es. When an interrupt occurs, the corresponding bit is set to 1. When multiple inte rrupts occ u r, onl y the first source is re gistered. Whe n an inte rrupt is disa bled, 1 is written to the co rresp[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 5 99 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 9 TMTOI 0 SH: R/WC PCI: R Target Memory Read Retry Timeout Interrupt Indicates that the master did not perform retry processing within 2 15 clocks in PCICLK when the PCIC is a target. This bit is detected only for memory rea[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 00 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 SDI 0 SH: R/WC PCI: R SERR Detection Interrupt Indicates that the assertion of SERR was det ected when the PCIC is a host. 0: A SERR detection interrupt was not generated 1: A SERR detection interrupt was generated When TT[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 01 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 3 TADIM 0 SH: R/WC PCI: R Target Abort Detection Interrupt for Master Indicates that transaction was terminated by a target abort when the PCIC is a master. 0: A target abort inte rrupt was not generated when the PCIC is a m[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 02 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 0 MRDPEI 0 SH: R/WC PCI: R Master Read Data Pa rity Error Interrupt Indicates that the PCIC detected a par ity error during data read from the target when the PCIC is a master. Note: A master read data parity error is detect[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 03 of 1658 REJ09B0261-0100 (7) PCI Interrup t Mask Register (PCIIMR) This register is the mask register for PCIIR. SH R/W: PCI R/W: SH R/W: PCI R/W: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit: Initial value: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R/W R R R R R R R R R R R R[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 04 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Desc ription 6 SDIM 0 SH: R/W PCI: R SERR Detection Interrupt Mask 0: SEDI disabled (masked) 1: SEDI enabled (not masked) 5 DPEITWM 0 SH: R/W PCI: R Data Parity Error Interrupt Mask for Target Write 0: DPEITW disabled (masked) 1: DPEITW[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 05 of 1658 REJ09B0261-0100 (8) PCI Error Ad dress Informati on Register ( PCIAIR) This register records PCI address info rmation when an error is detected. The value of this register is undefined until an interrupt is detected. Regardless of the informatio n on mask registers, etc, the val ue [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 06 of 1658 REJ09B0261-0100 (9) PCI Error Command Infor mation Register (P CICIR) This register records the PC I command in formation when an error is d etected. The value of this register is undefined until an interrupt is detected. Regardless of the informatio n on mask registers, etc, the va[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 07 of 1658 REJ09B0261-0100 (10) PCI Arbiter Interrupt Register (PCIAINT) In host mode, this re gister records interrupt s our ces. When multiple interrup ts occur, only the first source is regi stered. When a n interrupt i s disabled, the source is w ritten to t he correspondi ng bit in this r[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 08 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 11 MBTOI 0 SH: R/WC PCI: R Master Bus Time-Out Interrupt An interrupt is detected when IRDY is not asserted within 8 clock cycles during da ta transfer. 0: A master bus timeout interrupt was not generated 1: A master bus tim[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 09 of 1658 REJ09B0261-0100 (11) PCI Arbi ter Interrupt Mask Register (P CIAINTM) This register is the mask register fo r PCIAINT. SH R/W: PCI R/W: SH R/W: PCI R/W: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit: Initial value: R R R R R R R R R R R R R R RR R R R R R R R R R R R R R R RR [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 10 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 MAIM 0 SH: R/WC PCI: R Master-Abort Interrupt Mask 0: MAI disabled (masked) 1: MAI enabled (not masked) 1 RDPEIM 0 SH: R/WC PCI: R Read Data Parity Error Interrupt Mask 0: RDPEI disabled (masked) 1: RDPEI enabled (not mask[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 11 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 31 to 5 ⎯ All 0 SH: R PCI: R Reserved These bits are always read as 0. The write value should always be 0. 4 REQ3BME x SH: R PCI: R REQ3 Error Indicates that an error occurred when the device 3 ( REQ3 ) is a bus master 0: [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 12 of 1658 REJ09B0261-0100 (13) PCI PIO Address Re gister (PCIPAR) Setting this register generates configu ration cycles on the PCI b us. For detai ls, see section 13 .4.5 (2), Config uration Space Acc ess. SH R/W: PCI R/W: SH R/W: PCI R/W: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit: [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 13 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 15 to 11 DN xxxxx SH: R/W PCI: ⎯ Device Number These bits specify a device number for the configuration access target. A device number is represented by a 5-bit value in the range from 0 to 31. Corresponding to the device [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 14 of 1658 REJ09B0261-0100 (14) PCI Power Management Int errupt Register (PCIPINT) This register regist ers power manageme nt interrupt so urces. SH R/W: PCI R/W: SH R/W: PCI R/W: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit: Initial value: R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 15 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 0 PMD0 0 SH: R/WC PCI: ⎯ PCI Power Management D0 Status Transition Interrupt Indicates that an interrupt to request a transition to the PCI bus power-down mode was gen erated. 0: No D0 status transition interrupt was gener[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 16 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Desc ription 1 PMD1M 0 SH: R/W PCI: ⎯ PCI Power Management D1 Status Transition Interrupt Mask 0: PMD1 disabled (masked) 1: PMD1 enabled (not masked) 0 PMD0M 0 SH: R/W PCI: ⎯ PCI Power Management D0 Status Transition Interrupt Mask [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 17 of 1658 REJ09B0261-0100 (17) PCI Memory Bank Mask Register 0 (PCIMBMR0) This register is the mask regist er for PCIMBR0 . This register sp ecifies the memory space size on the PCI bus for a memory read or write to the PCI memory space 0 by the CPU or DMAC. See section 13.4.3 (2), Accessing [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 18 of 1658 REJ09B0261-0100 (18) PCI Memor y Bank Register 1 (PCIMBR1) This register specifies the upper 14 bits of t he memory space addr ess on the PC I bus for a memory read or write to the PCI memory space 1 by t he CPU or DM AC. See section 13.4.3 (2), Accessing PCI Memory Space. SH R/W: P[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 19 of 1658 REJ09B0261-0100 (19) PCI Memory Bank Mask Register 1 (PCIMBMR1) This register is the mask regist er for PCIMBR1 . This register sp ecifies the memory space size on the PCI bus for a memory read or write to the PCI memory space 1 by the CPU or DMAC. See section 13.4.3 (2), Accessing [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 20 of 1658 REJ09B0261-0100 (20) PCI Memor y Bank Register 2 (PCIMBR2) This register specifies the upper 14 bits of t he memory space addr ess on the PC I bus for a memory read or write to the PCI memory space 2 by t he CPU or DM AC. See section 13.4.3 (2), Accessing PCI Memory Space. SH R/W: P[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 21 of 1658 REJ09B0261-0100 (21) PCI Memory Bank Mask Register 2 (PCIMBMR2) This register is the mask regist er for PCIMBR2 . This register sp ecifies the memory space size on the PCI bus for a memory read or write to the PCI memory space 2 by the CPU or DMAC. See section 13.4.3 (2), Accessing [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 22 of 1658 REJ09B0261-0100 (22) PCI I/O Bank Re gister (PCIIOBR) This register specifies the upper 14 bits of t he I/O sp ace address on the PCI bu s for an I/O-read or I/O-write to the PCI I/O space by the CPU or DMAC. See section 13.4.3 (3), Accessing PCI I/O Space. SH R/W: PCI R/W: SH R/W: [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 23 of 1658 REJ09B0261-0100 (23) PCI I/O Bank Mask Register (P CIIOBMR) This register is the mask register for PCIIOB R. This register specifies the I/O space size on the PCI bus for an I/O-read or I/O-write to the PCI I/O space by the CPU or DMAC. See section 13.4.3 (3), Accessing PCI I/O Spac[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 24 of 1658 REJ09B0261-0100 (24) PCI Cache Snoop Control Re gister 0 (PCICSCR 0) An external PCI device ca n access memory of this LSI via the PC IC. When an PCI device accesses a cacheable area, the PCIC can issue cac he snoop commands to th e on-c hip caches. This register can specify the fun[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 25 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Desc ription 1, 0 SNPMD All 0 SH: R/W PCI: — Snoop Mode for PCICSAR0 These bits specify whether PCICSAR0 is compared with the SuperHyway bus address req uested by an external device, or not. When PCICSAR0 is s pecified to be compared,[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 26 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Desc ription 31 to 5 ⎯ All 0 SH: R PCI: — Reserved These bits are always read as 0. The write value should always be 0. 4 to 2 RANGE All 0 SH: R/W PCI: — Address Range to be Compared These bits specify the address range of PCICSAR[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 27 of 1658 REJ09B0261-0100 (26) PCI Cache Snoop Addre ss Register 0 (PCICSAR0) This register specifies the addres s to be compared with the PCI ad dress reque sted by an external PCI device to the PCIC. For details, see section 13.4 .4 (7), Cache Coherency. SH R/W: PCI R/W: SH R/W: PCI R/W: 16[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 28 of 1658 REJ09B0261-0100 (27) PCI Cache Snoop Addre ss Register 1 (PCICSAR1) This register specifies the addres s to be compa red with the PCI ad dress reque sted by an external PCI device to the PC IC. For details, see section 13.4.4 (7), Cache Coherency. SH R/W: PCI R/W: SH R/W: PCI R/W: 1[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 29 of 1658 REJ09B0261-0100 (28) PCI PIO Data Register (PCI PDR) By reading or writing to this register, a config uration cycle is generated on the PCI bu s. For details, see section 13.4.5 (2 ), Configuration Space Access. SH R/W: PCI R/W: SH R/W: PCI R/W: 16 17 18 19 20 21 22 23 24 25 26 27 2[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 30 of 1658 REJ09B0261-0100 13.4 Operation 13.4.1 Supported P CI Commands Table 13.4 Supported P CI Commands C/ BE [3:0] Commands PCI Master PCI Target 0000 Interrupt ackn owledge cycle No ⎯ 0001 Special cycle Yes * 1 ⎯ 0010 I/O read Yes Yes * 2 0011 I/O write Yes Yes * 2 0100 Reserved ⎯ [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 31 of 1658 REJ09B0261-0100 13.4.2 PCIC Initialization After a power-on reset, the ENBL bit in PCIE CR and the CFINIT bit in PCICR are cleared. At this time, if the PCIC operates as the PCI bus host (host m ode), device a rbitration is not perfor med on the PCI bus, and the bus mastershi p is a[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 32 of 1658 REJ09B0261-0100 13.4.3 Master Access This section describes how software contro ls the PCI whe n the PCIC is a bus master. This section describes the c ases where the PCIC is used i n both host mode and normal mode. (1) Address Map Table 13.5 shows the PCIC a ddress map. Table 13.5 [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 33 of 1658 REJ09B0261-0100 (2) Accessing PCI Memory Space Figure 13.2 s hows the mem ory map fr om the SuperH yway bus to the PCI bus. PCI memory space 1 64 MB PCI memory space 2 512 MB SHwy bus address space (4 GB) PCI memory space 0 16 MB Re g ister space 2 MB PCI I/O space 2 MB PCI address [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 34 of 1658 REJ09B0261-0100 For PCI memo ry space 0, t he middle six bits ([ 23:18]) are controlled by P CIMBMR0. • PCIMBMR0 [23:18] B '1111 11: PCI addres s [23:18] = Super Hyway bus address [23: 18] • PCIMBMR0 [23:18] B '0000 00: PCI addres s [23:18] = PCIMB R0 [23:18 ] The uppe[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 35 of 1658 REJ09B0261-0100 For PCI memory space 2 acce sses, the middl e eleven bits ([28:18]) are c ontrolled by PCIMBMR2. • PCIMBMR2 [28:18] B'1 1111 1111 11: PCI address [28 :18] = Su p er Hy w ay bu s address [28:18] • PCIMBMR2 [28:18] B'0 0000 0000 00: PCI address [28:18] = [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 36 of 1658 REJ09B0261-0100 (3) Accessing PCI I/O Space Burst transfers are not supported in I/O transfers. A ccess wit hin the size of 4-byte. The PCI I/O address space is a llocated from H' FD20 0000 to H'FE3F FFFF (2 M bytes). Address translation from SuperHyw ay bus to PCI local b[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 37 of 1658 REJ09B0261-0100 MSB 31 0 LSB SHwy data PCI bus data 1. Little endian A' B' C' D' A B C A' B' C' D' A B A B C PCI_Addr[2] = 1 PCI_Addr[2] = 0 31 0 SHwy data PCI bus data 2. Bi g endian A B C D A' B' C' D' ABC PCI_Addr[2] = 0[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 38 of 1658 REJ09B0261-0100 MSB 31 0 LSB SHwy data PCI bus data 1. Little endian A' B' C' D' A B C A' B' C' D' A BC D D A BC D PCI_Addr[2] = 1 PCI_Addr[2] = 0 MSB 31 0 LSB SHwy data PCI bus data 2. Bi g endian D C B A D' C' B' A' A B C[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 39 of 1658 REJ09B0261-0100 31 0 A 31 0 A 31 0 A 31 0 A B B B B C C C C D D D D AB AB BA AB CD CD DC CD CD AB CD DC CD AB AB BA Size Byte Word lon g - word Address 4n + 0 4n + 1 4n + 2 4n + 3 4n + 0 4n + 2 4n + 0 SHwy bus PCI bus Bi g -endian CPU Data Data (without swappin g ) Data (with swappi[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 40 of 1658 REJ09B0261-0100 13.4.4 Target Access This section describes how the PCIC in this LSI is accessed by an external PCI local bus master when the PCIC is used in both the host mode and normal mo de. (1) Accessing Me mory Space in This LSI Accesses to the PCIC in this LSI by an ex ternal[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 41 of 1658 REJ09B0261-0100 To access the address space in this LSI, use PCIMBAR0/1, PCILSR0/1, and PC ILAR0/1. PCI addresses can be allocated to by software. Th e PCIC has two types of registers for me mory mapping, Local Address Sp ace 0 (base 0) and Local Address Space 1 (base 1). By setting[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 42 of 1658 REJ09B0261-0100 MBARE PCI address 31 28 20 0 29 19 PCIMBAR0/1 PCILSR0/1 PCILAR0/1 SHwy bus address Compare 0 31 20 0 29 0 31 28 20 0 29 19 19 28 31 20 29 19 28 31 20 29 19 28 Figure 13.11 PCI Bus to Sup erHyway Bus Address Translation (2) Accessing PCIC I/O Space The PCI I/O address[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 43 of 1658 REJ09B0261-0100 (3) Accessing PCIC Registers Configuration Re gisters: Configuration registers should be read or written with (off set from configuration register space base address) by configuration accesses. A burst tra nsfer is cut off and terminated. Local Registers: Local regis[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 44 of 1658 REJ09B0261-0100 (6) Endian This LSI supports both the big and little en dian formats. Since the PCI local bus is inherently little endian, the PC IC supports both b yte swappi ng and non-byte swap ping. The endian format is specified by the TBS bit in PCICR. 31 MSB LSB 0 PCI bus dat[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 45 of 1658 REJ09B0261-0100 31 MSB LSB 0 PCI bus data SHwy data 1. Little endian A' B' C' D' A B C A' B' C' D' A B C A BC D PCI_Addr[2] = 1 PCI_Addr[2] = 0 31 MSB LSB 0 PCI bus data SHwy data D C B A D' C' B' A' D C B A D' C'[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 46 of 1658 REJ09B0261-0100 31 0 A 31 0 A 31 0 A 31 0 A B B B B C C C C D D D D AB AB BA AB CD CD DC CD CD AB CD DC CD AB AB BA Size Byte Wor d Lon g - word Address 4n + 0 4n + 1 4n + 2 4n + 3 4n + 0 4n + 2 4n + 0 PCI bus SHwy bus Bi g -endian CPU Data Data (without swappin g ) Data (with swapp[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 47 of 1658 REJ09B0261-0100 (7) Cache Coherency The PCIC su pports cache co herency fu nction. When the PCIC functions as a ta rget device, cache coherency is guaranteed on the PCI bus for accesses from a master device both i n host mode and normal mode. When a cacheable area of this LSI is acc[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 48 of 1658 REJ09B0261-0100 13.4.5 Host Mode (1) Operation in Host Mode The PCI interface of this LSI supp orts a subset of the PCI versio n 2.2 and can be connect ed to a device with a PCI bus in terface. According to the PCIC mo de, host mo de or normal mode, ope ration diffe rs in two points[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 49 of 1658 REJ09B0261-0100 31 30 24 16 23 15 11 10 87 2 1 0 Confi g uration address re g ister PCI bus address Reserved Bus No. Function No. Re g ister No. 0 0 0 0 Only one bit is set to 1. 31 11 1 0 8 7 2 1 0 Enable bit 0: Disabled 1: Enabled Device No. Figure 13.17 Address Ge neration for Ty[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 50 of 1658 REJ09B0261-0100 Subsequentl y, after the PCIC requi res the bus an d transfer data and the request is permitted, the priority chang es as follows: Device 0 > de vice 2 > devi ce 3 > device 1 > PCIC Then, after t he device 3 re quires the bus and transfer data and the re [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 51 of 1658 REJ09B0261-0100 The PCIC can retain err or information on t he PCI bus. When a n error occurs , the error address is stored in PCIAIR and the transf er type an d comma nd information are stored in PCICIR. When the PCIC is in host mode, the bus master informati on at the error occurr[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 52 of 1658 REJ09B0261-0100 D0 (Nomal state) D2 (Clock stopped) D1 (Bus idle) D3 (Power-down) Figure 13.18 Power Down State Tr ansitions on PCI Bus When the PCIC detects that t he power state (PS) bit in PC IPMCSR changes (PS is written by an external PCI device), it issues a power manageme nt [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 53 of 1658 REJ09B0261-0100 13.4.8 PCI Local Bus Basic Inter face The PCI interface of this LSI supports subset s in the PCI bus ve rsion 2.2 and it can be co nnected to a device with a PCI bus i nterface. The following figures show the ti ming in each operat ing mode. (1) Master Read/ Write Cy[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 54 of 1658 REJ09B0261-0100 PCICLK AD[31:0] PAR C/ B E[ 3 : 0 ] PC IF R AME I RDY D E VS EL T RDY IDSEL R E Q G NT Addr D0 AP DP0 Com BE0 L OCK Le g end: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Figure 13.20 Master Read [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 55 of 1658 REJ09B0261-0100 Addr D0 AP DP0 Co m BE0 D1 DPn-1 DPn BE1 BEn Dn PCICLK AD[31:0] PAR C/ B E[ 3 : 0 ] PC IF R AME I RDY D E VS EL T RDY IDSEL R E QOU T G NTIN Le g end: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command L OCK BEn: nth data byte e[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 56 of 1658 REJ09B0261-0100 Addr D0 AP DP0 Com BE0 D1 DPn-1 DP n BE1 BEn Dn PCICLK AD[31:0] PAR C/ B E[ 3 : 0 ] PC IF R AME I RDY D E VS EL T RDY IDSEL R E QOU T G NTIN Le g end: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command L OCK BEn: nth data byte e[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 57 of 1658 REJ09B0261-0100 (2) Target Read/Write Cycle Timing The PCIC returns retries to targ et memory read accesses from a n ex ternal master until 8 longword (32-bit) data are prepared in the PCIC internal FIFO. That is, the first target read is alwa ys responded by a retry. When a target [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 58 of 1658 REJ09B0261-0100 Addr D0 AP DP0 Co m BE0 Disconnect Confi g uration space access Lock PCICLK AD[31:0] PAR C/ B E[ 3 : 0 ] PC IF R AME I RDY D E VS EL T RDY IDSEL R E QOU T G NTIN Le g end: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command L OCK[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 59 of 1658 REJ09B0261-0100 DP0 Addr D0 AP Co m BE0 Disconnect Confi g uration space access Lock PCICLK AD[31:0] PAR C/ B E[ 3 : 0 ] PC IF R AME I RDY D E VS EL T RDY IDSEL R E QOU T G NTIN Le g end: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command L OCK[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 60 of 1658 REJ09B0261-0100 Addr D0 AP DP0 Com BE0 Disconnect Lock D1 DPn-1 DPn BE1 B En Dn PCICLK AD[31:0] PAR C/ B E[ 3 : 0 ] PC IF R AME I RDY D E VS EL T RDY IDSEL R E Q G NT Le g end: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command L OCK BEn: nth d[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 61 of 1658 REJ09B0261-0100 Addr D0 AP DP0 Com BE0 Disconnect Lock D1 DPn-1 DPn BE1 B En Dn PCICLK AD[31:0] PAR C/ B E[ 3 : 0 ] PC IF R AME I RDY D E VS EL T RDY IDSEL R E Q G NT Le g end: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command L OCK BEn: nth d[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 62 of 1658 REJ09B0261-0100 (3) Address/Data Stepping Timing By writing 1 to the SC bit in PCICMD, a wait (stepping ) of one clock can be inserted when the PCIC is dri ving the A D bus. As a result, the PCIC dri ves the AD bus with 2 cloc ks. This function can be used wh en the PCI bus load is [...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 63 of 1658 REJ09B0261-0100 D1 BE1 PCICLK AD[31:0] PAR C/ B E[ 3 : 0 ] PC IF R AME I RDY D E VS EL T RDY Le g end: Addr: PCI space address Dn: nth data AP: Address parity DPn: nth data parity Com: Command BEn: nth data byte enable Addr D0 AP DP0 Com BE0 Dn DPn-1 DPn BEn Figure 13.28 Target Memo[...]

13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 6 64 of 1658 REJ09B0261-0100[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 65 of 1658 REJ09B0261-0100 Section 14 Direct Memory Access Controller (DMAC) This LSI includes an on-c hip direct memory acce ss controller (DM A C). In stead of the CPU, the DMAC can be used to pe rform data trans f ers among e x ternal devices equippe d with DACK (transfer [...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 66 of 1658 REJ09B0261-0100 Figure 14.1 sh ows a block diagra m of the DMAC. P er ipheral bus controller DMA transfer end si g nal Iteration control DMAC channels 6 to 11 Re g ister control Start-up control Request priority control Bus interface Iteration control DMAC channels[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 67 of 1658 REJ09B0261-0100 14.2 Input/Output Pins The DMAC-related external pins are shown below. Table 14.1 shows the configuratio n of the pins th at are connected to external device. The DMAC has pins for four chan nels (channels 0 to 3) used in the e xternal b us. Table 1[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 68 of 1658 REJ09B0261-0100 14.3 Register Descriptions Table 14.2 sho ws the register configuration. Table 14.2 Register Config uration of the DMAC (1) Channel Name Abbr ev. R/W P4 Address Area 7 Address Access Size * 3 Sync clock 0 DMA source address register 0 SAR0 R/W H&apo[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 69 of 1658 REJ09B0261-0100 Channel Name Abbr ev. R/W P4 Address Area 7 Address Access Size * 3 Sync clock 0 DMA source address register B0 SARB0 R/W H'FC80 8120 H'1C80 8120 32 Bck DMA destination address register B0 DARB0 R/W H'FC80 8124 H'1C80 8124 32 Bck[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 70 of 1658 REJ09B0261-0100 Channel Name Abbr ev. R/W P4 Address Area 7 Address Access Size * 3 Sync clock 6 to 11 DMA operation register 1 DMAOR1 R/W * 2 H'FCC0 8060 H'1CC0 8060 16 Bck, Pck * 5 10 DMA source addr ess register 10 SAR10 R/W H'FCC0 8070 H'1CC[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 71 of 1658 REJ09B0261-0100 Table 14.2 Register Config uration of the DMAC (2) Channel Name Abbrev. Power-on Reset by PRESET Pin/WDT/ H-UDI Manual Reset by WDT/Mu ltiple Exception Sleep by SLEEP instruction Deep Sleep by SLEEP instruction (DSLP = 1) Module Standby 0 DMA source[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 72 of 1658 REJ09B0261-0100 Channel Name Abbrev. Power-on Reset by PRESET Pin/WDT/ H-UDI Manual Reset by WDT/Mu ltiple Exception Sleep by SLEEP instruction Deep Sleep by SLEEP instruction (DSLP = 1) Module Standby 0 DMA source address register B0 SARB0 Undefined Undefined Reta[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 73 of 1658 REJ09B0261-0100 Channel Name Abbrev. Power-on Reset by PRESET Pin/WDT/ H-UDI Manual Reset by WDT/Mu ltiple Exception Sleep by SLEEP instruction Deep Sleep by SLEEP instruction (DSLP = 1) Module Standby 8 DMA source address register 8 SAR8 Undef ined Undefined Retai[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 74 of 1658 REJ09B0261-0100 Channel Name Abbrev. Power-on Reset by PRESET Pin/WDT/ H-UDI Manual Reset by WDT/Mu ltiple Exception Sleep by SLEEP instruction Deep Sleep by SLEEP instruction (DSLP = 1) Module Standby 9 DMA source address register B9 SARB9 Undefined Undefined Reta[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 75 of 1658 REJ09B0261-0100 14.3.1 DMA Source Address Registers 0 to 11 (SAR0 to SAR11) SAR are 32-bit readable/writable registers that specify the source addres s of a DMA transfer. During a DMA transfer, these regi sters indicate the source address of the next tran sfer. A w[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 76 of 1658 REJ09B0261-0100 14.3.2 DMA Source Address Registers B0 to B3, B6 to B9 (SARB0 to SARB3, SARB6 to SARB9) SARB are 32-bit readable/writable reg isters that sp ecify the source address of a DMA transfer that is set in SAR again i n repeat/reload mode. The data written[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 77 of 1658 REJ09B0261-0100 14.3.3 DMA Destina tion Address Regis ters 0 to 11 (DAR0 to DA R11) DAR are 32-bit readable/writable registers t hat sp ecify the destination address of a DMA transfer. During a DMA transfer, these registers indicate the destination address of the n[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 78 of 1658 REJ09B0261-0100 14.3.4 DMA Desti nation Address Registers B0 t o B3, B6 to B9 (DARB0 to DARB 3, DARB6 to DARB9) DARB are 32-bit readable/writab l e registers that specify the destinati on address of a DMA transfer that is set in DAR agai n in repeat/reload m ode. T[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 79 of 1658 REJ09B0261-0100 14.3.5 DMA Trans fer Count Regi sters 0 to 11 (TCR0 t o TCR11) TCR are 32-bit readable/writable registers th at speci fy the DMA transfer coun t. When the valu e is set to H'00000001, H '00FFFFFF, H'00000000, the transfer coun t is 1,[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 80 of 1658 REJ09B0261-0100 14.3.6 DMA Transfe r Count Registers B0 to B 3, B6 to B9 (TCRB0 to TCRB 3, TCRB6 to TCRB9) TCRB are 32-bit readable/writable registers. Th e da ta written to TCR by the CPU is also written to TCRB. While the half end function is being used, TCRB are[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 81 of 1658 REJ09B0261-0100 14.3.7 DMA Channe l Control Registers 0 to 11 (CHCR 0 to CHCR11) CHCR are 32-bit readable/writable reg ister s that con trol the DMA tr ansfer mod e. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 010000000 0 000[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 82 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 27 to 25 RPT[2:0] 000 R/W DMA Setting Update Specific ation These bits are valid in only CHCR0 to CH CR3, and CHCR6 to CHCR9. 000: Normal mode 001: Repeat mode SAR/DAR/TCR are repeated 010: Repeat mode DAR[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 83 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 21 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 20 TS2 0 R/W DMA Transfer Size Specificati on Specifies the DMA transfer size with TS1 and TS0. When the transfer sourc[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 84 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 19 HE 0 R/(W) * Half End Flag After HIE (bit 18) is set to 1 and the number of transfers is half of TCR (one bit shift to right) which is set before transfer, HE is 1. • HE is set to 1 when the number of[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 85 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 17 AM 0 R/W Acknowledge Mode Selects whether DACK is output in a data read cycle or in a data write cycle. DACK is output only for LBSC space transfers. This bit is valid in only CHCR0 to CHCR3. 0: DACK ou[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 86 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 15, 14 DM[1:0] 00 R/W Destinati on Address Mode 1, 0 Specify whether the DMA destination address is incremented or decremented. 00: Destination address is fixed 01: Destination address is incremented byte [...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 87 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 11 to 8 RS[3:0] 0000 R/W Resource Sele ct 3 to 0 Specify the transfer request source. To change the transfer request source, the DMA enable (DE) bit should be cleared to 0. 0000: External request, or dual [...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 88 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 2 IE 0 R/W Interrupt Enab le Specifies whether an interrupt request is generated to the CPU at the end of the final DMA transfer. Setting this bit to 1 generates an interrupt request (DMINT) to the CPU whe[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 89 of 1658 REJ09B0261-0100 14.3.8 DMA Operati on Register 0, 1 (D MAOR0 and DM AOR1) DMAOR are 16-bit readable/writable registers that specify the priority of channels in DMA transfer. Also, these registers show the DM A transfer status. DMAOR 0 is a register c ommon to chann[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 90 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 11, 10 ⎯ All 0 R Reserved These bits are always read as 0. The write value shou ld always be 0. 9, 8 PR[1:0] 00 R/W Priority Mode 1, 0 Determine the priority between channels w hen there are transfer req[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 91 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 2 AE 0 R/(W) * Address Error Flag Indicates that an address error occurred during DMA transfer. This bit is set under following conditions. • The value set in SAR or DAR does not match to the transfer si[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 92 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Descriptions 0 DME 0 R/W DMA Master Enable Enables or disables DMA transfers on all chann els (channels 0 to 5) correspondi ng to DMAOR0, and all channels (channels 6 to 11) correspond ing to DMAOR1. If the DME bit, an[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 93 of 1658 REJ09B0261-0100 14.3.9 DMA Extende d Resource Selectors 0 to 5 (DMARS0 to DMARS5) DMARS are 16-bit readab le/writable regist ers. DMARS0, DMARS1, D MARS2, DMARS 3, DMARS4, an d DMARS5 s pecify DMA transfer request so urce from peripheral m odules for channels 0 an [...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 94 of 1658 REJ09B0261-0100 • DMARS4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit: Initial value: R/W: Ch9MID Ch9RID Ch8MID Ch8RID • DMARS5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000000000 [...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 95 of 1658 REJ09B0261-0100 • DMARS1 Bit Bit Name Initial Value R/W Descriptions 15 14 13 12 11 10 C3MID5 C3MID4 C3MID3 C3MID2 C3MID1 C3MID0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Transfer request source mo dule ID5 to ID0 for DMA channel 3 (MID) See table 14.3. 9 8 C3RID1 C3RI[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 96 of 1658 REJ09B0261-0100 • DMARS2 Bit Bit Name Initial Value R/W Descriptions 15 14 13 12 11 10 C5MID5 C5MID4 C5MID3 C5MID2 C5MID1 C5MID0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Transfer request source mo dule ID5 to ID0 for DMA channel 5 (MID) See table 14.3. 9 8 C5RID1 C5RI[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 97 of 1658 REJ09B0261-0100 • DMARS3 Bit Bit Name Initial Value R/W Descriptions 15 14 13 12 11 10 C7MID5 C7MID4 C7MID3 C7MID2 C7MID1 C7MID0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Transfer request source mo dule ID5 to ID0 for DMA channel 7 (MID) See table 14.3. 9 8 C7RID1 C7RI[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 98 of 1658 REJ09B0261-0100 • DMARS4 Bit Bit Name Initial Value R/W Descriptions 15 14 13 12 11 10 C9MID5 C9MID4 C9MID3 C9MID2 C9MID1 C9MID0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Transfer request source mo dule ID5 to ID0 for DMA channel 9 (MID) See table 14.3. 9 8 C9RID1 C9RI[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 6 99 of 1658 REJ09B0261-0100 • DMARS5 Bit Bit Name Initial Value R/W Descriptions 15 14 13 12 11 10 C11MID5 C11MID4 C11MID3 C11MID2 C11MID1 C11MID0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Transfer request source mo dule ID5 to ID0 for DMA channel 11 (MID) See table 14.3. 9 8 C11R[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 00 of 1658 REJ09B0261-0100 Table 14.3 List of Transfer Request Sources Peripheral Module Setting Value for One Channel (MID and RID fields) MID RID Function SSI0 H'03 B'000000 B'11 Transmit/receive SSI1 H'07 B'000001 B'11 Transmit/receive SCIF0 H[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 01 of 1658 REJ09B0261-0100 14.4 Operation When DMA transfe r is requested, t he DMAC starts transfer according to the determi n ed channel priority. When the transfer end conditio ns are satisfied, the DMAC ends transfer. Tran sfer requests have three mod es: auto-request mod[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 02 of 1658 REJ09B0261-0100 Choose whether DREQ is detected by edg e or level with the DREQ level (DL) bit and DREQ select (DS) bit in CHCR0 to CHCR3 shown in tabl e 14.5. The source of th e transfer request does not have to be the tra nsfer source o r transfer desti nation. T[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 03 of 1658 REJ09B0261-0100 (3) On-Chip Peripheral Module Request Mode On-chip peri pheral module request m ode is a mode that perf orms transfer b y DMA trans fer request signal from an on-chi p peripheral module. DMA tran sfer reque st si gnals include a tran smit data empty[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 04 of 1658 REJ09B0261-0100 Table 14.8 List of On-Chip Peripheral Module Request Modes CHCR DMARS RS[3:0] MID RID DMA Transfer Request Source DMA Transfer R equest Signal Source Destinatio n Bus Mode 1000 000000 11 SSI0 transmitter Transmit data empty request (In transmit mode[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 05 of 1658 REJ09B0261-0100 CHCR DMARS RS[3:0] MID RID DMA Transfer Request Source DMA Transfer R equest Signal Source Destinatio n Bus Mode 1000 001101 01 SCIF5 transmitter TXI (transmit FIFO data empty) Any SCFTDR5 Cycle steal 10 SCIF5 receiver RXI (receive FIFO data f ull) [...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 06 of 1658 REJ09B0261-0100 14.4.2 Channel Priority When the DMAC recei ves transfer requests on tw o or more channels simu ltaneously, it transfers data according to a determined priority. Modes are chosen from among fixed mode and round- robin mode . Modes are selected by bi[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 07 of 1658 REJ09B0261-0100 CH1 > CH2 > CH3 > CH4 > CH5 > CH0 CH0 > CH1 > CH2 > CH3 > CH4 > CH5 CH2 > CH3 > CH4 > CH5 > CH0 > CH1 CH0 > CH1 > CH2 > CH3 > CH4 > CH5 CH0 > CH1 > CH2 > CH3 > CH4 > CH5 CH0 [...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 08 of 1658 REJ09B0261-0100 Figure 14. 3 shows ho w the priori ty changes when channel 0 and cha nnel 3 tra nsfers are request ed simultaneousl y and a channel 1 transfer i s re quested during the channel 0 transfer. The DMAC operates as f ollows: 1. Transfer requests are gene[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 09 of 1658 REJ09B0261-0100 14.4.3 DMA Transfe r Types Tables 14.9 an d 14.10 sh ow the trans fer directi ons that can be s upported by the DM AC. DMA transfer type su pports dual address mode. A data transfer timing dep ends on the bus mode . Bus modes inc lude cycle steal mo[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 10 of 1658 REJ09B0261-0100 Table 14.10 DMA Transfer Directions for On-Chip Peripheral Module Request * 2 * 3 Transfer Destination Transfer Source LBSC Space DBSC Space PCIC Space On-Chip Peripheral Module * 1 L or U Memory LBSC Space N N N Y N DBSC Space N N N Y N PCIC Space [...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 11 of 1658 REJ09B0261-0100 (1) Dual Address Mode In dual address mode, both the transfer source and tr ansfer destination are accessed by address. The source and destination ca n be sp ecified externally or internally. Data is read from the transfer source in a data read cycl[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 12 of 1658 REJ09B0261-0100 Transfer source address Transfer destination address CLKOUT A25 to A0 C Sn RD WEn D31 to D0 DACKn (Active-low) Figure 14.5 Ex ample of DMA Transf er Timing in Dual Address Mode (Source: SRAM, Destin ation: DD R-SDRAM)[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 13 of 1658 REJ09B0261-0100 (2) Bus Modes Bus mode s include cycle steal m ode and burst mode. Th e modes are ch osen by th e TB and LCKN bits in CHCR. (a) Cycle Steal Mode • Normal mode 1 (CHCR.LCKN = 0, CHCR.TB = 0) In cycle steal normal mode 1, the DM AC gives the SuperHy[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 14 of 1658 REJ09B0261-0100 • Intermitte nt mode 16 (DMAOR. CMS = 10, CHCR.LCKN = 0 o r 1, CHCR .TB = 0) • Intermitte nt mode 64 (DMAOR. CMS = 11, CHCR.LCKN = 0 o r 1, CHCR .TB = 0) In intermittent mo de of cycle steal, the DMAC gives the Super Hyway bus masters hip to oth[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 15 of 1658 REJ09B0261-0100 SuperHyway bus cycle Read Write Read Write Read Write DR E Q CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU Figure 14.9 DMA Transf er Ti ming Example in Burst Mode (DREQ Low Level Detection) (3) Bus Mode and Channel Pri ority Figure 14.10 shows the b[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 16 of 1658 REJ09B0261-0100 DMA CH0 Cycle steal CH0 transfer source (a) CH0: Cycle steal mode CH1: Cycle steal mode Priority: CH0 > CH1 CPU DMA CH1 DMA CH0 DMA CH0 DMA CH0 DMA CH0 DMA CH0 DMA CH1 CPU DMA CH1 Cycle steal CH1 transfer source DMA CH0 Cycle steal CH1 transfer s[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 17 of 1658 REJ09B0261-0100 14.4.4 DMA Transfe r Flow After intended transfer conditio ns are set to SAR, DAR, TCR, CHCR, DMAOR, and DMARS, the DMAC transfers data according to the following procedure. 1. Ch ecks if transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMI F =[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 18 of 1658 REJ09B0261-0100 Notes: 1. In repeat mode, a transfer request is acceptted with TE =1 when HIE = 1 and HE = 0 (half end interrupt is enable and clear the HE to 0 after HE is set to 1). 2. In auto-request mode, transfer starts when bits NMIF, AE, and TE are all 0 or [...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 19 of 1658 REJ09B0261-0100 14.4.5 Repeat Mode Trans f er A repeat mode transfer of th e DMAC enab les a DMA tr ansfer to repeat without specifyi ng the transfer settings be fore a transfer. Using a r epeat mode tr ansfer with the half end functio n can execu te a double buffe[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 20 of 1658 REJ09B0261-0100 This function enables sequential voice compression by switching a storing buffer for data received consequenti ally and a data buffer f o r processing signals alternately. 14.4.6 Reload Mode Trans fer In a reload mode transfer, according to the se t[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 21 of 1658 REJ09B0261-0100 14.4.7 DREQ Pin Sampling Timing Figures 14.13 to 14.22 show t he timing that the DREQ input is sampled in each bus mode. Figures 14.13, 14.16, and 14.20 show t he timing that the DREQ input is sampled when byte transfer is performed in 8-, 1 6-, 32-[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 22 of 1658 REJ09B0261-0100 : Non-sensitive period CLK OUT Bus cycle DREQ (Risin g ed g e) DRAK (Hi g h-active) D ACK (Hi g h-active) Acceptance started Accepted after one cycle of CLKOUT at the first risin g ed g e of the divided-up DA CK 1st acceptance 2nd acceptance CPU CPU[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 23 of 1658 REJ09B0261-0100 CLKOUT Bus cycle DREQ ( Overrun 0, Hi g h level) DRAK (Hi g h-active) DACK (Hi g h-active) CLKOUT Bus cycle DREQ ( Overrun 1, Hi g h level) DRAK (Hi g h-active) DACK (Hi g h-active) CPU DMAC CPU 1st acceptance Acceptance started Accepted after one c[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 24 of 1658 REJ09B0261-0100 Bus cycle DREQ ( Overrun 0, Hi g h level) DRAK (Hi g h-active) DACK (Hi g h-active) Bus cycle DREQ ( Overrun 1, Hi g h level) DRAK (Hi g h-active) DACK (Hi g h-active) : Non-sensitive period CLK OUT Acceptance started Accepted after one cycle of CLK[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 25 of 1658 REJ09B0261-0100 Acceptance started Accepted after one cycle of CLKOUT after the end of the first of the multiple bus cycles 1st acceptance 2nd acceptance : Non-sensitive period Acceptance started Accepted after one cycle of CLKOUT at the risin g ed g e of DA CK 1st[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 26 of 1658 REJ09B0261-0100 Bus cycle ( Overrun 0, Hi g h level) DRAK (Hi g h-active) DACK (Hi g h-active) Bus cycle ( Overrun 1, Hi g h level) DRAK (Hi g h-active) DACK (Hi g h-active) Acceptance started Accepted after one cycle of CLKOUT at the fallin g ed g e of D ACK 1st a[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 27 of 1658 REJ09B0261-0100 Acceptance started Accepted after one cycle of CLK OUT at the first fallin g ed g e of the divided-up D ACK 1st acceptance 2nd acceptance : Non-sensitive period Acceptance started Accepted after one cycle of CLK OUT at the first risin g ed g e of th[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 28 of 1658 REJ09B0261-0100 Acceptance started Accepted after one cycle of CLK OUT after the end of the first of the multiple bus cycles 1st acceptance 2nd acceptance : Non-sensitive period Acceptance started Accepted after one cycle of CLK OUT at the risin g ed g e of DA CK 1[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 29 of 1658 REJ09B0261-0100 14.5 DMAC Interrupt Sources In the DMAC, each c hannel has 14 interrupt so urces: a DMA transfer en d/half-end interrupts request (DMINT0 t o DMINT 11), a DMA ad dress error interr upt request (DM AE0) commo n to channels 0 t o 5, and a DM A address[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 30 of 1658 REJ09B0261-0100 14.6 Usage Notes Note the following things in using this DMAC. 14.6.1 Stopping Modules and Changing Frequency When the DMAC is operating, it is prohibited to set or clear th e corresponding bit of MSTPCR1 that controls H -UDI, UBC, DMAC and G DTA mo[...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 31 of 1658 REJ09B0261-0100 14.6.6 DACK/DRE Q Setting If the IWRRD, IWRRS, and IWW bits in CSnBCR are set to B'000 (no idle cycles), DAC K of two or more DMA transfers may be connected. If DAC K of two or more DMA transfers is connected, operation is not guara nteed unde [...]

14. Direct Memory A ccess Controller (DMAC) Rev.1.00 Jan. 10, 2008 Page 7 32 of 1658 REJ09B0261-0100[...]

15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 33 of 1658 REJ09B0261-0100 Section 15 Clock Pulse Generator (CPG) The CPG generates cloc ks provided to the i n ternal and external bus interf aces of the SH7785, a nd controls p ower-down mode. The C PG consis ts of a crystal oscill ator circuit , PLLs, divi ders, and the control uni t[...]

15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 34 of 1658 REJ09B0261-0100 Oscillator circuit Control section Crystal oscillator circuit Divider 1 × 1 PLL circuit 1 × 72 × 36 Clock frequency control circuit FRQCR0 FRQCR1 MSTPCR1 Clock control circuit Bus interface Peripheral bus PLL circuit 2 × 1 CLKOUT CLKOUTENB Divider 2 × 1/2[...]

15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 35 of 1658 REJ09B0261-0100 The function of each block in the CP G is as follows. • PLL circuit 1 PLL circuit 1 multiplies the input clock frequen cy on the PLL circuit by 36 or 72. • PLL circuit 2 PLL circuit 2 matches the phases of the bus clock (Bck) a nd the cloc k of the CLKO UT[...]

15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 36 of 1658 REJ09B0261-0100 15.2 Input/Output Pins Table 15.1 sho ws the CPG pi n configurati on. Table 15.1 CPG Pin Configuration Pin Name Function I/O Description MODE0, MODE1, MODE2, MODE3, and MODE4 * 1 Mode Pins 0,1,2,3,4 Clock operating mode * 1 Input Select the clock operating mod[...]

15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 37 of 1658 REJ09B0261-0100 15.3 Clock Operating Modes Table 15.2 sho ws the relation ship between s etting of the mode pi ns (MODE0 to MODE4) an d the clock operating modes. Table 15.2 Clock Operating Modes a nd Operati ons of the Oscil lator and PLL s Setting of Mode Control Pins * 1 *[...]

15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 38 of 1658 REJ09B0261-0100 Table 15.3 Clock Operating Modes a nd Frequency Mul tiplication Ratio for E ach Clock (Both MODE 12 and MODE11 Are Set to High Le vel) Frequency Multiplication Ratio (for Input Clock) Clock Operating Mode FRQMR1 Initial Value CPU Clock Ick RAM Clock Uck SuperH[...]

15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 39 of 1658 REJ09B0261-0100 15.4 Register Descriptions Table 15.5 lists the registers. Table 15.6 shows t h e register st ates in each processing mode. Table 15.5 Register Configuration Register Name Abbreviation R/W P4 Addres s Area 7 Address Access Size Sync Clock Frequency control reg[...]

15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 40 of 1658 REJ09B0261-0100 Table 15.6 Register State in Eac h Processing M ode Register Name Abbreviation Power-on Reset by the PRESET Pin, WDT, or H-UDI Manual Reset by WDT or Multiple Exception Sleep or Deep Sleep by Sleep Instruction Frequency control register 0 FRQCR0 H'0000 00[...]

15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 41 of 1658 REJ09B0261-0100 15.4.1 Frequency Control Re gister 0 (FRQ CR0) FRQCR0 is a 32-bit readable and partially writab le register that executes a sequence for c hanging the frequency of each clock. After the sequence is executed, FRQCR0 is a u tomatically cleared to 0. FRQCR0 can o[...]

15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 42 of 1658 REJ09B0261-0100 15.4.2 Frequency Control Re gister 1 (FRQ CR1) FRQCR1 is a 32-bit readable /writable register that ca n select the di vision rati o of divi der 2 for the CPU clock (lc k), the Supe rHyway clock (SHck), the peripheral cl ock (Pck), the D DR clock (DDRck), the b[...]

15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 43 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 31 30 29 28 IFC3 IFC2 IFC1 IFC0 0 0 0 0 R/W R/W R/W R/W Frequency division ratio of the CPU clock (Ick) 0000: No change 0001: × 1/2 0010: × 1/4 0011: × 1/6 Others: Setting prohibited 27 26 25 24 UFC3 UFC2 UFC1 UFC0[...]

15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 44 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 11 10 9 8 S2FC3 S2FC2 S2FC1 S2FC0 0 0 0 0 R/W R/W R/W R/W Frequency division ratio of the GDTA clock (GAck) 0000: No change 0100: × 1/8 0101: × 1/12 Others: Setting prohibited 7 6 5 4 S3FC3 S3FC2 S3FC1 S3FC0 0 0 0 0[...]

15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 45 of 1658 REJ09B0261-0100 15.4.3 Frequency Displ ay Register 1 (FRQ MR1) FRQMR1 is a 32-bit reada ble regi ster that reads t he division ratio of divider 2 for the C PU clock (lck), the S uperHyway cloc k (SHck), the peripheral clock (Pck), t he DDR clock ( DDRck),the bus clock (Bck), [...]

15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 46 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 19 18 17 16 BFST3 BFST2 BFST1 BFST0 x x x 1 R R R R Frequency division ratio of the bus clock (Bck) 0101: × 1/12 0110: × 1/16 0111: × 1/18 1000: × 1/24 1001: × 1/32 1010: × 1/36 1011: × 1/48 15 14 13 12 MFST3 M[...]

15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 47 of 1658 REJ09B0261-0100 15.4.4 PLL Control Register (PLLCR) PLLCR is a 32-bit readable/writabl e register that controls the cl ock output on the CLKOUT pin. This register c an only be accessed in lo ngwords. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [...]

15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 48 of 1658 REJ09B0261-0100 15.5 Calculating the Frequency Table 15.7 sho ws the relation ship between t he division rat io of divi der 2 descri bed for freque ncy control regist er FRQCR1 a nd frequency disp lay regist er FRQMR1, an d the EXTAL input. Table 15.7 Rela tionship Betw een t[...]

15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 49 of 1658 REJ09B0261-0100 15.6 How to Change the Frequency To change t he frequenc y of the i nternal clock a nd the local bus clock (CLKOUT) with software, set frequency cont rol registers FRQCR0 and FR QCR1 accordi ng to the following proce dure. Tables 15.8 to 15.11 list the select [...]

15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 50 of 1658 REJ09B0261-0100 4. Set H 'CF000001 in FRQCR0 to enable ex ecution of the sequence that chang es the frequency. The sequence that change s the frequenc y starts. 5. The CLKOUTENB pin output changes to lo w leve l. After ten c ycles of the peripheral cl ock (Pck), an unst [...]

15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 51 of 1658 REJ09B0261-0100 Table 15.8 Selectable Combinations of Clock Frequency (CPU Clock: × 1/2, DDR Clock: × 1/4) Division ratio of divider 2 FRQMR1 read value CPU clock Ick RAM clock Uck SuperHyway clock SHck GDTA clock GAck DU clock DUck Peripheral clock Pck DDR clock DDRck Bus [...]

15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 52 of 1658 REJ09B0261-0100 Division ratio of divider 2 FRQMR1 read value CPU clock Ick RAM clock Uck SuperHyway clock SHck GDTA clock GAck DU clock DUck Peripheral clock Pck DDR clock DDRck Bus clock Bck H'122B 244B × 1/2 × 1/4 × 1/4 × 1/8 × 1/8 × 1/48 × 1/4 × 1/48 H'1[...]

15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 53 of 1658 REJ09B0261-0100 Division ratio of divider 2 FRQMR1 read value CPU clock Ick RAM clock Uck SuperHyway clock SHck GDTA clock GAck DU clock DUck Peripheral clock Pck DDR clock DDRck Bus clock Bck H'2228 2458 × 1/4 × 1/4 × 1/4 × 1/8 × 1/12 × 1/24 × 1/4 × 1/24 H'[...]

15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 54 of 1658 REJ09B0261-0100 Table 15.10 Selectable Combinations of Clock Frequency (CPU Clo ck: × 1/2, DDR Cl ock: × 1/6) Division ratio of divider 2 FRQMR1 read value CPU clock Ick RAM clock Uck SuperHyway clock SHck GDTA clock GAck DU clock DUck Peripheral clock Pck DDR clock DDRck B[...]

15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 55 of 1658 REJ09B0261-0100 Table 15.11 Selectable Combinations of Clock Frequency (CPU Clo ck: × 1/6, DDR Cl ock: × 1/6) Division ratio of divider 2 FRQMR1 read value CPU clock Ick RAM clock Uck SuperHyway clock SHck GDTA clock GAck DU clock DUck Peripheral clock Pck DDR clock DDRck B[...]

15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 56 of 1658 REJ09B0261-0100 15.7 Notes on Designing Board 1. Note on Using a Crystal Resonator Place the crystal resonator and ca pacitors clos e to the EXTAL and XTAL pins as muc h as possible. No other signal li nes should cross t he signal line of these pi ns. Induction may prevent co[...]

15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 57 of 1658 REJ09B0261-0100 CB1 RCB1 CPB1 CB2 RCB2 CPB2 CB3 RCB3 CPB3 CB4 RCB4 CPB4 CB5 RCB5 CPB5 Power supply 1 Power supply 2 SH7785 VDD-PLL1 VSS-PLL1 VDDA-PLL1 VSSA-PLL1 VDDQ-PLL1 VSSQ-PLL1 VDD-PLL2 VSS-PLL2 VDDQ-PLL2 VSSQ-PLL2 Recommended values: RCB1 = RCB2 = RCB3 = RCB4 = RCB5 = 10[...]

15. Clock Pulse Generator (CP G) Rev.1.00 Jan. 10, 2008 Page 7 58 of 1658 REJ09B0261-0100[...]

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 59 of 1658 REJ09B0261-0100 Section 16 Watchdog Timer and Reset (WDT) The watchdog timer and reset module (WDT) comprises a reset control unit and a w atchdog timer control uni t, and cont rols the powe r-on reset seq uence and inter nal reset of the L SI. The WDT is a single-cha nnel [...]

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 60 of 1658 REJ09B0261-0100 Figure 16. 1 is a block diagram of t h e WDT. PRESET MRESETOU T Watchdo g Timer and Reset module (WDT) STATUS[1:0] Internal reset request 2 WDTCNT WDTCSR WDTST Count-up si g nal Comparator Reset control circuit CPG Interrupt request Interrupt control circuit[...]

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 61 of 1658 REJ09B0261-0100 16.2 Input/Output Pins Table 16.1 shows the pin configuration of the WDT module. Table 16.1 Pin Configuration Pin name Function I/O Description PRESET Power-on reset input Input A low level input to this pin places the LSI in the power-on reset state. MRESET[...]

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 62 of 1658 REJ09B0261-0100 16.3 Register Descriptions Table 16.2 shows the registers of the WDT module. Table 16.3 show s t he register states in each operating m ode. Table 16.2 Register Configuration Register Name Abbreviation R/W P4 Address Area 7 Address Access Size Sync Clock Wat[...]

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 63 of 1658 REJ09B0261-0100 16.3.1 Watchdog Timer Stop Time Re gister (WDTST) WDTST is a 32-bit readable/writable register that specifies the time until wa tchdog timer counter WDTCNT overflows. The time until WD TCNT overflows becomes minimum when H'5A00 0001 is set, and maximum [...]

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 64 of 1658 REJ09B0261-0100 16.3.2 Watchdog Timer Control/Status Register (WDTCSR) WDTCSR is a 32 -bit readable /writable register com prising timer m ode-selecting bits and overflow flags. WDTCSR should be written to as a longwo rd unit, with H'A5 in the most significant byte. Th[...]

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 65 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 RSTS 0 R/W Reset Select Specifies the type of reset on WDTCNT overflow in watchdog timer mode. This setting is ignored in interval timer mode. 0: Power-on reset 1: Manual reset 4 WOVF 0 R/W Watchdog Timer Overflow[...]

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 66 of 1658 REJ09B0261-0100 16.3.3 Watchdog Timer Base Stop Time Register (WDTBST) WDTBST is a 32-bit readable/writable reg ister that specifies the tim e until counter WDTBCNT overflows when th e bus clock frequency has been ch anged. The time until WDTBCNT overflows becomes minimum w[...]

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 67 of 1658 REJ09B0261-0100 16.3.4 Watchdog Timer Counter (WDTCNT ) WDTCNT is a 32-bit read-onl y register comprising a 1 2-bit count er that is incremented by the WDTBCNT overflow signal. When WD TCNT overflows, a reset of the selected type is initiated in watchdog timer mode, or an i[...]

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 68 of 1658 REJ09B0261-0100 16.3.5 Watchdog Timer Base Counter (WDTBC NT) WDTBCNT is a 32-bit read- only regi ster comprisi ng an 18-bit c o unter tha t is incremente d by the peripheral cl ock (Pck). When WDTBC NT overflows, W DTCNT is i ncremented and WDTBCNT is cleared to H'000[...]

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 69 of 1658 REJ09B0261-0100 16.4 Operation 16.4.1 Reset Request Power-on reset and manual re set are available. Their request ing sources ar e described below. (1) Power-On Reset • Requesting sou rces ⎯ A low level inp ut on the PRESET pin ⎯ WDTCNT overflow when the WT/ IT bit is[...]

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 70 of 1658 REJ09B0261-0100 (2) Manual Re set • Requesting sou rces ⎯ A general e xception ot her than a use r break whil e the BL b it in SR is set t o 1. ⎯ WDTCNT overflow when both the WT/ IT and RSTS bits in WDTCSR are set to 1 • Branch addr ess: H'A000 0000 • Operat[...]

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 71 of 1658 REJ09B0261-0100 16.4.2 Using Watc hdog Timer Mo de 1. Set th e WDTCNT overflow time in WDTST. 2. Set the WT/ IT bit in WDTCSR to 1, and select the type of reset with the RSTS bit. 3. Wh en the TME bit in WDTCSR is set to 1, the WDT counter starts. 4. In w atchdog timer mode[...]

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 72 of 1658 REJ09B0261-0100 16.4.4 Time until WDT Counters Overflow The relationshi p between WDTCNT and WDTBCNT is shown in figure 1 6.2. The exampl e shown in the figure is the operation in in terval timer mode, where WDTCNT restarts counting after it has overflowe d. In watc hdog ti[...]

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 73 of 1658 REJ09B0261-0100 WDTBCNT is an 18-bit counter th at is incremented by the peripheral cloc k. If the period of peripheral cl ock Pck is represented a s tPck (ns), t he overflow t ime of WDTB CNT is expresse d as follows. 2 18 [bit] × tPck [ ns] = 0.262 × tPck [ms] WDTCNT is[...]

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 74 of 1658 REJ09B0261-0100 16.5 Status Pin Change Timing during Reset 16.5.1 Power-On Reset by PRESET Pin Since the PLL circuit is initialized when the LSI enters the power-on reset state, the PLL oscillation settling time needs to be ensured. This means that a high level must not b e[...]

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 75 of 1658 REJ09B0261-0100 (2) Power-On Re set Caused by PRESET Input during Normal Op eration It is necessary to ensure the PLL oscillation settli ng time wh en a power-on reset is initiated by low level input on the PRESET pin during normal operation. The timing of reset state indi [...]

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 76 of 1658 REJ09B0261-0100 (3) Power-On Re set Caused by PRESET Input in Sleep Mode It is necessary to ensure the PLL oscillation settling time when a power-on reset is initiated by a low level inp ut on the PRESET pin du ring sleep m ode. The timing of reset state i ndication on the [...]

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 77 of 1658 REJ09B0261-0100 16.5.2 Power-On Reset by Wa tchdog Timer Overflow The time period taken b y power-on reset o n watc hdog time r overflow (WDT reset holding time) is equal to or m o re than 40 c ycles of the pe ripheral clock (Pck). The transition time from watchdog timer ov[...]

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 78 of 1658 REJ09B0261-0100 (2) Power-On Re set Caused by Watchd og Timer Overflow in Sleep Mode The timing of indicating t he reset state or normal ope ration on t he STATUS[1:0] pins is synchronous with the per ipheral clock (Pck), and is therefore asyn chronous with the clocks input[...]

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 79 of 1658 REJ09B0261-0100 16.5.3 Manual Reset by Watc hdog Timer Overflow The time period taken by manual re set on watchdog timer overf low (WDT manual reset ho lding time) is equal to or more than 30 cy cles of the peripheral clock (Pck). The transition time from watchdog timer ove[...]

16. Watchdog Timer and Reset (WDT) Rev.1.00 Jan. 10, 2008 Page 7 80 of 1658 REJ09B0261-0100 (2) Manual Reset Cause d by Watchd og Timer Overflow in Sleep Mode The timing of indicating t he reset state or normal ope ration on t he STATUS[1:0] pins is synchronous with the per ipheral clock (Pck), and is therefore asyn chronous with the clocks input f[...]

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 81 of 1658 REJ09B0261-0100 Section 17 Power-Down Mode In power-down mod e, some of the on-chip mo dules and the CPU are stopped. This enables to reduce power consumption. 17.1 Features • Supports sleep mode, deep sleep mode, an d module st andby mode • Supports DDR2-SDRAM power supp ly backup mo[...]

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 82 of 1658 REJ09B0261-0100 Table 17.1 States of Power-Down Modes State On-Chip Peripheral Module Power- Down Mode Conditions of Transition CPG CPU On-Chip Memory DMAC GDTA Others Pin DDR2-SDRAM Releasing Methods Sleep mode SLEEP instruction executed (see section 17.4) Operate Stopped (contents of re[...]

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 83 of 1658 REJ09B0261-0100 17.2 Input/Output Pins Table 17.2 shows the pins rel ated to power-down mode. Table 17.2 Pin Configuration Pin name Function I/O Description STATUS1 Processing sta te 1 Output Indica te the operating states of this LSI STATUS0 Processing sta te 2 ST ATUS1 STATUS0 O peratin[...]

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 84 of 1658 REJ09B0261-0100 Table 17.4 Register States of CPG in E a ch Processing Mode Power-on Reset Manual Reset Sleep/ Deep Sleep Register Name Abbreviation By PRESET Pin/WDT/H-UDI By WDT By SLEEP Instruction Standby control register 0 * 1 MSTPCR0 H'0000 000 0 Retained Retained Standby contr[...]

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 85 of 1658 REJ09B0261-0100 17.3.1 Sleep Control Register (SLPCR) SLPCR is a 32-bit readable/writabl e register that can specify tr ansition to deep sleep mode. SLPCR can be accessed only in longword. This register is initialized by a power-on reset by the PRESET pin or power-on re set by WDT overflo[...]

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 86 of 1658 REJ09B0261-0100 17.3.2 Standby Control Register 0 (MSTPCR0) MSTPCR0 is a 32-bit readable/wr itable re gister that can specify whether each peripheral module operates or is stopped. M STPCR can be accessed only i n longword. This register is initialized by a power-on reset by the PRESET pi[...]

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 87 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 21, 20 MSTP[21:20] All 0 R/ W Module Stop Bit [21:20] Specify that the clock supp ly to the module of the corresponding bit is stopped [21]: SSI channel 1, [20]: SSI channel 0 0: The corresponding module operates 1: The clock to t[...]

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 88 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 9, 8 MSTP[9:8] All 0 R/W Module Stop Bit [9:8] Specify that the clock supp ly to the module of the corresponding bit is stopped [9]: TMU channels 3 to 5 [8]: TMU channels 2 to 0 0: The corresponding module operates 1: The clock to[...]

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 89 of 1658 REJ09B0261-0100 17.3.3 Standby Control Register 1 (MSTPCR1) MSTPCR1 is a 32-bit readab le/writable register that each module of H-UDI, UBC, DMAC, and GDTA operates or is stopped. MSTP CR1 can be accessed only in longword. This register is initialized by a power-on reset by the PRESET pin [...]

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 90 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 16 to 6 ⎯ All 0 R/W Reserve d These bits are always read as 0. The write value should always be 0. 5, 4 MSTP [105:104] All 0 R/W Module Stop Bit [105:104] Specifies that the clock supply to the DMAC channels of the corresponding[...]

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 91 of 1658 REJ09B0261-0100 17.3.4 Standby Display Register (MSTPM R) MSTPMR is a 32-bit readable register that indicates whether th e PCIC/display unit (DU)/DMAC/GDTA modules are i n the module st andby state. MSTPMR can be accessed onl y in longword. This register is initialized by a power-on reset[...]

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 92 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5, 4 MSTPS105 MSTPS104 All 0 R Module Stop Display Bit 105, 104 Indicates the state of clock supply to the DMAC channels of the corresponding bit MSTPS105: DMAC channels 11 to 6 MSTPS104: DMAC channels 5 to 0 0: The DMAC channels [...]

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 93 of 1658 REJ09B0261-0100 17.4 Sleep Mode 17.4.1 Transition to Sleep Mode When the SLEEP instruction is executed, the state is changed from t he program execution state to sleep mode. Al though the CPU is stop ped aft er th e instruction is executed, the conte nts of the CPU register are retained. [...]

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 94 of 1658 REJ09B0261-0100 17.5 Deep Sleep Mode 17.5.1 Transition to Deep Sleep Mode If a SLEEP instruction is e xecuted when the DSLP bit in SLPCR is set to 1, the chip switches from the pro gram executio n state to deep sl eep mode. The proce dure for a transi tion to deep slee p mode is as follow[...]

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 95 of 1658 REJ09B0261-0100 17.5.2 Releasing Deep Sleep Mode Deep sleep mode is released by means of a n interrupt (NMI , IRL, IRQ, GPIO, WDT inter val timer, or H-UDI) or a reset. In deep sleep mode, an inte rrupt request is accepted even if the BL bit in SR is set to 1. The SPC, SSR and other relat[...]

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 96 of 1658 REJ09B0261-0100 17.6 Module Standby Functions This LSI supports the module standby state, wh ere the clock supplied to on-chip mo dules is stopped. 17.6.1 Transition to Module Standby M ode By setting the MSTP bits in MSPTCR, the clock supply can be stopped to the corresponding module*. I[...]

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 97 of 1658 REJ09B0261-0100 17.7 Timing of the Changes on the STATUS Pins 17.7.1 Reset For details, see section 16.5, Status Pin Cha nge Timing during Reset. 17.7.2 Releasing Sleep Mode (1) When Sleep Mode Is Rele ased by an Interrupt Figure 17.1 shows the timin g of the changes in th e STATUS pin. I[...]

17. Power-Down Mode Rev.1.00 Jan. 10, 2008 Page 7 98 of 1658 REJ09B0261-0100[...]

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 7 99 of 1658 REJ09B0261-0100 Section 18 Timer Unit (TMU) This LSI incl udes an on-c hip 32-bi t timer uni t (TMU), whic h has six c hannels (chan nels 0 to 5) . 18.1 Features The TMU has the following features. • Auto-reload type 32-bit down-counter provided for each channel • Input capture funct[...]

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 00 of 1658 REJ09B0261-0100 Figure 18.1 show s a block diagra m of the TMU. Channel 0, 1 Channel 2 Channel 3, 4, 5 TCR TSTR0 TSTR1 Clock controller TCLK controller TCLK TUNI0 TUNI1 TUNI2 ICPI2 Pck/4 Pck/16 Pck/64 TUNI3 TUNI4 TUNI5 Prescaler T o each channel Interrupt controller Clock controller Inte[...]

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 01 of 1658 REJ09B0261-0100 18.2 Input/Output Pins Table 18.1 sho ws the TMU pi n configuratio n. Table 18.1 Pin Configuration Pin Name Abbrev. I/O Description Clock input TCLK Input External clo ck input pin for channels 0, 1 and 2 /input capture control input pin for channel 2[...]

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 02 of 1658 REJ09B0261-0100 18.3 Register Descriptions Tables 18.2 and 18.3 show t he TMU regi ster configurati on. Table 18.2 Register Configuration (1) Channel Register Name Abbrev. R/W P4 Address Area 7 Address Size Sync Clock Common to 0, 1, 2 Timer start register 0 TSTR0 R/ W H'FFD8 000 4 [...]

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 03 of 1658 REJ09B0261-0100 Table 18.3 Register Configuration (2) Channel Register Nam e Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/ Multiple Exceptions Sleep by SLEEP Instruction Module Standby Common to 0, 1, 2 Timer start register 0 TSTR 0 H'00 H'00 Retained Ret[...]

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 04 of 1658 REJ09B0261-0100 18.3.1 Timer Start Registers (TST Rn) (n = 0, 1 ) The TSTR registers are 8-bit r eadable/writable registers that specifies whether TCNT of the corresponding channel is operated or stopped. • TSTR0 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 STR0 STR1 STR2 — — — — — R/W R/[...]

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 05 of 1658 REJ09B0261-0100 • TSTR1 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 STR3 STR4 STR5 — — — — — R/W R/W R/W R R R R R BIt: Initial value: R/W: Bit Bit Name Initial Value R/W Description 7 to 3 — All 0 R Reserved These bits are always read as 0. The write value shou ld always be 0. 2 STR5 [...]

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 06 of 1658 REJ09B0261-0100 18.3.2 Timer Constant Regi sters (TCORn) (n = 0 to 5) The TCOR registers are 32-bi t readable/writ able registers. When a TCNT counte r underflows while counting do wn, the TCOR value is set in that TCNT, which con tinues counting down from the set value. 16 17 18 19 20 2[...]

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 07 of 1658 REJ09B0261-0100 18.3.4 Timer Control Registers (TCR n) (n = 0 to 5) The TCR registers are 16-bit read able/writable registers. Each TCR selects the c ount clock, specifies the edge when an external clock i s selected, an d controls i nterrupt generation when the flag indicati ng TCNT u n[...]

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 08 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 7 6 ICPE1 * 1 ICPE0 * 1 0 0 R/W R/W Input Capture Control These bits, provided in channel 2 only, specif y whether the input capture function is used, and control en abling or disabling of interrupt gener ation when the function [...]

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 09 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 R/W R/W R/W Timer Prescaler 2 to 0 These bits select the TCNT count clock. 000: Counts on Pck/4 001: Counts on Pck/16 010: Counts on Pck/64 011: Counts on Pck/256 100: Counts on Pck/1024 101, 110: Se[...]

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 10 of 1658 REJ09B0261-0100 18.4 Operation Each channel h as a 32-bit t imer counter (TCNT) and a 32-bit ti mer constant regi ster (TCOR). Each TCNT perf orms count-d own operation. The channel s have an aut o-reload funct ion that allows cyclic coun t operations, and can also perf orm external even[...]

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 11 of 1658 REJ09B0261-0100 (2) Auto-Rel oad Count Operation Figure 18.3 sh ows the TCNT auto-rel oad operation. TCNT value TCOR H'0000 0000 STR0 to STR5 UNF TCOR value is set in TCNT on underflow Time Figure 18.3 TCNT Auto-Reloa d Operation[...]

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 12 of 1658 REJ09B0261-0100 (3) TCNT Count Timing • Operating on internal cl ock Any of fi ve internal c ount cloc ks (Pck/4, Pc k/16, Pck/64, Pck/2 56, or Pck/ 1024) scaled fr om the peripheral clock can be selected as the co unt clock by m eans of the TP SC2 to TPSC0 bits in TCR. Figure 18.4 sho[...]

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 13 of 1658 REJ09B0261-0100 18.4.2 Input Capture Function Channel 2 has an input capture function. The procedure for using t he input captu re function i s as follows: 1. Use bits TPSC2 to TPSC 0 in TCR2 to set an internal cl ock as the timer operating cl ock. 2. Use bits IPCE1 a nd IPCE0 in TC R2 t[...]

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 14 of 1658 REJ09B0261-0100 18.5 Interrupts There are seven TMU in terrupt sources: underflow interrupts and the input capture inter rupt when the input capture function is used. Underflow interrupts are generate d on each of the channels, and input capture interrupts on chan nel 2 only. An underflo[...]

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 15 of 1658 REJ09B0261-0100 18.6 Usage Notes 18.6.1 Register Writes When writi ng to a TMU register, timer count ope ration must be stopped by clearing the sta rt bit (STR5 to STR0) for the relevant channel in TSTR. Note that TSTR can be written to, and th e UNF and ICPF bits in TCR can be cleared w[...]

18. Timer Unit (TMU) Rev.1.00 Jan. 10, 2008 Page 8 16 of 1658 REJ09B0261-0100[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 17 of 1658 REJ09B0261-0100 Section 19 Display Unit (DU) 19.1 Features The display unit (DU) has the fol lowing feat ures. Plane: The display surfaces normally called the fo reground, background, and cursor, are called planes in this section. Parame te rs for each plane can be set i ndepe nde ntly [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 18 of 1658 REJ09B0261-0100 CRT Scan Mode (CRT Sc an Method): Internal register settings can be used t o select from among three scan modes. • Non-interlaced mode • Interlaced s ync mode • Interlaced s ync & video mode YC → RGB Colorspace Conversion Functions: Image data sto red in Y C [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 19 of 1658 REJ09B0261-0100 Figure 19.1 sh ows a block diagra m of the display unit (DU). Pin control (output timin g adjustment) Display data format selection Priority contention determination 16 bit/pixel (no conversion) YC to RGB conversion Display timin g g eneration Color palette contention de[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 20 of 1658 REJ09B0261-0100 19.2 Input/Output Pins Table 19.1 sho ws the pin co nfiguration o f the display unit (DU). Table 19.1 Pin Conf iguration of t he Display Unit (DU) Pin Name Number I/O Function Signal Name Used in This Section DCLKIN 1 I/O Input dot clock DCLKIN DCLKOUT 1 Output Out put d[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 21 of 1658 REJ09B0261-0100 Pin Name Number I/O Function Signal Name Used in This Section DG5 1 Output Digital green 5 DB0 1 Output Digita l blue 0 DB1 1 Output Digita l blue 1 DB2 1 Output Digita l blue 2 DB3 1 Output Digita l blue 3 DB4 1 Output Digita l blue 4 DB5 1 Output Digita l blue 5 Note: [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 22 of 1658 REJ09B0261-0100 • Display mo de register (DSM R) ⎯ VSPM bit ( VSYNC pin mode) ⎯ ODPM bit (ODPM pin mode) ⎯ ODDF bit (OD DF pin mode) ⎯ DIPM bit (DISP pin m ode) ⎯ CSPM bit ( HSYNC pin mo de) ⎯ DIL bit (p olarity re versal bit of the DISP pin) ⎯ VSL bit (p olarity re vers[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 23 of 1658 REJ09B0261-0100 Table 19.2 Register Configuration Register Name Abbr. R/W P4 Address Area 7 Address Size Synchronous Clock Display control register s Display system control regis ter DSYSR R/W H'FFF80000 H'1FF80000 32 Pck Display mode register DSMR R/W H'FFF80 004 H'[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 24 of 1658 REJ09B0261-0100 Register Name Abbr. R/W P4 Address Area 7 Address Size Synchronous Clock DE signal start position register DESR R/W H'FFF80078 H'1FF80078 32 Pck DE signal width register DEWR R/W H'FFF8007C H'1FF8007C 32 Pck Display attribute registers Color palette 1[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 25 of 1658 REJ09B0261-0100 Register Name Abbr. R/W P4 Address Area 7 Address Size Synchronous Clock Plane 1 wrap-around memory width register P1WAMWR R/W H'FFF80 13C H'1FF8013 C 32 Pck Plane 1 blinking period register P1BTR R/W H'FFF80140 H'1FF80140 32 Pck Plane 1 transparent c[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 26 of 1658 REJ09B0261-0100 Register Name Abbr. R/W P4 Address Area 7 Address Size Synchronous Clock Plane 3 memory width register P3MWR R/W H'FFF80 304 H'1FF80304 32 Pck Plane 3 blend ratio register P3ALPHAR R/W H'FFF80308 H'1F F80308 32 Pck Plane 3 display size X register P3DS[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 27 of 1658 REJ09B0261-0100 Register Name Abbr. R/W P4 Address Area 7 Address Size Synchronous Clock Plane 4 display area start address 0 registe r P4DSA0R R/W H'FFF80420 H'1FF80420 32 Pck Plane 4 display area start address 1 registe r P4DSA1R R/W H'FFF80424 H'1FF80424 32 Pck Pl[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 28 of 1658 REJ09B0261-0100 Register Name Abbr. R/W P4 Address Area 7 Address Size Synchronous Clock Plane 5 wrap-around memory width register P5WAMWR R/W H'FFF80 53C H'1FF8053 C 32 Pck Plane 5 blinking period register P5BTR R/W H'FFF80540 H'1FF80540 32 Pck Plane 5 transparent c[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 29 of 1658 REJ09B0261-0100 Register Name Abbr. R/W P4 Address Area 7 Address Size Synchronous Clock Color palette registers Color palette 1 register 000 CP1_000R R/W H'F FF81000 H'1FF81000 32 Pck ⎯ Color palette 1 register 255 CP1_255R R/W H'F FF813FC H'1FF813FC 32 Pck Color [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 30 of 1658 REJ09B0261-0100 Table 19.3 Status of Re gisters in Each Processing Mode Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manual Reset by WDT Sleep by Sleep Instruction Module Standby Deep Sleep Bits with Internal Update Function Display control register s Display system cont[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 31 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manual Reset by WDT Sleep by Sleep Instruction Module Standby Deep Sleep Bits with Internal Update Function Display timing generation registers Horizontal display start position register HDSR Undefined Retained[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 32 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manual Reset by WDT Sleep by Sleep Instruction Module Standby Deep Sleep Bits with Internal Update Function Display attribute registers Color palette 1 transparent color register CP1TR H'00000 000 Retained[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 33 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manual Reset by WDT Sleep by Sleep Instruction Module Standby Deep Sleep Bits with Internal Update Function Plane 1 display position Y register P1DPYR Undefined Retained Retained Retained Retained All bits Plan[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 34 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manual Reset by WDT Sleep by Sleep Instruction Module Standby Deep Sleep Bits with Internal Update Function Plane 2 display size X register P2DSXR Undefined Retained Retained Retained Retained All bits Plane 2 [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 35 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manual Reset by WDT Sleep by Sleep Instruction Module Standby Deep Sleep Bits with Internal Update Function Plane 3 mode register P3MR H'00000000 Retained Retained Retained Retained All bits Plane 3 memory[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 36 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manual Reset by WDT Sleep by Sleep Instruction Module Standby Deep Sleep Bits with Internal Update Function Plane 3 transparent color 2 register P3TC2R Undefined Retained Retained Retained Retained All bits Pla[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 37 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manual Reset by WDT Sleep by Sleep Instruction Module Standby Deep Sleep Bits with Internal Update Function Plane 4 blinking period register P4BTR H'00000101 Retained Retained Retained Retained All bits Pl[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 38 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manual Reset by WDT Sleep by Sleep Instruction Module Standby Deep Sleep Bits with Internal Update Function Plane 5 wrap- around start position register P5WASPR Undefined Retained Retained Retained Retained All[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 39 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manual Reset by WDT Sleep by Sleep Instruction Module Standby Deep Sleep Bits with Internal Update Function Plane 6 display area start address 1 register P6DSA1R Undefined Retained Retained Retained Retained Al[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 40 of 1658 REJ09B0261-0100 Register Name Abbr. Power-On Reset by PRESET Pin/ WDT/ H-UDI Manual Reset by WDT Sleep by Sleep Instruction Module Standby Deep Sleep Bits with Internal Update Function Color palette 3 register 000 CP3_000R Undefined Retained Retained Retained Retained All bits ⎯ Color[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 41 of 1658 REJ09B0261-0100 19.3.1 Display Unit System Contro l Register The display unit system c ontrol re gister (DS YSR) sets the system operati on for the display unit (DU). R/W: Internal update: R/W: Internal update: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit: Initial value: R/W R R [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 42 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 16 IUPD 0 R/W Yes Internal Updating Disable When DRES = 1, internal update is performed regardless of this bit. For details of internal update, see (2) Internal Update in section 19.3, Regist er Descriptions. 0: [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 43 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 9 DRES 1 R/W None Display Reset 8 DEN 0 R/W Yes Display Enable 00: Starts display synchronization operation. In the case of a register not yet set, unexpected operation may oc cur; hence DRES should be set to 0 a[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 44 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 7, 6 TVM 10 R/W None TV Synchroniz ation Mode 00: Master mode HSYNC, VSYNC, CSYNC are output 01: Synchronization method switchin g mode When switching from TV sync mode to master mode, or from master mode to TV s[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 45 of 1658 REJ09B0261-0100 19.3.2 Display Mode Register (DSMR) The display m ode register (DSMR) set s the displa y operation of the display uni t. R/W: Internal update: R/W: Internal update: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit: Initial value: R/W R/W R/W R/W R R R R R/W R/W R/W R/[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 46 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 24 CSPM 0 R/W * CSYNC Pin Mode Settings in DSYSR are given priority over settings in this register. 0: CSYNC signal is output to the HSYNC pin 1: HSYNC signal is output to the HSYNC pin 23 to 20 ⎯ All 0 R ⎯ R[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 47 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 14, 13 CDEM 00 R/W * CDE Output Mode 00: CDE signal is output without change 01: CDE signal is output without change 10: Low level output outside of display interval (interval when DISP signal is inactive) 11: Hi[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 48 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 7, 6 CSY 00 R/W None CSYNC Mode For details of CSYNC waveform, refer to section 19.5.2, CSYNC. 00: The relation among VSYNC, HSYNC, and CSYNC is as follows. VSYNC HSYNC CSYNC Low level Low level High level Low le[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 49 of 1658 REJ09B0261-0100 19.3.3 Display Stat us Register (DS SR) The display st atus regist er (DSSR) is a register used to read, f rom outside, the internal state of the display unit (DU). R/W: Internal update: R/W: Internal update: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit: Initial v[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 50 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 20 DFB5 0 R None Display Frame Buffer 5 Flag 0: The address indicated by the pla ne 5 display area start address 0 register (P5DSA0R) in plane 5 is being used as the display are a start address 1: The address ind[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 51 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 16 DFB1 0 R None Display Frame Buffer 1 Flag 0: The address indicated by the pla ne 1 display area start address 0 register (P1DSA0R) in plane 1 is being used as the display are a start address 1: The address ind[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 52 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 13, 12 ⎯ All 0 R ⎯ Reserved These bits are always read as 0. The write value should always be 0. 11 VBK 0 R None Vertical Blanking Flag 0: Indicates the interval to the next display end after clearing to 0 th[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 53 of 1658 REJ09B0261-0100 19.3.4 Display Unit Status Registe r Clear Regi ster (DSRCR) The display unit status register cl ear register (DSRCR) is a regist er wh ich clears the various flags in DSSR. R/W: Internal update: R/W: Internal update: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit: [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 54 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 9 RICL Undefined W None Vertical Blanking Flag Clear 0: The RINT flag in DSSR is not changed. 1: The RINT flag in DSSR is cleared to 0. 8 HBCL Undefi ned W None Vertical Blanking Flag Clear 0: The HBK flag in DSS[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 55 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 31 to 16 ⎯ All 0 R ⎯ Reserved These bits are always read as 0. The write value should always be 0. 15 TVE 0 R/W None TV Synchronous Sign al Error Interrupt Enable 0: Disables interrupt by the TVR flag in DSSR[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 56 of 1658 REJ09B0261-0100 The followin g are condit ions, base d on DSSR and this re gister, for i ssuing a n interrupt t o the CPU from the displa y unit (DU). Conditions for issuing an interrupt = a + b + c + d + e • a = TVR · TVE • b = FRM · FRE • c = VBK · VBE • d = RINT · RIE •[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 57 of 1658 REJ09B0261-0100 19.3.6 Color Palette Co ntrol Register (CPC R) The color palette control register (CPCR) is a regi ster which enables switchi ng of the col or palette. For information on color palette switching, refer to section 19.4.8, Color P alettes. R/W: Internal update: R/W: Intern[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 58 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 18 CP3CE 0 R/W Yes Color Palette 3 Change Enable 0: Switching of color palette 3 is not performed. 1: Switching of color palette 3 is performed. Switching is performed when the DRES bit in DSYSR is changed from 1[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 59 of 1658 REJ09B0261-0100 19.3.7 Display Plane Priority Re gister (DPPR) The display plane pri o rity regist er (DPPR) sets the priori ty order for combining planes and turns the display on and of f. R/W: Internal update: R/W: Internal update: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit: [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 60 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 19 DPE5 0 R/W Yes Display Plane Priority 5 Enable 18 to 16 DPS5 100 R/W Yes Display Plane Priority 5 Select 1000: Selects and displays plane 1 in prior ity 5 1001: Selects and displays plane 2 in prior ity 5 1010[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 61 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 11 DPE3 0 R/W Yes Display Plane Priority 3 Enable 10 to 8 DPS3 010 R/W Yes Display Plane Priority 3 Select 1000: Selects and displays plane 1 in prior ity 3 1001: Selects and displays plane 2 in prior ity 3 1010:[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 62 of 1658 REJ09B0261-0100 19.3.8 Display Unit Extensional Function Enable Register (DEFR) The display unit extensio nal function e nable register (DEFR) e nables exten sion functio ns. DEFR should be set during display reset (the D RES bit and DEN bit in DSYSR should be set to 1 and to 0 res pect[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 63 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 4 ABRE 0 R/W None Alpha Blend R atio Enable 0: The 31 to 24 bits in the color palette registers 1 to 4 and the PnBRSL bits in the plane n blend ratio registers (PnALPHAR) are disabled. The alpha blend ratio is se[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 64 of 1658 REJ09B0261-0100 19.3.9 Horizontal Di splay Start Re gister (HDSR) The horizontal display start register (HDSR) sets the horizontal display sta rt position. T he value is retained during power-on reset and manu al reset. R/W: Internal update: R/W: Internal update: 16 17 18 19 20 21 22 23[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 65 of 1658 REJ09B0261-0100 19.3.10 Horizontal Display End Register (H DER) The horizontal display end register ( HDER) sets t he horizontal display end po sition. The value is retained during powe r-on reset and ma nual reset. R/W: Internal update: R/W: Internal update: 16 17 18 19 20 21 22 23 24 [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 66 of 1658 REJ09B0261-0100 19.3.11 Vertical Displ ay Start Register (VDS R) The vertical display start regi ster (VDSR) sets the vertical display sta rt position. The value is retained during power-on reset and manu al reset. R/W: Internal update: R/W: Internal update: 16 17 18 19 20 21 22 23 24 2[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 67 of 1658 REJ09B0261-0100 19.3.12 Vertical Displ ay End Register (VDER) The vertical display end register (VDER) set s the vertical displa y end position. The value is retained during powe r-on reset and ma nual reset. R/W: Internal update: R/W: Internal update: 16 17 18 19 20 21 22 23 24 25 26 2[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 68 of 1658 REJ09B0261-0100 19.3.13 Horizontal Cycle Register (HCR) The horizontal cycle register (HCR) sets the horizontal scan cycle.(period). Th e value is retained during powe r-on reset and manual reset. R/W: Internal update: R/W: Internal update: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 3[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 69 of 1658 REJ09B0261-0100 19.3.14 Horizontal Sync Width Re gister (HSWR) The horizontal sync width register (HS WR) sets the low -level pulse wi dth of the horizontal sync signal. The val ue is retained during power -on reset and ma nual reset. R/W: Internal update: R/W: Internal update: 16 17 18[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 70 of 1658 REJ09B0261-0100 19.3.15 Vertical Cycle Register (VCR) The vertical cycle register (VCR) sets the vertical scan interval. The va lue is retained during power-on reset and manual reset. R/W: Internal update: R/W: Internal update: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit: Initia[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 71 of 1658 REJ09B0261-0100 19.3.16 Vertical Sync Point Register (VSPR) The vertical s ync point re gister (VSPR) sets the star t position of the vertical sync signal in raster line units. The value is retain ed during power-on reset and manual reset. R/W: Internal update: R/W: Internal update: 16 [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 72 of 1658 REJ09B0261-0100 19.3.17 Equal Pulse Width Re gister (EQWR) The equal puls e width regi ster (EQWR ) sets the low -level pulse width of a pulse equi valent to the CSYNC signal. The value is retained duri ng power-on reset and ma nual reset. R/W: Internal update: R/W: Internal update: 16 [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 73 of 1658 REJ09B0261-0100 19.3.18 Separation Width Re gister (SPWR) The separation width regi ster (SPWR) sets the low -level pulse width of the se paration pulse for the CSYNC sig nal. The value is retained during pow er-on reset and manual reset. R/W: Internal update: R/W: Internal update: 16 1[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 74 of 1658 REJ09B0261-0100 19.3.19 CLAMP Signal Start Register (CL AMPSR) The CLAMP s ignal start re gister (CLAMPSR) sets the risi ng edge position of t he CLAMP signal . For timing charts for the CLAMP sign al and the DE signal, refer to section 19.5.6, CLA MP Signal and DE Signal . The value is[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 75 of 1658 REJ09B0261-0100 19.3.20 CLAMP Signal Width Register (CLAM PWR) The CLAMP signal width register (CLA MPWR) sets the high-level width of the CLAMP signal. The value is retained during power-on reset an d manual reset. R/W: Internal update: R/W: Internal update: Bit: Initial value: Bit: In[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 76 of 1658 REJ09B0261-0100 19.3.21 DE Signal Start Regis ter (DESR) The DE signal start re gister (DESR) sets the risi ng edge position of the DE signal. The value is retained during power-on reset and manu al reset. R/W: Internal update: R/W: Internal update: 16 17 18 19 20 21 22 23 24 25 26 27 2[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 77 of 1658 REJ09B0261-0100 19.3.22 DE Signal Width Re gister (DEW R) The DE signal width regi ster (DEWR) set s the high -level width of the DE s ignal. The val ue is retained during powe r-on reset and ma nual reset. R/W: Internal update: R/W: Internal update: 16 17 18 19 20 21 22 23 24 25 26 27 [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 78 of 1658 REJ09B0261-0100 19.3.23 Color Palette 1 Transparen t Color Register (CP1 TR) The color palette 1 transp arent color register (C P1TR) specifies the t ransparent color for c o lor palette 1. R/W: Internal update: R/W: Internal update: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit: [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 79 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 12 CP1IC 0 R/W Yes Color Palette 1 Index C 0: The color with index C in color palette 1 is not set to the transparent color. 1: The color with index C in color palette 1 is set to the transparent color. 11 CP1IB [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 80 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 5 CP1I5 0 R/W Yes Color Palette 1 Index 5 0: The color with index 5 in color palette 1 is not set to the transparent color. 1: The color with index 5 in color palette 1 is set to the transparent color. 4 CP1I4 0 [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 81 of 1658 REJ09B0261-0100 19.3.24 Color Palette 2 Transparen t Color Register (CP2 TR) The color palette 2 transp arent color register (C P2TR) specifies the transpa rent color of color palette 2. R/W: Internal update: R/W: Internal update: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit: Ini[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 82 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 12 CP2IC 0 R/W Yes Color Palette 2 Index C 0: The color with index C in color palette 2 is not set to the transparent color. 1: The color with index C in color palette 2 is set to the transparent color. 11 CP2IB [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 83 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 5 CP2I5 0 R/W Yes Color Palette 2 Index 5 0: The color with index 5 in color palette 2 is not set to the transparent color. 1: The color with index 5 in color palette 2 is set to the transparent color. 4 CP2I4 0 [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 84 of 1658 REJ09B0261-0100 19.3.25 Color Palette 3 Transparen t Color Register (CP3 TR) The color palette 3 transp arent color register (C P3TR) specifies the transpa rent color of color palette 3. R/W: Internal update: R/W: Internal update: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit: Ini[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 85 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 12 CP3IC 0 R/W Yes Color Palette 3 Index C 0: The color with index C in color palette 3 is not set to the transparent color. 1: The color with index C in color palette 3 is set to the transparent color. 11 CP3IB [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 86 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 5 CP3I5 0 R/W Yes Color Palette 3 Index 5 0: The color with index 5 in color palette 3 is not set to the transparent color. 1: The color with index 5 in color palette 3 is set to the transparent color. 4 CP3I4 0 [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 87 of 1658 REJ09B0261-0100 19.3.26 Color Palette 4 Transparen t Color Register (CP4 TR) The color palette 4 transp arent color register (C P4TR) specifies the transpa rent color of color palette 4. R/W: Internal update: R/W: Internal update: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit: Ini[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 88 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 12 CP4IC 0 R/W Yes Color Palette 4 Index C 0: The color with index C in color palette 4 is not set to the transparent color. 1: The color with index C in color palette 4 is set to the transparent color. 11 CP4IB [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 89 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 5 CP4I5 0 R/W Yes Color Palette 4 Index 5 0: The color with index 5 in color palette 4 is not set to the transparent color. 1: The color with index 5 in color palette 4 is set to the transparent color. 4 CP4I4 0 [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 90 of 1658 REJ09B0261-0100 19.3.27 Display Off Mode Output Register (DOOR) The display off mode output regist er (DOOR) sets the displ ay data output whe n the displa y is turned off. The valu e is retained during power-on reset and manual reset. R/W: Internal update: R/W: Internal update: 16 17 1[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 91 of 1658 REJ09B0261-0100 19.3.28 Color Detection Re gister (CDER) The color detection register (CDER) sets the color for color detection. When the display output data match the settin gs of this register, high level is output from the CDE pin. For i nformation on the ou tput color data format, p[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 92 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 1, 0 ⎯ All 0 R ⎯ Reserved These bits are always read as 0. The write value should always be 0. 19.3.29 Background P lane Out put Register (BPOR) The background plane output register (BPOR) sets th e color for[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 93 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 9, 8 ⎯ All 0 R ⎯ Reserved These bits are always read as 0. The write value should always be 0. 7 to 2 BPOB Undefined R/W Yes Background Plane Output Blue The blue-color display data to be output whe n there i[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 94 of 1658 REJ09B0261-0100 19.3.30 Raster Interrupt Offset Register (RINTOFSR) The raster interrupt of fset register (R INTOFSR) se ts t he raster offset value for raster interrupts. The value is retained during power-on reset an d manual reset. R/W: Internal update: R/W: Internal update: 16 17 18[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 95 of 1658 REJ09B0261-0100 19.3.31 Plane n Mode Register (PnMR) (n = 1 to 6) The plane n mode re gisters (PnMR, n = 1 to 6) set the dis p lay operatio n for plane n. R/W: Internal update: R/W: Internal update: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit: Initial value: R/W R/W R R R/W R R [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 96 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 14 to 12 PnSPIM 0 R/W Yes Plane n Super Impose Mode 000: Transparent color processing is p erformed for plane n. When plane n is in the transparent color, the lower plane is displayed. 001: Blending of plane n an[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 97 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 9, 8 PnCPSL 0 R/W Yes Plan e n Color Palette Select When the PnDDF bit is set to 8 bits/pixel, specifies the color palette to be used. 00: Selects the color palette 1 01: Selects the color palette 2 10: Selects t[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 98 of 1658 REJ09B0261-0100 19.3.32 Plane n Memory Width Register (PnMWR) (n = 1 to 6) The plane n m emory width regist ers (PnMWR , n = 1 to 6) s et the memory width f or plane n. The value is retained during power-on reset an d manual reset. R/W: Internal update: R/W: Internal update: 16 17 18 19[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 8 99 of 1658 REJ09B0261-0100 19.3.33 Plane n Blending Ratio Register (PnALPHAR) (n = 1 to 6) The plane n bl ending ratio registers (PnALPHAR , n = 1 to 6) set the blen d ratios an d blend rat io selection for plane n. R/W: Internal update: R/W: Internal update: 16 17 18 19 20 21 22 23 24 25 26 27 28[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 00 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description Plane n Blending Ratio Select This bit is valid when the following two conditions are satisfied. • When the PnSPIM bit in PnMR specifies blending. • When the ABRE bit in DEFR is set to 1. 00: The PnALPHA bits[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 01 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 7 to 0 PnALPHA Undefined R/W Yes Plane n Blending Rati o The alpha value ( α ) which is the bl end ratio for plane n should be set. Blending result = ( α × plane n + (H'100 − α ) × lower plane)/ H&apo[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 02 of 1658 REJ09B0261-0100 19.3.35 Plane n Display Size Y Register (PnDSYR) (n = 1 to 6) The plane n display size Y registers (PnDSYR, n = 1 to 6) set the display size in the vertical direction for plane n. The value is retained duri ng power-on reset and manual reset. R/W: Internal update: R/W: I[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 03 of 1658 REJ09B0261-0100 19.3.36 Plane n Display Position X Register (PnDPXR) (n = 1 to 6) The plane n di splay posi tion X regi sters (PnDP XR, n = 1 to 6) set the horizontal start positions on the display monito r for plane n. The value is retained during pow er-on reset and manual reset. R/W:[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 04 of 1658 REJ09B0261-0100 19.3.37 Plane n Display Positio n Y Register (PnDPY R) (n = 1 to 6) The plane n display position Y registers (PnDPYR, n = 1 to 6) set the vertical start pos ition on the display mo nitor of pl ane n. The value is retai ned during po wer-on reset a nd manual rese t. R/W: [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 05 of 1658 REJ09B0261-0100 19.3.38 Plane n Display Area Start Address 0 Register (Pn DSA0R) (n = 1 to 6) The plane n display area start addr ess 0 registers (PnDSA0R, n = 1 to 6) set the memory area in frame buffer 0 for plane n. The value is retai n ed during po wer-on reset and ma nual reset. R/[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 06 of 1658 REJ09B0261-0100 19.3.39 Plane n Display Area Start Address 1 Register (Pn DSA1R) (n = 1 to 6) The plane n display area start addr ess 1 registers (PnDSA1R, n = 1 to 6) set the memory area in frame buffer 1 for plane n. The value is retai n ed during po wer-on reset and ma nual reset. R/[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 07 of 1658 REJ09B0261-0100 19.3.40 Plane n Start Positi on X Register (PnSP XR) (n = 1 to 6) The plane n start position X registers (PnSPXR, n = 1 to 6) set the horizontal start position of plane n in me mory. The valu e is retained du ring power- on reset and man ual reset. R/W: Internal update: [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 08 of 1658 REJ09B0261-0100 19.3.41 Plane n Start Positi on Y Register (PnSP YR) (n = 1 to 6) The plane n start position Y registers (PnSPYR, n = 1 to 6) set the vertical start position of plane n in memory. The value is retained during power-on reset and manual reset. R/W: Internal update: R/W: In[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 09 of 1658 REJ09B0261-0100 19.3.42 Plane n Wrap Around Start Position Re gister (PnWASPR) (n = 1 to 6) The plane n wrap-around star t pos ition re gisters (PnW ASPR, n = 1 t o 6) set t he Y direction st art position of one wrap-around area of pl ane n. The value is ret ained during powe r-on reset[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 10 of 1658 REJ09B0261-0100 19.3.43 Plane n Wrap Around Mem o ry Width Register (Pn WAMWR) (n = 1 to 6) The plane n w rap-arou nd memory wi dth registers (PnWA MWR, n = 1 t o 6) set the wrap-aro und Y-direction me mory width for plane n. The v alue is retaine d during power-on reset and manual rese[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 11 of 1658 REJ09B0261-0100 19.3.44 Plane n Blinking Time Regis ter (PnBTR) (n = 1 to 6) The plane n bl inking time regi sters (PnBTR, n = 1 to 6) set the displa y interval length fo r plane n. When the PnBM bit in PnMR is set to the auto disp lay change mode (blinking mode), by setting, in this re[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 12 of 1658 REJ09B0261-0100 19.3.45 Plane n Transparent Color 1 Register (PnTC1R) (n = 1 to 6) The plane n transparent col o r 1 regi sters (PnTC1R, n = 1 to 6) set a transparent color for plane n, in 8 bits/pixel data format. The valu e is re tained during power-on reset and manual reset. R/W: Int[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 13 of 1658 REJ09B0261-0100 19.3.46 Plane n Transparent Color 2 Register (PnTC2R) (n = 1 to 6) The plane n transparent col o r 2 regi sters (PnTC2R, n = 1 to 6) set a transparent color for plane n in the 16 bits/pixel, ARGB data fo rmat. The value is retained during power-on reset and man ual reset[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 14 of 1658 REJ09B0261-0100 19.3.47 Plane n Memory Length Register (PnMLR) (n = 1 to 6) The plane n memory length registers (PnM LR, n = 1 to 6) set th e memory length (Y-direction memory area) for plane n. R/W: Internal update: R/W: Internal update: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 15 of 1658 REJ09B0261-0100 19.3.48 Color Palett e 1 Register 000 to 255 (CP1_0 00R to CP1_255R ) The color palette 1 registers 000 to 255 (CP1_ 000R to CP1_255R) ar e a group of 256 registers which set si x bits for eac h of the RGB components of a color, and are used as a c olor palette capable o[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 16 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 9, 8 ⎯ All 0 R ⎯ Reserved These bits are always read as 0. The write value should always be 0. 7 to 2 CP1_000B to CP1_255B Undefined R/W Yes Color Palette 1_000 to 255 Bl ue Blue-color data of color palette 1[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 17 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 31 to 24 CP2_000A to CP2_255A Undefined R/W Yes Color Palette 2_000 to 255 Bl ending Ratio To enable this bit, the ABRE bit in DEFR should be set to 1. In the initial state, this bit is not enabled. When the PnBR[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 18 of 1658 REJ09B0261-0100 19.3.50 Color Palett e 3 Register 000 to 255 (CP3_0 00R to CP3_255R ) The color palette 3 registers 000 to 255 (CP3_ 000R to CP3_255R) ar e a group of 256 registers which set si x bits for eac h of the RGB components of a color, a nd are used as a c olor palett e capable[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 19 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 9, 8 ⎯ All 0 R ⎯ Reserved These bits are always read as 0. The write value should always be 0. 7 to 2 CP3_000B to CP3_255B Undefined R/W Yes Color Palette 3_000 to 255 Bl ue Blue-color data of color palette 3[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 20 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 31 to 24 CP4_000A to CP4_255A Undefined R/W Yes Color Palette 4_000 to 255 Bl ending Ratio To enable this bit, the ABRE bit in DEFR should be set to 1. In the initial state, this bit is not enabled. When the PnBR[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 21 of 1658 REJ09B0261-0100 19.3.52 External Sync hronization Control Re gister (ESCR) The external synchronization control regi ster (ESCR) controls the dot clock. R/W: Internal update: R/W: Internal update: 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit: Initial value: R/W R R R R/W R R R R [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 22 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 4 to 0 FRQSEL 0 R/W None Frequency Select To enable this bit, the DCKE bit in DEFR should be set to 1. In the initial state, bit 4 is fixed at 0, and the frequency division ratio is up to 16. 00000: Frequency div[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 23 of 1658 REJ09B0261-0100 19.3.53 Output Signal Timing Adju stment Register (OTAR) The output signal timing adjustme nt register (OTAR) selects the timing for the output signal. For information on adjustment timing, refer to secti on 19.5.5, Output Sign al Timing Adj u stment. R/W: Internal updat[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 24 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 30 to 28 DEA 0 R/W None DE Output Timing Adjustment 000: Adjustment of output timing is not performed. The DE signal is output at the rising edge of the dot clock, with the reference timing. 001: The DE signal is[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 25 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 26 to 24 CLAMPA 0 R/W None CLAMP Output Timing Adjust ment 000: Adjustment of output timing is not performed. The CLAMP signal is output at the rising edge of the dot clock, with the reference timing. 001: The CL[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 26 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 22 to 20 DRGBA 0 R/W None Digital IR GV Output Timing Adjustment 000: Adjustment of output timing is not performed. The RGB signal is output at the rising edge of the dot clock, with the reference timing. 001: Th[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 27 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 10 to 8 CDEA 0 R/W None CDE Output Timing Adjustment 000: Adjustment of output timing is not performed. The CDE signal is output at the rising edge of the dot clock, with the reference timing. 001: The CDE signal[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 28 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 6 to 4 DISPA 0 R/W None DISP Output Timing Adjustment 000: Adjustment of output timing is not performed. The DISP signal is output at the rising edge of the dot clock, with the reference timing. 001: The DISP sig[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 29 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Internal Update Description 2 to 0 SYNCA 0 R/W None SYNC * Output Timing Adjustment 000: Adjustment of output timing is not performed. The SYNC * signal is output at the rising edge of the dot clock, with the reference timing. 001: The SYNC[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 30 of 1658 REJ09B0261-0100 19.4 Operation 19.4.1 Configuration of O utput Screen The display unit (DU) e xecutes wind ow displays with up to a maximum of six win dow layers. Each of these windows is cal led a "plane", a n d the orde r of stacking of the plane s can be set arbitrarily. Fo[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 31 of 1658 REJ09B0261-0100 Table 19.4 Displa y Functions of Planes Display Data Format Display On/Off 8 bits/ pixel 16 bits/ pixel ARGB YC Superpositi oning Blink -ing Size Scroll -ing Wrap- around Plane 1 O O * 1 O O O * 2 α blending/ transparent color/ EOR operation O X, Y arbitrary O O Plane 2[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 32 of 1658 REJ09B0261-0100 F rame buff er 2 A double-b uffer function is used to s witch the frame buff er between drawing side and display side The superpositioning order can be specified arbitrarily . Background color can be specified. F rame buff er 1 F rame buff er 2 F rame buff er 1 Output pl[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 33 of 1658 REJ09B0261-0100 19.4.2 Display On/Off All plane di splay ca n be turned on and off usi ng the DEN bit in DSY SR. When t h e DEN bit is 0, the display data set in DOO R is displayed. Display is turned on and off for planes 1 to 6 usi ng DPPR. Under the followi ng display conditi ons, dis[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 34 of 1658 REJ09B0261-0100 19.4.3 Plane Parameter For each plane, a display area start position, memory wid th, display start position, and d isplay size are set using registers. The followings are the schematic diagra m of start positions and sizes related to planes and the registers used f or se[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 35 of 1658 REJ09B0261-0100 Table 19.6 Memory Parameter/ Mo ni tor Parameter Settin g Registers No. Names Used in the Figure Setting Registers Description 1 MWX (Plane memory width) PnMWR The plane X-direction memory width is set between 16 and 4096 pixe ls, in 16 pixel units. 2 DSA (Display area s[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 36 of 1658 REJ09B0261-0100 19.4.4 Memory Allocation A display start address for the di splay screen can be set indi vidu ally for each plane. Leading addresses for the memory areas us ed are set in each of t he display area start address regi sters. In the display unit (DU), the displa y area star[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 37 of 1658 REJ09B0261-0100 19.4.5 Input Display Da ta Format The following format is u sed for input color data used in display. • 8 bit/pixel A color palette index is u sed. The color palette is used to conv ert and display image data into RGB data with 6 bits for each RGB color (RGB666). The a[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 38 of 1658 REJ09B0261-0100 • 16 bit/pixel: ARGB The ARGB le vels are rep resented usi ng A:1, R :5, G:5, B: 5 bits (ARGB 555). In addition to t he RGB values, an alpha value is set. Blending control using the A value is valid when the PnSPIM bit in PnMR i s set to pe rform blending; whe n A = 1,[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 39 of 1658 REJ09B0261-0100 • UYVY format A+3 A+2 A+1 A A A+1 A+2 A+3 31 23 15 7 0 31 23 15 7 0 Address A Y1 V0 Y0 U0 Address A U0 Y0 V0 Y1 Address A+4 Y3 V2 Y2 U2 Address A+4 U2 Y2 V2 Y3 Address A+8 Y5 V4 Y4 U4 Address A+8 U4 Y4 V4 Y5 Little endian Big endian • YUYV format A+3 A+2 A+1 A A A+1 [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 40 of 1658 REJ09B0261-0100 19.4.6 Output Data Format When outputting digital RG B data from the display unit (DU), the d isplay data format is expanded into the RGB 666 format before output. The format at the time of output is as indicated in the following table. Table 19.8 Output Data Format Pin [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 41 of 1658 REJ09B0261-0100 Endian conve rsion in each of the u nits indica ted below is shown i n figure 1 9.4. B0 B1 B2 B3 B4 B5 B6 B7 A 63 0 B8 B9 B10 B11 B12 B13 B14 B15 A + 8 Data B7 B6 B5 B4 B3 B2 B1 B0 63 0 B15 B14 B12 B11 B10 B9 B8 127 64 W0 W1 W2 W3 63 0 W4 W5 W6 W7 63 0 127 W3 W2 W1 W0 W7[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 42 of 1658 REJ09B0261-0100 19.4.8 Color Palettes 8 bits/pixel data employs color palettes. Four co lor palettes can be used; these are called color palette 1, color palette 2 , color palette 3, and color palette 4. The color palette used in each plane can be set to any among c olor palette 1, colo[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 43 of 1658 REJ09B0261-0100 19.4.9 Superposition ing of Planes For each plane, three types of combined s uperposit ioning are p ossible: α blending, transparent colors, and EOR operations. By settin g the PnSPIM bits in PnMR, the superpositioned disp lay type can be selected. However, α bl ending[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 44 of 1658 REJ09B0261-0100 Table 19.11 RGB888 Bit Configurat ion in Each Display Data Format Data Format R (8 bits) G (8 bits) B (8 bits) 8 bits/pixel R (6 bits) 0 0 G (6 bits) 0 0 B (6 bits) 0 0 16 bits/pixel R (5 bits) 0 0 0 G (6 bits) 0 0 B (5 bits) 0 0 0 ARGB R (5 bits) 0 0 0 G (5 bits) 0 0 0 [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 45 of 1658 REJ09B0261-0100 When the PnDDF bit in PnMR is set to ARGB, and moreover th e PnSPIM bit in PnMR is set to perform ble nding, α blending is performed a ccording to the A value of the i nput ARGB data format. Transparent Colors: For each plane, tra n spar ent color pr ocessing can b e pe[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 46 of 1658 REJ09B0261-0100 Table 19.12 Transparent Colo r Specification Registers Data Format Transparent Color Specification Bit Color Palette Select Bit Transparent Color Specification Register ⎯ (PnMR) /PnTC (PnMR) /PnCPSL ⎯ 0 ⎯ PnTC1R 1 00 CP1TR 1 01 CP2TR 1 10 CP3TR 8 bits/pixel 1 11 CP[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 47 of 1658 REJ09B0261-0100 19.4.10 Display Conte ntion Color Palette Contention: Whe n performing α blending and EOR operat ions, if the same col or palette is selected for bot h planes with the input display data format at 8 bi ts/pixel, color palette contention ma y occur. This is because co nt[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 48 of 1658 REJ09B0261-0100 P1 P1 P2 P3 ΔΔΔ X X P2 ΔΔ X Δ X P3 Δ X ΔΔ X P1 P1 P1 P1 P2 P2 P3 BPOR P1 P1 P1 α P3 P1 P2 ⊕ P3 P2 ⊕ P3 P2 P3 BPOR P1 α P2 P1 α P2 P1 P1 P2 P3 BPOR P1 α P2 P1 α P2 P1 α P3 P1 P2 P2 P3 BPOR P1(P2 ⊕ P3) P1 α P2 P1 α P3 P1 P2 ⊕ P3 P2 P3 BPOR Color pa[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 49 of 1658 REJ09B0261-0100 Plane Priority Order: The display priority order fo r planes is set using DPPR; if one plane is set in two or more places in the priority order, the place with highe st priority is selected. For example, if the setting in DPPR is H'00CBD888, then the results of the [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 50 of 1658 REJ09B0261-0100 19.4.12 Scroll Display By setting display area and display screen sizes and start positio ns independently for each plane, smooth scroll processing can be pe rformed independently for each plane. The display ca n be scrolled by cyclicall y setting the pla ne n display st[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 51 of 1658 REJ09B0261-0100 19.4.13 Wraparoun d Display In addition to display scrolling, wrap-around display, which can be used in spherical scrolling , is possible for each plane. Whe n en abling wra p-around dis play, the Pn WAE bit in P nMR is set. A s a result of changing the plane n display s[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 52 of 1658 REJ09B0261-0100 19.4.14 Upper-Left Overflow Displ ay For each plane, a display start position i n memory (PnSPXR, PnSPYR ) and dis play size (PnDSXR, P nDSYR) ca n be set arbitra rily, so that by combining a nd using t hese registers, a reas overflowing the upper-left relative to the mo[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 53 of 1658 REJ09B0261-0100 19.4.15 Double Buffer Control The double buffer c ontrol of the displa y unit (DU) includes two types of f unctions, whi ch are a manual displ ay change mode in whi ch displ ay swit ching is al l controlled by software, and an a uto display chan ge mode to realize blinki[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 54 of 1658 REJ09B0261-0100 19.4.16 Sync Mode In order to facilitate synchronization with external equipment, in addition to master mod e, a TV synchronizatio n function is provided. Sel ection of master mode an d TV sync mo de is performe d using the TVM bit in DSYSR. Regar dless of the s ynchroni[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 55 of 1658 REJ09B0261-0100 TV (sync signal generation circuit): Master Clock HSYNC VSYNC R,G,B This LSI: Slave DCLKIN DR5-DR0 DG5-DG0 DB5-DB0 Input 2 Input 1 Output Display Switching between master (input 2) and slave (input 1) by CDE. VSY N C ODDF CDE H SY N C Field signal Figure 19.12 Signal Flo[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 56 of 1658 REJ09B0261-0100 19.5 Display Control 19.5.1 Display Timing Generation In the displa y unit (DU), displ ay timing is generated for the horiz ontal direction and ve rtical direction of t he display screen . Display t iming is set by using display timi ng generati on registers. Figure 19.1[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 57 of 1658 REJ09B0261-0100 Table 19.13 Variables Defined in Display Screen Variables Contents Units hc * 1 Horizontal scan period Dot clock hsw Horizontal sync pulse width Dot clock xs From rise of HSYNC to display start position in the horizontal direction of the displ ay screen Dot clock xw Disp[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 58 of 1658 REJ09B0261-0100 Table 19.14 Correspondence Tabl e of Settin gs of Display Timing Genera tion Regi sters Synchronization Method Register Name Bit Name Master Mode TV Sync Mode Horizontal display start position register (HDSR) HDS hsw + xs - 19 hsw + xs – 24 * 2 Horizontal display end p[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 59 of 1658 REJ09B0261-0100 19.5.2 CSYNC When in master mo de, a CSYNC (composite sync) si gnal is output. EQWR is use d to set the low- level pulse width of the CSYNC equ al pulse. SPWR is used to set the low-level pulse width of the CSYNC separa tion pulse. The CSYNC waveform is selected using th[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 60 of 1658 REJ09B0261-0100 VSYNC CSYNC (CSY = 00) EQW (CSY = 10) (CSY = 11) 1/2HC 1/2HC SPW HSW HSYNC HC Equivalent pulse: 2.5 rasters Separation pulse: 2.5 rasters Equivalent pulse: 2.5 rasters Equivalent pulse: 3 rasters Separation pulse: 3 rasters Equivalent pulse: 3 rasters When HC is odd, it [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 61 of 1658 REJ09B0261-0100 19.5.3 Scan Meth od The scan method can be selected from among non-interlaced mode, i nterlaced sy nc mode, and interlaced sync & video mode . The mode is selected usi ng the SCM bit in DSYSR. • Non-interlaced mode In this scan method, one fram e consists of a sing[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 62 of 1658 REJ09B0261-0100 Raster scanned in an odd field Raster scanned in an even field 00 01 02 03 04 05 06 07 08 09 00 01 02 03 04 05 06 07 08 09 00 01 02 03 04 05 06 07 08 09 00 02 04 06 08 0A 0C 0E 10 12 01 03 05 07 09 0B 0D 0F 11 13 Interlaced sync & video mode Non-interlaced mode Inter[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 63 of 1658 REJ09B0261-0100 • Example of verti cal scan period Non-interlaced mode: 1/60 seco nd/field, 1/30 second/field Interlaced m ode: 1/30 second/ frame Interlaced s ync & video mode : 1/30 second/ frame • Display in non-interlaced method In this method, all lines are di splayed at on[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 64 of 1658 REJ09B0261-0100 • Display in interlaced method At every sca n period VC of the input vi deo signal, even lines an d odd line s are switche d and displayed in al ternation, and a single screen (one f rame) is com bined and displ ayed (with the afterimage of the prece ding VC) with a pe[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 65 of 1658 REJ09B0261-0100 19.5.4 Color Detection When output display data matches a col or set in CDER, high level is output fr om the CDE pi n. The CDEM bit in DSMR can be used to fix th e level outside display intervals. Also, the CDEL bit in DSMR can be used to select the polarity of the outpu[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 66 of 1658 REJ09B0261-0100 19.5.5 Output Signal Timing Adju stment The display unit (DU) e nables selection of output timing, with respect to t he output dot clock, of the various output signals (the four sync signals HSYNC, VSYNC, CSYNC, ODDF, as well as DISP, CDE, CLAMP, DE, digital RGB signals)[...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 67 of 1658 REJ09B0261-0100 19.5.6 CLAMP Signal and DE Signal The display unit (DU) ge nerates a CLAMP signal a nd DE signal, independent of the DIS P signal indicating the display interval. The rising-edge start position and high-level wid th of the CLAMP signal and DE signal, with reference to t [...]

19. Display Unit (DU) Rev.1.00 Jan. 10, 2008 Page 9 68 of 1658 REJ09B0261-0100 19.6 Power-Down Sequence When execu ting the power-dow n sequence by the follow ing modes or function s, turn off the display in advance. 1. Sleep mode 2. Deep sleep mode 3. Module standby 4. Change of frequenc y 5. Manual reset Even when t h e displ ay unit ( DU) enters[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 69 of 1658 REJ09B0261-0100 Section 20 Graphics Data Translati on Accelerator (GDTA) This block i ncorporates a YUV data con version proces sing module (C L) that converts data in the YUV 4:2:0 fo rmat to YUV 4:2: 2 or ARGB for mat, as well as a video proc essing module [...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 70 of 1658 REJ09B0261-0100 Figure 20. 1 shows the GDTA bloc k diagram. SuperHyway bus External memory Tar g et interface Initiator interface (external) (external) Control re g ister Buffer RAM interface RAM 0 interface arbiter CL/MC interface Buffer RAM 0 (8 Kbytes) Buf[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 71 of 1658 REJ09B0261-0100 (1) Target Interface The target interface controls access by t he CPU to the GDTA i nternal registers, buffer RAM 0/1, and CL and MC function blocks (i mage processing functi on bloc ks). The target interface places a request queue/r esponse q[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 72 of 1658 REJ09B0261-0100 (6) Buffer RA M Buffer RAM consists of two SRAM units each w ith an 8-Kbyte capacity. The RAM is used to store color c onversion table dat a for CL f unctions (b uffer RAM 0) and t o store IDC T data for M C functions (buff er RAM 1). The en t[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 73 of 1658 REJ09B0261-0100 20.2 GDTA Address Space Figure 20.2 shows the GDTA addr ess space (physical addresses). Th e GDTA consists of a number of functio n blocks; the address space is divi ded into function bl ock units owned b y the respect ive blocks. However, not[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 74 of 1658 REJ09B0261-0100 20.3 Register Descriptions Table 20.1 to 20.3 show t he register c onfiguration of the GDT A. Table 20.4 t o 20.6 show the register states i n each processi ng mode. Table 20.1 GDTA Regi ster Configurati on (GDTA Common Registers) Name Abbrevi[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 75 of 1658 REJ09B0261-0100 Table 20.2 GDTA Regis ter Configuration (CL Block) Name Abbreviation R/W P4 Address Area 7 Address Access Size Sync Clock CL command FIFO CLCF W H'FE40 100 0 H'1E40 1000 32 GAck CL control register CLCR R/ W H'FE40 1004 H'1[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 76 of 1658 REJ09B0261-0100 Table 20.3 GDTA Regis ter Configuration (MC Block) Name Abbreviation R/W P4 Address Area 7 Address Access Size Sync Clock MC command FIFO MCCF W H'FE40 2000 H'1E40 2000 32 GAck MC status register MCSR R H'FE40 200 4 H'1E40 [...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 77 of 1658 REJ09B0261-0100 Table 20.4 GDTA Register State s in Each Processing Mode (G DTA Common Registers ) Register Abbreviation Power-On Reset Ma nual Reset Sleep Deep Sleep GACMR H'0000 0000 H'0000 0000 Retained Retain ed GACER H'0000 0000 H'000[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 78 of 1658 REJ09B0261-0100 Table 20.6 GDTA States in Each Processing Mode (MC Block) Register Abbreviation Power-On Reset Manual Reset Sleep Deep Sleep Module Standby MCCF H'0000 0000 H'0000 0000 Retained H'0000_0000 H'0000_0000 MCSR H'0000 000 [...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 79 of 1658 REJ09B0261-0100 20.3.1 GA Mask Register (GACMR) GACMR is in t he GDTA commo n re gister bl ock and enables writing t o the GA enable regist er (GACER). Writing to GACER is enabled by writing of the key code to this register. In the initial state, the key code[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 80 of 1658 REJ09B0261-0100 20.3.2 GA Enable Register (GACER) GACER is in t h e GDTA co mmon register block and c ontrols t he block operat ion. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 81 of 1658 REJ09B0261-0100 20.3.3 GA Interrupt Source Indica ting Register (GACISR) GACISR is in the GDTA common register block an d indicates the stat es of interr upt source s for each module. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 82 of 1658 REJ09B0261-0100 20.3.4 GA Interrupt Source Indicati on Clear Register (GACICR) GACICR is in the GDTA c ommon register bloc k and clears interrupt so urce indication for each module. Bits in this register are read as 0. 16 17 18 19 20 21 22 23 24 25 26 27 28 2[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 83 of 1658 REJ09B0261-0100 20.3.5 GA Interrupt Enable Register (GACIER) GACIER is i n the GDT A common re gister block and sets interrupt output fo r each mod ule. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 84 of 1658 REJ09B0261-0100 20.3.6 GA CL Input Data Ali gnment Register (DRCL _CTL) DRCL_CTL is in the GDTA common regist er block and specifies data al ignment of C L input data. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ⎯ ⎯ ⎯ [...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 85 of 1658 REJ09B0261-0100 20.3.7 GA CL Output Data Ali gnment Register (DWCL_CTL) DWCL_CTL i s in the GDT A common re gister block and specifies data alignment of CL out put data. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ⎯ ⎯ ?[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 86 of 1658 REJ09B0261-0100 20.3.8 GA MC Input Data Alignment Register (D RMC_CTL) DRMC_CTL i s in the GDTA common re gister block an d specifies data al ignment of MC input data. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ⎯ ⎯ ⎯ [...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 87 of 1658 REJ09B0261-0100 20.3.9 GA MC Output Data Alignment Regist er (DWMC_CTL) DWMC_CTL i s in the GDT A common re gister block an d specifies data alignment of MC output data. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ⎯ ⎯ ?[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 88 of 1658 REJ09B0261-0100 20.3.10 GA Buffer RAM 0 Data Alignment Register (DCP_CTL) DCP_CTL is i n the GDT A common regi ster bloc k an d specifies d ata alignment of the data stored in buffer RAM 0. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 89 of 1658 REJ09B0261-0100 20.3.11 GA Buffer RAM 1 Data Alig nment Register (DID_CTL) DID_CTL is i n the GDTA co mmon register block and specifies data alignment of the data st ored in buffer RAM 1. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 90 of 1658 REJ09B0261-0100 20.3.12 CL Command FIFO (CLCF) CLCF is in the CL register block and receives co mma nds. This register uses the FIFO method and recognizes four command parameters according to the writin g order. This register does not re tain the written valu[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 91 of 1658 REJ09B0261-0100 2. Setting Method When Setting Values in Succession When setting values in this register in succe ssion, the CL module is able to receive the next command while the CL_CFF bit in CLSR is 0. To perform processing by changing the command alone, [...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 92 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 1 CL_OA 0 R/W Specifi es output address mode 0: Output address incremented When the output access size is 4 bytes, the address is incremented by H'4; when the output acces s size is 32 bytes, the[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 93 of 1658 REJ09B0261-0100 20.3.14 CL Status Re gister (CLSR) CLSR is in t he CL regi ster block an d i ndicates the i nternal states of the CL. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ?[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 94 of 1658 REJ09B0261-0100 20.3.15 CL Frame Width Settin g Register (CLWR) CLWR is in the CL regi ster block a nd sets the in put image wi dth in pi xel units. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 95 of 1658 REJ09B0261-0100 20.3.16 CL Frame Height Settin g Register (CLHR) CLHR is in the CL register block and sets the input image heigh t in line units. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ?[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 96 of 1658 REJ09B0261-0100 20.3.17 CL Input Y P adding Size Setting Regis ter (CLIYPR) CLIYPR is in the CL re gister bloc k and sets t he input Y pa dding size in byte uni ts. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ⎯ ⎯ ⎯ ⎯[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 97 of 1658 REJ09B0261-0100 20.3.18 CL Input UV Padding Size Setting Re gister (CLIUVPR) CLIUVPR is in the CL register bloc k and sets the input U V padding size in byte units. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ⎯ ⎯ ⎯ ⎯[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 98 of 1658 REJ09B0261-0100 20.3.19 CL Output Padding Size Setting Re gister (CLOPR) CLOPR is i n the CL regi ster block a n d sets the o utput paddin g size in byt e units. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ⎯ ⎯ ⎯ ⎯ ?[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 9 99 of 1658 REJ09B0261-0100 20.3.20 CL Palette Pointer Register (CLPLPR) CLPLPR is in the CL register block and sets the color conversion table pointer. Th e RAM 0 address used for a work area shoul d be specified. This register setting is used only in the ARBG conversio[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 000 of 1658 REJ09B0261-0100 20.3.21 MC Command FIFO (MCCF) MCCF is in the MC register block a nd receives commands. This register uses the FIFO method and recognizes a maximum of eight comman d parameters a ccording to the writing or der. This register does not retain t[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 001 of 1658 REJ09B0261-0100 Writing Order Intra Macroblock Processing Forward Macroblock Processing Reverse Macroblock Processing Bidirectional Macroblock Processing End Command Command parameter 1 Bits 31 to 26: cbp Bits 2 to 0: H'0 Bits 31 to 2 6: cbp Bits 2 to 0[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 002 of 1658 REJ09B0261-0100 ⎯ Bit 26: In dicates whether or not the V IDCT data exists (0: I DCT data is i nvalid, 1: IDCT data is valid) • mbcol: Row position in macrob lock units (number of macroblocks) • mbrow: Col umn positi on in macrobl ock units (number of [...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 003 of 1658 REJ09B0261-0100 20.3.22 MC Status Register (MCSR) MCSR is in t he MC regi ster block a nd in dicates the internal states of the MC. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 004 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Desc ription 2 to 0 MC_CFS All 0 R Command pointer status display 000: MCCF command parameter 1 setting wait state 001: MCCF command parameter 2 setting wait state 010: MCCF command parameter 3 setting wait stat[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 005 of 1658 REJ09B0261-0100 20.3.24 MC Frame Hei ght Setting Regi ster (MCHR ) MCHR is in t he MC register block a n d sets t he input imag e height in l ine units. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ?[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 006 of 1658 REJ09B0261-0100 20.3.25 MC Y Padding Size Setting Register (MCYPR) MCYPR is in the MC register block and set s the input Y padding si ze in byte unit s. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ?[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 007 of 1658 REJ09B0261-0100 20.3.26 MC UV Padding Size Setti ng Regis t er (MCUVPR) MCUVPR is i n the MC regi ster block and sets the in put UV paddin g size in byte units. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ⎯ ⎯ ⎯ ⎯ ?[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 008 of 1658 REJ09B0261-0100 20.3.27 MC Outpu t Frame Y Poin ter Register (MCOYPR) MCOYPR is i n the MC re gister block and specifies t he Y poi nter address f or an outp ut frame. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 MC_OYPT R/W[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 009 of 1658 REJ09B0261-0100 20.3.29 MC Outpu t Frame V Poin ter Register (MCOVPR) MCOVPR is i n the MC re gister block and specifies t he V poi nter address f or an outp ut frame. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 MC_OVPT R/W[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 010 of 1658 REJ09B0261-0100 20.3.31 MC Past Frame U Pointer Register (MCPUPR) MCPUPR is i n the MC regist er block and speci fies the U pointer address fo r a past frame. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 MC_PUPT R/W R/W R/W [...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 011 of 1658 REJ09B0261-0100 20.3.33 MC Future Frame Y P ointer Register (MCFYPR) MCFYPR is i n the MC regist er block and specifi es the Y pointer addre ss for a future frame. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 MC_FYPT R/W R/W[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 012 of 1658 REJ09B0261-0100 20.3.35 MC Future Frame V P ointer Register (MCFVPR) MCFVPR is i n the MC regist er block and specifi es the V pointer addre ss for a future frame. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 MC_FVPT R/W R/W[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 013 of 1658 REJ09B0261-0100 20.4 GDTA Operation 20.4.1 Explanation of CL Operation By writing 1 to the CL_EN bit in GACER, re gisters in the CL register unit can be accessed. After setting, as ini tial values, t he input frame widt h/height, in put paddi ng size, output[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 014 of 1658 REJ09B0261-0100 Table 20.7 shows YU YV4:2:2 conv ersion sequen ce shown in figur e 20.3. No. in the table corresponds to th e number used in figure 20.3. Table 20.7 YUY V4:2: 2 Conversion Sequence No. Operation Description (1) Input data reading YUV-separate[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 015 of 1658 REJ09B0261-0100 (2) Overview of ARGB Conver sion Functions The following shows an outlin e of the ARGB conversion specification. Frame hei g ht DDR2-SDRAM AR B G AR B G AR B G AR B G AR B G AR B G AR B G BR B G BR B G BR B G AR B G AR B G AR B G AR B G AR B [...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 016 of 1658 REJ09B0261-0100 Table 20.8 shows ARGB 8888 conversion sequence sh own in figure 20 .4. No. in the table corres ponds to the n umber used i n figure 20.4. (1) and (2) corresp ond to the numbers in figure 20.3. Table 20.8 ARGB8888 Conversion Sequence No. Opera[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 017 of 1658 REJ09B0261-0100 No. Operation Description (4) ARGB conversion ARGB data is generated from color information read from buffer RAM 0 using the following formula, and the conv erted data is output in the format shown in the display image of figure 20.4. ARGB co[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 018 of 1658 REJ09B0261-0100 [Step (1) Clear the CL access mask] After the CPU sets the key code in GACMR within the bus interface, set GACER to enable access to the CL function block. [Step (2) Initialize the CL function block] The CPU sets the frame width/hei g ht, inp[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 019 of 1658 REJ09B0261-0100 20.4.2 Explanation of MC Operation By writing 1 to the MC_EN bit in GACER, registers in the MC register unit can be accessed. After setting, as initial va lues, the input frame wi dth/heigh t, input YUV p adding size, output frame YUV pointer[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 020 of 1658 REJ09B0261-0100 (1) Estimated Im age Generation Fu nction The following shows an outlin e of the estimated image generation function . Output frame Y pointer (current) Output frame U pointer (current) Output frame V pointer (current) Past frame Y pointer Pas[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 021 of 1658 REJ09B0261-0100 Table 20.9 shows estimated image generation sequ ence shown in figure 20.6. No. in the table corresponds to th e number used in figure 20.6 . Table 20.9 Estimated Im age Generation Sequence No. Operation Description (1) Calculation of output [...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 022 of 1658 REJ09B0261-0100 No. Operation Description (2) Calculation of output position (nth row and below) The following formulae are used to co mpute output positions (nth row and below) (DDR2-SDRAM output address). Output address formulae for nth row and below • Y[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 023 of 1658 REJ09B0261-0100 No. Operation Description (3) Calculation of input position (first row) The following formulae are used to comput e input position (first row) (DDR2- SDRAM input address). First row input address formulae • Y input comparison address Calcul[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 024 of 1658 REJ09B0261-0100 No. Operation Description (3) Calculation of input position (first row) • U/V input comparison address Calculation formula: Past frame U poi nt value (base point) + [(mbrow × 8 + (Recon_down/2>> 1)) × (width/2 + U padding)] + [mbcol[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 025 of 1658 REJ09B0261-0100 No. Operation Description (4) Calculation of input position (nth row and below) The following formulae are used to compute input positions (nth row and below) (DDR2-SDRAM input addr ess). Input address formulae for nth row and below • Y inp[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 026 of 1658 REJ09B0261-0100 No. Operation Description (6) Half-pixel correction processing Half-pixel correction processing is performe d for the data read in (5). (For the Y pointer: 16 to the right and 16 downward in 4 pi xel units, for a total of 256 processed) * The[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 027 of 1658 REJ09B0261-0100 No. Operation Description (7) IDCT data reading IDCT data stored in buffer RAM 1 is read. (Only blocks specified by a CBP setting of 1 are read from buffer RAM 1.) The IDCT data should be stored in bu ffer RAM 1 as 16-bit si gned data. (The s[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 028 of 1658 REJ09B0261-0100 Start End Is an interrupt used to recognize processing completion ? Continuous processing ? [Step (1) Clear the MC access mask] After the CPU sets the key code in GACMR within the bus interface, set GACER to enable access to the MC function b[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 029 of 1658 REJ09B0261-0100 20.5 Interrupt Processing In the GDTA, there are four type s of interrupt source s. There ar e three interrupt flags for C L processing end, MC processing end, an d CL/MC errors, use d to identify interrupt sources. T he interrupt e nable bit[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 030 of 1658 REJ09B0261-0100 D0 D1 D2 D3 D4 D5 D6 D7 D4 D5 D6 D7 D0 D1 D2 D3 D7 D6 D5 D4 D3 D2 D1 D0 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D3 D2 D1 D0 D7 D6 D5 D4 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D1 D0 D3 D2 D5 D4 D7 D6 D0 D1 D2 D3 D4 D5 D6 D7 D0[...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 031 of 1658 REJ09B0261-0100 20.7 Usage Notes When using the GDTA, note the following: 20.7.1 Regarding Module Stoppage During GDTA operation, t he CPG register setti ngs must not be done to sto p a module (ot h er modules as well as the GDT A). If a mo dule is stoppe d [...]

20. Graphics Data Translation Accele rator (GDTA) Rev.1.00 Jan. 10, 2008 Page 1 032 of 1658 REJ09B0261-0100 20.7.3 Regarding Frequenc y Changes During GDTA operatio n, the CPG register set ting must not be used t o change frequency . If frequenc y is change d during GDTA operati on, the GDTA processi ng is stop ped and p rocessing contents set in C[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 033 of 1658 REJ09B0261-0100 Section 21 Serial Communi cation Interface with FIFO (SCIF) This LSI is equipped with a 6-ch annel serial communication inte rface with built-i n FIFO buffers (Serial Communication Interface with FIFO: SCIF). The SCIF can perf orm both asy[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 034 of 1658 REJ09B0261-0100 • Full-duplex communication cap ability The transmitter and receiver are independent units, e nabling transmission and reception to be performed sim ultaneously. The transmitter and receiver both have a 64-stage FIFO buffer structure, en[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 035 of 1658 REJ09B0261-0100 Figure 21.1 show s a block diagra m of the SCIF. Figures 21. 2 to 21.6 show bloc k diagrams of the I/O ports in the SCIF . There are six cha nnels in this LSI. In figures 21.2 to 21.6, the channel number is omitted. SCFRDRn (128 sta g es) [...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 036 of 1658 REJ09B0261-0100 SPTRW D7 D6 R Q D RTSIO C SPTRR SPTRW R Q D RTSDT C SCIF0_RTS Reset Reset Peripheral bus Modem control enable si g nal * SCIF0_RTS si g nal Le g end: SPTRW: Write to SCSPTR SPTRR: Read from SCSPTR Note: * SCSPTR The SCIF0_RTS pin function [...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 037 of 1658 REJ09B0261-0100 SPTRW D5 D4 R Q D CTSIO C SPTRR SPTRW R Q D CTSDT C SCIF0_CTS Le g end: SPTRW: Write to SCSPTR SPTRR: Read from SCSPTR Note: * The SCIF0_CTS pin function is desi g nated as modem control by the MCE bit in SCFCR. Modem control enable si g n[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 038 of 1658 REJ09B0261-0100 SPTRW D3 D2 R Q D SCKIO C SPTRR SPTRW R Q D SCKDT C Clock output enab le si g nal * Serial clock output si g nal * Serial clock input si g nal * Serial input enable si g nal * P er ipheral bus Reset Reset Le g end: SPTRW: Write to SCSPTR S[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 039 of 1658 REJ09B0261-0100 SPTRR Le g end: SPTRR: Read from SCSPTR SCIFn_RXD Peripheral bus Serial receive data Figure 21.6 SCIFn_RXD Pin (n = 0 to 5) 21.2 Input/Output Pins Table 21.1 sho ws the SCIF pi n configuration. Since the pin functi ons are the sa me in eac[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 040 of 1658 REJ09B0261-0100 21.3 Register Descriptions The SCIF has t he following registers. Si nce the register functions a re the same in eac h channel, the channel number is omitted in th e description below. Table 21.2 Register Configuration (1) Ch. Register Nam[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 041 of 1658 REJ09B0261-0100 Ch. Register Name Abbrev. R/ W P4 Address Area 7 Address Size Sync Clock 2 Serial mode register 2 SCSMR2 R/W H'FFEC 0000 H'1FEC 0000 16 Pck Bit rate register 2 SCBRR2 R/W H'FFEC 0004 H'1FEC 0004 8 Pck Serial control reg[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 042 of 1658 REJ09B0261-0100 Ch. Register Name Abbrev. R/ W P4 Address Area 7 Address Size Sync Clock 4 Serial mode register 4 SCSMR4 R/W H'FFEE 0000 H'1FEE 0000 16 Pck Bit rate register 4 SCBRR4 R/W H'FFEE 0004 H'1FEE 0004 8 Pck Serial control reg[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 043 of 1658 REJ09B0261-0100 Table 21.2 Register Configuration (2) Ch. Register Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/Multiple Exception Sleep/Deep Sleep by SLEEP Instruction Module Standby 0 Serial mode register 0 SCSMR0 H'0000[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 044 of 1658 REJ09B0261-0100 Ch. Register Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/M ultiple Exception Sleep/Deep Sleep by SLEEP Instruction Module Standby 2 Serial mode register 2 SCSMR2 H'0000 H'0000 Retained Retained Bit ra[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 045 of 1658 REJ09B0261-0100 Ch. Register Name Abbrev. Power-on Reset by PRESET Pin/ WDT/H-UDI Manual Reset by WDT/Multiple Exception Sleep/Deep Sleep by SLEEP Instruction Module Standby 4 Serial mode register 4 SCSMR4 H'0000 H'0000 Retained Retained Bit rat[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 046 of 1658 REJ09B0261-0100 21.3.1 Receive Shift Register (SCRSR) SCRSR is the register used to receive se rial data. The SCIF sets serial data input from t he SCIF_RXD pin in SCRSR in the order received, starting with the LSB (bit 0), and conv erts it to parallel da[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 047 of 1658 REJ09B0261-0100 21.3.3 Transmit Shift Register (SCTSR) SCTSR is a register used to transmit serial data. To perform ser ial data transm ission, the SCIF first transfers transmit data from SCFTDR t o SCTSR, then s ends the data to the T XD pin start ing wi[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 048 of 1658 REJ09B0261-0100 21.3.5 Serial Mode Register (SCSMR) SCSMR is a 16-bit register used to set the SCIF's serial communication format and select the baud rate generator cl ock source. SCSMR can always be read from and written to by th e CPU. 0 1 2 3 4 5 [...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 049 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 PE 0 R/W Parity Enable In asynchronous mode, selects whether or n ot parity bit addition is performed in transmission, and p arity bit checking is performed in reception. In clocked synchronous [...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 050 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 3 STOP 0 R/W Stop Bit Length In asynchronous mode, selects 1 or 2 bits as the stop bit length. The stop bit se tting is valid only in asynchronous mode. Since the stop bit is not added in clocked [...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 051 of 1658 REJ09B0261-0100 21.3.6 Serial Control Register (SCSCR) SCSCR is a register used to enable/disable tran smission/reception by SCIF, serial clock output, interrupt requests, and t o select transmission/reception cloc k source for the SCIF. SCSCR can always [...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 052 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 RIE 0 R/W Receive Interrupt Enable * 1 Enables or disables generati on of a receive-data-full interrupt (RXI) request when the RDF flag or DR flag in SCFSR is set to 1, a receive-error interrupt[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 053 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 4 RE 0 R/W Receiv e Ena ble Enables or disables the start of serial recepti on by the SCIF. Serial reception is started when a start bit or a synchronization clock input is detected in asynchronou[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 054 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 1 0 CKE1 CKE0 0 0 R/W R/W Clock Enable 1, 0 These bits select the SCIF clock source and whether to enable or disable the clock output from the SCIF_SCK pin. The CKE1 and CKE0 bits are used togethe[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 055 of 1658 REJ09B0261-0100 21.3.7 Serial Status Register n (SCFSR) SCFSR is a 16-bit register that consists of stat us flags that indicate th e opera ting status o f the SCIF. SCFSR can be always read fr om or written to by the CPU. However, 1 ca nnot be written to [...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 056 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 7 ER 0 R/W * 1 Receiv e Error Indicates that a framing error or parity error occurred during reception. The ER flag is not affected and retains its previous state when the RE bit in SCSCR is clear[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 057 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 TDFE 1 R/W * 1 Transmit FIFO Data Empty Indicates that data has been transferred from SCFTDR to SCTSR, the number of data bytes in SCFTDR has fallen to or below the transmit trigger data count s[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 058 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 3 FER 0 R Framing Error Display In asynchronous mode, indicates whether o r not a framing error has been found in the data that is to be read from SCFRDR. 0: There is no framing error t hat is to [...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 059 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 1 RDF 0 R/W * 1 Receive FIFO Data Full Indicates that the received dat a has been transferred from SCRSR to SCFRDR, and the number of receive data bytes in SCFRDR is equa l to or greater than the [...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 060 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 0 DR 0 R/W * 1 Receive Data Ready In asynchronous mode, indicates that there are fewer than the receive trigger setting count of data bytes in SCFRDR, and no further data has arrived for at least [...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 061 of 1658 REJ09B0261-0100 21.3.8 Bit Rate Regis t er n (SCB RR) SCBRR is an 8-bit register tha t sets the serial transmission/reception bit rate in accorda nce with the baud rate g enerator operat ing clock selec t ed by the CKS1 and CKS0 bits in SCSMR. SCBRR can a[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 062 of 1658 REJ09B0261-0100 21.3.9 FIFO Control Register n (SCF CR) SCFCR is a register that performs data count resetting and trigger data number setting for transmit and receive FIFO registers, a nd also contains a loopback test enable bit. SCFCR can always be read[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 063 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 5 4 TTRG1 TTRG0 0 0 R/W R/W Transmit FIFO Data Count Trigger These bits are used to set the number of remaining transmit data bytes that sets the TDFE flag in SCFSR. The TDFE flag is set when the [...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 064 of 1658 REJ09B0261-0100 21.3.10 Transmit FIFO Data Count Register n (SCTFDR) SCTFDR is a 16-bit register t hat indicates the nu mber of transmit data bytes stored in SCFTDR. SCTFDR ca n always be read from the CPU. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 [...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 065 of 1658 REJ09B0261-0100 21.3.11 Receive FIFO Data Coun t Register n (SCRFDR) SCRFDR is a 16-bit register that indicates t he number of receive data bytes stored in SCFRDR. SCRFDR can always be rea d from the C PU. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 066 of 1658 REJ09B0261-0100 21.3.12 Serial Port Regi ster n (SCSPTR) SCSPTR is a 1 6-bit readable/ writable regi ster that co ntrols input/ output and dat a for the port pins multiplexed with th e serial communication interface (SCIF) pins at all time s. Input data c[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 067 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 6 RTSDT * — R/W Serial Port SCIF_RTS Port Data Specifies the serial port SCIF_RTS pin input/output data. Input or output is s pecified by the RTSIO bit. In output mode, the RTSDT bit value is ou[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 068 of 1658 REJ09B0261-0100 Bit Bit Name Initial Value R/W Description 2 SCKDT — R/W Serial Port Clock Port Data Specifies the serial port SCIF_SCK pin input/output data. Input or output is s pecified by the SCKIO bit. In output mode, the SCKDT bit value is output [...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 069 of 1658 REJ09B0261-0100 21.3.13 Line Status Register n (SCLSR) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 ORER ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯⎯ R/W * R R R R R R R R R R R R R RR BIt: Initial value: R/W: Note: *[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 070 of 1658 REJ09B0261-0100 21.3.14 Serial Error Register n (SCRER) SCRER is a 16-bit register tha t indicates the numb er of rece ive errors in the data in SCFRDR. SCRER can always be read from t h e CPU. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 071 of 1658 REJ09B0261-0100 21.4 Operation 21.4.1 Overview The SCIF can perform serial communication i n asynchro nous mode, i n which sync hronization is achieved chara cter by charact er and in clocked synch ronous mode , in whic h synchroniza tion is achieved wi t[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 072 of 1658 REJ09B0261-0100 Clocked Synchron ous Mode • Data length: Fixed at 8 bits • LSB first for data transmission and reception • Detection of overru n errors during reception • Choice of pe ripheral cl ock (Pck) or SCIF_S CK pin i nput as SCI F clock so[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 073 of 1658 REJ09B0261-0100 Table 21. 5 SCSMR and S CSCR Sett ings for SCIF Clock Source Selectio n SCSMR SCSCR Settings Bit 7: C/ A Bit 1: CKE1 Bit 0: CKE0 Mode Clock Source SCIF_SCK Pin Function 0 SCIF does not use SCIF_SCK pin 0 1 Internal Outputs clock with frequ[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 074 of 1658 REJ09B0261-0100 21.4.2 Operation in Asynchronous Mode In asynchronous mode, a character that consists of data wit h a start bit in dicating the st art of communication a nd a stop bit indicating the end of communication is transm itted or r eceived. In th[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 075 of 1658 REJ09B0261-0100 (1) Data Transfer Format Table 21.6 shows the data transfe r formats that can be u sed. Any of 8 tr ansfer formats can be selected according to the SCSMR settings. Table 21.6 Serial Transfer Formats (Asynchronou s Mode) SCSMR Settings Seri[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 076 of 1658 REJ09B0261-0100 (2) Clock Either an inte rnal clock generated b y the on-c hip baud rat e generator or an external clock inp ut at the SCIF_SCK pin can be selected as the SC IF's se rial cl ock, accordi ng to the setti ngs of t he C/ A bit in SCSMR a[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 077 of 1658 REJ09B0261-0100 Figure 21.8 shows a sample SCIF initialization flowch art. Start of initialization Clear TE and RE bits in SCSCR to 0 Set TFCL and RFCL bits in SCFCR to 1 Set CKE1 and CKE0 bits in SCSCR (leavin g TIE, RIE, TE, and RE bits cleared to 0) Se[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 078 of 1658 REJ09B0261-0100 (4) Serial Da ta Transmissi on (Asynchron ous Mode) Figure 21.9 s hows a sample flow chart for se rial transmission. Use the following procedure for serial data transmi ssion af ter enab ling the SCI F for transmis sion. Start of transmiss[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 079 of 1658 REJ09B0261-0100 In serial transmission, the SCIF operates a s follows. 1. Wh en data is written to SCFTDR, the SCIF transfers the data from SCFTDR to SCTSR and starts transmission. Confirm that the TDFE flag in SCFSR is set to 1 before writing transmit da[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 080 of 1658 REJ09B0261-0100 Figure 21.10 s h ows an exa mple of the operation for transmission in asynch ronous mode. 1 0 D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1 1 TDFE TEND Serial data Start bit Data Parity bit Stop bit Start bit Idle state (mark state) Idle state (mark sta[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 081 of 1658 REJ09B0261-0100 (5) Serial Data Reception (Asynchronous Mode) Figure 21.12 shows a sample flowchart fo r serial reception. Use the following procedure for serial data recep tion after enabling th e SCIF for reception. Start of reception Read ER, DR, BRK f[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 082 of 1658 REJ09B0261-0100 Error handlin g Receive error handlin g ER = 1? BRK = 1? Break handlin g DR = 1? Read receive data in SCFRDR Clear DR, ER, BRK fla g s in SCFSR, and ORER fla g in SCLSR, to 0 End Yes Yes Yes No Overrun error handlin g ORER = 1? Yes No No N[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 083 of 1658 REJ09B0261-0100 In serial reception, the SCIF operates as follows. 1. Th e SCIF monitors the transmission line, an d if a 0-start bit is detected, performs internal synchronization and starts receptio n. 2. The received data is stored in SCRSR in LSB-to-M[...]

21. Serial Communication Interface with FIFO (S CIF) Rev.1.00 Jan. 10, 2008 Page 1 084 of 1658 REJ09B0261-0100 5. When modem cont rol is ena bled, the SCIF_RTS signal is output when SCFRDR is empt y. When SCIF_R TS is 0, recepti on is possible. Whe n SCIF_RTS is 1, t his indicates that SCFRDR contai ns bytes of data equal to or mo re than the SCIF_[...]