Texas Instruments TMS320DM646x manual

TMS320DM646x DMSoC Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) Module User's Guide Literature Number: SPRUEQ6 December 2007[...]

2 SPRUEQ6 – December 2007 Submit Documentation Feedback[...]

Contents Preface .............................................................................................................................. 10 1 Introduction .............................................................................................................. 12 1.1 Purpose of the Peripheral ............................................[...]

4.3 PHY Acknowledge Status Register (ALIVE) ................................................................ 73 4.4 PHY Link Status Register (LINK) ............................................................................. 73 4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) ............................ 74 4.6 MDIO Link Stat[...]

5.36 MAC Source Address High Bytes Register (MACSRCADDRHI) ....................................... 116 5.37 MAC Hash Address Register 1 (MACHASH1) ............................................................ 117 5.38 MAC Hash Address Register 2 (MACHASH2) ............................................................ 117 5.39 Back Off Test Register ([...]

List of Figures 1 EMAC and MDIO Block Diagram ........................................................................................ 13 2 Ethernet Configuration—MII Connections .............................................................................. 15 3 Ethernet Configuration—GMII Connections ...........................................[...]

53 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) ................................................ 96 54 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) ............................................... 97 55 Receive Interrupt Mask Set Register (RXINTMASKSET) ............................................................. 98 5[...]

List of Tables 1 EMAC and MDIO Signals for MII Interface ............................................................................. 16 2 EMAC and MDIO Signals for GMII Interface ........................................................................... 17 3 Ethernet Frame Description .............................................................[...]

48 Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions ...................................... 93 49 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions ................................ 94 50 MAC Input Vector Register (MACINVECTOR) Field Descriptions ................................................... 95 51 [...]

Preface SPRUEQ6 – December 2007 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the TMS320DM646x Digital Media System-on-Chip. Included are the features of the EMAC and MDIO modu[...]

www.ti.com Related Documentation From Texas Instruments SPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth manage[...]

1 Introduction 1.1 Purpose of the Peripheral 1.2 Features User's Guide SPRUEQ6 – December 2007 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module in[...]

www.ti.com 1.3 Functional Block Diagram Configuration bus DMA memory transfer controller Peripheral bus EMAC control module EMAC module MDIO module G/MII bus MDIO bus EMAC/MDIO interrupts ARM interrupt controller 4 Introduction • No-chain mode truncates frame to first buffer for network analysis applications. • Emulation support. • Loopback m[...]

www.ti.com 1.4 Industry Standard(s) Compliance Statement 2 Architecture 2.1 Clock Control 2.1.1 MII Clocking 2.1.2 GMII Clocking Architecture The EMAC and MDIO interrupts are combined within the control module, so only the control module interrupt needs to be monitored by the application software or device driver. The EMAC control module combines t[...]

www.ti.com 2.2 Memory Map 2.3 Signal Descriptions 2.3.1 Media Independent Interface (MII) Connections MTCLK MTXD(7−0) MTXEN MCOL MCRS MRCLK MRXD(7−0) MRXDV MRXER MDCLK MDIO Physical layer device (PHY) System core Transformer 2.5 MHz, 25 MHz or 125 MHz RJ−45 EMAC MDIO Architecture The EMAC peripheral includes internal memory that is used to ho[...]

www.ti.com Architecture Table 1. EMAC and MDIO Signals for MII Interface Signal Type Description MTCLK I Transmit clock (MTCLK). The transmit clock is a continuous clock that provides the timing reference for transmit operations. The MTXD and MTXEN signals are tied to this clock. The clock is generated by the PHY and is 2.5 MHZ at 10 Mbps operation[...]

www.ti.com 2.3.2 Gigabit Media Independent Interface (GMII) Connections MTCLK MTXD[7−0] MTXEN MCOL MCRS MRCLK MRXD[7−0] MRXDV MRXER MDCLK MDIO Physical layer device (PHY) System core Transformer 2.5 MHz, 25 MHz, RJ−45 EMAC MDIO GMTCLK or 125 MHz RFTCLK Architecture Figure 3 shows a device with integrated EMAC and MDIO interfaced via a GMII co[...]

www.ti.com Architecture Table 2. EMAC and MDIO Signals for GMII Interface (continued) Signal Type Description MCRS I Carrier sense (MCRS). The MCRS pin is asserted by the PHY when the network is not idle in either transmit or receive. The pin is de-asserted when both transmit and receive are idle. This signal is not necessarily synchronous to MTCLK[...]

www.ti.com 2.4 Ethernet Protocol Overview 2.4.1 Ethernet Frame Format Preamble SFD Destination Source Len Data 7 1 6 6 2 46−1500 4 FCS Number of bytes Legend: SFD=Start Frame Delimeter; FCS=Frame Check Sequence (CRC) Architecture Ethernet provides an unreliable, connection-less service to a networking application. A brief overview of the Ethernet[...]

www.ti.com 2.4.2 Ethernet’s Multiple Access Protocol 2.5 Programming Interface 2.5.1 Packet Buffer Descriptors Architecture Nodes in an Ethernet Local Area Network are interconnected by a broadcast channel, as a result, when an EMAC port transmits a frame, all the adapters on the local network receive the frame. Carrier Sense Multiple Access with[...]

www.ti.com SOP | EOP 60 0 60 pBuf fer pNext Packet A 60 bytes 0 SOP Fragment 1 Packet B 512 1514 pBuf fer pNext 512 bytes EOP 0 0 −−− Packet B Fragment 3 500 bytes 502 pBuf fer −−− 500 pNext −−− pBuf fer pNext Packet B Fragment 2 502 bytes SOP | EOP 0 1514 bytes Packet C 1514 pBuf fer pNext (NULL) 1514 Architecture Table 4. Basic [...]

www.ti.com 2.5.2 Transmit and Receive Descriptor Queues Architecture The EMAC module processes descriptors in linked list chains as discussed in Section 2.5.1 . The lists controlled by the EMAC are maintained by the application software through the use of the head descriptor pointer registers (HDP). Since the EMAC supports eight channels for both t[...]

www.ti.com 2.5.3 Transmit and Receive EMAC Interrupts Architecture The EMAC processes descriptors in linked list chains as discussed in Section 2.5.1 , using the linked list queue mechanism discussed in Section 2.5.2 . The EMAC synchronizes descriptor list processing through the use of interrupts to the software application. The interrupts are cont[...]

www.ti.com 2.5.4 Transmit Buffer Descriptor Format Architecture A transmit (TX) buffer descriptor ( Figure 7 ) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 1 shows the transmit buffer descriptor described by a C structure. Figure 7. Transmit Buffer Descriptor Form[...]

www.ti.com 2.5.4.1 Next Descriptor Pointer 2.5.4.2 Buffer Pointer 2.5.4.3 Buffer Offset 2.5.4.4 Buffer Length 2.5.4.5 Packet Length 2.5.4.6 Start of Packet (SOP) Flag Architecture The next descriptor pointer points to the 32-bit word aligned memory address of the next buffer descriptor in the transmit queue. This pointer is used to create a linked [...]

www.ti.com 2.5.4.7 End of Packet (EOP) Flag 2.5.4.8 Ownership (OWNER) Flag 2.5.4.9 End of Queue (EOQ) Flag 2.5.4.10 Teardown Complete (TDOWNCMPLT) Flag 2.5.4.11 Pass CRC (PASSCRC) Flag Architecture When set, this flag indicates that the descriptor points to a packet buffer that is last for a given packet. In the case of a single fragment packet, bo[...]

www.ti.com 2.5.5 Receive Buffer Descriptor Format 2.5.5.1 Next Descriptor Pointer 2.5.5.2 Buffer Pointer Architecture A receive (RX) buffer descriptor ( Figure 8 ) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 2 shows the receive buffer descriptor described by a C [...]

www.ti.com 2.5.5.3 Buffer Offset Architecture Example 2. Receive Buffer Descriptor in C Structure Format /* // EMAC Descriptor // // The following is the format of a single buffer descriptor // on the EMAC. */ typedef struct _EMAC_Desc { struct _EMAC_Desc *pNext; /* Pointer to next descriptor in chain */ Uint8 *pBuffer; /* Pointer to data buffer */[...]

www.ti.com 2.5.5.4 Buffer Length 2.5.5.5 Packet Length 2.5.5.6 Start of Packet (SOP) Flag 2.5.5.7 End of Packet (EOP) Flag 2.5.5.8 Ownership (OWNER) Flag 2.5.5.9 End of Queue (EOQ) Flag Architecture This 16-bit field is used for two purposes: • Before the descriptor is first placed on the receive queue by the application software, the buffer leng[...]

www.ti.com 2.5.5.10 Teardown Complete (TDOWNCMPLT) Flag 2.5.5.11 Pass CRC (PASSCRC) Flag 2.5.5.12 Jabber Flag 2.5.5.13 Oversize Flag 2.5.5.14 Fragment Flag 2.5.5.15 Undersized Flag 2.5.5.16 Control Flag 2.5.5.17 Overrun Flag 2.5.5.18 Code Error (CODEERROR) Flag 2.5.5.19 Alignment Error (ALIGNERROR) Flag 2.5.5.20 CRC Error (CRCERROR) Flag Architectu[...]

www.ti.com 2.5.5.21 No Match (NOMATCH) Flag 2.6 EMAC Control Module Arbiter and bus switches CPU DMA Controllers 8K byte descriptor memory Configuration registers Interrupt control and pacing logic EMAC interrupts MDIO interrupts Configuration bus T ransmit and Receive 4 interrupts to ARM 2.6.1 Internal Memory 2.6.2 Bus Arbiter Architecture This fl[...]

www.ti.com 2.6.3 Interrupt Control 2.6.3.1 Transmit Pulse Interrupt 2.6.3.2 Receive Pulse Interrupt Architecture The EMAC control module combines multiple interrupt conditions generated by the EMAC and MDIO modules into four separate interrupt signals ( Table 5 ) that are mapped to a CPU interrupt via the CPU interrupt controller. The four separate[...]

www.ti.com 2.6.3.3 Receive Threshold Pulse Interrupt 2.6.3.4 Miscellaneous Pulse Interrupt 2.6.4 Interrupt Pacing Architecture The EMAC control module receives the eight individual receive threshold interrupts originating from the EMAC module, one for each of the eight channels, and combines them into a single receive threshold pulse interrupt to t[...]

www.ti.com 2.7 MDIO Module 2.7.1 MDIO Module Components EMAC control module Control registers and logic PHY monitoring Peripheral clock MDIO clock generator USERINT MDIO interface polling PHY MDCLK MDIO LINKINT Configuration bus 2.7.1.1 MDIO Clock Generator Architecture If the rate of transmit pulse interrupt inputs is much less than the target tra[...]

www.ti.com 2.7.1.2 Global PHY Detection and Link State Monitoring 2.7.1.3 Active PHY Monitoring 2.7.1.4 PHY Register User Access 2.7.2 MDIO Module Operational Overview Architecture The MDIO module continuously polls all 32 MDIO addresses in order to enumerate the PHY devices in the system. The module tracks whether or not a PHY on a particular addr[...]

www.ti.com 2.7.2.1 Initializing the MDIO Module 2.7.2.2 Writing Data To a PHY Register 2.7.2.3 Reading Data From a PHY Register Architecture A round-robin arbitration scheme is used to schedule transactions that may be queued using both USERACCESS0 and USERACCESS1. The application software must check the status of the GO bit in USERACCESS n before [...]

www.ti.com 2.7.2.4 Example of MDIO Register Access Code Architecture The MDIO module uses the MDIO user access register (USERACCESS n ) to access the PHY control registers. Software functions that implement the access process may simply be the following four macros: Start the process of reading a PHY register • PHYREG_read( regadr, phyadr ) Start[...]

www.ti.com 2.8 EMAC Module 2.8.1 EMAC Module Components Clock and reset logic Receive DMA engine Interrupt controller Transmit DMA engine Control registers Configuration bus EMAC control module Configuration bus RAM State FIFO Receive FIFO Transmit MAC transmitter Statistics receiver MAC SYNC 2.8.1.1 Receive DMA Engine 2.8.1.2 Receive FIFO Architec[...]

www.ti.com 2.8.1.3 MAC Receiver 2.8.1.4 Receive Address 2.8.1.5 Transmit DMA Engine 2.8.1.6 Transmit FIFO 2.8.1.7 MAC Transmitter 2.8.1.8 Statistics Logic 2.8.1.9 State RAM 2.8.1.10 EMAC Interrupt Controller 2.8.1.11 Control Registers and Logic 2.8.1.12 Clock and Reset Logic Architecture The MAC receiver detects and processes incoming network frame[...]

www.ti.com 2.8.2 EMAC Module Operational Overview Architecture After reset, initialization, and configuration, the application software running on the host may initiate transmit operations. Transmit operations are initiated by host writes to the appropriate transmit channel head descriptor pointer contained in the state RAM block. The transmit DMA [...]

www.ti.com 2.9 Media Independent Interface (MII) 2.9.1 Data Reception 2.9.1.1 Receive Control 2.9.1.2 Receive Inter-Frame Interval 2.9.1.3 Receive Flow Control Architecture The following sections discuss the operation of the Media Independent Interface (MII) in 10 Mbps and 100 Mbps mode. An IEEE 802.3 compliant Ethernet MAC controls the interface. [...]

www.ti.com Architecture 2.9.1.3.1 Collision-Based Receive Buffer Flow Control Collision-based receive buffer flow control provides a means of preventing frame reception when the EMAC is operating in half-duplex mode (the FULLDUPLEX bit is cleared in MACCONTROL). When receive flow control is enabled and triggered, the EMAC generates collisions for r[...]

www.ti.com 2.9.2 Data Transmission 2.9.2.1 Transmit Control 2.9.2.2 CRC Insertion 2.9.2.3 Adaptive Performance Optimization (APO) 2.9.2.4 Interpacket-Gap (IPG) Enforcement 2.9.2.5 Back Off Architecture The EMAC passes data to the PHY from the transmit FIFO (when enabled). Data is synchronized to the transmit clock rate. Transmission begins when the[...]

www.ti.com 2.9.2.6 Transmit Flow Control 2.9.2.7 Speed, Duplex, and Pause Frame Support Architecture Incoming pause frames are acted upon, when enabled, to prevent the EMAC from transmitting any further frames. Incoming pause frames are only acted upon when the FULLDUPLEX and TXFLOWEN bits in the MAC control register (MACCONTROL) are set. Pause fra[...]

www.ti.com 2.10 Packet Receive Operation 2.10.1 Receive DMA Host Configuration 2.10.2 Receive Channel Enabling Architecture To configure the receive DMA for operation the host must: • Initialize the receive addresses. • Initialize the receive channel n DMA head descriptor pointer registers (RX n HDP) to 0. • Write the MAC address hash n regis[...]

www.ti.com 2.10.3 Receive Address Matching 2.10.4 Hardware Receive QOS Support 2.10.5 Host Free Buffer Tracking Architecture The receive address block can store up to 32 addresses to be filtered or matched. Before enabling packet reception, all the address RAM locations should be initialized, including locations to be unused. The system software is[...]

www.ti.com 2.10.6 Receive Channel Teardown 2.10.7 Receive Frame Classification Architecture to the appropriate receive channel n free buffer count registers (RX n FREEBUFFER). The EMAC decrements the appropriate channel’s free buffer value for each buffer used. When the host reclaims the frame buffers, the host should write the channel free buffe[...]

www.ti.com 2.10.8 Promiscuous Receive Mode Architecture When the promiscuous receive mode is enabled by setting the RXCAFEN bit in the receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE), nonaddress matching frames that would normally be filtered are transferred to the promiscuous channel. Address matching frames that woul[...]

www.ti.com 2.10.9 Receive Overrun Architecture Table 6. Receive Frame Treatment Summary (continued) Address Match RXCAFEN RXCEFEN RXCMFEN RXCSFEN Receive Frame Treatment 1 X 1 1 0 Proper/oversize/jabber/code/align/CRC data and control frames transferred to address match channel. No undersized/fragment frames are transferred. 1 X 1 1 1 All address m[...]

www.ti.com 2.11 Packet Transmit Operation 2.11.1 Transmit DMA Host Configuration 2.11.2 Transmit Channel Teardown 2.12 Receive and Transmit Latency Architecture The transmit DMA is an eight channel interface. Priority between the eight queues may be either fixed or round-robin as selected by the TXPTYPE bit in the MAC control register (MACCONTROL).[...]

www.ti.com 2.13 Transfer Node Priority 2.14 Reset Considerations 2.14.1 Software Reset Considerations Architecture Receive overrun is prevented if the receive memory cell latency is less than the time required to transmit a 64-byte cell on the wire (0.512 ms in 1 Gbps mode, 5.12 ms in 100 Mbps mode, or 51.2ms in 10 Mbps mode). The latency time incl[...]

www.ti.com 2.14.2 Hardware Reset Considerations 2.15 Initialization 2.15.1 Enabling the EMAC/MDIO Peripheral 2.15.2 EMAC Control Module Initialization Architecture When a hardware reset occurs, the EMAC peripheral has its register values reset and all the components return to their default state. After the hardware reset, the EMAC needs to be initi[...]

www.ti.com Architecture Example 4. EMAC Control Module Initialization Code Uint32 tmpval ; /* Disable all the EMAC/MDIO interrupts in the control module */ EmacControlRegs->CONTROL.C_RX_EN = 0; EmacControlRegs->CONTROL.C_TX_EN = 0; EmacControlRegs->CONTROL.C_RX_THRESH_EN = 0; EmacControlRegs->CONTROL.C_MISC_EN = 0; /* Wait about 100 cyc[...]

www.ti.com 2.15.3 MDIO Module Initialization Architecture The MDIO module is used to initially configure and monitor one or more external PHY devices. Other than initializing the software state machine (details on this state machine can be found in the IEEE 802.3 standard), all that needs to be done for the MDIO module is to enable the MDIO engine [...]

www.ti.com 2.15.4 EMAC Module Initialization Architecture The EMAC module is used to send and receive data packets over the network. This is done by maintaining up to eight transmit and receive descriptor queues. The EMAC module configuration must also be kept up-to-date based on PHY negotiation results returned from the MDIO module. Most of the wo[...]

www.ti.com 2.16 Interrupt Support 2.16.1 EMAC Module Interrupt Events and Requests EMACcore MDIOcore RXTHRESHOLDPEND(0..7) Receivethresholdinterrupt RXPEND(0..7) Receiveinterrupt TXPEND(0..7) T ransmitinterrupt ST A TPEND HOSTPEND MDIO_USER Miscellaneousinterrupt MDIO_LINKINT Interruptcontrolandpacinglogic 2.16.1.1 [...]

www.ti.com 2.16.1.2 Transmit Packet Completion Interrupts 2.16.1.3 Receive Packet Completion Interrupts Architecture The transmit DMA engine has eight channels, with each channel having a corresponding interrupt (TXPEND n ). The transmit interrupts are level interrupts that remain asserted until cleared by the CPU. Each of the eight transmit channe[...]

www.ti.com 2.16.1.4 Statistics Interrupt 2.16.1.5 Host Error Interrupt Architecture The EMAC write to the completion pointer actually stores the value in the state RAM. The CPU written value does not actually change the register value. The host written value is compared to the register content (which was written by the EMAC) and if the two values a[...]

www.ti.com 2.16.2 MDIO Module Interrupt Events and Requests 2.16.2.1 Link Change Interrupt 2.16.2.2 User Access Completion Interrupt 2.16.3 Proper Interrupt Processing 2.16.4 Interrupt Multiplexing Architecture The MDIO module generates two interrupt events: • LINKINT: Serial interface link change interrupt. Indicates a change in the state of the[...]

www.ti.com 2.17 Power Management 2.18 Emulation Considerations Architecture Each of the three main components of the EMAC peripheral can independently be placed in reduced-power modes to conserve power during periods of low activity. The power management of the EMAC peripheral is controlled by the processor Power and Sleep Controller (PSC). The PSC[...]

www.ti.com 3 EMAC Control Module Registers 3.1 EMAC Control Module Identification and Version Register (CMIDVER) EMAC Control Module Registers Table 9 lists the memory-mapped registers for the EMAC control module. See the device-specific data manual for the memory address of these registers. Table 9. EMAC Control Module Registers Slave VBUS Address[...]

www.ti.com 3.2 EMAC Control Module Software Reset Register (CMSOFTRESET) 3.3 EMAC Control Module Emulation Control Register (CMEMCONTROL) EMAC Control Module Registers The software reset register (CMSOFTRESET) is shown in Figure 14 and described in Table 11 . Figure 14. EMAC Control Module Software Reset Register (CMSOFTRESET) 31 16 Reserved R-0 15[...]

www.ti.com 3.4 EMAC Control Module Interrupt Control Register (CMINTCTRL) EMAC Control Module Registers The interrupt control register (CMINTCTRL) is shown in Figure 16 and described in Table 13 . Figure 16. EMAC Control Module Interrupt Control Register (CMINTCTRL) 31 30 18 17 16 Reserved Reserved INTPACEEN R/W-0 R-0 R/W-0 15 12 11 0 Reserved INTP[...]

www.ti.com 3.5 EMAC Control Module Receive Threshold Interrupt Enable Register 3.6 EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN) EMAC Control Module Registers (CMRXTHRESHINTEN) The receive threshold interrupt enable register (CMRXTHRESHINTEN) is shown in Figure 17 and described in Table 14 . Figure 17. EMAC Control Module Receiv[...]

www.ti.com 3.7 EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN) EMAC Control Module Registers The transmit interrupt enable register (CMTXINTEN) is shown in Figure 19 and described in Table 16 . Figure 19. EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN) 31 16 Reserved R-0 15 8 7 0 Reserved TXPULSEEN R-0 R/W-0 LE[...]

www.ti.com 3.8 EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN) EMAC Control Module Registers The miscellaneous interrupt enable register (CMMISCINTEN) is shown in Figure 20 and described in Table 17 . Figure 20. EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN) 31 16 Reserved R-0 15 4 3 2 1 0 Reserv[...]

www.ti.com 3.9 EMAC Control Module Receive Threshold Interrupt Status Register 3.10 EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT) EMAC Control Module Registers (CMRXTHRESHINTSTAT) The receive threshold interrupt status register (CMRXTHRESHINTSTAT) is shown in Figure 21 and described in Table 18 . Figure 21. EMAC Control Module[...]

www.ti.com 3.11 EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT) EMAC Control Module Registers The transmit interrupt status register (CMTXINTSTAT) is shown in Figure 23 and described in Table 20 . Figure 23. EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT) 31 16 Reserved R-0 15 8 7 0 Reserved TXPULSEINTTSTAT[...]

www.ti.com 3.12 EMAC Control Module Miscellaneous Interrupt Status Register (EWMISCSTAT) EMAC Control Module Registers The miscellaneous interrupt status register (EWMISCSTAT) is shown in Figure 24 and described in Table 21 . Figure 24. EMAC Control Module Miscellaneous Interrupt Status Register (CMMISCINTSTAT) 31 16 Reserved R-0 15 4 3 2 1 0 Reser[...]

www.ti.com 3.13 EMAC Control Module Receive Interrupts per Millisecond Register (CMRXINTMAX) 3.14 EMAC Control Module Transmit Interrupts per Millisecond Register (CMTXINTMAX) EMAC Control Module Registers The receive interrupts per millisecond register (CMRXINTMAX) is shown in Figure 25 and described in Table 22 . Figure 25. EMAC Control Module Re[...]

www.ti.com 4 MDIO Registers 4.1 MDIO Version Register (VERSION) MDIO Registers Table 24 lists the memory-mapped registers for the MDIO module. See the device-specific data manual for the memory address of these registers. Table 24. Management Data Input/Output (MDIO) Registers Offset Acronym Register Description Section 0h VERSION MDIO Version Regi[...]

www.ti.com 4.2 MDIO Control Register (CONTROL) MDIO Registers The MDIO control register (CONTROL) is shown in Figure 28 and described in Table 26 . Figure 28. MDIO Control Register (CONTROL) 31 30 29 28 24 23 21 20 19 18 17 16 IDLE ENABLE Rsvd HIGHEST_USER_CHANNEL Reserved PREAMBLE FAULT FAULTENB Reserved R-1 R/W-0 R-0 R-1 R-0 R/W-0 R/W1C-0 R/W-0 R[...]

www.ti.com 4.3 PHY Acknowledge Status Register (ALIVE) 4.4 PHY Link Status Register (LINK) MDIO Registers The PHY acknowledge status register (ALIVE) is shown in Figure 29 and described in Table 27 . Figure 29. PHY Acknowledge Status Register (ALIVE) 31 16 ALIVE R/W1C-0 15 0 ALIVE R/W1C-0 LEGEND: R/W = Read/Write; W1C = Write 1 to clear, write of 0[...]

www.ti.com 4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) MDIO Registers The MDIO link status change interrupt (unmasked) register (LINKINTRAW) is shown in Figure 31 and described in Table 29 . Figure 31. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) 31 16 Reserved R-0 15 2 1 0 Reserved LINKINTRAW R-0 R/[...]

www.ti.com 4.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) MDIO Registers The MDIO link status change interrupt (masked) register (LINKINTMASKED) is shown in Figure 32 and described in Table 30 . Figure 32. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) 31 16 Reserved R-0 15 2 1 0 Reserved LINKINTMASKED [...]

www.ti.com 4.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) MDIO Registers The MDIO user command complete interrupt (unmasked) register (USERINTRAW) is shown in Figure 33 and described in Table 31 . Figure 33. MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) 31 16 Reserved R-0 15 2 1 0 Reserved USERINTR[...]

www.ti.com 4.8 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) MDIO Registers The MDIO user command complete interrupt (masked) register (USERINTMASKED) is shown in Figure 34 and described in Table 32 . Figure 34. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) 31 16 Reserved R-0 15 2 1 0 Reserved USERI[...]

www.ti.com 4.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) MDIO Registers The MDIO user command complete interrupt mask set register (USERINTMASKSET) is shown in Figure 35 and described in Table 33 . Figure 35. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) 31 16 Reserved R-0 15 2 1 0 Reserved US[...]

www.ti.com 4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) MDIO Registers The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in Figure 36 and described in Table 34 . Figure 36. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) 31 16 Reserved R-0 15 2 1 [...]

www.ti.com 4.11 MDIO User Access Register 0 (USERACCESS0) MDIO Registers The MDIO user access register 0 (USERACCESS0) is shown in Figure 37 and described in Table 35 . Figure 37. MDIO User Access Register 0 (USERACCESS0) 31 30 29 28 26 25 21 20 16 GO WRITE ACK Reserved REGADR PHYADR R/W1S-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 15 0 DATA R/W-0 LEGEND: R = R[...]

www.ti.com 4.12 MDIO User PHY Select Register 0 (USERPHYSEL0) MDIO Registers The MDIO user PHY select register 0 (USERPHYSEL0) is shown in Figure 38 and described in Table 36 . Figure 38. MDIO User PHY Select Register 0 (USERPHYSEL0) 31 16 Reserved R-0 15 8 7 6 5 4 0 Reserved LINKSEL LINKINTENB Rsvd PHYADRMON R-0 R/W-0 R/W-0 R-0 R/W-0 LEGEND: R/W =[...]

www.ti.com 4.13 MDIO User Access Register 1 (USERACCESS1) MDIO Registers The MDIO user access register 1 (USERACCESS1) is shown in Figure 39 and described in Table 37 . Figure 39. MDIO User Access Register 1 (USERACCESS1) 31 30 29 28 26 25 21 20 16 GO WRITE ACK Reserved REGADR PHYADR R/W1S-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 15 0 DATA R/W-0 LEGEND: R = R[...]

www.ti.com 4.14 MDIO User PHY Select Register 1 (USERPHYSEL1) MDIO Registers The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 40 and described in Table 38 . Figure 40. MDIO User PHY Select Register 1 (USERPHYSEL1) 31 16 Reserved R-0 15 8 7 6 5 4 0 Reserved LINKSEL LINKINTENB Rsvd PHYADRMON R-0 R/W-0 R/W-0 R-0 R/W-0 LEGEND: R/W =[...]

www.ti.com 5 Ethernet Media Access Controller (EMAC) Registers Ethernet Media Access Controller (EMAC) Registers Table 39 lists the memory-mapped registers for the EMAC. See the device-specific data manual for the memory address of these registers. Table 39. Ethernet Media Access Controller (EMAC) Registers Offset Acronym Register Description Secti[...]

www.ti.com Ethernet Media Access Controller (EMAC) Registers Table 39. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description Section 164h MACSTATUS MAC Status Register Section 5.30 168h EMCONTROL Emulation Control Register Section 5.31 16Ch FIFOCONTROL FIFO Control Register Section 5.32 170h MACCONFIG MAC[...]

www.ti.com Ethernet Media Access Controller (EMAC) Registers Table 39. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description Section 678h RX6CP Receive Channel 6 Completion Pointer Register Section 5.49 67Ch RX7CP Receive Channel 7 Completion Pointer Register Section 5.49 Network Statistics Registers 200h[...]

www.ti.com 5.1 Transmit Identification and Version Register (TXIDVER) 5.2 Transmit Control Register (TXCONTROL) Ethernet Media Access Controller (EMAC) Registers The transmit identification and version register (TXIDVER) is shown in Figure 41 and described in Table 40 . Figure 41. Transmit Identification and Version Register (TXIDVER) 31 16 TXIDENT[...]

www.ti.com 5.3 Transmit Teardown Register (TXTEARDOWN) Ethernet Media Access Controller (EMAC) Registers The transmit teardown register (TXTEARDOWN) is shown in Figure 43 and described in Table 42 . Figure 43. Transmit Teardown Register (TXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved TXTDNCH R-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; - n [...]

www.ti.com 5.4 Receive Identification and Version Register (RXIDVER) 5.5 Receive Control Register (RXCONTROL) Ethernet Media Access Controller (EMAC) Registers The receive identification and version register (RXIDVER) is shown in Figure 44 and described in Table 43 . Figure 44. Receive Identification and Version Register (RXIDVER) 31 16 RXIDENT R-0[...]

www.ti.com 5.6 Receive Teardown Register (RXTEARDOWN) Ethernet Media Access Controller (EMAC) Registers The receive teardown register (RXTEARDOWN) is shown in Figure 46 and described in Table 45 . Figure 46. Receive Teardown Register (RXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved RXTDNCH R-0 R/W-0 LEGEND: R = Read only; R/W = Read/Write; - n = v[...]

www.ti.com 5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Ethernet Media Access Controller (EMAC) Registers The transmit interrupt status (unmasked) register (TXINTSTATRAW) is shown in Figure 47 and described in Table 46 . Figure 47. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) 31 16 Reserved R-0 15 8 Reserved R-0 [...]

www.ti.com 5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Ethernet Media Access Controller (EMAC) Registers The transmit interrupt status (masked) register (TXINTSTATMASKED) is shown in Figure 48 and described in Table 47 . Figure 48. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) 31 16 Reserved R-0 15 8 Reserved R[...]

www.ti.com 5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET) Ethernet Media Access Controller (EMAC) Registers The transmit interrupt mask set register (TXINTMASKSET) is shown in Figure 49 and described in Table 48 . Figure 49. Transmit Interrupt Mask Set Register (TXINTMASKSET) 31 16 Reserved R-0 15 8 Reserved R-0 76543210 TX7MASK TX6MASK TX[...]

www.ti.com 5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Ethernet Media Access Controller (EMAC) Registers The transmit interrupt mask clear register (TXINTMASKCLEAR) is shown in Figure 50 and described in Table 49 . Figure 50. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) 31 16 Reserved R-0 15 8 Reserved R-0 76543210 TX7MA[...]

www.ti.com 5.11 MAC Input Vector Register (MACINVECTOR) 5.12 MAC End Of Interrupt Vector Register (MACEOIVECTOR) Ethernet Media Access Controller (EMAC) Registers The MAC input vector register (MACINVECTOR) is shown in Figure 51 and described in Table 50 . Figure 51. MAC Input Vector Register (MACINVECTOR) 31 28 27 26 25 24 23 16 Reserved STATPEND [...]

www.ti.com 5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Ethernet Media Access Controller (EMAC) Registers The receive interrupt status (unmasked) register (RXINTSTATRAW) is shown in Figure 53 and described in Table 52 . Figure 53. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) 31 16 Reserved R-0 15 8 Reserved R-0 76[...]

www.ti.com 5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Ethernet Media Access Controller (EMAC) Registers The receive interrupt status (masked) register (RXINTSTATMASKED) is shown in Figure 54 and described in Table 53 . Figure 54. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) 31 16 Reserved R-0 15 8 Reserved R-0[...]

www.ti.com 5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) Ethernet Media Access Controller (EMAC) Registers The receive interrupt mask set register (RXINTMASKSET) is shown in Figure 55 and described in Table 54 . Figure 55. Receive Interrupt Mask Set Register (RXINTMASKSET) 31 16 Reserved R-0 15 8 Reserved R-0 76543210 RX7MASK RX6MASK RX5M[...]

www.ti.com 5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Ethernet Media Access Controller (EMAC) Registers The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 56 and described in Table 55 . Figure 56. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) 31 16 Reserved R-0 15 8 Reserved R-0 76543210 RX7MASK [...]

www.ti.com 5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) 5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Ethernet Media Access Controller (EMAC) Registers The MAC interrupt status (unmasked) register (MACINTSTATRAW) is shown in Figure 57 and described in Table 56 . Figure 57. MAC Interrupt Status (Unmasked) Register ([...]

www.ti.com 5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) 5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Ethernet Media Access Controller (EMAC) Registers The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure 59 and described in Table 58 . Figure 59. MAC Interrupt Mask Set Register (MACINTMASKSET) 31 16 Reserved R-0[...]

www.ti.com 5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Ethernet Media Access Controller (EMAC) Registers The receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) is shown in Figure 61 and described in Table 60 . Figure 61. Receive Multicast/Broadcast/Promiscuous Channel Enable Register[...]

www.ti.com Ethernet Media Access Controller (EMAC) Registers Table 60. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions (continued) Bit Field Value Description 22 RXCEFEN Receive copy error frames enable bit. Enables frames containing errors to be transferred to memory. The appropriate error bit will [...]

www.ti.com Ethernet Media Access Controller (EMAC) Registers Table 60. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions (continued) Bit Field Value Description 2-0 RXMULTCH 0-7h Receive multicast channel select 0 Select channel 0 to receive multicast frames 1h Select channel 1 to receive multicast fra[...]

www.ti.com 5.22 Receive Unicast Enable Set Register (RXUNICASTSET) Ethernet Media Access Controller (EMAC) Registers The receive unicast enable set register (RXUNICASTSET) is shown in Figure 62 and described in Table 61 . Figure 62. Receive Unicast Enable Set Register (RXUNICASTSET) 31 16 Reserved R-0 15 8 Reserved R-0 76543210 RXCH7EN RXCH6EN RXCH[...]

www.ti.com 5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) Ethernet Media Access Controller (EMAC) Registers The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 63 and described in Table 62 . Figure 63. Receive Unicast Clear Register (RXUNICASTCLEAR) 31 16 Reserved R-0 15 8 Reserved R-0 76543210 RXCH7EN RXCH6EN RXCH5EN RXCH4[...]

www.ti.com 5.24 Receive Maximum Length Register (RXMAXLEN) 5.25 Receive Buffer Offset Register (RXBUFFEROFFSET) Ethernet Media Access Controller (EMAC) Registers The receive maximum length register (RXMAXLEN) is shown in Figure 64 and described in Table 63 . Figure 64. Receive Maximum Length Register (RXMAXLEN) 31 16 Reserved R-0 15 0 RXMAXLEN R/W-[...]

www.ti.com 5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) 5.27 Receive Channel 0-7 Flow Control Threshold Register (RX nFLOWTHRESH) Ethernet Media Access Controller (EMAC) Registers The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) is shown in Figure 66 and described in Table 65 . Figure 66.[...]

www.ti.com 5.28 Receive Channel 0-7 Free Buffer Count Register (RX nFREEBUFFER) Ethernet Media Access Controller (EMAC) Registers The receive channel 0-7 free buffer count register (RX n FREEBUFFER) is shown in Figure 68 and described in Table 67 . Figure 68. Receive Channel n Free Buffer Count Register (RX n FREEBUFFER) 31 16 Reserved R-0 15 0 RX [...]

www.ti.com 5.29 MAC Control Register (MACCONTROL) Ethernet Media Access Controller (EMAC) Registers The MAC control register (MACCONTROL) is shown in Figure 69 and described in Table 68 . Figure 69. MAC Control Register (MACCONTROL) 31 18 17 16 Reserved GIGFORCE Reserved R-0 R/W-0 R-0 15 14 13 12 11 10 9 8 Reserved RXOFFLENBLOCK RXOWNERSHIP RXFIFOF[...]

www.ti.com Ethernet Media Access Controller (EMAC) Registers Table 68. MAC Control Register (MACCONTROL) Field Descriptions (continued) Bit Field Value Description 5 GMIIEN GMII enable bit. 0 GMII RX and TX are held in reset. 1 GMII RX and TX are enabled for receive and transmit. 4 TXFLOWEN Transmit flow control enable bit. This bit determines if i[...]

www.ti.com 5.30 MAC Status Register (MACSTATUS) Ethernet Media Access Controller (EMAC) Registers The MAC status register (MACSTATUS) is shown in Figure 70 and described in Table 69 . Figure 70. MAC Status Register (MACSTATUS) 31 30 24 23 20 19 18 16 IDLE Reserved TXERRCODE Rsvd TXERRCH R-0 R-0 R-0 R-0 R-0 15 12 11 10 8 RXERRCODE Reserved RXERRCH R[...]

www.ti.com Ethernet Media Access Controller (EMAC) Registers Table 69. MAC Status Register (MACSTATUS) Field Descriptions (continued) Bit Field Value Description 10-8 RXERRCH 0-3h Receive host error channel. These bits indicate which receive channel the host error occurred on. This field is cleared to 0 on a host read. 0 The host error occurred on [...]

www.ti.com 5.31 Emulation Control Register (EMCONTROL) 5.32 FIFO Control Register (FIFOCONTROL) Ethernet Media Access Controller (EMAC) Registers The emulation control register (EMCONTROL) is shown in Figure 71 and described in Table 70 . Figure 71. Emulation Control Register (EMCONTROL) 31 16 Reserved R-0 15 2 1 0 Reserved SOFT FREE R-0 R/W-0 R/W-[...]

www.ti.com 5.33 MAC Configuration Register (MACCONFIG) 5.34 Soft Reset Register (SOFTRESET) Ethernet Media Access Controller (EMAC) Registers The MAC configuration register (MACCONFIG) is shown in Figure 73 and described in Table 72 . Figure 73. MAC Configuration Register (MACCONFIG) 31 24 23 16 TXCELLDEPTH RXCELLDEPTH R-18h R-44h 15 8 7 0 ADDRESST[...]

www.ti.com 5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) 5.36 MAC Source Address High Bytes Register (MACSRCADDRHI) Ethernet Media Access Controller (EMAC) Registers The MAC source address low bytes register (MACSRCADDRLO) is shown in Figure 75 and described in Table 74 . Figure 75. MAC Source Address Low Bytes Register (MACSRCADDRLO) 3[...]

www.ti.com 5.37 MAC Hash Address Register 1 (MACHASH1) 5.38 MAC Hash Address Register 2 (MACHASH2) Ethernet Media Access Controller (EMAC) Registers The MAC hash registers allow group addressed frames to be accepted on the basis of a hash function of the address. The hash function creates a 6-bit data value (Hash_fun) from the 48-bit destination ad[...]

www.ti.com 5.39 Back Off Test Register (BOFFTEST) 5.40 Transmit Pacing Algorithm Test Register (TPACETEST) Ethernet Media Access Controller (EMAC) Registers The back off test register (BOFFTEST) is shown in Figure 79 and described in Table 78 . Figure 79. Back Off Random Number Generator Test Register (BOFFTEST) 31 26 25 16 Reserved RNDNUM R-0 R-0 [...]

www.ti.com 5.41 Receive Pause Timer Register (RXPAUSE) 5.42 Transmit Pause Timer Register (TXPAUSE) Ethernet Media Access Controller (EMAC) Registers The receive pause timer register (RXPAUSE) is shown in Figure 81 and described in Table 80 . Figure 81. Receive Pause Timer Register (RXPAUSE) 31 16 Reserved R-0 15 0 PAUSETIMER R-0 LEGEND: R = Read o[...]

www.ti.com 5.43 MAC Address Low Bytes Register (MACADDRLO) Ethernet Media Access Controller (EMAC) Registers The MAC address low bytes register used in address matching (MACADDRLO), is shown in Figure 83 and described in Table 82 . Figure 83. MAC Address Low Bytes Register (MACADDRLO) 31 21 20 19 18 16 Reserved VALID MATCHFILT CHANNEL R-0 R/W-x R/W[...]

www.ti.com 5.44 MAC Address High Bytes Register (MACADDRHI) 5.45 MAC Index Register (MACINDEX) Ethernet Media Access Controller (EMAC) Registers The MAC address high bytes register (MACADDRHI) is shown in Figure 84 and described in Table 83 . Figure 84. MAC Address High Bytes Register (MACADDRHI) 31 24 23 16 MACADDR2 MACADDR3 R/W-0 R/W-0 15 8 7 0 M[...]

www.ti.com 5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TX nHDP) 5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RX nHDP) Ethernet Media Access Controller (EMAC) Registers The transmit channel 0-7 DMA head descriptor pointer register (TX n HDP) is shown in Figure 86 and described in Table 85 . Figure 86. Transmit C[...]

www.ti.com 5.48 Transmit Channel 0-7 Completion Pointer Register (TX nCP) 5.49 Receive Channel 0-7 Completion Pointer Register (RX nCP) Ethernet Media Access Controller (EMAC) Registers The transmit channel 0-7 completion pointer register (TX n CP) is shown in Figure 88 and described in Table 87 . Figure 88. Transmit Channel n Completion Pointer Re[...]

www.ti.com 5.50 Network Statistics Registers 5.50.1 Good Receive Frames Register (RXGOODFRAMES) 5.50.2 Broadcast Receive Frames Register (RXBCASTFRAMES) 5.50.3 Multicast Receive Frames Register (RXMCASTFRAMES) Ethernet Media Access Controller (EMAC) Registers The EMAC has a set of statistics that record events associated with frame traffic. The sta[...]

www.ti.com 5.50.4 Pause Receive Frames Register (RXPAUSEFRAMES) 5.50.5 Receive CRC Errors Register (RXCRCERRORS) 5.50.6 Receive Alignment/Code Errors Register (RXALIGNCODEERRORS) 5.50.7 Receive Oversized Frames Register (RXOVERSIZED) Ethernet Media Access Controller (EMAC) Registers The total number of IEEE 802.3X pause frames received by the EMAC [...]

www.ti.com 5.50.8 Receive Jabber Frames Register (RXJABBER) 5.50.9 Receive Undersized Frames Register (RXUNDERSIZED) 5.50.10 Receive Frame Fragments Register (RXFRAGMENTS) 5.50.11 Filtered Receive Frames Register (RXFILTERED) Ethernet Media Access Controller (EMAC) Registers See Section 2.5.5 for definitions of alignment, code, and CRC errors. Over[...]

www.ti.com 5.50.12 Receive QOS Filtered Frames Register (RXQOSFILTERED) 5.50.13 Receive Octet Frames Register (RXOCTETS) 5.50.14 Good Transmit Frames Register (TXGOODFRAMES) 5.50.15 Broadcast Transmit Frames Register (TXBCASTFRAMES) Ethernet Media Access Controller (EMAC) Registers To determine the number of receive frames discarded by the EMAC for[...]

www.ti.com 5.50.16 Multicast Transmit Frames Register (TXMCASTFRAMES) 5.50.17 Pause Transmit Frames Register (TXPAUSEFRAMES) 5.50.18 Deferred Transmit Frames Register (TXDEFERRED) 5.50.19 Transmit Collision Frames Register (TXCOLLISION) 5.50.20 Transmit Single Collision Frames Register (TXSINGLECOLL) Ethernet Media Access Controller (EMAC) Register[...]

www.ti.com 5.50.21 Transmit Multiple Collision Frames Register (TXMULTICOLL) 5.50.22 Transmit Excessive Collision Frames Register (TXEXCESSIVECOLL) 5.50.23 Transmit Late Collision Frames Register (TXLATECOLL) 5.50.24 Transmit Underrun Error Register (TXUNDERRUN) 5.50.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE) Ethernet Media Access C[...]

www.ti.com 5.50.26 Transmit Octet Frames Register (TXOCTETS) 5.50.27 Transmit and Receive 64 Octet Frames Register (FRAME64) 5.50.28 Transmit and Receive 65 to 127 Octet Frames Register (FRAME65T127) 5.50.29 Transmit and Receive 128 to 255 Octet Frames Register (FRAME128T255) 5.50.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T5[...]

www.ti.com 5.50.31 Transmit and Receive 512 to 1023 Octet Frames Register (FRAME512T1023) 5.50.32 Transmit and Receive 1024 to RXMAXLEN Octet Frames Register (FRAME1024TUP) 5.50.33 Network Octet Frames Register (NETOCTETS) 5.50.34 Receive FIFO or DMA Start of Frame Overruns Register (RXSOFOVERRUNS) Ethernet Media Access Controller (EMAC) Registers [...]

www.ti.com 5.50.35 Receive FIFO or DMA Middle of Frame Overruns Register (RXMOFOVERRUNS) 5.50.36 Receive DMA Overruns Register (RXDMAOVERRUNS) Ethernet Media Access Controller (EMAC) Registers The total number of frames received on the EMAC that had either a FIFO or DMA middle of frame (MOF) overrun. An MOF overrun frame is defined as having all of[...]

www.ti.com Appendix A Glossary Appendix A Broadcast MAC Address— A special Ethernet MAC address used to send data to all Ethernet devices on the local network. The broadcast address is FFh-FFh-FFh-FFh-FFh-FFh. The LSB of the first byte is odd, qualifying it as a group address; however, its value is reserved for broadcast. It is classified separat[...]

www.ti.com Appendix A Link— The transmission path between any two instances of generic cabling. Multicast MAC Address— A class of MAC address that sends a packet to potentially more than one recipient. A group address is specified by setting the LSB of the first MAC address byte to 1. Thus, 01h-02h-03h-04h-05h-06h is a valid multicast address. [...]

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