Cypress CY7C67200 manuel d'utilisation

EZ-OTG™ Programmable USB On-The-Go CY7C67200 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-08014 Rev . *G Revised November 14, 2006 EZ-OTG Features • Single-chip programmable USB du al-role (Host/Peripheral) controller with two configurable Serial Interface Engines (SIEs) [...]

CY7C67200 Document #: 38-08014 Rev . *G Page 2 of 78 Introduction EZ-OTG™ (CY7C67200) is Cypress Semiconductor ’s first USB On-The-Go (OTG) host/periphera l controller . EZ-OT G is designed to easi ly interface to most high-performance CPUs to add USB host functionality . EZ-OTG has its own 16-bit RISC processor to act as a coprocessor or opera[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 3 of 78 USB Interface EZ-OTG has two built-in Host/P eripheral SIEs that each have a single USB transceiver , mee ting the USB 2 .0 specifica tion requirements for full and l ow speed (high spee d is not support- e d) . In H os t mo d e, E Z- O TG s upp ort s two downstream ports; each supports control, [...]

CY7C67200 Document #: 38-08014 Rev . *G Page 4 of 78 UART Features • Supports baud rates of 900 to 1 15.2K •8 - N - 1 UART Pins I 2 C EEPROM Interface EZ-OTG provides a master-onl y I2C interface for extern al se- rial EEPROMs. The serial EEPROM can be used to store ap- plication-specific code and data. This I2C inte rface is only to be used fo[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 5 of 78 Host Port Interface (HPI) EZ-OTG has an HPI interface. The HPI interface provides DMA access to the EZ-OTG internal memory by an external host, plus a bidirectional mailbox regi ster for supporting high-level communication proto cols. This port is designed to be the primary high -speed conne ctio[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 6 of 78 Charge Pump Features • Meets OTG Supplement Requirements, see T able 41, “DC Characteristics: Charge Pump,” on page 66 . Charge Pump Pins Booster Interface EZ-OTG has an on-chip pow er booster circuit for use with power supplies that range between 2.7V and 3.6V . The booster circuit boosts [...]

CY7C67200 Document #: 38-08014 Rev . *G Page 7 of 78 Crystal Pins Boot Configuration Interface EZ-OTG can boot into any one of four modes. T he mode it boots into is determined by the TT L voltage level of GPIO[31:30] at the time nRESET is deasserted. Ta b l e 1 4 shows the dif ferent bo ot pin combinat ions possible . After a reset pin event occur[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 8 of 78 Minimum Hardware Require ments for St andalone Mode – Periphera l Only Power Savings and Reset Description The EZ-OTG modes and reset condi tions are described in this section. Power Savings Mode Descr iption EZ-OTG has one main power savi ngs mode, Sleep. For detailed information on Sle ep mod[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 9 of 78 External (Remote) Wakeup Source There are several po ssi ble events available to w ake EZ-OTG from Sleep mode as shown in Ta b l e 1 5 . These may also be used as remote wakeup options fo r USB applications. See section “Power Control Register [0xC00A] [R/W]” on page 13 . Upon wakeup, co de b[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 10 of 78 Registers Some registers have different functions for a read vs. a wri te access or USB host vs. U SB de vice mode. Ther efore, registers of this type have multi ple definitions for the same address. The default registe r values listed in this data sheet may be altered to some other value during[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 1 1 of 78 Bank Register [0xC002] [R /W ] Figure 8. Bank Register Register Descrip tion The Bank regi ster map s registers R 0–R15 into RAM. The eleven MSBs of this reg ister are used as a base ad dress for registers R0–R15. A register address is automatically generated by: 1. Shifting the four LSBs o[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 12 of 78 CPU Speed Registe r [0xC008] [R/W] Figure 10. CPU Speed Register Register Descrip tion The CPU S peed register allows the pr ocessor to operate at a user se lected speed. This re gister on ly affects the CPU; all other peripheral timing is still based on the 48 -MHz system cl ock (unless otherwi[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 13 of 78 Power Control Registe r [0xC00A] [R/W] Figure 1 1. Power Control Register Register Descrip tion The Power Control register controls the power-down and wakeup options. Either the sleep mod e or the halt mode options can be selected. All other writable bits in this register can be used as a wakeup[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 14 of 78 Halt Enable (Bit 0) Setting this bit to ‘1’ immediately initiates HAL T mode. While in HAL T mode, only the CPU is stopped. T he internal clock still runs and all peripheral s still operate, including the U SB engines. The power sa vings using HAL T in most cases will be minimal, but in appl[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 15 of 78 UART Interrupt Enable (Bit 3) The UART Interrupt Enable bit enables or di sables the following UART hardware interrupts: UAR T T X and UART RX. 1: Enable UART interrupt 0: Disable UART interrupt GPIO Interrupt Enable (Bit 2) The GPIO Interrupt Enable bit ena bles or disables the Gen eral Purpose[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 16 of 78 USB Diagnostic Register [0xC03C] [R/W] Figure 14. USB Diagnostic Register Register Descrip tion The USB Diagnostic Register provides control o f diagnostic modes. It is inte nded for use by device chara cterization tests, not for normal operations. Th is register is Read/Write by the on-chip CPU[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 17 of 78 Watchdog Timer Register [0xC00C] [R/W] Figure 15. W atchdog Timer Register Register Descrip tion The W atchdog T imer register prov ides status and control over the W atchdog timer . The Watchdog timer can also interrupt the processor . Tim eo ut F l a g (Bit 5) The T imeout Flag bit indicates i[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 18 of 78 Timer n Register [R/W] • T i mer 0 Re gister 0xC010 • T i mer 1 Re gister 0xC012 Figure 16. T imer n Register Register Descrip tion The T imer n Register sets the Timer n count. Both T imer 0 and T i mer 1 decremen t by one every 1-µs clock tick. Each can provide an interrupt to the CPU whe[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 19 of 78 Port A D+ St atus (Bit 13) The Port A D+ S tatus bit is a read-only bit that indicates the value of DA T A+ on Port A. 1: D+ is high 0: D+ is low Port A D– St atus (Bit 12) The Port A D– S tatus bit is a read-only bit that indicates the value of DA T A– on Port A. 1: D– is high 0: D– i[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 20 of 78 Host n Control Register [R/W] • Host 1 Control Register 0xC080 • Host 2 Control Register 0xC0A0 Figure 18. Host n Control Register Register Descrip tion The Host n Control regi ster allows high-level USB transaction control. Preamble Enab le (Bit 7) The Preamble Enable bi t enables or disabl[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 21 of 78 Host n Address Register [R/W] • Host 1 Ad dress Regi ster 0xC0 82 • Host 2 Ad dress Regi ster 0xC0A2 Figure 19. Host n Address Reg ister Register Descrip tion The Host n Address register is used as the ba se pointer into memory space for the cur r ent host transactions. Address (Bits [15:0])[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 22 of 78 Host n Endpoint S tatus Register [R] • Host 1 Endpoint S tatus Register 0xC086 • Host 2 Endpoint S tatus Register 0xC0A6 Figure 21. Host n End p oint St atus Registe r Register Descrip tion The Host n Endpoint S tatus register is a re ad-only register that provides st atus for the last USB t[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 23 of 78 ACK Flag (Bit 0) The ACK Flag bit indicates two different conditions depending on the transfer type. For non-Isochro nous transfers, this bit represents a transaction endin g by receiving or sending an ACK packet. For Isochronous tran sfers, this bit represents a successful transaction that wil [...]

CY7C67200 Document #: 38-08014 Rev . *G Page 24 of 78 Host n Count Result Register [R] • Host 1 Count Result Register 0xC088 • Host 2 Count Result Register 0xC0A8 Figure 23. Host n Count Result Register Register Descrip tion The Host n Count Resu lt register is a re ad-only register th at contains the size difference in bytes between the H ost [...]

CY7C67200 Document #: 38-08014 Rev . *G Page 25 of 78 Host n Interrupt Enable Register [R/W] • Host 1 Interrupt Enable Register 0xC08C • Host 2 Interrupt Enable Register 0xC0AC Figure 25. Host n Interrupt Enable Register Register Descrip tion The Host n Inte rrupt Enable register allow s control over host-related interrupts. In this register a [...]

CY7C67200 Document #: 38-08014 Rev . *G Page 26 of 78 Host n St atus Register [R/W] • Host 1 S tatus Register 0xC090 • Host 2 S t atus Regi ster 0xC0B0 Figure 26. Host n S t atus Regis ter Register Descrip tion The Host n S tatus register prov ides status information for host operation. Pending interrupts can be cleared by writi ng a ‘1’ to[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 27 of 78 Host n SOF/EOP Count Register [R/W] • Host 1 SOF/EOP Count Register 0xC092 • Host 2 SOF/EOP Count Register 0xC0B2 Figure 27. Host n SOF/EOP Co unt Register Register Descrip tion The Host n SOF/EOP Count regi ster contains the SOF/EOP Count V alue that is loaded into the SOF/EOP counter . Thi[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 28 of 78 Host n Frame Register [R] • Host 1 Frame Register 0xC096 • Host 2 Frame Register 0xC0B6 Figure 29. Host n Fra me Register Register Descrip tion The Host n Frame register ma intains the ne xt frame number to be transm itted (c urrent fr ame number + 1). This value is updated after each SOF tr[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 29 of 78 Figure 30. Device n Endpoint n Control Register Register Descrip tion The Device n Endpoint n Control re gister provides control ove r a single EP in device mode. There are a total of eight endpoints for each of the two ports. All endpoints have the same definition for their Device n Endpoint n [...]

CY7C67200 Document #: 38-08014 Rev . *G Page 30 of 78 Device n Endpoint n Address Register [R/W] • Device n Endpoint 0 Address Register [D evice 1: 0x0202 Device 2: 0x0282] • Device n Endpoint 1 Address Register [D evice 1: 0x0212 Device 2: 0x0292] • Device n Endpoint 2 Address Register [D evice 1: 0x0222 Device 2: 0x02A2] • Device n Endpoi[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 31 of 78 Register Descrip tion The Device n Endpoint n Count register desi gnates the maximum pa cket size that can be received fr om the host for OUT transfers for a single endpoint. This register also designates the packet size to be sent to the host in response to the next IN token fo r a single endpo[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 32 of 78 I N Exception Fl ag (Bit 8) The IN Exception Flag bit indicates whe n the d evice received an IN packet when armed fo r an OUT . 1: Received IN when armed for OUT 0: Received OUT when armed for OUT Stall F la g (Bit 7) The S tall Flag bit indi cates that a S tall packet was sent to the host. 1: [...]

CY7C67200 Document #: 38-08014 Rev . *G Page 33 of 78 Device n Endpoint n Count Result Register [R/W] • Device n Endpoint 0 Count Result Register [Device 1: 0x0208 Device 2: 0x0288] • Device n Endpoint 1 Count Result Register [Device 1: 0x0218 Device 2: 0x0298] • Device n Endpoint 2 Count Result Register [Device 1: 0x0228 Device 2: 0x02A8] ?[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 34 of 78 Device n Interrupt Ena ble Register [R/W] • Device 1 Interrupt Enable Re gister 0xC08C • Device 2 Interrupt Enable Re gister 0xC0AC Figure 35. Device n Interrupt Enable Register Register Descrip tion The Device n Interrupt Enable re gister provides control ove r device-related inte rrupts in[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 35 of 78 EP5 Interrupt Enable (Bit 5) The EP5 Interrupt Enable bit en ables or disables an en dpoint five (EP5) T ransaction Done interrupt. An EPx Transaction Done interrupt triggers when any of the foll owing responses or events occur in a transaction for the devi ce’s given Endpoint: send/receive AC[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 36 of 78 Device n Address Register [W] • Device 1 Address Register 0xC08E • Device 2 Address Register 0xC0AE Figure 36. Device n Add ress Register Register Descrip tion The Device n Address register hold s the device address assigned by the host. T his register initializes to the default address 0 at[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 37 of 78 Reset Interrupt Flag (Bit 8) The Reset Interrupt Flag b it indicates if th e USB Reset Detected interrupt has triggered. 1: Interrupt triggered 0: Interrupt did not trigger EP7 Interrupt Flag (Bit 7) The EP7 Interrupt Flag bit indicates if the endpoint seven (EP7) T ransaction Done in terrupt ha[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 38 of 78 Device n Frame Number Register [R] • Device 1 Frame Number Register 0xC092 • Device 2 Frame Number Register 0xC0B2 Figure 38. Device n Frame Number Regis ter Register Descrip tion The Device n Frame Number register is a re ad only register that contains the Frame number of the l ast SOF pack[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 39 of 78 OTG Control Registers There is one register dedicat ed for OTG operation. This register is covered in this se ction and summarized in Ta b l e 2 8 . OTG Control Register [0xC098] [R/W] Figure 40. OTG Contro l Regist er Register Descrip tion The OTG Control register allows control and mo nitoring[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 40 of 78 VBUS V alid Flag (Bit 0) The VBUS V alid Flag bit indicates whether OTG VBus is greater than 4.4V . Af ter turning on VBUS, firmware should wait at least 10 µs before this reading this bit. 1: OTG VBus is greater then 4 .4V 0: OTG VBus is less then 4.4V Reserved All reserved bits must be writte[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 41 of 78 HSS Enable (Bit 7) The HSS Enable bit routes HSS to GPIO[15:12]. 1: HSS is routed to GPIO 0: HSS is not r outed to GPIOs. GPIO[15:12] are free for other purposes . SPI Enable (Bit 5) The SPI Enable bit routes SPI to GPIO[1 1:8]. If the SAS Enable bit is set, it overrides and ro utes the SPI_nSSI[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 42 of 78 Writing a 1 to any bit will output a high voltage on the corresponding GPIO pin. Reserved All reserved bits must be written as ‘0’. GPIO 0 Input Data Register [0xC020] [R] Figure 44. GPIO 0 Input Data Register Register Descrip tion The GPIO 0 Input Data register re ads the input data of the [...]

CY7C67200 Document #: 38-08014 Rev . *G Page 43 of 78 Register Descrip tion The GPIO 0 Direction register controls the d irection of the GPIO data pins (input/out put). The GPI O 0 Di rec tion reg iste r cont ro ls GPIO15 to GPIO0 while the GPIO 1 Directi on register controls GPIO31 to GPIO19. When any bit of this register is set to ‘1’, the co[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 44 of 78 HSS Control Register [0xC070] [R /W ] Figure 48. HSS Control Register Register Descrip tion The HSS Control register pr ovides high-le vel status and control over the H SS por t. HSS Enable (Bit 15) The HSS Enable bit enables or disables HSS operation. 1: Enables HSS operation 0: Disables HSS op[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 45 of 78 T ransmit Read y (Bit 4) The T ransmit Ready bit i s a read only bit that indicates if the HSS T ra nsmit FIFO is ready for the CPU to load new data for transmission. 1: HSS transmit FIFO ready for loading 0: HSS transmit FIFO not ready for loading Packet Mode Select (Bit 3) The Packet Mode Sele[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 46 of 78 HSS T ransmit Gap Regist er [0xC074] [R/W] Figure 50. HSS T ra nsmit Gap Regis t er Register Descrip tion The HSS Transmit Gap register is only valid in block transmit mo de. It allow s for a programmable number of stop bits to be inse rted thus overwriting the One Stop Bit in the H SS Control r[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 47 of 78 HSS Receive Address Register [0xC078] [R/W] Figure 52 . HSS Recei ve Addre ss Regist er Register Descrip tion The HSS Receive Address register is used as the base poi nter address for the next HSS block receive transfer . Address (Bits [15:0]) The Address field sets the base pointer address for [...]

CY7C67200 Document #: 38-08014 Rev . *G Page 48 of 78 HSS T ransm it Address Register [0 xC07C] [R/W ] Figure 54 . HSS T ransmit Address R egister Register Descrip tion The HSS Transmit Address register is used as the base pointer address fo r the next HSS block transmit transfer . Address (Bits [15:0]) The Address field sets the base pointer addre[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 49 of 78 HPI Breakpoint Register [0x0 140 ] [R] Figure 56. HPI Breakpoint Re gister Register Descrip tion The HPI Breakpoint register is a special on-chip memory loca tion, which the ex ternal processor can access using normal HPI memory read/write cycles. This register is re ad-only by the CPU but is re[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 50 of 78 SOF/EOP2 to CPU Enable (Bit 12) The SOF/EOP2 to CPU Enabl e bit routes the SOF/EOP2 interrupt to the on-chip CPU. Since the SOF/EOP2 interrupt can be routed to both the on-chip C PU and the HPI port the firmware must ensure only one of the two (CPU, HPI) resets the interrup t. 1: Route signal to[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 51 of 78 SIEXmsg Register [W] • SIE1msg Register 0x0144 • SIE2msg Register 0x0148 Figure 58. SIEXmsg Register Register Descrip tion The SIEXmsg register allows an interru pt to be generated on the HPI port. Any write to this regi ster causes the SIEXmsg flag in the HPI S tatus Port to go high and als[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 52 of 78 HPI S tat us Port [] [HPI: R] Figure 60. HPI S t atus Port Register Descrip tion The HPI S tatus Port provides the external host proce ssor with the MailBox status bits plus several SIE status bits. This register is not accessible from the on-chip CPU. The a dditional SIE status bits are provide[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 53 of 78 mode this read only bit indicates if any of the endpoint inter- rupts occurs on Device 2. Firmware needs to determine which endpoint interrupt occurred. 1: Interrupt triggered 0: Interrupt did not trigger Done1 Flag (Bit 2) In host mode the Done 1 Flag bit is a read-only bit that indicates if a [...]

CY7C67200 Document #: 38-08014 Rev . *G Page 54 of 78 3Wire Enable (Bit 15) The 3Wire Enable bit indicates if the MISO and MOSI data lines are tied together allowi ng on ly half duplex operation. 1: MISO and MOSI data lines are tied together 0: Normal MISO and MOSI Full D uplex operation (not tied together) Phase Select (Bit 14) The Phase Select bi[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 55 of 78 SPI Control Reg ister [0xC0CA] [R/W] Figure 62. SPI Contro l Re gister Register Descrip tion The SPI Control register controls the SPI port. Fields a pply to both master and slave mode unless otherwise no ted. SCK Strobe (B it 15) The SCK S trobe bit starts the SCK strobe at the selected frequen[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 56 of 78 Receive Bit Length (Bits [2:0]) The Receive Bit Length field controls whe ther a fu ll byte or pa rtial byte will be recei ved. If Receive Bit Length is ‘00 0’ then a full byte will be received. If Receive Bit Length is ‘001’ to ‘1 1 1’, then the value indicates the number of bits th[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 57 of 78 T ransmit Interrupt Flag (Bit 1) The T ransmit Interrupt Flag is a read only bit that indicates a byte mode transmit interrupt has triggered. 1: Indicates a byte mode transmit interrupt has triggered 0: Indicates a byte mode transmi t interrupt has not triggered T ransfer Inte rrupt Flag (Bit 0)[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 58 of 78 CRC Enable (Bit 13) The CRC Enable bit enables or disa bles the CRC operation. 1: Enables CRC operation 0: Disables CRC operation CRC Clear (Bit 12) The CRC Clear bit will cl ear the CRC with a load of all on es. This bit is self clearing and always reads ‘0’. 1: Clear CRC with all ones 0: N[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 59 of 78 Data Ready bit of the SPI Control register is set to ‘1’. Writing to this register in PIO byte mode will initia te a transfer of data, the number of bits defined by T ransmit Bit Length fie ld in the SPI Control register . Data (Bit s [7:0]) The Data field contains data received or to be tra[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 60 of 78 SPI Receive Address Register [0xC0DC [R/W ] Figure 71. SPI Rece ive Address Register Register Descrip tion The SPI Receive Address register is issued as the base address for the SPI Receive DMA. Address (Bits [15:0]) The Address field sets the base address for the SPI receive DMA. SPI Receive Co[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 61 of 78 UART Control Register [0xC0E0] [R/W] Figure 73. UART Control Register Register Descrip tion The UART Control register enables or disables the UART allowing GPIO7 (UART_TXD) and GPIO6 (UART_RXD) to be freed up for general use. This re gister must also be written to set the baud rate, which is bas[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 62 of 78 Receive Full (Bit 1) The Receive Full bit indicates whether the receive buffer is full. It can be p rogrammed to interru pt the CPU a s interrupt #5 when the buffer is full. T his ca n be done thoug h the UART bit of the Interrupt Enable register (0xC00E). This bit w ill automat- ically be clear[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 63 of 78 Pin Diagram The following describes the CY7C67200 48-pin FBGA. Figure 76. EZ-O TG Pin Diagra m Pin Descriptions T able 38.Pin Descript ions Pin Name Ty p e Description H3 GPIO31/SCK IO GPIO31: General Purpose IO SCK: I2C EEPROM SCK F3 GPIO30 /SDA IO GPIO30: General Purpose IO SDA: I2C EEPROM SDA[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 64 of 78 H6 GPIO20/A 1 IO GPIO20: General Purpose IO A1: HPI A1 F5 GPIO19/A0 IO GPIO19: General Purpose IO A0: HPI A0 F6 GPIO15/D15/CTS/ nSSI IO GPIO15: General Purpose IO D15: D15 for HPI CTS: HSS CTS nSSI: SPI nSSI E4 GPIO14/D14/RTS IO GPIO14: General Purpose IO D14: D14 for HPI RTS: HSS RTS E5 GPIO13/[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 65 of 78 Absolute Maximum Ratings This section lists the absolute maximum ratings. S tresses above those listed can cause permanent damage to the device. Exposure to maximum rated conditions for extended p eriods can affect device operation a nd reliability . S torage T emperature ... ... ... ...........[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 66 of 78 DC Characteristics Notes 6. All tests were co nducted with Charge pump off . 7. I CC and I CCB values are the same regardl ess of US B host or peripheral configur ation. 8. There is no appreciable dif ference in I CC and I CCB values when only one transceiver is powered. T able 40.DC Characteris[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 67 of 78 USB T ransceive r USB 2.0-compatible in full- and low-speed modes. This product was tested as compliant to th e USB-IF specification under the test ident ification nu mber (TID) of 10039 0449 and is listed on t he USB-IF’ s integrators lis t. AC Timing Characteristics Reset Timing V A_SESS_V A[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 68 of 78 Clock Timing I 2 C EEPROM Timing Parameter Description Min. Ty p . Max. Unit f CLK Clock Frequency 12.0 MHz v XINH [10] Clock Input High (XT ALOUT left floating) 1.5 3.0 3.6 V t CLK Clock Period 83.17 83.33 83.5 ns t HIGH Clock High T ime 36 44 ns t LOW Clock Low T ime 36 4 4 ns t RISE Clock Ris[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 69 of 78 HPI (Host Port Interface) Write Cycle Timing Note 1 1. T = system clock period = 1/48 MHz. Parameter Description Min. T ypical Ma x. Unit t ASU Address Setup –1 ns t AH Address Hold –1 ns t CSSU Chip Select Setup –1 ns t CSH Chip Select Hold –1 ns t DSU Data Setup 6 ns t WDH Wr i t e Da [...]

CY7C67200 Document #: 38-08014 Rev . *G Page 70 of 78 HPI (Host Port Interface ) Read Cycle Timing Parameter Description Min. Ty p . Max. Unit t ASU Address Setup –1 ns t AH Address Hold –1 ns t CSSU Chip Select Setup –1 ns t CSH Chip Select Hold –1 ns t ACC Data Access T ime, from HPI_nRD falling 1 T [1 1] t RDH Read Dat a Hold, re lative [...]

CY7C67200 Document #: 38-08014 Rev . *G Page 71 of 78 HSS BYTE Mode T ransmit qt_clk, CPU_A, CPUHSS_cs, C PU_wr are internal signals, in clude d in t he diagram to illustrate relati onship between CPU opera- tions and HSS port operations. Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_TxD HIGH = data bit value ‘1’. BT = bit time = 1/ba[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 72 of 78 Hardware CTS/RTS Handshake t CTSset-u p : HSS_CTS se tup time be fore HSS_RTS = 1.5T min. t CTShold : HSS_CTS hold time afte r ST ART bit = 0 ns min. T = 1/48 MHz. When RTS/CTS hardware handshake is enabled, transmission can be held off by deasserting HSS_CTS at least 1.5T before HSS_RTS. T r an[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 73 of 78 Register Summary T able 42. Register Summary R/W Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 1 1 Bit 10 Bit 9 Bit 8 Default High Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Low R 0x0 140 HPI Breakp oint Address. .. 0000 0000 ...Address 0000 0 000 R 0x0 14 2 Interrupt Routin g VB[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 74 of 78 R/W 0xC024 GPIO 1 Output Dat a GPIO31 GPIO30 GPIO29 Reserved GPIO24 0000 0000 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 Reserved 0000 0000 R 0xC026 GP IO 1 Input Dat a GPIO31 GPIO30 GPIO29 Reserved GPIO24 0000 0000 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 Reserved 0000 0000 R/W 0xC028 GPIO 1 Direction GPIO31[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 75 of 78 R/W 0xC090 Hos t 1 S tatus VBUS Interr upt Flag ID Interrupt Flag Reserved SOF/EOP Interrupt Flag Reserved xxxx xxxx Reserved Port A Wake Interrupt Flag Reserved Port A Con- nect Change Interrupt Flag Reserved Po rt A SE0 Sta t us Reserved Done Interrupt Flag xxxx xxxx R/W 0xC090 Device 1 S tatu[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 76 of 78 R/W 0xC0D6 SPI Data Port t Reserved xxxx xxxx Data xxxx xxxx R/W 0xC0D8 SPI Transmit Address Address... 0000 0000 ...Address 0000 0 000 R/W 0xC0DA SPI T ransmit Count Reserved Count... 0000 0000 ...Count 0000 0000 R/W 0xC0DC SPI Receive Add ress Address... 0000 0000 ...Address 0000 0 000 R/W 0xC[...]

CY7C67200 Document #: 38-08014 Rev . *G Page 77 of 78 © Cypress Semico nductor Corpor ation, 2006. Th e information cont ained herein is subject to chan ge without noti ce. Cypress Semico nductor Corporation assumes no resp on sibility for the use of any circuitry o ther than circui try embodied i n a Cypress prod uct. Nor does it convey or imply [...]

CY7C67200 Document #: 38-08014 Rev . *G Page 78 of 78 Document History Page Document Title: CY7C67200 EZ-OTG™ Programmabl e USB On-The-Go Host/Peripheral Co ntro ller Document Number: 38-08014 REV . ECN NO. Issu e Date Orig. of Change Description of Change ** 1 1 1872 03/22/02 MUL New Data Sheet *A 1 16988 08/ 23/02 MUL Preliminary Data Sheet *B [...]