Français dropdown-ico

Intel SL22U manuel d'utilisation

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35

Aller à la page of

Les manuels d’utilisation similaires

Un bon manuel d’utilisation

Les règles imposent au revendeur l'obligation de fournir à l'acheteur, avec des marchandises, le manuel d’utilisation Intel SL22U. Le manque du manuel d’utilisation ou les informations incorrectes fournies au consommateur sont à la base d'une plainte pour non-conformité du dispositif avec le contrat. Conformément à la loi, l’inclusion du manuel d’utilisation sous une forme autre que le papier est autorisée, ce qui est souvent utilisé récemment, en incluant la forme graphique ou électronique du manuel Intel SL22U ou les vidéos d'instruction pour les utilisateurs. La condition est son caractère lisible et compréhensible.

Qu'est ce que le manuel d’utilisation?

Le mot vient du latin "Instructio", à savoir organiser. Ainsi, le manuel d’utilisation Intel SL22U décrit les étapes de la procédure. Le but du manuel d’utilisation est d’instruire, de faciliter le démarrage, l'utilisation de l'équipement ou l'exécution des actions spécifiques. Le manuel d’utilisation est une collection d'informations sur l'objet/service, une indice.

Malheureusement, peu d'utilisateurs prennent le temps de lire le manuel d’utilisation, et un bon manuel permet non seulement d’apprendre à connaître un certain nombre de fonctionnalités supplémentaires du dispositif acheté, mais aussi éviter la majorité des défaillances.

Donc, ce qui devrait contenir le manuel parfait?

Tout d'abord, le manuel d’utilisation Intel SL22U devrait contenir:
- informations sur les caractéristiques techniques du dispositif Intel SL22U
- nom du fabricant et année de fabrication Intel SL22U
- instructions d'utilisation, de réglage et d’entretien de l'équipement Intel SL22U
- signes de sécurité et attestations confirmant la conformité avec les normes pertinentes

Pourquoi nous ne lisons pas les manuels d’utilisation?

Habituellement, cela est dû au manque de temps et de certitude quant à la fonctionnalité spécifique de l'équipement acheté. Malheureusement, la connexion et le démarrage Intel SL22U ne suffisent pas. Le manuel d’utilisation contient un certain nombre de lignes directrices concernant les fonctionnalités spécifiques, la sécurité, les méthodes d'entretien (même les moyens qui doivent être utilisés), les défauts possibles Intel SL22U et les moyens de résoudre des problèmes communs lors de l'utilisation. Enfin, le manuel contient les coordonnées du service Intel en l'absence de l'efficacité des solutions proposées. Actuellement, les manuels d’utilisation sous la forme d'animations intéressantes et de vidéos pédagogiques qui sont meilleurs que la brochure, sont très populaires. Ce type de manuel permet à l'utilisateur de voir toute la vidéo d'instruction sans sauter les spécifications et les descriptions techniques compliquées Intel SL22U, comme c’est le cas pour la version papier.

Pourquoi lire le manuel d’utilisation?

Tout d'abord, il contient la réponse sur la structure, les possibilités du dispositif Intel SL22U, l'utilisation de divers accessoires et une gamme d'informations pour profiter pleinement de toutes les fonctionnalités et commodités.

Après un achat réussi de l’équipement/dispositif, prenez un moment pour vous familiariser avec toutes les parties du manuel d'utilisation Intel SL22U. À l'heure actuelle, ils sont soigneusement préparés et traduits pour qu'ils soient non seulement compréhensibles pour les utilisateurs, mais pour qu’ils remplissent leur fonction de base de l'information et d’aide.

Table des matières du manuel d’utilisation

  • Page 1

    i In tel® 64 Ar chitectur e x2APIC Specification Re ference Number: 318148-004 March 2010[...]

  • Page 2

    ii INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNE CTION WITH INT EL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPE L OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANT- E D B Y TH I S D O C U M E NT . E X C E P T A S P R O V ID E D I N INTEL’ S T ERMS AND C ONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSU MES NO LIABILITY WHATSOEV[...]

  • Page 3

    1-1 INTR ODUCTION CHAPT ER 1 IN TRODUCTION 1.1 IN TRODUCTION The xAPIC architecture provided a key me chanism for interrupt delivery in many generations of Intel processors and platforms across different market segments. This document describes the x2APIC architecture which is extended from the xAPIC archi- tecture (the latter was first implemented[...]

  • Page 4

    1-2 IN TRODUCTION However no modifications are required to PCI or PCIe device s that support direct interrupt delivery to the processors via Me ssage Signaled Interrupts. Similarly no modifications are required to the IOxAPI C. The routing of interrupts fr om these devices in x2APIC mode leverages the inte rrupt remapping architecture specified in [...]

  • Page 5

    1-3 INTR ODUCTION 1.4 R EF ERENC ES • Intel ® 64 and IA-32 Architectures Software Developer’s Manual (in five volumes) http://developer .intel.com/products/processor/manuals/index.htm • Intel Virtualization T echnology for Directed I/O, Rev 1.1 specification http://download.intel.com/technology/com puting/vptech/Intel(r)_VT_for_Direc t_IO.pd[...]

  • Page 6

    1-4 IN TRODUCTION This page intentionally left blank[...]

  • Page 7

    2-1 LO C A L X 2A PIC ARCHITECTURE CHAPT ER 2 LO C A L X 2APIC ARCHIT ECTUR E 2.1 X 2APIC ENHANCEMEN TS The key enhancements provided by the x2 A PIC architecture o ver xAPIC are the following: • Support for two modes of operation to pr ovide backward compatibility and exten- sibility for future platform innov ations: — In xAPIC compatibility m[...]

  • Page 8

    2-2 LO C A L X 2APIC ARCHITECTU RE 2.2 DET ECTING AND ENABLING X 2APIC A processor’s support to operate its local APIC in the x2APIC mode can be detected by querying the extended feature flag in formation reported by CPUID . When CPUID is executed with EAX = 1, the returned value in ECX[Bit 21] indicates processor ’ s support for the x2APIC mod[...]

  • Page 9

    2-3 LO C A L X 2A PIC ARCHITECTURE bit 10 to zero. Se ction 2.7, “x2APIC ST A TE TRANSITIONS” provides a detailed state diagram for the state transitions allowed for the local APIC. 2.3 X 2APIC MODE R EGISTER IN T ERF ACE In xAPIC mode, the software model for accessing the APIC registers is through a memory mapped interface. Specifically , the [...]

  • Page 10

    2-4 LO C A L X 2APIC ARCHITECTU RE • The SELF IPI register is available only if x2APIC mode is enabled. The MSR address space is compressed to allow for future growth. Ev ery 32 bit register on a 128- bit boundary in the legacy MMIO space is mapped to a single MSR in the local x2APIC MSR address s pace. The upper 32-bits of all x2APIC MSRs (excep[...]

  • Page 11

    2-5 LO C A L X 2A PIC ARCHITECTURE 0120H 012H ISR bits 64:95 Read Only. 0130H 013H ISR bits 96:127 Read Only. 0140H 014H ISR bits 128:159 Read On ly. 0150H 015H ISR bits 160:191 Read On ly. 0160H 016H ISR bits 192:223 Read On ly. 0170H 017H ISR bits 224:255 Read On ly. 0180H 018H T rigger Mode Regi ster (TMR); bits 0:31 Rea d O nl y. 0190H 019H TMR[...]

  • Page 12

    2-6 LO C A L X 2APIC ARCHITECTU RE 2.3.3 Reserv ed Bit Checking Section 2.3.2 and Ta b l e 2 - 2 specifies the reserved bit de finitions for the APIC regis- ters in x2APIC mode. Non-zero writes (by WRMSR instruction) to reserv ed bits to these registers will raise a general protection fault exception while reads return zeros (RsvdZ semantics). 0320[...]

  • Page 13

    2-7 LO C A L X 2A PIC ARCHITECTURE 2.3.4 Error Handling RDMSR and WRMSR operations to reserved addresses in the x2APIC mode will r aise a GP fault. (Note: In xAPIC mode, an APIC error is indicated in the Er ror Status Register on an illegal register access.) Additionally reserved bit violations cause GP faults as detailed in Section 2.3.3 . Beyond [...]

  • Page 14

    2-8 LO C A L X 2APIC ARCHITECTU RE Other semantics change related to reading/ writin g the ICR in x2APIC mode vs. xAPIC mode are: • Completion of the WRMSR instruction to the ICR does not guar antee that the interrupt to be dispatched has been rece ived by the targeted processors. If the system software usage requires this guar antee, then the sy[...]

  • Page 15

    2-9 LO C A L X 2A PIC ARCHITECTURE last write to the ESR. Errors are collecte d regardless of L VT Error mask bit, but the APIC will only issue an interrupt due to the error if the L VT Error mask bit is cleared. In the x2APIC mode, the write of a zero valu e is enforced. Softw are writes zero’ s to the ESR to clear the error status. Writes of a [...]

  • Page 16

    2-10 LO C A L X 2APIC ARCHITECTU RE 2.3.7 VM-e xit Contr ols for MSRs and x2APIC R egisters The VMX architecture allows a VMM to specify l i s t s o f M S R s t o b e l o a d e d o r s t o r e d o n VMX transitions usin g the VMX-tr ansition MSR areas (see VM-exit MSR -store address field, VM-exit MSR -load address filed, and VM-entry MSR -load add[...]

  • Page 17

    2-11 LO C A L X 2A PIC ARCHITECTURE than 32 bits in its hardware. System software should be agnostic to the actual number of bits that are implemented. All non-implemented bits will return zeros on reads by software. The APIC ID value of FFFF_FFFFH and the highest v alue corresponding to the imple- mented bit-width of the local APIC ID register in [...]

  • Page 18

    2-12 LO C A L X 2APIC ARCHITECTU RE In the xAPIC mode, the Destination Format R egister (DFR) through MMIO interface determines the choice of a flat logical mode or a clustered logical mode. Flat logical mode is not supported in the x2APIC mode. Hence the Destination Format Register (DFR) is eliminated in x2APIC mode. The 32-bit logical x2APIC ID f[...]

  • Page 19

    2-13 LO C A L X 2A PIC ARCHITECTURE 2.4.3 Interrup t Command Regis ter In x2APIC mode, the layout of the Interrupt Command Re gister is shown in Figure 2- 5 . The lower 32 bits of ICR in x2APIC mode is identical to the lower half of the ICR in xAPIC mode, except bit 12 (Delivery Status) is not used since it is not needed in X2APIC mode. 1 The desti[...]

  • Page 20

    2-14 LO C A L X 2APIC ARCHITECTU RE debugging; however , software should not assume the value returned by reading the ICR is the last written value. A destination ID value of FFFF_FFFFH is used for broadcast of interrupts in both logical destination and physical destination modes. 2.4.4 Deriving Logical x2APIC ID fr om the Local x2APIC ID In x2APIC[...]

  • Page 21

    2-15 LO C A L X 2A PIC ARCHITECTURE The SELF IPI register is a write-only regist er . A RDMSR instruction with address of the SELF IPI register will raise a GP fault. The handling and prioritization of a self-IPI sent via the SELF IPI register is architec- turally identical to that for an IPI sent vi a the ICR fro m a legacy xAPIC unit. Specifi- ca[...]

  • Page 22

    2-16 LO C A L X 2APIC ARCHITECTU RE Directed EOI capability is intended to enable system software to perform directed EOIs to specific IOxAPICs in the system. System software desiring to perform a directed EOI would do the following: • inhibit the broadcast of EOI message by setting bit 12 of the Spurious Interrupt V ector Re gister , and • fol[...]

  • Page 23

    2-17 LO C A L X 2A PIC ARCHITECTURE x2APIC modes of a local x2APIC u nit. Layout of the Local APIC V ersion register is as shown in Figure 2-8 . The Directed EOI feature is supported if bit 24 is set to 1. 2.6 IN TERA CTION WITH PROCESSOR C ORE OPERA TING MODES Similar to the xAPIC architecture, the APIC registers defined in the x2APIC architec- tu[...]

  • Page 24

    2-18 LO C A L X 2APIC ARCHITECTU RE • The local APIC ID is initialized by hardw are with a 32 bit ID (x2APIC ID). The lowest 8 bits of the x2APIC ID is the le gacy local xAPIC ID, and is stored in the upper 8 bits of the A PIC register for access in xAPIC mode. • The following APIC registers are reset to all zeros for those fields that are defi[...]

  • Page 25

    2-19 LO C A L X 2A PIC ARCHITECTURE 2.7 .1.1 x2APIC A fter R ESET The valid transitions from the xAPIC mode state are: • to the x2APIC mode by setting EXT to 1 (resulting EN=1, EXTD= 1). The physical x2APIC ID (see Figure 2-3 ) is preserved across this tr ansition and the logical x2APIC ID (see Figure 2-4 ) is initialized by hardware during this [...]

  • Page 26

    2-20 LO C A L X 2APIC ARCHITECTU RE A RESET in the disabled state place s the x2 APIC in the xAPIC mode. All APIC registers (including the local APIC ID regist er) are initialized as described in Se ction 2.7.1 . An INIT in the disabled state keeps the x2APIC in the disabled state. 2.7 .1.4 S tate Changes From xAPIC Mode t o x2APIC Mode After APIC [...]

  • Page 27

    2-21 LO C A L X 2A PIC ARCHITECTURE processor topology . The relevant information in CPUID leaves 01H and 04H do not directly map to individual lev els of the topology , but merely relate to the sharing characteristics below different levels. The extended topology enumeration leaf of CPUID provides topology information and data that simplify the al[...]

  • Page 28

    2-22 LO C A L X 2APIC ARCHITECTU RE The lowest level number is zero. Level numbe r = 0 is reserved to specify SMT -rel ated topology information (see Hyper- Threading T e chnology in Section 7.8 of “Intel® 64 and IA-32 Architectures Software Developer’ s Manual“, V ol. 3A). I f SMT is not present in a processor implementation but CPUID leaf [...]

  • Page 29

    2-23 LO C A L X 2A PIC ARCHITECTURE 2.8.1 Consistency o f APIC IDs and CPUID The consistency of physical x2APIC ID in MSR 802H in x2A PIC mode and the 32-bit value returned in CPUID .0BH:EDX is facilitated by processor hardware. CPUID.0BH:EDX will report the full 32 bit ID, in xAPIC and x2APIC mode. This allows BIOS to determine if a system has pro[...]

  • Page 30

    2-24 LO C A L X 2APIC ARCHITECTU RE • R e-directible/Lowest Priority inter-processor interrupts are not supported in the x2APIC architecture.[...]

  • Page 31

    2-25 LO C A L X 2A PIC ARCHITECTURE This page intentionally left blank[...]

  • Page 32

    2-26 LO C A L X 2APIC ARCHITECTU RE[...]

  • Page 33

    Index-1 INDEX A APIC . . . . . . . . . . . . . . . . . . . . . . . 1, 2, 1, 6, 7, 9, 17 APIC ID . . . . . . . . . . . . . . . . . . . . . . . . . 3, 11, 14, 23 C CPUID instruction deterministic cache parameters leaf . . . . . . . . 21 D DFR Destination Format Register . . . . . . . . . 3, 12, 18 E EOI End Of Interrupt register . . . . . . . . . . .[...]

  • Page 34

    Index-2 S SELF IPI register . . . . . . . . . . . . . . . . . . . . . . . . 4, 7 SVR Spurious Interrupt Vector Register . . . . . . . . . 16 T TMR Trigger Mode Register . . . . . . . . . . 5, 15, 16, 18 TPR Task Priority Register . . . . . . . . . . . . . . . 4, 7, 18 X x2APIC . . . . . . . . . . . . . . . . . . . . . . . 2, 1, 2, 15, 23 x2APIC ID [...]

  • Page 35

    Index-3 This page intentionally left blank[...]