Siemens ERTEC200 manuel d'utilisation

Copyright © Siemens AG 2007. All rights reserved. Page 1 ERTEC 200 Manual Technical data subject to change Version 1.1.0 . RTEC 200 E nhanced R eal- T ime E thernet C ontroller E Manual[...]

Edition (04/2007) Disclaimer of Liabilit y We have checked the contents of this manual for agreement with the hard ware and software described. Since deviations c annot be precluded entirely, we cannot guarantee full agreement. However, the data in this manual are reviewed regularl y. Necessary corrections are included in subsequent editions. Sugge[...]

Preface Target Audience of this Manual This manual is intended for hard ware developers who want to use the ERTEC 200 for new prod ucts. Experi ence working with processors and designin g emb edded syst ems and kno wledge of Ethernet are required for this. It described all ERT E C function grou ps in details and provid es informati on that you must[...]

This manual will be updated a s requir ed. You can find t he current version of the m anual on the Internet at http://www.siemens.com/comdec . Guide To help you quickly find the information you need, this manual contains the follo wing aids: o A complete table of contents as well as a list of a ll figures and tables in the manual are pro vided at t[...]

Contents 1 Introduc tion ................................................................................................................... ......... 9 1.1 Applications of the ER TEC 200 .................................................................................................. ............ 9 1.2 Features of the ERTE C 200 .................[...]

4.4.2 F-Timer Register Descrip tion ................................................................................................... ...... 44 4.5 Watchdog Ti mers ................................................................................................................ ................... 45 4.5.1 Watchdog Ti mer 0........................[...]

11.1.3 ETM9 Regi sters ................................................................................................................. ............ 94 11.2 Trace Inte rface ................................................................................................................ ....................... 95 11.3 JTAG Inte rface ..............[...]

List of Figures Figure 1: ERTEC 200 Block Diagr am .................................................................................................................... 10 Figure 2: ERTEC 200 Packa ge Descr iption .......................................................................................................... 11 Figure 3: Structure of ARM9[...]

1 Introduction The ERTEC 200 is intended for the implem en tation of PROF INET devices with RT and IRT functional it y. With its integrated ARM946 process or and 2-port Ethernet s witch with integrated PHYs and the option to connect an external host processor system to a lo cal bus interface, it meets all the r equirements for impl ementing PROFINE[...]

1.3 Structure of the ERTEC 200 The figure below sho ws the function groups with the common communication p aths. DMA- Cont rol ler AHB/APB Bridge GPI O Maste r Master P P o r t s 7 APB 50MHz / 32 Bit 74 LBU / MII + SMI / ETM / GPIO 1 x UART SPI1 Interfa ce 3 x Timer, Watchdog, F-Timer ARM9 clock 50MHz 100MHz 1 1 25MHz SC-Bus (50MHz) 32 Bit 2-Por t [...]

1.4 ERTEC 200 Package The ERTEC 200 is supplied in an FBGA package with 304 pins. The distanc e between the pins is 0.8 mm. T he package dimensions are 19 m m x 19 mm. Figure 2: ERTEC 200 Package Description Soldering instructions for the ERT EC 200 can be found in the foll owing documents: /10/ Soldering instructions for lead -based block. /11/ So[...]

1.5 Signal Function Description ERTEC 200 Pin Description The ERTEC 200 Ethernet communic ation block is available i n a 304-pin FBGA package. The signal names of the ERTEC 200 are described in this section. 1.5.1 GPIO 0 to 31 and Alternative Function s Various signals are multiple xe d on the same pin. These mult ip lexed signals can contai n u p [...]

No. Signal Name Alternative Function 1 Alternative Function 2 Alternative Function 3 I/O (Reset) Pull- PIN No. Comment General Purpose I/O / I/O 23 GPIO22 SPI1_SFRMIN DBGACK B/I/O/(I) up F10 GPIO or SPI1 (I) or Debug (O) This GPIO is used as chip select when booting from Nand Flash or SPI ROM. 24 GPIO23 SPI1_SCLKIN Reser ved B/I/O/(I) up D10 GPIO o[...]

1.5.4 Clock and Reset No. Signal Name I/O (Reset) Pull- PIN No. Comment CLOCK / RESET GENERATION 42 CLKP_A I (I) B14 Quartz connection 43 CLKP_B O D14 Quartz connection 44 F_CLK I (I) B13 F_CLK for F-c ounter 45 REF_CLK Dependent on PIN CONFIG[1] A15 Tristate or reference clock output, 25 MHz 46 RESET_N I (I) up B7 PowerOn reset 1.5.5 Test Pins No.[...]

No. Signal Name Alternative Reset Functio n I/O (Reset) Pull- PIN No. Comment EMIF (External Memory Interface) 66 A13 O (O) G2 Address bit 13 SDRAM: Address 11 67 A14 O (O) G1 Address bit 14 SDRAM: Address 12 68 A15 BOOT1 B (I) dn H2 Address bit 15 ERTEC 200 boot mode (ext. PU may be necessar y) 69 A16 BOOT2 B (I) dn J2 Address bit 16 / ERTEC 200 b[...]

No. Signal Name Alternative Reset Functio n I/O (Reset) Pull- PIN No. Comment EMIF (External Memory Interface) 109 WR_N O (O) A4 Write strobe 110 RD_N O (O) B5 Read strobe 111 CS_PER0_N O (O) D5 Chip Sel ect Bank 1 (ROM); boot area 112 CS_PER1_N O (O) A5 Chip s elect bank 2 113 CS_PER2_N O (O) A6 Chip s elect bank 3 114 CS_PER3_N O (O) B6 Chip s el[...]

No. Function 1 LBU Config (6,5,2)=xx0b Function 2 PHY Debug and GPIO[44:32] Config (6,5,2)=011b Function 3 ETM Trace and GPIO[44:32] Config (6,5,2)=101b Function 4 Reserved [6,5,2]=111b IO (Reset See Config [6,5,2]) Pull - PIN No. Comment LBU / MII-Interface 141 LBU_A16 GPIO32 GPIO32 I/B/B/B (GPIO:I) up W9 LBU or GPIO 142 LBU_A17 GPIO33 GPIO33 I/B/[...]

No. Function 1 LBU Config (6,5,2)=xx0b Function 2 PHY Debug and GPIO[44:32] Config (6,5,2)=011b Function 3 ETM Trace and GPIO[44:32] Config (6,5,2)=101b Function 4 Reserved [6,5,2]=111b IO (Reset See Config [6,5,2]) Pull - PIN No. Comment LBU / MII-Interface 166 LBU_D12 SMI_MDC B/O/I/O (LBU : I) up W14 LBU or MII 167 LBU_D13 SMI_MDIO B/O/I/O (LBU :[...]

No. Signal Name I/O Pull- PIN No. Comment PHY1 and PHY2 196 P1SDxN I F19 Port1 FX dif ferential SD input 197 P1SDxP I G19 Port1 FX differential SD input 198 P1TDxN O C22 Port1 FX differential transmit output 199 P1TDxP O C21 Port1 FX differential transmit output 200 P1RDxN I E21 Port1 FX differential recei ve input 201 P1RDxP I E22 Port1 FX differe[...]

Signal description: IO = Signal direction from perspective of the application I: Input O: Output B: Bidirectional P: Power supply Pull- = Internal pull-up/pull-down resistor connected to the signa l pin up: Internal pull-up dn: Internal pull-down PU/PD = External resistances necessary, depe nding on application PU: External pull-up PD: External pu [...]

2 ARM946E-S Processor The ARM946E-S processor is impleme nted in the ERTEC 200. This description is based on / 1 / and / 2 /. 2.1 Structure of ARM946E-S An ARM946E-S processor system is used. The figur e below shows the structure of the pr ocessor. In addition to the processor core, the system contains one data cache, one in struction cache, a memo[...]

2.2 Description of ARM946E-S The ARM946E-S processor system is a member of the AR M9 Thumb famil y. It has a processor core with Harvard architecture. Compared to the standard ARM9 famil y, th e ARM946E-S has an enhanc ed V5TE architecture perm itting faster switching between ARM and T humb code segments and an enhanced multi plier stru cture. In a[...]

2.6 Memory Protection Unit (MPU) The memory protection unit enabl es the user to partition s pecific memory areas (I-cache, D-cache, or DT CM) into various regions and to assign different attrib utes to them. A maximum of 8 regions of variable size can be set. If regions ov erlap, the attributes of the hig her re gion number apply. Settings for eac[...]

2.9.1 Prioritization of Interrupts It is possible to set the priorities of the IRQ and FIQ interrupts. Priorities 0 to 15 can be assigned to IRQ interrupts while priorities 0 to 7 can be assigned to FIQ interrupts. T he hig hest priority is 0 for both interru pt levels. After a reset, all IR Q interrupt inputs are set to priority 15 and all FIQ int[...]

The CPU accepts an IRQ-/FIQ request by reading the IRVEC/F IVEQ register. This register contains the binar y-co ded vector number of the highest priority interrupt request at th e moment. Each of the two interrupt vector registers can be referenced using t wo different addresses. The interrupt controller interpre ts the reading of the ve ctor regis[...]

2.9.9 IRQ Interrupts as FIQ Interrupt Sources Interrupts from the IRQ interrupt can be placed on FIQ6 and FIQ7 können. The interrupts of the FIQ interrupt c ontroller are used for debug ging, monitoring address area acc ess, and for the watchdog. FIQ interrupts no. 4 and 5 are the interrupts for embedded ICE RT communication. The UART can also be [...]

PRIOREG 1 0x0074 4 bytes R/W 0x0000000F .... ... ... .... ... ... .... PRIOREG15 0x00AC 4 bytes R/W 0x0000000F Priority register 15 Table 4: Overview of Interrupt Control Register 2.9.11 ICU Register Description IRVEC R Addr.: 0x5000_0000 Default: 0xFFFF_FFFF Description Interrupt vector register Input with highest priority pending interru pt requ [...]

FIQACK R Addr.: 0x5000_0018 Default: 0xFFFF_FFFF Description Fast interrupt vector register with F IQ acknowledge Confirmation of fast interrupt request by reading the ass ociated interrupt vector Bit No. Name Description 2 – 0 FIVEC Binary code of FIQ number 31 – 3 Vector ID Valid FIQ vector: always ‘1’. Default vector: always ‘1’ (als[...]

FIQIRR R Addr.: 0x5000_0050 Default: 0x0000_0020 Description FIQ request register Indication of the fast interrupt request detected with a positive edge Bit No. Name Description 7 – 0 FIQIRR Inputs 0 to 7 of the FIQ interru pt controller '0' = No request '1' = Request is occurred FIQ_MASKREG R/W Addr.: 0x5000_0054 Default: 0x0[...]

SWIRREG R/W Addr.: 0x5000_006C Default: 0x0000_0000 Description Soft ware interrupt register Specification of interrupt requests Bit No. Name Description 15 – 0 SWIRREG Interrupt input 0 to 15 0 =No interrupt request 1=Set interrupt request PRIOREG 0 R/W Addr.: 0x5000_0070 Default: 0x0000_000F … …. PRIOREG 15 R/W Addr.: 0x5000_00AC Default: 0[...]

2.10 ARM946E-S Register The ARM946E-S uses CP15 registers for s ystem control. Consequently, the follo wing settings are possible: • Configure cache t ype and cache memory area • Configure tightly coupl ed mem ory area • Configure memory protection unit for various regions a nd memor y types • Assign system option paramet ers • Configure [...]

3 Bus System of the ERTEC 200 Internally, the ERTEC 200 has t wo buses.  High-performance communication bus (multilay er AHB bus)  I/O bus (A PB bus) The following function blocks are connec ted directly to the multilayer AHB bus:  ARM946E-S (Master)  IRT switch (Master/Slave)  LBU (Master)  Interrupt controller (Slave)  EMIF i[...]

4 I/O on APB bus The ERTEC 200 block has multiple I/O function blocks. They are connected to the 32-bi t APB I/O bus. The ARM946E-S, DMA controller and LBU interface can acces s the I/O. The following I/O are available.  8 Kbyte Boot ROM  32-bit GPIO (*)  UART  SPI interface  Timer 0 - 2  F-timer  Watchdog  System control re[...]

The following download modes are supp orted: BOOT(3) BOOT(2) BOOT (1) BOOT(0) BOOTING O F 0 0 0 0 External ROM with 8-bit data width 0 0 0 1 External ROM with 16-bit data width 0 0 1 0 External ROM with 32-bit data width 1 0 0 0 Fast External ROM with 8-bit data width 1 0 0 1 Fast External ROM with 16-bit data width 1 0 1 0 Fast External ROM with 3[...]

4.2 General Purpose I/O (GPIO) Up to 45 General Purpose Inputs/Outputs are availab le i n the ERT EC 200. These are divide d into t wo groups: • GPIO[31:0] 32 bits on the APB I/O bus • GPIO[44:32] 13 bits as an alternat ive function on the LBU interface The GPIOs [31 : 0] can be used as follows • Inputs • Outputs • One of up to 3 addition[...]

4.2.1 Address Assignment of GPIO Regist ers The GPIO registers are 32 bits in width. T he registers ca n be read or written to with 8-bit, 16-bit, or 32-bit accesses. GPIO (Base Address 0x4000_2500) Register Name Offset Address Address Area Access Default Des cription GPIO_IOCTRL 0x0000 4 bytes W/R 0xFFFFFFFF Configuration reg ister for GPIO GPIO_O[...]

17:16 GPIO8_PORT_MODE Port GPIO[8]; 19:18 GPIO9_PORT_MODE Port GPIO[9]; 21:20 GPIO10_PORT_MODE Port GPIO[10]; 23:22 GPIO11_PORT_MODE Port GPIO[11]; 25:24 GPIO12_PORT_MODE Port GPIO[12]; 27:26 GPIO13_PORT_MODE Port GPIO[13]; 29:28 GPIO14_PORT_MODE Port GPIO[14]; 31:30 GPIO15_PORT_MODE Port GPIO[15]; GPIO_PORT_MODE_H W/R Addr.: 0x4000_2510 Default: 0[...]

GPIO2_ IN R Addr.: 0x4000_2528 Default: Port assignment Description Input register f o r General Purpose IO [44:32] Bit No. Name Description 31..13 Reserved Reserved 12..0 GPIO2_IN[44:32] 0: GPIO i nputx = 0, 1: GPIO input x = 1 4.3 Timer 0/1/2 Three independent timers are integrate d in t he ERTEC 200. The y can be used for internal mon itorin g o[...]

4.3.1.1 Timer 0/1 Interrupts The timer 0/1 interrupt is active (High) starting from t he point at which the timer value is counted down to 0. The timer interrupt is deactivated (Lo w) when the reload value is automatically reloaded or t he "LOAD“ bit is set by the user. The interrupt is not reset when the relo ad val ue 0 is loaded. If the t[...]

4.3.3 Address Assignment of Timer Registe rs The timer registers are 32 bits in width. For read/ write acce ss of the timer registers to be meaningful, a 32-bit access is required. However, a byte-by- byte write op eration is not inte rcepted b y the hardware. Timer (Base Address 0x4000_2000) Register Name Offset Address Address Area Access Default[...]

CTRL_STAT1 R/W Addr.: 0x4000_2004 Default: 0x0000_0000 Description Control/status register 1. Configuration and c ontrol bits for Timer No. 1. Bit No. Name Description 0 Run/xStop *) Stop/start of timer: 0: Timer is stopped 1: Timer is running Note: If this bit = 0, the timer interrupt is inactive (0) and the status bit (Bit 5) is reset (0). 1 Load[...]

RELD_PREDIV R/W Addr.: 0x4000_2014 Default: 0x0000_0000 Description Reload re gister for the two prescalers Bit No. Name Description 7:0 Prediv [7:0] Relo ad value of prescaler 0 15:8 Prediv [15:8] Reload va lue of prescaler 1 31-16 Reserved Not relevant (read=0) TIM0 R Addr.: 0x4000_2018 Default: 0x0000_0000 TIM1 R Addr.: 0x4000_201C Default: 0x00[...]

4.4 F-Timer Function An F-timer is integrated in the ERTEC 200 in add ition to the sy stem timers. This timer works independently of the system clock and can be used for fail-safe applicati ons, for example. T he F-timer is triggered via the alternative “F _CLK” functi on at the external “BYP_CLK” inpu t. External triggering is not possible[...]

4.4.1 Address Assignment of F-Timer Regis ters The F-timer registers are 32 bits in width . The registers can be written to in 32-bit width only . F-Counter (Base Address 0x4000_2700) Register Name Offset Address Addre ss Are a Access Default Description F-COUNTER-VAL 0x0000 4 bytes R 0x00000000 F-counter value register F-COUNTER-RES 0x0004 4 bytes[...]

4.5 Watchdog Timers Two watchdog timers are integrated in the E RTEC 200. The wa tchdog tim ers are inte nd ed for stand-alone monitoring of processes. The working clock of 50 MHz is derived fr om the PLL the sam e as the processor clock. 4.5.1 Watchdog Timer 0 Watchdog timer 0 is a 32-bit down-counter to which the WDOUT 0_N outpu t is assigned. Th[...]

4.5.6 Watchdog Registers The watchdog registers are 32 bits in width. For read/writ e access of the watchdog regis t ers to be mea ningful, a 32-bit access is required. However, a byte-by-byte w rit e operation is not intercept ed by the hardware. To prevent the watchdog registers from being written to inad vertently, e.g., in the event of an undef[...]

RELD0_LOW R/W Addr.: 0x4000_2104 Default: 0x0000_FFFF Description Reload re gister 0_Low. Reload value for bits 15:0 of watchdog counter 0. Bit No. Name Description 15-0 Reload0 [15:0] Reload valu e for bits 15:0 of watchdog counter 0. 31-16 Key bits Ke y bits for writing to this register (read=0). If bits 31-16=9876h, writing of bits 0-15 of this [...]

4.6 UART Interf ace A UART interface is implemented in t he ERT E C 200. T he inputs and outputs of t he UART interface are available as an alternative function at GPIO po rt [12:8]. For this purpose, the I/O must be a ssigned to the relevant inputs and outputs and the alternative function must be assigned (see GPIO register description). If the UA[...]

The baud rate generation is d erived from the internal 50 MHz APB clock. The resulting deviatio ns from the standard baud rates used are so small that a secure data transmissio n is achieved. The baud rate is calculated ac cording to the following formula: F UARTCLK F UARTCLK BR = ----------------------------- or BAUDDIV = (------------------------[...]

4.6.2 UART Register Description UARTDR R/W Addr.: 0x4000_2300 Default: 0x-- Description UART data registers Bit No. Name Description 7 – 0 ------- WRITE: - If FIFO is enabled, the written data are entered in t he FIFO. - If FIFO is disabled, the written data ar e entered in the Transmit holdi ng register (the first word in the Transmit FIFO). REA[...]

UARTLCR_H R/W Addr.: 0x4000_2308 Default: 0x00 Description UART line cont rol register high byte bit rate and control reg ister bits 22 to 16 Bit No. Name Description 0 BRK Send break = 1 A LOW level is sent continuously at the Transmit output. 1 PEN Parity enable = 1 Parity check and gener ation are enabled. 2 EPS If PEN = 1 Even parity select = 1[...]

UARTCR R/W Addr.: 0x4000_2314 Default: 0x00 Description UART control registers Bit No. Name Description 0 UART EN UART Enable = 1 UART sending/receiv in g of data is enabled 1 SIREN SIR enable = 1 IrDA SIR Endec is ena bled. The bit can only b e chan ged if UARTEN = 1 2 SIRLP IrDA SIR Low power mode 3 MSIE Modem status interrupt enab le = 1 Interru[...]

UARTIIR/UARTICR R/W Addr.: 0x4000_231C Default: 0x00 Description UART interrupt i dentificatio n register (read) UART interrupt clear register (write) Bit No. Name Description 0 MIS (Read) Modem Interru pt Status This bit is set if UARTMSINTR is active. 1 RIS (Read) Receive Interrupt Status This bit is set if UARTRXINTR is active. 2 TIS (Read) Tran[...]

4.7 Synchronous Interface SPI An SPI interface is implemented in the ERTEC 200. T he inpu ts and outputs of the SPI inte rface are avai labl e as an alternative function at GPIO po rt [23:16]. For this purpose, the I/O must be assigned to the relev ant inputs and outputs and the alternative function m ust be assig ne d (see GPIO register descriptio[...]

For the synchronous clock out put of the SPI interface, the following frequencies ar e calculated acc ording to the assigned SPI registers: 50 MHz SCLKOUT = ----------------------------- CPSDRV * (1+SCR) The SPI parameters can assume the following values: CPSDRV From 2 to 254 SCR From 0 to 255 This yields a frequency ra nge of • 769 Hz (CPSDRV = [...]

4.7.2 SPI Register Description SSPCR0 R/W Addr.: 0x4000_2200 Default: 0x0000 Description Control register 0. Configur ation frame format and baud rate for SPI. Bit No. Name Description 3 - 0 DSS Data Size Select 0000 Reserved (undefined) 1000 9-Bit Data 0001 Reserved (undefined) 1001 10 -Bit Data 0010 Reserved (undefined) 1010 11 -Bit Data 0011 4-B[...]

15-7 ------- Reserved Read: Value is undefined Write: Should always be written with zero SSPDR R/W Addr.: 0x4000_2208 Default: 0x---- Description SPI data register Bit No. Name Description 15-0 DATA (15:0) Tr ansmit/Recei ve FIFO Read = Receive FIFO Write = Transmit FIFO (If < 16 bits of data, the user must write the data to the Transmit FIFO in[...]

SSPIIR/SSPICR R/W Addr.: 0x40 00_2214 Default: 0x0000 Description SPI interrupt i dentification register (read) SPI interrupt clear register (write) Bit No. Name Description 0 RIS (Read) SPI Receive FIFO service request interrupt status 0 = SSPRXINTR is not active 1 = SSPRXINTR is active 1 TIS (Read) SPI Transmit FIFO se rvice request interrupt sta[...]

UART_CLK 0x0070 4 bytes R/W 0x00000000 UART clock selection 50MHz/6MHz Table 16: Over view of System Control Re gisters 4.8.2 System Control Register Description ID_REG R Addr.: 0x4000_2600 Default: 0x4027_0100 Description Identificati on of ERTEC 200. Bit No. Name Description 31..16 ERTEC200-ID ERTEC 200 id entifier: 4027h 15..8 HW-RELEASE HW rele[...]

PLL_STAT_REG R/W Addr.: 0x4000_2614 Default: 0x0007_0005 Description Status register for PLL of ERTEC 200 a nd i nterrupt control for FIQ3 Bit No. Name Description 31..18 Reserved Reserved 17 INT_MASK_LOSS INT_MASK_LOSS: Interrupt masking for INT_LOSS_STATE 0: Interrupt is enabled 1: Interrupt is masked Read/write accessible 16 INT_MASK_LOCK INT_MA[...]

QVZ_AHB_M R Addr.: 0x4000_2630 Default: 0x0000_0000 Description Master identifie r of an incorrect addressing on the multila yer AHB Bit No. Name Description 31:4 Reserved Reserved 3 QVZ_AHB_DMA DMA 2 QVZ_AHB_IRT IRT 1 QVZ_AHB_LBU LBU 0 QVZ_AHB_ARM946 ARM946 QVZ_APB_ADR R Addr.: 0x4000_2634 Default: 0x0000_0000 Description Address of inc orrect add[...]

ARM9_CTRL R/W Addr.: 0x4000_2650 Default: 0x0000_1939 Description Check of ARM 9 inp uts that ar e not accessible from exter nal pins. This register can only be w ritten to if th e Write enable bit is set in the ARM9_WE register. T his register can only be changed for debuggin g purposes! Bit No. Name Description 31:14 Reserved Reserv ed 13 BIGENDI[...]

12:10 P2_PHY_MODE 000: 10BASE-T HD, Auto-Neg disabled 001: 10BASE-T FD, Auto-Neg disable d 010: 100BASE-TX/FX HD, Auto-Neg dis abled 011: 100BASE-TX/FX FD, Auto-Neg disabl ed 100: 100BASE-TX HD annou nce d, Auto-Neg enabled 101: 100BASE-TX HD announce d, Auto-Neg enabled, Rep eater Mode 110: PHY starts in Power Down Mode 111: Auto-Neg enabled, Auto[...]

5 General Hardw are Functions 5.1 Clock Generation and Clock Supply The clock system of the ERTEC 200 basically consists of f our clock systems that are decoup led through asynchr onous transfers. This includes the follo wing clock systems: • ARM946E-S together with AHB bus, APB bus, and IRT • LBU • JTAG Interface • PHYs and Ethernet MACs 5[...]

5.1.2 JTAG Clock Supply The clock supply for the JTAG interface is im plem ented using the JT AG_CLK pin. The frequency range i s between 0 and 10 MHz. The boundar y s can and the ICE macro cell of the ARM946E -S are enabled via the JT AG interface. 5.1.3 Clock Supply for PHYs and Ethernet MACs Both Ethernet MACs are connected to the integrated PHY[...]

f/MHz t/µs t LOCK = 645 µs 35 Power- up PLL a c t i v e R e s e t 300 Figure 11: Pow er-Up Phase of the PLL The lock status of the PLL is monitored by the hard ware. Loss of the input cl ock and PLL not locked status is signale d with interrupt FIQ3. The state of the PLL can also be read out in the PII_STAT_REG system control register. A filter i[...]

5.3 Address Sp Monitoring mechan egal accesses, and timeout. The followi • AHB bus • APB bus • EMIF 5.3.1 AHB Bus Mo Separate address space mo DMA, LBU). If an AHB master addresses an un e and an FIQ2 interrupt is triggered at the ARM9 AHB_A DR system control register and the associated access t ype (re ad, write, HTRANS, HSIZE) is stored in [...]

Config [6] Config [5] Config [4] Config [3] Config [2] Config [1] Meaning - - - - - 1 REF_CLK tristate - - - - - 0 REF_CLK output (25 MHz) - 1 - - 0 - LBU = On, LBU-CFG: LBU_WR_N has read/write control - 0 - - 0 - LBU = On, LBU-CFG: Separate read and write line 1 - - - 0 - LBU = On, LBU_POL_RDY: LBU_RDY_N is high active 0 - - - 0 - LBU = On, LBU_PO[...]

6 External Memor y Interface (EMIF) In order to access an external memory area, an E xternal M emory I nter F ace is incorp orated in the ERTEC 200. The interface contains one SDRAM memor y controller and one SR AM memory control eac h for asynchronous memor y and I/O. Both interfaces can be assigned separat ely as active interfaces. That is, the d[...]

6.1 Address Assignment of EMIF Registers The EMIF registers are 32 bits in width . These registers can only be written to with double words. EMIF (Base Address 0x7000_0 000) Register Name Offset Address Addre ss Are a Access Default Description Revision_Code_and _Status 0x0000 4 bytes R 0x00000100 Revision code and status register Async_Wait_Cycle [...]

SDRAM Bank Config W/R Addr.: 0x7000_0008 Default: 0x0000_20A0 Description SDRAM bank config re gister Bit No. Name Description 31..14 Reserved Reserved 13* CL CAS latency 0: SDRAM is activated with CAS latency = 2 1: SDRAM is activated with CAS latency = 3 12..11 Reserved Reserved 10..8* ROWS 000: 8-row address lines 001: 9-row address lines 010: 1[...]

Async Bank 0 Config W/R Addr.: 0x7000_0010 Default: 0x3FFF_FFF2 Async Bank 1 Config W/R Addr.: 0x7000_0014 Default: 0x3FFF_FFF2 Async Bank 2 Config W/R Addr.: 0x7000_0018 Default: 0x3FFF_FFF2 Async Bank 3 Config W/R Addr.: 0x7000_001C Default: 0x3FFF_FFF2 Description Setting of timing and d ata bus width fo r access via asynchronous interface CS_PE[...]

Extended Config W/R Addr.: 0x7000_0020 Default: 0x0303_0000 Description Setting of addit ional functionalities Bit No. Name Description 31 Reserved Reserved 30 T EST_1 Test Mode 1 0: 200 µs delay after system reset (SDRAM power-up) 1: Delay after system reset is immediatel y ter minated 29 T EST_2 Test Mode 2 0: Normal function 1: All SDRAM access[...]

7 Local Bus Unit (LBU). The ERTEC 200 can also be operate d from an external host pr ocessor. The LBU bus i nte rfaces are ava ilable for this purpose: The bus system is selected using the CONFIG[2] input pin. CONFIG[2] = 0 LBU bus system is active CONFIG[2] = 1 LBU bus system is inactive (supplement al function PHY debug, ETM trace, GPIO[44:32] ca[...]

The four segments are addressed vi a the t wo LBU_SEG[1:0] inputs. LBU_SEG[1 : 0] Addressed Segment 00 LBU_PAGE0 01 LBU_PAGE1 10 LBU_PAGE2 11 LBU_PAGE3 Copyright © Siemens AG 2007. All rights reserved. 75 ERTEC 200 Manual Technical data subject to change Version 1.1.0[...]

7.1 Page Range Setting The page size of each page is set in the PAGEx_RANGE_H IGH and PAGEx_RANGE_LOW range registers (x = 0 to 3). Together, the two page range registers yield a 32-bit addres s register. The size of the page varies bet ween 256 bytes and 2 MBytes. Therefore, Bits 0 to 7 and Bits 22 to 31 of th e PAGEx_RANGE register remain u nchan[...]

7.3 LBU Address Mapping The following table illustrates an e xampl e of the ERTEC 200 Address Ma pping from the Perspective of an External H os t Processor: Seg(1:0) AD(19: 0) SEGMENT Distribution SEGMENT Size Comment 00 0_0000h 1MB 1MB Page SDRAM (1 Mbyte) 00 Range: 0010 0000h 00 F_FFFFh Offset: 2000 0000h 01 0_0000h 64k 1MB Page KRAM (64 Kbytes) [...]

7.4 Page Control Setting The user can use the page control reg ister to set the type of access to the relevant page. Certain areas of the ERTEC 200 must be implemented with a 32-bit data access in ord er to ensure data consistency. For other areas, an 8-bit or 16- bit data access is permitted. The follo wing table sh ows which ERTEC 200 address are[...]

7.5.1 LBU Read from ERTEC 200 w ith separa te Read/Write line (LB U_RDY_N activ e lo w) LBU_CS_R_N/ LBU_CS_M_N LBU_RD_N LBU_A(2 0:0)A/ LBU_SEG (1:0)/ LBU_BE (1:0 )_N LBU_RDY_N LBU_D(15:0) t CSRS t ARS t RRE t RDE t RTD t RDH t RAH t RCSH t RAP t RR Fig u re 13: L BU-Read-Sequence wi th separate RD/WR line Parameter Description Min Max t CSRS chip s[...]

7.5.2 LBU Write to ERTEC 200 with separa t e Read/ Write line (LBU_RDY_N active lo w) LBU_CS_R_N/ LBU_CD_M_N LBU_WR_N LBU_A(20:0)/ LBU_SEG(1:0) LBU_BE(1:0)_N LBU_RDY_N LBU_D(15:0) t CSW S t AW S t WR E t WD V t WD H t WAH t WC SH t RTW t RAP t WR Figu re 14: LBU-Write-Sequence with sep arate RD/WR line Parameter Description Min Max t CSWS chip sele[...]

7.5.3 LBU Read from ERTEC 200 w ith common Read/Write line (LBU_ RDY_ N active low) LBU_CS_R _N/ LBU_CS _M_N LBU_W R LBU_A(20:0) / LBU_SEG (1:0)/ LBU_BE (1:0 )_N LBU_RD Y LBU_D(15: 0) t WC S t ACS t CRE t CDE t RTD t CDH t CAH t CW H t RAP t RR Figu re 15: LBU-Read-Sequence w i th common RD/WR line Parameter Description Min Max t WCS write signal d[...]

7.5.4 LBU Write to ERTEC 200 with common Read/ Write line (LBU_RDY_N active low) LBU_CS_R_ N/ LBU_CS _M_N LBU_W R_N LBU_A(2 0:0)/ LBU_SEG (1:0)/ LBU_BE(1:0)_N LBU_RD Y LBU_D(15: 0) t WC S t ACS t CRE t CDV t CDH t CAH t CW H t RTC t RAP t WR Figure 16: LBU-Write-Sequence w ith common RD/WR line Parameter Description Min Max t WCS write signal a sse[...]

7.7 Address Assignment of LBU Registers The LBU registers are 16 bits in width . These registers can only be written to with words. The LBU pagi ng configuration registers are addressed via the "LBU _CS_R_N” input. LBU Register Name Offset Address Address Area Access Default Description LBU_P0_RG_L 0x0000 2 bytes W/R 0x0000 LBU pagex rang e [...]

LBU_P0_RG_H W/R Addr.: LBU_CS_R_ N+0x02 Default: 0x0000_0001 (64k ) LBU_P1_RG_H W/R Addr.: LBU_CS_R_ N+0x1 2 Default: 0x0000_0010 (1M) LBU_P2_RG_H W/R Addr.: LBU_CS_R_ N+0x2 2 Default: 0x0000_0020 (2M) LBU_P3_RG_H W/R Addr.: LBU_CS_R_ N+0x3 2 Default: 0x0000_0000 (2 k) Description High word of LBU Pagex_Range_register Bit No. Name Description 15..0[...]

8 DMA-Controller The ERTEC 200 has a 1-channel DMA co ntroller. T his enables da ta to be transferred without placi ng an additional load on the ARM946E-S. The following data transfers are possible: SOURCE TA RGET SYNCHRONIZATION Peripheral (1) Memory Source Memory Peripheral (1) Target Peripheral (1) Peripheral (1) Source and Target Memory Memory [...]

8.1 DMA Register Address Assignment The DMA registers are 32 bits in width . The registers can be written to with 32-bit accesses only. Only the ARM946E- S processor can access the registers. DMA-Register (Start 0x8000_0000) Register Name Offset Address Address Area Access Default Description DMAC0_SRC_ADDR_REG 0x0000 4 b ytes R/W 0x00000000 DMA St[...]

(DMAC0ConfReg) Channel Config (*) W/R Addr.: 0x8000_000C Default: 0x0000_0000 Description Control Bits. 31 START/ABORT Write: 0: Stop Transfer 1: Start Transfer Read: 0: Transfer completed or stopped 1: Transfer not yet complete 30 Reserved Reserv ed 29 INTR_ENABLE (****) 1: Enable interrupt 28..27 SYNCHRONIZATION 00: None 01: Destination 10: Sourc[...]

9 Multiport Ethernet PHY A 2-fold multiport PHY (Physical Layer T ransceiver) that supports the following transfer modes is integrated in th e ERTEC 200: • 10BASE-T • 100BASE-TX • 100BASE-FX These transfer modes are availab le separat ely for eac h port and can be set differently. The PHY is compatible with the follo wing standards: • IEEE8[...]

• P1/2_PHYADDRESS 4..0 Port1 = 00000b; Port2 = 00001b • P1/2_PHYMODE 2..0 see PHY_CONFIG in the SYSTEM-CONT ROL register area • P1/2_MIIMODE 1..0 MII-Interface (permanently set) • P1/2_SMIISOURCESYNC Normal SMII-Mode • P1/2_FXMODE see PHY_CONFIG in the SYST EM-CONTROL register area • P1/2_AUTOMIDIXEN see PHY_CONFIG in the SYST EM-CONTRO[...]

Power-State is approximately 15 mW per PHY. The Lo w-Power-Mode is exited again with Link-Pulses or Packets on the MII interface. The digital modes are reinitiali zed, but the configur ation is not saved again. When the Power Down state is exited, a 256-µs reset is generat ed internall y to stabilize the PLL before the PHY is again ready for opera[...]

10 Memory Description This section presents a detailed descriptio n of t he memory areas of all integrated function groups. 10.1 Memory Partitioning of the ERTEC 200 The table below lists the AHB masters alon g with th eir options for accessing various memory areas. Start- and Endadress Seg. Function Area for ARM 9 Function Area for IRTE Function A[...]

10.2 Detailed Memory Description The table below prese nts a detailed de scription of the mem ory segments. Mirrored segments should not be used for addressing to ensure compat ible memory expansion at a later date. Segment Contents Größe A dressbereich Beschreibung 0 Boot-ROM (0-8kB) or EMIF-SDRAM (0-128MB) or EMIF-Memory(0-64MB) or Locked I-Cac[...]

Segment Contents Größe A dressbereich Beschreibung 5 ARM-ICU 256 MB 5000_0000- 5FFF_FFFF ARM – Interrupt-Controller 128 Byte physical Note2 6 Not used 256 MB 600 0_0000- 6FFF_FFFF 7 EMIF-Register 256 MB 7000_ 0000- 7FFF_FFFF Steuer-Register for external Mem ory-Interface 64 Byte physical Note2 8 DMA-Register 256 MB 8000_0000- FFFF_FFFF DMA-Cont[...]

11 Test and Debugging 11.1 ETM9 Embedded Trace Macrocell An ETM9 module is integrated in the ARM9 46E-S of t he ERT EC 200 to enable the instruction code and data to be traced. The ARM946E-S supplies the ET M module with the sign als needed to carr y out the trace functions. The ETM9 module is operated by means of the T rac e interface or JTAG inte[...]

11.2 Trace Interface The trace interface is paramet erize d, enabled, and disabled b y means of a connecte d de bugger (e.g. by Lauterbach) on the JTAG interface. A Trace port is provided in the ERT EC 200 for tracing inter nal processor states: • PIPESTA [2:0] • TRACESYNC • TRACECLK • TRACEPKT[7:0] The PIPESTA[2:0], TRACEPKT[7:0], and TRAC[...]

12 Miscellaneous 12.1 Acronyms/Glossary: AHB AM B A A dvanc ed H igh Performance B us (Multimaster, Bursts) AMB A A dvanced M icrocontroller B us A rchitecture APB AMB A A dvanced P eriph eral B us (Single master, bursts) BIST B uilt I n S elf T est ComDeC Com munication, De velopment & C ertification DTCM D ata T ightly C oupled M em ory ERTEC[...]

12.2 References: /1/ Technical Reference Manual ARM946E-S REV1 16 February 2001 (DDI 0201A_946ES.PDF ); /2/ Technical Reference Manu al ARM946E-S 16 December 1999 (DDI_ 0165 A_9E-S_TRM. PDF); /3/ AHB PCI Bridge Revision2.5 08 July 2002 (amba2pci_r e v2.5.pdf); /4/ AMBA Specification (Revision 2.0), 1999; ARM /5/ ARM Prime Cell TM UART (PL010) Techn[...]