Texas Instruments TMS320C674X manuel d'utilisation

TMS320C674x/OMAP-L1x Processor Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) Module User's Guide Literature Number: SPRUFL5B April 2011[...]

2 SPRUFL5B – April 2011 Submit Documentation Feedback © 2011, Texas Instruments Incorporated[...]

Preface ...................................................................................................................................... 10 1 Introduction ...................................................................................................................... 12 1.1 Purpose of the Peripheral .....................................[...]

www.ti.com (C0RXIMAX-C2RXIMAX) ............................................................................................. 68 3.13 EMAC Control Module Interrupt Core Transmit Interrupts Per Millisecond Registers (C0TXIMAX-C2TXIMAX) .............................................................................................. 69 4 MDIO Registers .[...]

www.ti.com 5.31 Emulation Control Register (EMCONTROL) ...................................................................... 114 5.32 FIFO Control Register (FIFOCONTROL) ......................................................................... 114 5.33 MAC Configuration Register (MACCONFIG) .........................................................[...]

www.ti.com List of Figures 1 EMAC and MDIO Block Diagram ........................................................................................ 13 2 Ethernet Configuration—MII Connections .............................................................................. 15 3 Ethernet Configuration—RMII Connections ................................[...]

www.ti.com 47 Transmit Interrupt Mask Set Register (TXINTMASKSET) ........................................................... 92 48 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) ..................................................... 93 49 MAC Input Vector Register (MACINVECTOR) ..............................................................[...]

www.ti.com List of Tables 1 EMAC and MDIO Signals for MII Interface ............................................................................. 15 2 EMAC and MDIO Signals for RMII Interface ........................................................................... 16 3 Ethernet Frame Description ..................................................[...]

www.ti.com 46 Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions ..................................... 92 47 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions ............................... 93 48 MAC Input Vector Register (MACINVECTOR) Field Descriptions .................................................[...]

Preface SPRUFL5B – April 2011 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the device. Included are the features of the EMAC and MDIO modules, a discussion of their architectu[...]

www.ti.com Related Documentation From Texas Instruments SPRUGM7 — OMAP-L138 Applications Processor System Reference Guide. Describes the System-on-Chip (SoC) including the ARM subsystem, DSP subsystem, system memory, device clocking, phase-locked loop controller (PLLC), power and sleep controller (PSC), power management, ARM interrupt controller [...]

User's Guide SPRUFL5B – April 2011 EMAC/MDIO Module 1 Introduction This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the device. Included are the features of the EMAC and MDIO modules, a discussion of their ar[...]

DMA Master 8KCPPI RAM Interrupt Combiner C0 C1 C2 ControlModule EMAC Module MDIO Module EMAC Interrupts MDIO Interrupts Interrupts EMACSubSystem RegisterBus DMA Bus MII/RMIIBus MDIOBus www.ti.com Introduction 1.3 Functional Block Diagram Figure 1 shows the three main functional modules of the EMAC/MDIO peripheral: • EMAC cont[...]

Architecture www.ti.com 1.4 Industry Standard(s) Compliance Statement The EMAC peripheral conforms to the IEEE 802.3 standard, describing the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer specifications. The IEEE 802.3 standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2[...]

MII_TXCLK MII_TXD[3−0] MII_TXEN MII_COL MII_CRS MII_RXCLK MII_RXD[3−0] MII_RXDV MII_RXER MDIO_CLK MDIO_D Physical layer device (PHY) System core Transformer 2.5 MHz or 25 MHz RJ−45 EMAC MDIO www.ti.com Architecture The individual EMAC and MDIO signals for the MII interface are summarized in Table 1 . For more information, refer to either the [...]

RMII_TXD[1-0] RMII_TXEN RMII_MHZ_50_CLK RMII_RXD[1-0] RMII_CRS_DV RMII_RXER MDIO_CLK MDIO_D MDIO EMAC Physical Layer Device (PHY) T ransformer 50MHz RJ-45 Architecture www.ti.com Table 1. EMAC and MDIO Signals for MII Interface (continued) Signal Type Description MDIO_CLK O Management data clock (MDIO_CLK). The MDIO data clock is sourced by the [...]

Preamble SFD Destination Source Len Data 7 1 6 6 2 46−1500 4 FCS Number of bytes Legend: SFD=Start Frame Delimeter; FCS=Frame Check Sequence (CRC) www.ti.com Architecture 2.4 Ethernet Protocol Overview A brief overview of the Ethernet protocol is given in the following subsections. See the IEEE 802.3 standard document for in-depth information on [...]

Architecture www.ti.com 2.4.2 Ethernet ’s Multiple Access Protocol Nodes in an Ethernet Local Area Network are interconnected by a broadcast channel -- when an EMAC port transmits a frame, all the adapters on the local network receive the frame. Carrier Sense Multiple Access with Collision Detection (CSMA/CD) algorithms are used when the EMAC ope[...]

SOP | EOP 60 0 60 pBuffer pNext Packet A 60 bytes 0 SOP Fragment 1 Packet B 512 1514 pBuffer pNext 512 bytes EOP 0 0 −−− Packet B Fragment 3 500 bytes 502 pBuffer −−− 500 pNext −−− pBuffer pNext Packet B Fragment 2 502 bytes SOP | EOP 0 1514 bytes Packet C 1514 pBuffer pNext (NULL) 1514 www.ti.com Architecture Table 4. Basic Descr[...]

Architecture www.ti.com 2.5.2 Transmit and Receive Descriptor Queues The EMAC module processes descriptors in linked lists as discussed in Section 2.5.1 . The lists used by the EMAC are maintained by the application software through the use of the head descriptor pointer registers (HDP). The EMAC supports eight channels for transmit and eight chann[...]

www.ti.com Architecture 2.5.3 Transmit and Receive EMAC Interrupts The EMAC processes descriptors in linked list chains as discussed in Section 2.5.1 , using the linked list queue mechanism discussed in Section 2.5.2 . The EMAC synchronizes descriptor list processing through the use of interrupts to the software application. The interrupts are cont[...]

Architecture www.ti.com Figure 7. Transmit Buffer Descriptor Format Word 0 31 0 Next Descriptor Pointer Word 1 31 0 Buffer Pointer Word 2 31 16 15 0 Buffer Offset Buffer Length Word 3 31 30 29 28 27 26 25 16 SOP EOP OWNER EOQ TDOWNCMPLT PASSCRC Reserved 15 0 Packet Length Example 1. Transmit Buffer Descriptor in C Structure Format /* // EMAC Descri[...]

www.ti.com Architecture 2.5.4.1 Next Descriptor Pointer The next descriptor pointer points to the 32-bit word aligned memory address of the next buffer descriptor in the transmit queue. This pointer is used to create a linked list of buffer descriptors. If the value of this pointer is zero, then the current buffer is the last buffer in the queue. T[...]

Architecture www.ti.com 2.5.4.7 End of Packet (EOP) Flag When set, this flag indicates that the descriptor points to a packet buffer that is last for a given packet. In the case of a single fragment packet, both the start of packet (SOP) and EOP flags are set. Otherwise, the descriptor pointing to the last packet buffer for the packet sets the EOP [...]

www.ti.com Architecture 2.5.5 Receive Buffer Descriptor Format A receive (RX) buffer descriptor ( Figure 8 ) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 2 shows the receive buffer descriptor described by a C structure. 2.5.5.1 Next Descriptor Pointer This pointer[...]

Architecture www.ti.com Example 2. Receive Buffer Descriptor in C Structure Format /* // EMAC Descriptor // // The following is the format of a single buffer descriptor // on the EMAC. */ typedef struct _EMAC_Desc { struct _EMAC_Desc *pNext; /* Pointer to next descriptor in chain */ Uint8 *pBuffer; /* Pointer to data buffer */ Uint32 BufOffLen; /* [...]

www.ti.com Architecture 2.5.5.4 Buffer Length This 16-bit field is used for two purposes: • Before the descriptor is first placed on the receive queue by the application software, the buffer length field is first initialized by the software to have the physical size of the empty data buffer pointed to by the buffer pointer field. • After the em[...]

Architecture www.ti.com 2.5.5.11 Pass CRC (PASSCRC) Flag This flag is set by the EMAC in the SOP buffer descriptor if the received packet includes the 4-byte CRC. This flag should be cleared by the software application before submitting the descriptor to the receive queue. 2.5.5.12 Jabber Flag This flag is set by the EMAC in the SOP buffer descript[...]

Arbiter and bus switches CPU DMA Controllers 8K byte descriptor memory Configuration registers Interrupt logic Interrupts to CPU EMAC interrupts MDIO interrupts Configuration bus T ransmit and Receive www.ti.com Architecture 2.6 EMAC Control Module The EMAC control module ( Figure 9 ) interfaces the EMAC and MDIO modules to the rest of the system, [...]

Architecture www.ti.com 2.6.3 Interrupt Control Interrupt conditions generated by the EMAC and MDIO modules are combined into four interrupt signals that are routed to three independent interrupt cores in the EMAC control module; the interrupt cores then relay the interrupt signals to the CPU interrupt controller. The EMAC control module uses two s[...]

EMAC control module Control registers and logic PHY monitoring Peripheral clock MDIO clock generator USERINT MDIO interface polling PHY MDCLK MDIO LINKINT Configuration bus www.ti.com Architecture Figure 10. MDIO Module Block Diagram 2.7.1.1 MDIO Clock Generator The MDIO clock generator controls the MDIO clock based on a divide-down of the peripher[...]

Architecture www.ti.com 2.7.2 MDIO Module Operational Overview The MDIO module implements the 802.3 serial management interface to interrogate and control an Ethernet PHY, using a shared two-wired bus. It separately performs autodetection and records the current link status of up to 32 PHYs, polling all 32 MDIO addresses. Application software uses [...]

www.ti.com Architecture 2.7.2.1 Initializing the MDIO Module The following steps are performed by the application software or device driver to initialize the MDIO device: 1. Configure the PREAMBLE and CLKDIV bits in the MDIO control register (CONTROL). 2. Enable the MDIO module by setting the ENABLE bit in CONTROL. 3. The MDIO PHY alive status regi[...]

Architecture www.ti.com 2.7.2.4 Example of MDIO Register Access Code The MDIO module uses the MDIO user access register (USERACCESS n ) to access the PHY control registers. Software functions that implement the access process may simply be the following four macros: • PHYREG_read( regadr, phyadr ) Start the process of reading a PHY register • P[...]

Clock and reset logic Receive DMA engine Interrupt controller Transmit DMA engine Control registers Configuration bus EMAC control module Configuration bus RAM State FIFO Receive FIFO Transmit MAC transmitter Statistics receiver MAC SYNC MII address Receive RMII www.ti.com Architecture 2.8 EMAC Module This section discusses the architecture and bas[...]

Architecture www.ti.com 2.8.1.4 Transmit DMA Engine The transmit DMA engine is the interface between the transmit FIFO and the CPU. It interfaces to the CPU through the bus arbiter in the EMAC control module. 2.8.1.5 Transmit FIFO The transmit FIFO consists of three cells of 64-bytes each and associated control logic. The FIFO buffers data in prepa[...]

www.ti.com Architecture The EMAC module operates independently of the CPU. It is configured and controlled by its register set mapped into device memory. Information about data packets is communicated by use of 16-byte descriptors that are placed in an 8K-byte block of RAM in the EMAC control module (CPPI buffer descriptor memory). For transmit ope[...]

Architecture www.ti.com In either case, receive flow control prevents frame reception by issuing the flow control appropriate for the current mode of operation. Receive flow control prevents reception of frames on the EMAC until all of the triggering conditions clear, at which time frames may again be received by the EMAC. Receive flow control is e[...]

www.ti.com Architecture 2.9.2 Data Transmission The EMAC passes data to the PHY from the transmit FIFO (when enabled). Data is synchronized to the transmit clock rate. Transmission begins when there are TXCELLTHRESH cells of 64 bytes each, or a complete packet, in the FIFO. 2.9.2.1 Transmit Control A jam sequence is output if a collision is detecte[...]

Architecture www.ti.com 2.9.2.6 Transmit Flow Control Incoming pause frames are acted upon, when enabled, to prevent the EMAC from transmitting any further frames. Incoming pause frames are only acted upon when the FULLDUPLEX and TXFLOWEN bits in the MAC control register (MACCONTROL) are set. Pause frames are not acted upon in half-duplex mode. Pau[...]

www.ti.com Architecture 2.10 Packet Receive Operation 2.10.1 Receive DMA Host Configuration To configure the receive DMA for operation the host must: • Initialize the receive addresses. • Initialize the receive channel n DMA head descriptor pointer registers (RX n HDP) to 0. • Write the MAC address hash n registers (MACHASH1 and MACHASH2), if[...]

Architecture www.ti.com 2.10.4 Hardware Receive QOS Support Hardware receive quality of service (QOS) is supported, when enabled, by the Tag Protocol Identifier format and the associated Tag Control Information (TCI) format priority field. When the incoming frame length/type value is equal to 81.00h, the EMAC recognizes the frame as an Ethernet Enc[...]

www.ti.com Architecture 2.10.7 Receive Frame Classification Received frames are proper (good) frames, if they are between 64 bytes and the value in the receive maximum length register (RXMAXLEN) bytes in length (inclusive) and contain no code, align, or CRC errors. Received frames are long frames, if their frame count exceeds the value in RXMAXLEN.[...]

Architecture www.ti.com Table 5. Receive Frame Treatment Summary Address Match RXCAFEN RXCEFEN RXCMFEN RXCSFEN Receive Frame Treatment 0 0 X X X No frames transferred. 0 1 0 0 0 Proper frames transferred to promiscuous channel. 0 1 0 0 1 Proper/undersized data frames transferred to promiscuous channel. 0 1 0 1 0 Proper data and control frames trans[...]

www.ti.com Architecture 2.10.9 Receive Overrun The types of receive overrun are: • FIFO start of frame overrun (FIFO_SOF) • FIFO middle of frame overrun (FIFO_MOF) • DMA start of frame overrun (DMA_SOF) • DMA middle of frame overrun (DMA_MOF) The statistics counters used to track these types of receive overrun are: • Receive start of fram[...]

Architecture www.ti.com 2.11 Packet Transmit Operation The transmit DMA is an eight channel interface. Priority between the eight queues may be either fixed or round-robin as selected by the TXPTYPE bit in the MAC control register (MACCONTROL). If the priority type is fixed, then channel 7 has the highest priority and channel 0 has the lowest prior[...]

www.ti.com Architecture 2.12 Receive and Transmit Latency The transmit and receive FIFOs each contain three 64-byte cells. The EMAC begins transmission of a packet on the wire after TXCELLTHRESH (configurable through the FIFO control register) cells, or a complete packet, are available in the FIFO. Transmit underrun cannot occur for packet sizes of[...]

Architecture www.ti.com 2.14 Reset Considerations 2.14.1 Software Reset Considerations Peripheral clock and reset control is done through the Power and Sleep Controller (PSC) module included with the device. For more on how the EMAC, MDIO, and EMAC control module are disabled or placed in reset at runtime from the registers located in the PSC modul[...]

www.ti.com Architecture 2.15 Initialization 2.15.1 Enabling the EMAC/MDIO Peripheral When the device is powered on, the EMAC peripheral may be in a disabled state. Before any EMAC specific initialization can take place, the EMAC needs to be enabled; otherwise, its registers cannot be written and the reads will all return a value of zero. The EMAC/M[...]

Architecture www.ti.com 2.15.4 EMAC Module Initialization The EMAC module is used to send and receive data packets over the network. This is done by maintaining up to eight transmit and receive descriptor queues. The EMAC module configuration must also be kept up-to-date based on PHY negotiation results returned from the MDIO module. Most of the wo[...]

www.ti.com Architecture 2.16 Interrupt Support 2.16.1 EMAC Module Interrupt Events and Requests The EMAC module generates 26 interrupt events: • TXPEND n : Transmit packet completion interrupt for transmit channels 0 through 7 • RXPEND n : Receive packet completion interrupt for receive channels 0 through 7 • RXTHRESHPEND n : Receive packet c[...]

Architecture www.ti.com When the EMAC completes a packet reception, the EMAC issues an interrupt to the CPU by writing the packet's last buffer descriptor address to the appropriate channel queue's receive completion pointer located in the state RAM block. The interrupt is generated by the write when enabled by the interrupt mask, regardl[...]

www.ti.com Architecture The receive host error conditions are: • Ownership bit not set in input buffer • Zero buffer pointer The application software must acknowledge the EMAC control module after receiving host error interrupts by writing the appropriate C n MISC key to the EMAC End-Of-Interrupt Vector (MACEOIVECTOR). See Section 5.12 for the [...]

Architecture www.ti.com 2.16.2.2 User Access Completion Interrupt When the GO bit in one of the MDIO register USERACCESS0 transitions from 1 to 0 (indicating completion of a user access) and the corresponding USERINTMASKSET bit in the MDIO user command complete interrupt mask set register (USERINTMASKSET) corresponding to USERACCESS0 is set, a user[...]

www.ti.com Architecture 2.17 Power Management Each of the three main components of the EMAC peripheral can independently be placed in reduced-power modes to conserve power during periods of low activity. The power management of the EMAC peripheral is controlled by the processor Power and Sleep Controller (PSC). The PSC acts as a master controller f[...]

EMAC Control Module Registers www.ti.com 3 EMAC Control Module Registers Table 8 lists the memory-mapped registers for the EMAC control module. See your device-specific data manual for the memory address of these registers. Table 8. EMAC Control Module Registers Offset Acronym Register Description Section 0h REVID EMAC Control Module Revision ID Re[...]

www.ti.com EMAC Control Module Registers Table 8. EMAC Control Module Registers (continued) Offset Acronym Register Description Section 70h C0RXIMAX EMAC Control Module Interrupt Core 0 Receive Interrupts Per Section 3.12 Millisecond Register 74h C0TXIMAX EMAC Control Module Interrupt Core 0 Transmit Interrupts Per Section 3.13 Millisecond Register[...]

EMAC Control Module Registers www.ti.com 3.2 EMAC Control Module Software Reset Register (SOFTRESET) The EMAC Control Module Software Reset Register (SOFTRESET) is shown in Figure 13 and described in Table 10 . Figure 13. EMAC Control Module Software Reset Register (SOFTRESET) 31 16 Reserved R-0 15 1 0 Reserved RESET R-0 R/W-0 LEGEND: R/W = Read/Wr[...]

www.ti.com EMAC Control Module Registers 3.3 EMAC Control Module Interrupt Control Register (INTCONTROL) The EMAC control module interrupt control register (INTCONTROL) is shown in Figure 14 and described in Table 11 . The settings in the INTCONTROL register are used in conjunction with the CnRXIMAX and CnTXIMAX registers. Figure 14. EMAC Control M[...]

EMAC Control Module Registers www.ti.com 3.4 EMAC Control Module Interrupt Core Receive Threshold Interrupt Enable Registers (C0RXTHRESHEN-C2RXTHRESHEN) The EMAC control module interrupt core 0-2 receive threshold interrupt enable register (C n RXTHRESHEN) is shown in Figure 15 and described in Table 12 . Figure 15. EMAC Control Module Interrupt Co[...]

www.ti.com EMAC Control Module Registers 3.5 EMAC Control Module Interrupt Core Receive Interrupt Enable Registers (C0RXEN-C2RXEN) The EMAC control module interrupt core 0-2 receive interrupt enable register (C n RXEN) is shown in Figure 16 and described in Table 13 Figure 16. EMAC Control Module Interrupt Core 0-2 Receive Interrupt Enable Register[...]

EMAC Control Module Registers www.ti.com 3.6 EMAC Control Module Interrupt Core Transmit Interrupt Enable Registers (C0TXEN-C2TXEN) The EMAC control module interrupt core 0-2 transmit interrupt enable register (C n TXEN) is shown in Figure 17 and described in Table 14 Figure 17. EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Enable Regis[...]

www.ti.com EMAC Control Module Registers 3.7 EMAC Control Module Interrupt Core Miscellaneous Interrupt Enable Registers (C0MISCEN-C2MISCEN) The EMAC control module interrupt core 0-2 miscellaneous interrupt enable register (C n MISCEN) is shown in Figure 18 and described in Table 15 Figure 18. EMAC Control Module Interrupt Core 0-2 Miscellaneous I[...]

EMAC Control Module Registers www.ti.com 3.8 EMAC Control Module Interrupt Core Receive Threshold Interrupt Status Registers (C0RXTHRESHSTAT-C2RXTHRESHSTAT) The EMAC control module interrupt core 0-2 receive threshold interrupt status register (C n RXTHRESHSTAT) is shown in Figure 19 and described in Table 16 Figure 19. EMAC Control Module Interrup[...]

www.ti.com EMAC Control Module Registers 3.9 EMAC Control Module Interrupt Core Receive Interrupt Status Registers (C0RXSTAT-C2RXSTAT) The EMAC control module interrupt core 0-2 receive interrupt status register (C n RXSTAT) is shown in Figure 20 and described in Table 17 Figure 20. EMAC Control Module Interrupt Core 0-2 Receive Interrupt Status Re[...]

EMAC Control Module Registers www.ti.com 3.10 EMAC Control Module Interrupt Core Transmit Interrupt Status Registers (C0TXSTAT-C2TXSTAT) The EMAC control module interrupt core 0-2 transmit interrupt status register (C n TXSTAT) is shown in Figure 21 and described in Table 18 Figure 21. EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Statu[...]

www.ti.com EMAC Control Module Registers 3.11 EMAC Control Module Interrupt Core Miscellaneous Interrupt Status Registers (C0MISCSTAT-C2MISCSTAT) The EMAC control module interrupt core 0-2 miscellaneous interrupt status register (C n MISCSTAT) is shown in Figure 22 and described in Table 19 Figure 22. EMAC Control Module Interrupt Core 0-2 Miscella[...]

EMAC Control Module Registers www.ti.com 3.12 EMAC Control Module Interrupt Core Receive Interrupts Per Millisecond Registers (C0RXIMAX-C2RXIMAX) The EMAC control module interrupt core 0-2 receive interrupts per millisecond register (C n RXIMAX) is shown in Figure 23 and described in Table 20 Figure 23. EMAC Control Module Interrupt Core 0-2 Receiv[...]

www.ti.com EMAC Control Module Registers 3.13 EMAC Control Module Interrupt Core Transmit Interrupts Per Millisecond Registers (C0TXIMAX-C2TXIMAX) The EMAC control module interrupt core 0-2 transmit interrupts per millisecond register (C n TXIMAX) is shown in Figure 24 and described in Table 21 Figure 24. EMAC Control Module Interrupt Core 0-2 Tran[...]

MDIO Registers www.ti.com 4 MDIO Registers Table 22 lists the memory-mapped registers for the MDIO module. See your device-specific data manual for the memory address of these registers. Table 22. Management Data Input/Output (MDIO) Registers Offset Acronym Register Description Section 0h REVID MDIO Revision ID Register Section 4.1 4h CONTROL MDIO [...]

www.ti.com MDIO Registers 4.2 MDIO Control Register (CONTROL) The MDIO control register (CONTROL) is shown in Figure 26 and described in Table 24 . Figure 26. MDIO Control Register (CONTROL) 31 30 29 28 24 23 21 20 19 18 17 16 IDLE ENABLE Rsvd HIGHEST_USER_CHANNEL Reserved PREAMBLE FAULT FAULTENB Reserved R-1 R/W-0 R-0 R-1 R-0 R/W-0 R/W1C-0 R/W-0 R[...]

MDIO Registers www.ti.com 4.3 PHY Acknowledge Status Register (ALIVE) The PHY acknowledge status register (ALIVE) is shown in Figure 27 and described in Table 25 . Figure 27. PHY Acknowledge Status Register (ALIVE) 31 0 ALIVE R/W1C-0 LEGEND: R/W = Read/Write; W1C = Write 1 to clear (writing a 0 has no effect); - n = value after reset Table 25. PHY [...]

www.ti.com MDIO Registers 4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) The MDIO link status change interrupt (unmasked) register (LINKINTRAW) is shown in Figure 29 and described in Table 27 . Figure 29. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) 31 16 Reserved R-0 15 2 1 0 Reserved USERPHY1 USERPHY0[...]

MDIO Registers www.ti.com 4.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) The MDIO link status change interrupt (masked) register (LINKINTMASKED) is shown in Figure 30 and described in Table 28 . Figure 30. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) 31 16 Reserved R-0 15 2 1 0 Reserved USERPHY1 USERP[...]

www.ti.com MDIO Registers 4.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) The MDIO user command complete interrupt (unmasked) register (USERINTRAW) is shown in Figure 31 and described in Table 29 . Figure 31. MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) 31 16 Reserved R-0 15 2 1 0 Reserved USERACCE[...]

MDIO Registers www.ti.com 4.8 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) The MDIO user command complete interrupt (masked) register (USERINTMASKED) is shown in Figure 32 and described in Table 30 . Figure 32. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) 31 16 Reserved R-0 15 2 1 0 Reserved USERA[...]

www.ti.com MDIO Registers 4.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) The MDIO user command complete interrupt mask set register (USERINTMASKSET) is shown in Figure 33 and described in Table 31 . Figure 33. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) 31 16 Reserved R-0 15 2 1 0 Reserved US[...]

MDIO Registers www.ti.com 4.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in Figure 34 and described in Table 32 . Figure 34. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) 31 16 Reserved R-0 15 2 1 [...]

www.ti.com MDIO Registers 4.11 MDIO User Access Register 0 (USERACCESS0) The MDIO user access register 0 (USERACCESS0) is shown in Figure 35 and described in Table 33 . Figure 35. MDIO User Access Register 0 (USERACCESS0) 31 30 29 28 26 25 21 20 16 GO WRITE ACK Reserved REGADR PHYADR R/W1S-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 15 0 DATA R/W-0 LEGEND: R/W =[...]

MDIO Registers www.ti.com 4.12 MDIO User PHY Select Register 0 (USERPHYSEL0) The MDIO user PHY select register 0 (USERPHYSEL0) is shown in Figure 36 and described in Table 34 . Figure 36. MDIO User PHY Select Register 0 (USERPHYSEL0) 31 16 Reserved R-0 15 8 7 6 5 4 0 Reserved LINKSEL LINKINTENB Rsvd PHYADRMON R-0 R/W-0 R/W-0 R-0 R/W-0 LEGEND: R/W =[...]

www.ti.com MDIO Registers 4.13 MDIO User Access Register 1 (USERACCESS1) The MDIO user access register 1 (USERACCESS1) is shown in Figure 37 and described in Table 35 . Figure 37. MDIO User Access Register 1 (USERACCESS1) 31 30 29 28 26 25 21 20 16 GO WRITE ACK Reserved REGADR PHYADR R/W1S-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 15 0 DATA R/W-0 LEGEND: R/W =[...]

MDIO Registers www.ti.com 4.14 MDIO User PHY Select Register 1 (USERPHYSEL1) The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 38 and described in Table 36 . Figure 38. MDIO User PHY Select Register 1 (USERPHYSEL1) 31 16 Reserved R-0 15 8 7 6 5 4 0 Reserved LINKSEL LINKINTENB Rsvd PHYADRMON R-0 R/W-0 R/W-0 R-0 R/W-0 LEGEND: R/W =[...]

www.ti.com EMAC Module Registers 5 EMAC Module Registers Table 37 lists the memory-mapped registers for the EMAC. See your device-specific data manual for the memory address of these registers. Table 37. Ethernet Media Access Controller (EMAC) Registers Offset Acronym Register Description Section 0h TXREVID Transmit Revision ID Register Section 5.1[...]

EMAC Module Registers www.ti.com Table 37. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description Section 164h MACSTATUS MAC Status Register Section 5.30 168h EMCONTROL Emulation Control Register Section 5.31 16Ch FIFOCONTROL FIFO Control Register Section 5.32 170h MACCONFIG MAC Configuration Register Sect[...]

www.ti.com EMAC Module Registers Table 37. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description Section 67Ch RX7CP Receive Channel 7 Completion Pointer Register Section 5.49 Network Statistics Registers 200h RXGOODFRAMES Good Receive Frames Register Section 5.50.1 204h RXBCASTFRAMES Broadcast Receive Fra[...]

EMAC Module Registers www.ti.com 5.1 Transmit Revision ID Register (TXREVID) The transmit revision ID register (TXREVID) is shown in Figure 39 and described in Table 38 . Figure 39. Transmit Revision ID Register (TXREVID) 31 0 TXREV R-4EC0 020Dh LEGEND: R = Read only; - n = value after reset Table 38. Transmit Revision ID Register (TXREVID) Field D[...]

www.ti.com EMAC Module Registers 5.3 Transmit Teardown Register (TXTEARDOWN) The transmit teardown register (TXTEARDOWN) is shown in Figure 41 and described in Table 40 . Figure 41. Transmit Teardown Register (TXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved TXTDNCH R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 40[...]

EMAC Module Registers www.ti.com 5.4 Receive Revision ID Register (RXREVID) The receive revision ID register (RXREVID) is shown in Figure 42 and described in Table 41 . Figure 42. Receive Revision ID Register (RXREVID) 31 0 RXREV R-4EC0 020Dh LEGEND: R = Read only; - n = value after reset Table 41. Receive Revision ID Register (RXREVID) Field Descr[...]

www.ti.com EMAC Module Registers 5.6 Receive Teardown Register (RXTEARDOWN) The receive teardown register (RXTEARDOWN) is shown in Figure 44 and described in Table 43 . Figure 44. Receive Teardown Register (RXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved RXTDNCH R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 43. R[...]

EMAC Module Registers www.ti.com 5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) The transmit interrupt status (unmasked) register (TXINTSTATRAW) is shown in Figure 45 and described in Table 44 . Figure 45. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) 31 16 Reserved R-0 15 8 Reserved R-0 76543210 TX7PEND TX6PEND TX5[...]

www.ti.com EMAC Module Registers 5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) The transmit interrupt status (masked) register (TXINTSTATMASKED) is shown in Figure 46 and described in Table 45 . Figure 46. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) 31 16 Reserved R-0 15 8 Reserved R-0 76543210 TX7PEND TX6PEND [...]

EMAC Module Registers www.ti.com 5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET) The transmit interrupt mask set register (TXINTMASKSET) is shown in Figure 47 and described in Table 46 . Figure 47. Transmit Interrupt Mask Set Register (TXINTMASKSET) 31 16 Reserved R-0 15 8 Reserved R-0 76543210 TX7MASK TX6MASK TX5MASK TX4MASK TX3MASK TX2MAS[...]

www.ti.com EMAC Module Registers 5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) The transmit interrupt mask clear register (TXINTMASKCLEAR) is shown in Figure 48 and described in Table 47 . Figure 48. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) 31 16 Reserved R-0 15 8 Reserved R-0 76543210 TX7MASK TX6MASK TX5MASK TX4MASK T[...]

EMAC Module Registers www.ti.com 5.11 MAC Input Vector Register (MACINVECTOR) The MAC input vector register (MACINVECTOR) is shown in Figure 49 and described in Table 48 . Figure 49. MAC Input Vector Register (MACINVECTOR) 31 28 27 26 25 24 23 16 Reserved STATPEND HOSTPEND LINKINT0 USERINT0 TXPEND R-0 R-0 R-0 R-0 R-0 R-0 15 8 7 0 RXTHRESHPEND RXPEN[...]

www.ti.com EMAC Module Registers 5.12 MAC End Of Interrupt Vector Register (MACEOIVECTOR) The MAC end of interrupt vector register (MACEOIVECTOR) is shown in Figure 50 and described in Table 49 . Figure 50. MAC End Of Interrupt Vector Register (MACEOIVECTOR) 31 16 Reserved R-0 15 5 4 0 Reserved INTVECT R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read o[...]

EMAC Module Registers www.ti.com 5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) The receive interrupt status (unmasked) register (RXINTSTATRAW) is shown in Figure 51 and described in Table 50 . Figure 51. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) 31 16 Reserved R-0 15 14 13 12 11 10 9 8 RX7THRESHPEND RX6THRESHPEN[...]

www.ti.com EMAC Module Registers 5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) The receive interrupt status (masked) register (RXINTSTATMASKED) is shown in Figure 52 and described in Table 51 . Figure 52. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) 31 16 Reserved R-0 15 14 13 12 11 10 9 8 RX7THRESHPEND RX6THRESH[...]

EMAC Module Registers www.ti.com 5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) The receive interrupt mask set register (RXINTMASKSET) is shown in Figure 53 and described in Table 52 . Figure 53. Receive Interrupt Mask Set Register (RXINTMASKSET) 31 16 Reserved R-0 15 14 13 12 11 10 9 8 RX7THRESHMASK RX6THRESHMASK RX5THRESHMASK RX4THRESHMA[...]

www.ti.com EMAC Module Registers 5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 54 and described in Table 53 . Figure 54. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) 31 16 Reserved R-0 15 14 13 12 11 10 9 8 RX7THRESHMASK RX6THRESHMASK RX5THRESHMASK[...]

EMAC Module Registers www.ti.com 5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) The MAC interrupt status (unmasked) register (MACINTSTATRAW) is shown in Figure 55 and described in Table 54 . Figure 55. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) 31 16 Reserved R-0 15 2 1 0 Reserved HOSTPEND STATPEND R-0 R-0 R-0 LEGEND: R[...]

www.ti.com EMAC Module Registers 5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure 57 and described in Table 56 . Figure 57. MAC Interrupt Mask Set Register (MACINTMASKSET) 31 16 Reserved R-0 15 2 1 0 Reserved HOSTMASK STATMASK R-0 R/W1S-0 R/W1S-0 LEGEND: R/W = Read/Write; R [...]

EMAC Module Registers www.ti.com 5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) The receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) is shown in Figure 59 and described in Table 58 . Figure 59. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) 31 30 29 28 2[...]

www.ti.com EMAC Module Registers Table 58. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions (continued) Bit Field Value Description 22 RXCEFEN Receive copy error frames enable bit. Enables frames containing errors to be transferred to memory. The appropriate error bit will be set in the frame EOP buff[...]

EMAC Module Registers www.ti.com Table 58. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions (continued) Bit Field Value Description 2-0 RXMULTCH 0-7h Receive multicast channel select 0 Select channel 0 to receive multicast frames 1h Select channel 1 to receive multicast frames 2h Select channel 2 to r[...]

www.ti.com EMAC Module Registers 5.22 Receive Unicast Enable Set Register (RXUNICASTSET) The receive unicast enable set register (RXUNICASTSET) is shown in Figure 60 and described in Table 59 . Figure 60. Receive Unicast Enable Set Register (RXUNICASTSET) 31 16 Reserved R-0 15 8 Reserved R-0 76543210 RXCH7EN RXCH6EN RXCH5EN RXCH4EN RXCH3EN RXCH2EN [...]

EMAC Module Registers www.ti.com 5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 61 and described in Table 60 . Figure 61. Receive Unicast Clear Register (RXUNICASTCLEAR) 31 16 Reserved R-0 15 8 Reserved R-0 76543210 RXCH7EN RXCH6EN RXCH5EN RXCH4EN RXCH3EN RXCH2EN RXCH1EN R[...]

www.ti.com EMAC Module Registers 5.24 Receive Maximum Length Register (RXMAXLEN) The receive maximum length register (RXMAXLEN) is shown in Figure 62 and described in Table 61 . Figure 62. Receive Maximum Length Register (RXMAXLEN) 31 16 Reserved R-0 15 0 RXMAXLEN R/W-5EEh LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 61. R[...]

EMAC Module Registers www.ti.com 5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) is shown in Figure 64 and described in Table 63 . Figure 64. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) 31 16 Reserved R-0 15 8 7 0 [...]

www.ti.com EMAC Module Registers 5.28 Receive Channel Free Buffer Count Registers (RX0FREEBUFFER-RX7FREEBUFFER) The receive channel 0-7 free buffer count register (RX n FREEBUFFER) is shown in Figure 66 and described in Table 65 . Figure 66. Receive Channel n Free Buffer Count Register (RX n FREEBUFFER) 31 16 Reserved R-0 15 0 RX n FREEBUF WI-0 LEG[...]

EMAC Module Registers www.ti.com 5.29 MAC Control Register (MACCONTROL) The MAC control register (MACCONTROL) is shown in Figure 67 and described in Table 66 . Figure 67. MAC Control Register (MACCONTROL) 31 16 Reserved R-0 15 14 13 12 11 10 9 8 RMIISPEED RXOFFLENBLOCK RXOWNERSHIP Rsvd CMDIDLE TXSHORTGAPEN TXPTYPE Reserved R/W-0 R/W-0 R/W-0 R-0 R/W[...]

www.ti.com EMAC Module Registers Table 66. MAC Control Register (MACCONTROL) Field Descriptions (continued) Bit Field Value Description 4 TXFLOWEN Transmit flow control enable bit. This bit determines if incoming pause frames are acted upon in full-duplex mode. Incoming pause frames are not acted upon in half-duplex mode, regardless of this bit set[...]

EMAC Module Registers www.ti.com 5.30 MAC Status Register (MACSTATUS) The MAC status register (MACSTATUS) is shown in Figure 68 and described in Table 67 . Figure 68. MAC Status Register (MACSTATUS) 31 30 24 23 20 19 18 16 IDLE Reserved TXERRCODE Rsvd TXERRCH R-0 R-0 R-0 R-0 R-0 15 12 11 10 8 RXERRCODE Reserved RXERRCH R-0 R-0 R-0 7 3210 Reserved R[...]

www.ti.com EMAC Module Registers Table 67. MAC Status Register (MACSTATUS) Field Descriptions (continued) Bit Field Value Description 15-12 RXERRCODE 0-Fh Receive host error code. These bits indicate that EMAC detected receive DMA related host errors. The host should read this field after a host error interrupt (HOSTPEND) to determine the error. Ho[...]

EMAC Module Registers www.ti.com 5.31 Emulation Control Register (EMCONTROL) The emulation control register (EMCONTROL) is shown in Figure 69 and described in Table 68 . Figure 69. Emulation Control Register (EMCONTROL) 31 16 Reserved R-0 15 2 1 0 Reserved SOFT FREE R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Ta[...]

www.ti.com EMAC Module Registers 5.33 MAC Configuration Register (MACCONFIG) The MAC configuration register (MACCONFIG) is shown in Figure 71 and described in Table 70 . Figure 71. MAC Configuration Register (MACCONFIG) 31 24 23 16 TXCELLDEPTH RXCELLDEPTH R-3h R-3h 15 8 7 0 ADDRESSTYPE MACCFIG R-2h R-2h LEGEND: R = Read only; - n = value after rese[...]

EMAC Module Registers www.ti.com 5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) The MAC source address low bytes register (MACSRCADDRLO) is shown in Figure 73 and described in Table 72 . Figure 73. MAC Source Address Low Bytes Register (MACSRCADDRLO) 31 16 Reserved R-0 15 8 7 0 MACSRCADDR0 MACSRCADDR1 R/W-0 R/W-0 LEGEND: R/W = Read/Write[...]

www.ti.com EMAC Module Registers 5.37 MAC Hash Address Register 1 (MACHASH1) The MAC hash registers allow group addressed frames to be accepted on the basis of a hash function of the address. The hash function creates a 6-bit data value (Hash_fun) from the 48-bit destination address (DA) as follows: Hash_fun(0)=DA(0) XOR DA(6) XOR DA(12) XOR DA(18)[...]

EMAC Module Registers www.ti.com 5.39 Back Off Test Register (BOFFTEST) The back off test register (BOFFTEST) is shown in Figure 77 and described in Table 76 . Figure 77. Back Off Random Number Generator Test Register (BOFFTEST) 31 26 25 16 Reserved RNDNUM R-0 R-0 15 12 11 10 9 0 COLLCOUNT Reserved TXBACKOFF R-0 R-0 R-0 LEGEND: R = Read only; - n =[...]

www.ti.com EMAC Module Registers 5.41 Receive Pause Timer Register (RXPAUSE) The receive pause timer register (RXPAUSE) is shown in Figure 79 and described in Table 78 . Figure 79. Receive Pause Timer Register (RXPAUSE) 31 16 Reserved R-0 15 0 PAUSETIMER R-0 LEGEND: R = Read only; - n = value after reset Table 78. Receive Pause Timer Register (RXPA[...]

EMAC Module Registers www.ti.com 5.43 MAC Address Low Bytes Register (MACADDRLO) The MAC address low bytes register used in address matching (MACADDRLO), is shown in Figure 81 and described in Table 80 . Figure 81. MAC Address Low Bytes Register (MACADDRLO) 31 21 20 19 18 16 Reserved VALID MATCHFILT CHANNEL R-0 R/W-x R/W-x R/W-x 15 8 7 0 MACADDR0 M[...]

www.ti.com EMAC Module Registers 5.44 MAC Address High Bytes Register (MACADDRHI) The MAC address high bytes register (MACADDRHI) is shown in Figure 82 and described in Table 81 . Figure 82. MAC Address High Bytes Register (MACADDRHI) 31 24 23 16 MACADDR2 MACADDR3 R/W-x R/W-x 15 8 7 0 MACADDR4 MACADDR5 R/W-x R/W-x LEGEND: R/W = Read/Write; -x = val[...]

EMAC Module Registers www.ti.com 5.46 Transmit Channel DMA Head Descriptor Pointer Registers (TX0HDP-TX7HDP) The transmit channel 0-7 DMA head descriptor pointer register (TX n HDP) is shown in Figure 84 and described in Table 83 . Figure 84. Transmit Channel n DMA Head Descriptor Pointer Register (TX n HDP) 31 0 TX n HDP R/W-x LEGEND: R/W = Read/W[...]

www.ti.com EMAC Module Registers 5.48 Transmit Channel Completion Pointer Registers (TX0CP-TX7CP) The transmit channel 0-7 completion pointer register (TX n CP) is shown in Figure 86 and described in Table 85 . Figure 86. Transmit Channel n Completion Pointer Register (TX n CP) 31 0 TX n CP R/W-x LEGEND: R/W = Read/Write; - n = value after reset; -[...]

EMAC Module Registers www.ti.com 5.50 Network Statistics Registers The EMAC has a set of statistics that record events associated with frame traffic. The statistics values are cleared to zero 38 clocks after the rising edge of reset. When the GMIIEN bit in the MACCONTROL register is set, all statistics registers (see Figure 88 ) are write-to-decrem[...]

www.ti.com EMAC Module Registers 5.50.4 Pause Receive Frames Register (RXPAUSEFRAMES) The total number of IEEE 802.3X pause frames received by the EMAC (whether acted upon or not). A pause frame is defined as having all of the following: • Contained any unicast, broadcast, or multicast address • Contained the length/type field value 88.08h and [...]

EMAC Module Registers www.ti.com 5.50.7 Receive Oversized Frames Register (RXOVERSIZED) The total number of oversized frames received on the EMAC. An oversized frame is defined as having all of the following: • Was any data or MAC control frame that matched a unicast, broadcast, or multicast address, or matched due to promiscuous mode • Was gre[...]

www.ti.com EMAC Module Registers To determine the number of receive frames discarded by the EMAC for any reason, sum the following statistics (promiscuous mode disabled): • Receive fragments • Receive undersized frames • Receive CRC errors • Receive alignment/code errors • Receive jabbers • Receive overruns • Receive filtered frames T[...]

EMAC Module Registers www.ti.com 5.50.15 Broadcast Transmit Frames Register (TXBCASTFRAMES) The total number of good broadcast frames transmitted on the EMAC. A good broadcast frame is defined as having all of the following: • Any data or MAC control frame destined for address FF-FF-FF-FF-FF-FFh only • Was of any length • Had no late or exces[...]

www.ti.com EMAC Module Registers 5.50.20 Transmit Single Collision Frames Register (TXSINGLECOLL) The total number of frames transmitted on the EMAC that experienced exactly one collision. Such a frame is defined as having all of the following: • Was any data or MAC control frame destined for any unicast, broadcast, or multicast address • Was a[...]

EMAC Module Registers www.ti.com 5.50.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE) The total number of frames on the EMAC that experienced carrier loss. Such a frame is defined as having all of the following: • Was any data or MAC control frame destined for any unicast, broadcast, or multicast address • Was any size • The carrie[...]

www.ti.com EMAC Module Registers 5.50.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511) The total number of 256-byte to 511-byte frames received and transmitted on the EMAC. Such a frame is defined as having all of the following: • Any data or MAC control frame that was destined for any unicast, broadcast, or multicast addre[...]

EMAC Module Registers www.ti.com 5.50.34 Receive FIFO or DMA Start of Frame Overruns Register (RXSOFOVERRUNS) The total number of frames received on the EMAC that had either a FIFO or DMA start of frame (SOF) overrun. An SOF overrun frame is defined as having all of the following: • Was any data or MAC control frame that matched a unicast, broadc[...]

www.ti.com Appendix A Glossary Broadcast MAC Address— A special Ethernet MAC address used to send data to all Ethernet devices on the local network. The broadcast address is FFh-FFh-FFh-FFh-FFh-FFh. The LSB of the first byte is odd, qualifying it as a group address; however, its value is reserved for broadcast. It is classified separately by the [...]

Appendix A www.ti.com Multicast MAC Address— A class of MAC address that sends a packet to potentially more than one recipient. A group address is specified by setting the LSB of the first MAC address byte to 1. Thus, 01h-02h-03h-04h-05h-06h is a valid multicast address. Typically, an Ethernet MAC looks for only certain multicast addresses on a n[...]

www.ti.com Appendix B Revision History Table 88 lists the changes made since the previous version of this document. Table 88. Document Revision History Reference Additions/Modifications/Deletions Figure 2 Changed figure. Section 2.5.2 Changed first paragraph. Section 2.5.3 Changed third paragraph. 135 SPRUFL5B – April 2011 Revision History Submit[...]

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