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Cypress Semiconductor CY7C1361C manuale d’uso - BKManuals
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Cypress Semiconductor CY7C1361C manuale d’uso

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Un buon manuale d’uso

Le regole impongono al rivenditore l'obbligo di fornire all'acquirente, insieme alle merci, il manuale d’uso Cypress Semiconductor CY7C1361C. La mancanza del manuale d’uso o le informazioni errate fornite al consumatore sono la base di una denuncia in caso di inosservanza del dispositivo con il contratto. Secondo la legge, l’inclusione del manuale d’uso in una forma diversa da quella cartacea è permessa, che viene spesso utilizzato recentemente, includendo una forma grafica o elettronica Cypress Semiconductor CY7C1361C o video didattici per gli utenti. La condizione è il suo carattere leggibile e comprensibile.

Che cosa è il manuale d’uso?

La parola deriva dal latino "instructio", cioè organizzare. Così, il manuale d’uso Cypress Semiconductor CY7C1361C descrive le fasi del procedimento. Lo scopo del manuale d’uso è istruire, facilitare lo avviamento, l'uso di attrezzature o l’esecuzione di determinate azioni. Il manuale è una raccolta di informazioni sull'oggetto/servizio, un suggerimento.

Purtroppo, pochi utenti prendono il tempo di leggere il manuale d’uso, e un buono manuale non solo permette di conoscere una serie di funzionalità aggiuntive del dispositivo acquistato, ma anche evitare la maggioranza dei guasti.

Quindi cosa dovrebbe contenere il manuale perfetto?

Innanzitutto, il manuale d’uso Cypress Semiconductor CY7C1361C dovrebbe contenere:
- informazioni sui dati tecnici del dispositivo Cypress Semiconductor CY7C1361C
- nome del fabbricante e anno di fabbricazione Cypress Semiconductor CY7C1361C
- istruzioni per l'uso, la regolazione e la manutenzione delle attrezzature Cypress Semiconductor CY7C1361C
- segnaletica di sicurezza e certificati che confermano la conformità con le norme pertinenti

Perché non leggiamo i manuali d’uso?

Generalmente questo è dovuto alla mancanza di tempo e certezza per quanto riguarda la funzionalità specifica delle attrezzature acquistate. Purtroppo, la connessione e l’avvio Cypress Semiconductor CY7C1361C non sono sufficienti. Questo manuale contiene una serie di linee guida per funzionalità specifiche, la sicurezza, metodi di manutenzione (anche i mezzi che dovrebbero essere usati), eventuali difetti Cypress Semiconductor CY7C1361C e modi per risolvere i problemi più comuni durante l'uso. Infine, il manuale contiene le coordinate del servizio Cypress Semiconductor in assenza dell'efficacia delle soluzioni proposte. Attualmente, i manuali d’uso sotto forma di animazioni interessanti e video didattici che sono migliori che la brochure suscitano un interesse considerevole. Questo tipo di manuale permette all'utente di visualizzare tutto il video didattico senza saltare le specifiche e complicate descrizioni tecniche Cypress Semiconductor CY7C1361C, come nel caso della versione cartacea.

Perché leggere il manuale d’uso?

Prima di tutto, contiene la risposta sulla struttura, le possibilità del dispositivo Cypress Semiconductor CY7C1361C, l'uso di vari accessori ed una serie di informazioni per sfruttare totalmente tutte le caratteristiche e servizi.

Dopo l'acquisto di successo di attrezzature/dispositivo, prendere un momento per familiarizzare con tutte le parti del manuale d'uso Cypress Semiconductor CY7C1361C. Attualmente, sono preparati con cura e tradotti per essere comprensibili non solo per gli utenti, ma per svolgere la loro funzione di base di informazioni e di aiuto.

Sommario del manuale d’uso

  • Pagina 1

    9-Mbit ( 256K x 36/512K x 18 ) Flow-Throu g h SRAM CY7C1361C CY7C1363C Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05541 Rev . *F Revised September 14, 2006 Features • Supports 100, 133-MHz bus operations • Support s 100-MHz bus opera tio ns (Automotive) • 256K × 3[...]

  • Pagina 2

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 2 of 31 ADDRESS REGISTER BURST COUNTER AND LOGIC CLR Q1 Q0 ENABLE REGISTER SENSE AMPS OUTPUT BUFFERS INPUT REGISTERS MEMORY ARRAY MODE A [1:0] ZZ DQ s DQP A DQP B DQP C DQP D A 0, A1, A ADV CLK ADSP ADSC BW D BW C BW B BW A BWE CE1 CE2 CE3 OE GW SLEEP CONTROL DQ A , DQP A BYTE WRITE REGISTER DQ[...]

  • Pagina 3

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 3 of 31 Pin Configurations A A A A A 1 A 0 NC NC V SS V DD NC A A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP A DQP C DQ C DQ C V DDQ V SSQ DQ C DQ C DQ C DQ C V SSQ V DDQ D[...]

  • Pagina 4

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 4 of 31 Pin Configurations (continued) A A A A A 1 A 0 NC NC V SS V DD NC NC A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP A DQP C DQ C DQ C V DDQ V SSQ DQ C DQ C DQ C DQ C [...]

  • Pagina 5

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 5 of 31 Pin Configurations (continued) 234 5 67 1 A B C D E F G H J K L M N P R T U V DDQ NC/288M NC/144M DQP C DQ C DQ D DQ C DQ D AA A A ADSP V DDQ CE 2 A DQ C V DDQ DQ C V DDQ V DDQ V DDQ DQ D DQ D NC NC V DDQ V DD CLK V DD V SS V SS V SS V SS V SS V SS V SS V SS NC/512M NC/1G NC NC TDO TCK [...]

  • Pagina 6

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 6 of 31 Pin Configurations (continued) 165-Ball FBGA Pinout ( 3 Chip Enable) CY7C1361C (256 K x 36) 23 4 567 1 A B C D E F G H J K L M N P R TDO NC/288M NC/144M DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE A CE 2 DQ C DQ D DQ D MODE NC DQ C DQ C DQ D DQ D DQ D NC/36M NC/72M V DDQ BW D BW A [...]

  • Pagina 7

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 7 of 31 Pin Definitions Name I/O Description A 0 , A 1 , A Input- Synchronous Address Inpu ts used to select one of the address location s. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE 1 , CE 2 , and CE 3 [2] are sampled active . A [1:0] feed the 2-bit counter . B[...]

  • Pagina 8

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 8 of 31 V SS Ground Ground for the core of the device . V SSQ I/O Ground Ground for the I /O circuitry . TDO JT AG serial outp ut Synchronous Serial data-out to the JT AG circuit . Delivers d ata on the negative edge of TCK. If the JT AG feature is not bein g utilized , this pin sh ould be lef [...]

  • Pagina 9

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 9 of 31 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge o f the clock. Maximum access delay from the clock rise (t CDV ) is 6.5 ns (133-MHz device). The CY7C1361C/CY7C1363C su pports secondary cache in systems utilizing either a linear or in[...]

  • Pagina 10

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 10 of 31 ZZ Mode Electrical Characteristics Parameter Description T est Con ditions Min. Max. Un it I DDZZ Sleep mode standby current ZZ > V DD – 0.2V Comm/ind’l 50 mA Automotive 60 mA t ZZS Device operation to ZZ ZZ > V DD – 0.2V 2t CYC ns t ZZREC ZZ recovery time ZZ < 0.2V 2t C[...]

  • Pagina 11

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 1 1 of 31 Partial T ruth T able for Read/Write [3, 8] Function (CY7C136 1C) GW BWE BW D BW C BW B BW A Read H H X X X X R e a d H L HHHH Write Byte (A, DQP A )H L H H H L Write Byte (B, DQP B )H L H H L H Write Bytes (B, A, DQP A , DQP B )H L H H L L Write Byte (C, DQP C ) HLHLH H Write Bytes ([...]

  • Pagina 12

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 12 of 31 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1361C/CY7C1363C incorpora tes a serial boundary scan test access port (T AP) in the BGA package only . The TQFP package does not offer this functionality . This part operates in accordance with IEEE S t andard 1 149.1-1900, b ut doesn?[...]

  • Pagina 13

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 13 of 31 TDI and TDO ba lls as show n in the T ap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE in struction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in th e pre v i o us section. When [...]

  • Pagina 14

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 14 of 31 PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection o f another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is[...]

  • Pagina 15

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 15 of 31 3.3V T AP AC T est Conditions Input pulse levels ............ .............. .............. ........ V SS to 3.3V Input rise and fall times ......... .............. ...................... ... ... 1 ns Input timing referenc e levels ............ ......................... ...... 1.5V Out[...]

  • Pagina 16

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 16 of 31 Scan Register Sizes Register Name Bit Size (x 36) Bit Size (x 18) Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order (1 19-ball BGA package) 71 71 Boundary Scan Order (165-ball FBGA package) 71 71 Identification Codes Instruction Code Description EXTEST 000 Captures I/O ring conte[...]

  • Pagina 17

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 17 of 31 1 19-Ball BGA Boundary Scan Order CY7C1361C (256K x 36) CY7C13 63C (512K x 18) Bit # ball ID Signal Name Bit # ball ID Signal Name Bit # ball ID Signal Name Bit # ball ID Signal Name 1 K4 CLK 37 P4 A0 1 K4 CLK 37 P4 A0 2H 4 G W 38 N4 A1 2 H4 GW 38 N 4 A1 3M 4B W E 39 R6 A 3 M4 BWE 39 R[...]

  • Pagina 18

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 18 of 31 165-Ball FBGA Boundary Scan Order CY7C1361C (256K x 36) CY7C1363C (512K x 18) Bit # ball ID Signal Name Bit # ball ID Signal Name Bit # ball ID Signal Name Bit # ball ID Signal Name 1 B6 CLK 37 R6 A0 1 B6 CLK 37 R6 A0 2B 7 G W 38 P6 A1 2 B7 GW 38 P6 A1 3A 7 B W E 39 R4 A 3 A7 BWE 39 R4[...]

  • Pagina 19

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 19 of 31 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. .............. ..... –65°C to + 150°C Ambient T emperature with Power Applied ........... ............................ ..... –55°C to + 125°C Su[...]

  • Pagina 20

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 20 of 31 Cap acitance [15] Parameter Description T est Conditions 100 TQ FP Max. 11 9 B G A Max. 165 FBGA Max. Unit C IN Input Cap acitance T A = 25 ° C, f = 1 MHz, V DD = 3.3V V DDQ = 2.5V 55 5 p F C CLK Clock Input Capacitance 5 5 5 pF C I/O Input/Output Capacitance 5 7 7 pF Thermal Resist a[...]

  • Pagina 21

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 21 of 31 Switching Characteristics Over the Operating Range [20, 21] Parameter De scription –133 –100 Unit Min. Max. Min. Max. t POWER V DD (T ypical) to the first Access [1 6] 11 m s Clock t CYC Clock Cycle T ime 7.5 10 ns t CH Clock HIGH 3.0 4.0 ns t CL Clock LOW 3.0 4.0 ns Output Times t[...]

  • Pagina 22

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 22 of 31 Timing Diagrams Read Cycle Timing [22] Note: 22. On this diagram, when CE is L OW: CE 1 is LOW , CE 2 is HIGH and CE 3 is LOW. When CE is HIGH: CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A1 t CEH t CES Data Out (Q) High-Z t CLZ t DOH [...]

  • Pagina 23

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 23 of 31 Write Cycle T iming [22, 23] Note: 23. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW X LOW. Timing Diagrams (continued) t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A1 t CEH t CES High-Z BURST READ BURST WRITE D(A2) D(A2 + 1) D(A2 + 1) D(A1) D(A[...]

  • Pagina 24

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 24 of 31 Read/Write Cycle Timing [22, 24, 25 ] Notes: 24. The data bus (Q) remain s in high-Z following a WRIT E cycl e, unless a new read access is initiated by ADSP or ADSC . 25. GW is HIGH. Timing Diagrams (continued) t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A2 t CEH t CES Single WR[...]

  • Pagina 25

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 25 of 31 ZZ Mode T iming [26, 27] Notes: 26. Device must be deselected when ente ring ZZ mode. See Cycle Descr iptions t ab le for all possible signal conditi ons to deselect the device. 27. DQs are in high -Z when exiting ZZ sl eep mode. Timing Diagrams (continued) t ZZ I SUPPLY CLK ZZ t ZZREC[...]

  • Pagina 26

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 26 of 31 Ordering Information Not all of the speed, package and temperature ranges are av ailable. Please contact your local sales representative or visit www .cypress .com for actua l products offered . Speed (MHz) Or dering Code Pac kage Diagram Part and Package T ype Operatin g Range 133 CY7[...]

  • Pagina 27

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 27 of 31 100 CY7C1361C-100AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Fre e (3 Chip Enable) Commercial CY7C1363C-100AXC CY7C1361C-100AJXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (2 Chip Enable) CY7C1363C-100AJXC CY7C1361C-100BGC 51-851 15 1 1 9-bal[...]

  • Pagina 28

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 28 of 31 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMAT[...]

  • Pagina 29

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 29 of 31 Package Diagrams (continued) 1.27 20.32 2 16 5 4 37 L E A B D C H G F K J U P N M T R 12.00 19.50 30° TYP. 2.40 MAX. A1 CORNER 0.70 REF. U T R P N M L K J H G F E D C A B 21 43 65 7 Ø1.00(3X) REF. 7.62 22.00±0.20 14.00±0.20 1.27 6 0±0.10 C 0.15 C B A 0.15(4X) Ø0.05 M C Ø0.75±0.[...]

  • Pagina 30

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 30 of 31 © Cypress Semi con duct or Cor po rati on , 20 06 . The information contained he re i n is su bject to change without notice. C ypr ess S em i c on duct or Corpo ration assu mes no resp onsib ility for th e u se of any circuitry o ther than circui try embodied i n a Cypress prod uct. [...]

  • Pagina 31

    CY7C1361C CY7C1363C Document #: 38-05541 Rev . *F Page 31 of 31 Document History Page Document Title: CY7C1361C/CY7C1363C 9-Mbit (256K x 36/5 12K x 18) Flow-Through SRAM Document Number: 38-05541 REV . ECN NO. Issue Date Orig . of Change Description of Cha nge ** 241690 See ECN R KF New data sheet *A 2 78969 See ECN RKF Changed Boundary Scan order [...]