Texas Instruments TMS320C67X/C67X+ DSP manuale d’uso

TMS320C67x/C67x+ DSP CPU and Instruction Set Reference Guide Literature Number: SPRU733 May 2005[...]

IMPORT ANT NOTICE T exas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orde[...]

iii Read This First SPRU733 Preface Read This First About This Manual The TMS320C6000 ™ digital signal processor (DSP) platform is part of the TMS320 ™ DSP family . The TMS320C62x ™ DSP generation and the TMS320C64x ™ DSP generation comprise fixed-point devices in the C6000 ™ DSP platform, and the TMS320C67x ™ DSP generation comprises f[...]

T rademarks iv SPRU733 Read This First TMS320C672x DSP Peripherals Overview Reference Guide (literature number SPRU723) describes the peripherals available on the TMS320C672x DSPs. TMS320C6000 T echnical Brief (literature number SPRU197) gives an introduction t o the TMS320C62x and TMS320C67x DSPs, development tools, and third-party support. TMS320[...]

Contents v Contents SPRU733 Contents 1 Introduction 1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Summarizes the features of the TMS320 family of products and presents typical applications. Describes the TMS320C67x DSP and lists their key features. 1.1 T[...]

Contents vi SPRU733 Contents 3 Instruction Set 3-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Describes the assembly language instructions of the TMS320C67x DSP . Also described are parallel operations, conditional operations, resource constraints, and addressi[...]

Contents vii Contents SPRU733 CLR (Clear a Bit Field) 3-77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMPEQ (Compare for Equality , Signed Integers) 3-80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMPEQDP (Compare for Equality , Double-Precision Floating-Point V alues) [...]

Contents viii SPRU733 Contents MPYI (Multiply 32-Bit by 32-Bit Into 32-Bit Result) 3-157 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPYID (Multiply 32-Bit by 32-Bit Into 64-Bit Result) 3-159 . . . . . . . . . . . . . . . . . . . . . . . . . . . MPYLH (Multiply Signed 16 LSB by Signed 16 MSB) 3-161 . . . . . . . . . . . . . . . . . . [...]

Contents ix Contents SPRU733 SPINT (Convert Single-Precision Floating-Point V alue to Integer) 3-228 . . . . . . . . . . . . . . . SPTRUNC (Convert Single-Precision Floating-Point V alue to Integer With T runcation) 3-230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSHL (Shift Left With Saturation) 3-232 [...]

Contents x SPRU733 Contents 4.2.1 1 MPYI Instruction 4-29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.12 MPYID Instruction 4-30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.13 MPYDP Instruction 4-31 . . . . . . . . . . . . . . [...]

Contents xi Contents SPRU733 A Instruction Compatibility A-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lists the instructions that are common to the C62x, C64x, and C67x DSPs. B Mapping Between Instruction and Functional Unit B-1 . . . . . . . . . . . . . . . . . . . . . . . . [...]

Figures xii SPRU733 Figures Figures 1 − 1 TMS320C67x DSP Block Diagram 1-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 − 1 TMS320C67x CPU Data Paths 2-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 − 2 Storage Scheme for 40-Bit Data in a R[...]

Figures xiii Figures SPRU733 4 − 18 T wo-Cycle DP Instruction Phases 4-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 − 19 Four-Cycle Instruction Phases 4-25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 − 20 INTDP Instruction Phases 4-26 .[...]

T ables xiv SPRU733 T ables T ables 1 − 1 T ypical Applications for the TMS320 DSPs 1-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 − 1 40-Bit/64-Bit Register Pairs 2-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 − 2 Functional Units and Operat[...]

T ables xv T ables SPRU733 3 − 19 Data T ypes Supported by LDH(U) Instruction 3-131 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 − 20 Data T ypes Supported by LDH(U) Instruction (15-Bit Offset) 3-135 . . . . . . . . . . . . . . . . . . . . . . 3 − 21 Register Addresses for Accessing the Control Registers 3-182 . . .[...]

T ables xvi SPRU733 T ables 5 − 1 Interrupt Priorities 5-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 − 2 Interrupt Control Registers 5-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A − 1 Instruction Co[...]

Examples xvii Examples SPRU733 Examples 3 − 1 Fully Serial p-Bit Pattern in a Fetch Packet 3-17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 − 2 Fully Parallel p-Bit Pattern in a Fetch Packet 3-17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 − 3 Partially Serial p-Bit Pattern in [...]

1-1 Introduction SPRU733 a Introduction The TMS320C6000 ™ digital signal processor (DSP) platform is part of the TMS320 ™ DSP family . The TMS320C62x ™ DSP generation and the TMS320C64x ™ DSP generation comprise fixed-point devices in the C6000 ™ DSP platform, and the TMS320C67x ™ DSP generation comprises floating- point devices in the [...]

TMS320 DSP Family Overview Introduction 1-2 SPRU733 1.1 TMS320 DSP Family Overview Th e TMS320 ™ DSP family consists of fixed-point, floating-point, and multipro- cessor digital signal processors (DSPs). TMS320 ™ DSPs have an architec- ture designed specifically for real-time signal processing. T able 1 − 1 lists some typical applications for[...]

TMS320C6000 DSP Family Overview 1-3 Introduction SPRU733 T able 1 − 1. T ypical Applications for the TMS320 DSPs Automotive Consumer Control Adaptive ride control Antiskid brakes Cellular telephones Digital radios Engine control Global positioning Navigation Vibration analysis V oice commands Digital radios/TVs Educational toys Music synthesizers[...]

TMS320C67x DSP Features and Options Introduction 1-4 SPRU733 1.3 TMS320C67x DSP Features and Options Th e C6000 devices execute up to eight 32-bit instructions per cycle. The C67x CP U consists of 32 general-purpose 32-bit registers and eight functional units. These eight functional units contain:  T wo multipliers  Six ALUs The C6000 generat[...]

TMS320C67x DSP Features and Options 1-5 Introduction SPRU733  40-bit arithmetic options add extra precision for vocoders and other computationally intensive applications  Saturation and normalization provide support for key arithmetic operations  Field manipulation and instruction extract, set, clear , and bit counting support common opera[...]

TMS320C67x DSP Features and Options Introduction 1-6 SPRU733 Th e V elociTI architecture of the C6000 platform of devices make them the first off-the-shelf DSPs to use advanced VLIW to achieve high performance through increased instruction-level parallelism. A traditional VLIW architecture consists of multiple execution units running in parallel, p[...]

TMS320C67x DSP Architecture 1-7 Introduction SPRU733 1.4 TMS320C67x DSP Architecture Figure 1 − 1 is the block diagram for the C67x DSP . The C6000 devices come with program memory , which, on some devices, can be used as a program cache. The devices also have varying sizes of data memory . Peripherals such as a direct memory access (DMA) control[...]

TMS320C67x DSP Architecture Introduction 1-8 SPRU733 1.4.1 Central Processing Unit (CPU) Th e C67x CPU, in Figure 1 − 1, is common to all the C62x/C64x/C67x devices. The CPU contains:  Program fetch unit  Instruction dispatch unit  Instruction decode unit  T wo data paths, each with four functional units  32 32-bit registers  Co[...]

TMS320C67x DSP Architecture 1-9 Introduction SPRU733  DM A Controller (C6701 DSP only) transfers data between address ranges in the memory map without intervention by the CPU. The DMA controller has four programmable channels and a fifth auxiliary channel.  EDMA Controller performs the same functions as the DMA controller . The EDMA has 16 pr[...]

2-1 CPU Data Paths and Control SPRU733 CPU Data Paths and Control This c hapter focuses o n t he CPU, p roviding i nformation about t he d ata p aths a nd control registers. The two register files and the data cross paths are described. T opic Page 2.1 Introduction 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

Introduction CPU Data Paths and Control 2-2 SPRU733 2.1 Introduction The components of the data path for the TMS320C67x CPU are shown in Figure 2 − 1. These components consist of:  T wo general-purpose register files (A and B)  Eight functional units (.L1, .L2, .S1, .S2, .M1, .M2, .D1, and .D2)  T wo load-from-memory data paths (LD1 and [...]

General-Purpose Register Files 2-3 CPU Data Paths and Control SPRU733 Figure 2 − 1. TMS320C67x CPU Data Paths 8 8 2X 1X .L2 .S2 .M2 .D2 (B0 − B15) (A0 − A15) .D1 .M1 .S1 .L1 long src dst src2 src1 src1 src1 src1 src1 src1 src1 src1 8 8 long dst long dst dst dst dst dst dst dst dst src2 src2 src2 src2 src2 src2 src2 long src Control register f[...]

General-Purpose Register Files CPU Data Paths and Control 2-4 SPRU733 T able 2 − 1. 40-Bit/64-Bit Register Pairs Register Files A B Devices A1:A0 B1:B0 C67x DSP A3:A2 B3:B2 A5:A4 B5:B4 A7:A6 B7:B6 A9:A8 B9:B8 A1 1:A10 B1 1:B10 A13:A12 B13:B12 A15:A14 B15:B14 A17:A16 B17:B16 C67x+ DSP only A19:A18 B19:B18 A21:A20 B21:B20 A23:A22 B23:B22 A25:A24 B2[...]

Functional Units 2-5 CPU Data Paths and Control SPRU733 2.3 Functional Units The eight functional units in the C6000 data paths can be divided into two groups of four; each functional unit in one data path is almost identical to the corresponding unit in the other data path. The functional units are described in T able 2 − 2. Most data lines in t[...]

Register File Cross Paths CPU Data Paths and Control 2-6 SPRU733 2.4 Register File Cross Paths Each functional unit reads directly from and writes directly to the register file within its own data path. That is, the .L1, .S1, .D1, and .M1 units write to register file A and the .L2, .S2, .D2, and .M2 units write to register file B. The register file[...]

Data Address Paths 2-7 CPU Data Paths and Control SPRU733 2.6 Data Address Paths The data address paths (DA1 and DA2) are each connected to the .D units in both data paths. This allows data addresses generated by any one path to access data to or from any register . The DA1 and DA2 resources and their associated data paths are specified as T1 and T[...]

Control Register File CPU Data Paths and Control 2-8 SPRU733 2.7.1 Register Addresses for Accessing the Control Registers T able 2 − 4 lists the register addresses for accessing the control register file. One unit (.S2) can read from and write to the control register file. Each control register is accessed by the MVC instruction. See the MVC inst[...]

Control Register File 2-9 CPU Data Paths and Control SPRU733 2.7.2 Pipeline/Timing of Control Register Accesses All MVC instructions are single-cycle instructions that complete their access of the explicitly named registers in the E1 pipeline phase. This is true whether MVC is moving a general register to a control register , or conversely . In all[...]

Control Register File CPU Data Paths and Control 2-10 SPRU733 2.7.3 Addressing Mo de Re gi st er (A MR ) Fo r each of the eight registers (A4–A7, B4–B7) that can perform linear or circu- lar addressing, the addressing mode register (AMR) specifies the addressing mode. A 2-bit field for each register selects the address modification mode: linear[...]

Control Register File 2-1 1 CPU Data Paths and Control SPRU733 T able 2 − 5. Addressing Mode Register (AMR) Field Descriptions (Continued) Bit Description V alue Field 13 − 12 B6 MODE 0 − 3h Address mode selection for register file B6. 0 Linear modification (default at reset) 1h Circular addressing using the BK0 field 2h Circular addressing u[...]

Control Register File CPU Data Paths and Control 2-12 SPRU733 T able 2 − 5. Addressing Mode Register (AMR) Field Descriptions (Continued) Bit Description V alue Field 3 − 2 A5 MODE 0 − 3h Address mode selection for register file a5. 0 Linear modification (default at reset) 1h Circular addressing using the BK0 field 2h Circular addressing usin[...]

Control Register File 2-13 CPU Data Paths and Control SPRU733 2.7.4 Control Status Register (CSR) The control status register (CSR) contains control and status bits. The CSR is shown in Figure 2 − 4 and described in T able 2 − 7. For the PWRD, EN, PCC, and DCC fields, see the device-specific data manual to see if it supports the options that th[...]

Control Register File CPU Data Paths and Control 2-14 SPRU733 T able 2 − 7. Control Status Register (CSR) Field Descriptions Bit Field V alue Description 31 − 24 CPU ID 0 − FFh Identifies the CPU of the device. Not writable by the MVC instruction. 0 − 1h Reserved 2h C67x CPU 3h C67x+ CPU 4h − FFh Reserved 23 − 16 REVISION ID 0 − FFh I[...]

Control Register File 2-15 CPU Data Paths and Control SPRU733 T able 2 − 7. Control Status Register (CSR) Field Descriptions (Continued) Bit Description V alue Field 7 − 5 PCC 0 − 7h Program cache control mode. Writable by the MVC instruction. See the TMS320C621x/C671x DSP T wo-Level Internal Memory Reference Guide (SPRU609). 0 Direct-mapped [...]

Control Register File CPU Data Paths and Control 2-16 SPRU733 2.7.5 Interrupt Clear Register (ICR) The interrupt clear register (ICR) allows you to manually clear the maskable interrupts (INT15 − INT4) in the interrupt flag register (IFR). Writing a 1 to any of the bits in ICR causes the corresponding interrupt flag (IF n ) to be cleared in IFR. [...]

Control Register File 2-17 CPU Data Paths and Control SPRU733 2.7.6 Interrupt Enable Register (IER) The interrupt enable register (IER) enables and disables individual interrupts. The IER is shown in Figure 2 − 7 and described in T able 2 − 9. Figure 2 − 7. Interrupt Enable Register (IER) 31 16 Reserved R-0 1 5 1 4 1 3 1 2 1 1 1 0 9876543 2 1[...]

Control Register File CPU Data Paths and Control 2-18 SPRU733 2.7.7 Interrupt Flag Register (IFR) The interrupt flag register (IFR) contains the status of INT4 − INT15 and NMI interrupt. Each corresponding bit in the IFR is set to 1 when that interrupt occurs; otherwise, the bits are cleared to 0. If you want to check the status of interrupts, us[...]

Control Register File 2-19 CPU Data Paths and Control SPRU733 2.7.8 Interrupt Return Pointer Register (IRP) The interrupt return pointer register (IRP) contains the return pointer that directs the CPU to the proper location to continue program execution after processing a maskable interrupt. A branch using the address in IRP ( B IRP ) in your inter[...]

Control Register File CPU Data Paths and Control 2-20 SPRU733 2.7.9 Interrupt Set Register (ISR) The interrupt set register (ISR) allows you to manually set the maskable inter- rupts (INT15 − INT4) in the interrupt flag register (IFR). W riting a 1 to any of the bits in ISR causes the corresponding interrupt flag (IF n ) to be set in IFR. Writ - [...]

Control Register File 2-21 CPU Data Paths and Control SPRU733 2.7.10 Interrupt Service T able Pointer Register (ISTP) Th e interrupt service table pointer register (ISTP) is used to locate the interrupt service routine (ISR). The ISTB field identifies the base portion of the address of the interrupt service table (IST) and the HPEINT field identifi[...]

Control Register File CPU Data Paths and Control 2-22 SPRU733 2.7.1 1 Nonmaskable Interrupt (NMI) Return Pointer Register (NRP) The NMI return pointer register (NRP) contains the return pointer that directs the CPU to the proper location to continue program execution after NMI processing. A branch using the address in NRP ( B NRP ) in your interrup[...]

Control Register File Extensions 2-23 CPU Data Paths and Control SPRU733 2.8 Control Register File Extensions Th e C67x DSP has three additional configuration registers to support floating- point operations. The registers specify the desired floating-point rounding mode for the .L and .M units. They also contain fields to warn if src1 and src2 are [...]

Control Register File Extensions CPU Data Paths and Control 2-24 SPRU733 Figure 2 − 14. Floating-Point Adder Configuration Register (F ADCR) 31 27 26 25 24 23 22 21 20 19 18 17 16 Reserved RMODE UNDER INEX OVER INFO INV AL DEN2 DEN1 NAN2 NAN1 R-0 R/W-0 R/W-0 R/W-0 R/W -0 R/W-0 R/W-0 R/W -0 R/W-0 R/W-0 R/W -0 1 5 1 1 1 0 9 8 76543210 Reserved RMOD[...]

Control Register File Extensions 2-25 CPU Data Paths and Control SPRU733 T able 2 − 14. Floating-Point Adder Configuration Register (F ADCR) Field Descriptions (Continued) Bit Description V alue Field 20 INV AL 0 A signed NaN (SNaN) is not a source. 1 A signed NaN (SNaN) is a source. NaN is a source in a floating-point to integer conversion or wh[...]

Control Register File Extensions CPU Data Paths and Control 2-26 SPRU733 T able 2 − 14. Floating-Point Adder Configuration Register (F ADCR) Field Descriptions (Continued) Bit Description V alue Field 7 INEX Inexact results status for .L1. 0 1 Result differs from what would have been computed had the exponent range and precision been unbounded; n[...]

Control Register File Extensions 2-27 CPU Data Paths and Control SPRU733 2.8.2 Floating-Point Auxiliary Configuration Register (F AUCR) The floating-point auxiliary register (F AUCR) contains fields that specify underflow or overflow , the rounding mode, NaNs, denormalized numbers, and inexact results for instructions that use the .S functional uni[...]

Control Register File Extensions CPU Data Paths and Control 2-28 SPRU733 T able 2 − 15. Floating-Point Auxiliary Configuration Register (F AUCR) Field Descriptions (Continued) Bit Description V alue Field 25 UNORD Source to a compare operation for .S2 0 NaN is not a source to a compare operation. 1 NaN is a source to a compare operation. 24 UND R[...]

Control Register File Extensions 2-29 CPU Data Paths and Control SPRU733 T able 2 − 15. Floating-Point Auxiliary Configuration Register (F AUCR) Field Descriptions (Continued) Bit Description V alue Field 17 NAN2 NaN select for .S2 src2 . 0 src2 is not NaN. 1 src2 is NaN. 16 NAN1 NaN select for .S2 src1 . 0 src1 is not NaN. 1 src1 is NaN. 15 − [...]

Control Register File Extensions CPU Data Paths and Control 2-30 SPRU733 T able 2 − 15. Floating-Point Auxiliary Configuration Register (F AUCR) Field Descriptions (Continued) Bit Description V alue Field 5 INFO Signed infinity for .S1. 0 Result is not signed infinity . 1 Result is signed infinity . 4 INV AL 0 A signed NaN (SNaN) is not a source.[...]

Control Register File Extensions 2-31 CPU Data Paths and Control SPRU733 2.8.3 Floating-Point Multiplier Configuration Register (FMCR) The floating-point multiplier configuration register (FMCR) contains fields that specify underflow or overflow , the rounding mode, NaNs, denormalized numbers, and inexact results for instructions that use the .M fu[...]

Control Register File Extensions CPU Data Paths and Control 2-32 SPRU733 T able 2 − 16. Floating-Point Multiplier Configuration Register (FMCR) Field Descriptions (Continued) Bit Description V alue Field 23 INEX Inexact results status for .M2. 0 1 Result differs from what would have been computed had the exponent range and precision been unbounde[...]

Control Register File Extensions 2-33 CPU Data Paths and Control SPRU733 T able 2 − 16. Floating-Point Multiplier Configuration Register (FMCR) Field Descriptions (Continued) Bit Description V alue Field 15 − 11 Reserved 0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. 10 − 9 RMODE 0 − [...]

Control Register File Extensions CPU Data Paths and Control 2-34 SPRU733 T able 2 − 16. Floating-Point Multiplier Configuration Register (FMCR) Field Descriptions (Continued) Bit Description V alue Field 2 DEN1 Denormalized number select for .M1 src1 . 0 src1 is not a denormalized number . 1 src1 is a denormalized number . 1 NAN2 NaN select for .[...]

3-1 Instruction Set SPRU733 Instruction Set This chapter describes the assembly language instructions of the TMS320C67x DSP . Also described are parallel operations, conditional operations, resource constraints, and addressing modes. The C67x floating-point DSP uses all of the instructions available to the TMS320C62x ™ DSP but it also uses other [...]

Instruction Operation and Execution Notations Instruction Set 3-2 SPRU733 3.1 Instruction Operation and Execution Notations T able 3 − 1 explains the symbols used in the instruction descriptions. T able 3 − 1. Instruction Operation and Execution Notations Symbol Meaning abs(x) Absolute value of x and Bitwise AND − a Perform 2s-complement subt[...]

Instruction Operation and Execution Notations 3-3 Instruction Set SPRU733 T able 3 − 1. Instruction Operation and Execution Notations (Continued) Symbol Meaning gmpy Galois Field Multiply i2 T wo packed 16-bit integers in a single 32-bit register i4 Four packed 8-bit integers in a single 32-bit register int 32-bit integer value int(x) Convert x t[...]

Instruction Operation and Execution Notations Instruction Set 3-4 SPRU733 T able 3 − 1. Instruction Operation and Execution Notations (Continued) Symbol Meaning sint Signed 32-bit integer value slong Signed 40-bit integer value sllong Signed 64-bit integer value slsb16 Signed 16-bit integer value in lower half of 32-bit register smsb16 Signed 16-[...]

Instruction Operation and Execution Notations 3-5 Instruction Set SPRU733 T able 3 − 1. Instruction Operation and Execution Notations (Continued) Symbol Meaning umsb16 Unsigned 16-bit integer value in upper half of 32-bit register u2 T wo packed unsigned 16-bit integers in a single 32-bit register u4 Four packed unsigned 8-bit integers in a singl[...]

Instruction Operation and Execution Notations Instruction Set 3-6 SPRU733 T able 3 − 1. Instruction Operation and Execution Notations (Continued) Symbol Meaning > Greater than >= Greater than or equal to < Less than <= Less than or equal to << Shift left >> Shift right >>s Shift right with sign extension >>z Sh[...]

Instruction Syntax and Opcode Notations 3-7 Instruction Set SPRU733 3.2 Instruction Syntax and Opcode Notations T able 3 − 2 explains the syntaxes and opcode fields used in the instruction descriptions. The C 64x C PU 32-bit opcodes are mapped in Appendix C t hrough Appendix G . T able 3 − 2. Instruction Syntax and Opcode Notations Symbol Meani[...]

Instruction Syntax and Opcode Notations Instruction Set 3-8 SPRU733 T able 3 − 2. Instruction Syntax and Opcode Notations (Continued) Symbol Meaning scst n bit n of the signed constant field sn sign src source src1 source 1 src2 source 2 srcms stg n bit n of the constant stg t side of source/destination ( src/dst ) register; 0 = side A, 1 = side [...]

Overview of IEEE Standard Single- and Double-Precision Formats 3-9 Instruction Set SPRU733 3.3 Overview of IEEE Standard Single- and Double-Precision Formats Floating-point operands are classified as single-precision (SP) and double- precision (DP). Single-precision floating-point values are 32-bit values stored in a single register . Double-precis[...]

Overview of IEEE Standard Single- and Double-Precision Formats Instruction Set 3-10 SPRU733 T able 3 − 3. IEEE Floating-Point Notations Symbol Meaning s Sign bit e Exponent field f Fraction (mantissa) field x Can have value of 0 or 1 (don’t care) NaN Not-a-Number (SNaN or QNaN) SNaN Signal NaN QNaN Quiet NaN NaN_out QNaN with all bits in the f [...]

Overview of IEEE Standard Single- and Double-Precision Formats 3-1 1 Instruction Set SPRU733 Figure 3 − 1 shows the fields of a single-precision floating-point number repre- sented within a 32-bit register . Figure 3 − 1. Single-Precision Floating-Point Fields 31 e 23 22 0 30 s f Legend : s sign bit (0 = positive, 1 = negative) e 8-bit exponent[...]

Overview of IEEE Standard Single- and Double-Precision Formats Instruction Set 3-12 SPRU733 T able 3 − 5 shows hexadecimal and decimal values for some single-precision floating-point numbers. Figure 3 − 2 shows the fields of a double-precision floating-point number repre- sented within a pair of 32-bit registers. T able 3 − 5. Hexadecimal and[...]

Overview of IEEE Standard Single- and Double-Precision Formats 3-13 Instruction Set SPRU733 Normalized: − 1 s × 2 (e − 1023) × 1.f 0 < e < 2047 Denormalized (Subnormal): − 1 s × 2 − 1022 × 0.f e = 0; f nonzero T able 3 − 6 shows the s, e, and f values for special double-precision floating- point numbers. T able 3 − 6. Special [...]

Delay Slots Instruction Set 3-14 SPRU733 3.4 Delay Slots The execution of floating-point instructions can be defined in terms of delay slots and functional unit latency . The number of delay slots is equivalent to the number of additional cycles required after the source operands are read for the result to be a vail able fo r reading. For a single-[...]

Delay Slots 3-15 Instruction Set SPRU733 T able 3 − 8. Delay Slot and Functional Unit Latency Instruction T ype Delay Slots Functional Unit Latency Read Cycles † Write Cycles † Single cycle 0 1 i i 2-cycle DP 1 1 i i, i + 1 DP compare 1 2 i, i + 1 1 + 1 4-cycle 3 1 i i + 3 INTDP 4 1 i i + 3, i + 4 Load 4 1 i i, i + 4 ‡ MPYSP2DP 4 2 i i + 3,[...]

Parallel Operations Instruction Set 3-16 SPRU733 3.5 Parallel Operations Instructions are always fetched eight at a time. This constitutes a fetch packet . The basic format of a fetch packet is shown in Figure 3 − 3. Fetch packets are aligned on 256-bit (8-word) boundaries. Figure 3 − 3. Basic Format of a Fetch Packet pppp pppp Instruction A 00[...]

Parallel Operations 3-17 Instruction Set SPRU733 Example 3 − 1. Fully Serial p -Bit Pattern in a Fetch Packet This p- bit pattern: 0000 0000 Instruction A Instruction B Instruction C Instruction D Instruction E Instruction F Instruction G Instruction H 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 results in this execution sequence: Cycle/Execute Packe[...]

Parallel Operations Instruction Set 3-18 SPRU733 Example 3 − 3. Partially Serial p -Bit Pattern in a Fetch Packet This p- bit pattern: 31 0 31 0 31 0 31 0 0011 31 0 31 0 31 0 31 0 0110 Instruction A Instruction B Instruction C Instruction D Instruction E Instruction F Instruction G Instruction H results in this execution sequence: Cycle/Execute P[...]

Conditional Operations 3-19 Instruction Set SPRU733 3.6 Conditional Operations Most instructions can be conditional. The condition is controlled by a 3-bit opcode field ( creg ) that specifies the condition register tested, and a 1-bit field ( z ) that specifies a test for zero or nonzero. The four MSBs of every opcode are creg and z . The specifie[...]

Resource Constraints Instruction Set 3-20 SPRU733 3.7 Resource Constraints No two instructions within the same execute packet can use the same resources. Also, no two instructions can write to the same register during the same cycle. The following sections describe how an instruction can use each of the resources. 3.7.1 Constraints on Instructions [...]

Resource Constraints 3-21 Instruction Set SPRU733 3.7.3 Constraints on Cross Paths (1X and 2X) On e unit (either a .S, .L, or .M unit) per data path, per execute packet, can read a source operand from its opposite register file via the cross paths (1X and 2X). For example, the .S1 unit can read both its operands from the A register file; or it can [...]

Resource Constraints Instruction Set 3-22 SPRU733 3.7.4 Constraints on Loads and Stores Load and store instructions can use an address pointer from one register file while loading to or storing from the other register file. T wo load and store instructions using a destination/source from the same register file cannot be issued in the same execute p[...]

Resource Constraints 3-23 Instruction Set SPRU733 3.7.5 Constraints on Long (40-Bit) Data Because the .S and .L units share a read register port for long source operands and a write register port for long results, only one long result may be issued per register file in an execute packet. All instructions with a long result on the .S and .L units ha[...]

Resource Constraints Instruction Set 3-24 SPRU733 3.7.6 Constraints on Register Reads More than four reads of the same register cannot occur on the same cycle. Conditional registers are not included in this count. The following exe cute pa ckets are invalid: MPY .M1 A1, A1, A4 ; five reads of register A1 || ADD .L1 A1, A1, A5 || SUB .D1 A1, A2, A3 [...]

Resource Constraints 3-25 Instruction Set SPRU733 3.7.7 Constraints on Register Writes T wo instructions cannot write to the same register on the same cycle. T wo instructions with the same destination can be scheduled in parallel as long as they do not write to the destination register on the same cycle. For example, an MPY issued on cycle i follo[...]

Resource Constraints Instruction Set 3-26 SPRU733 3.7.8 Constraints on Floating-Point Instructions If an instruction has a multicycle functional unit latency , it locks the functional unit for the necessary number of cycles. Any new instruction dispatched to that functional unit during this locking period causes undefined results. If an instruction[...]

Resource Constraints 3-27 Instruction Set SPRU733 MPYDP No other instruction on the same side can use the cross path on cycles i, i + 1, i + 2, and i + 3. MPYSPDP No other instruction on the same side can use the cross path on cycles i and i + 1. Other hazards exist because instructions have varying numbers of delay slots, an d need the functional [...]

Resource Constraints Instruction Set 3-28 SPRU733 MPYI A 4-cycle instruction cannot be scheduled on that func- tional unit on cycle i + 4, i + 5, or i + 6. A MPYDP instruction cannot be scheduled on that func- tional unit on cycle i + 4, i + 5, or i + 6. A MPYSPDP instruction cannot be scheduled on that functional unit on cycle i + 4, i + 5, or i +[...]

Resource Constraints 3-29 Instruction Set SPRU733 MPYSPDP A 4-cycle instruction cannot be scheduled on that func- tional unit on cycle i + 2 or i + 3. A MPYI instruction cannot be scheduled on that function- al unit on cycle i + 2 or i + 3. A MPYID instruction cannot be scheduled on that func- tional unit on cycle i + 2 or i + 3. A MPYDP instructio[...]

Addressing Modes Instruction Set 3-30 SPRU733 3.8 Addressing Modes The addressing modes on the C67x DSP are linear , circular using BK0, and circular using BK1. The addressing mode is specified by the addressing mode register (AMR), described in section 2.7.3. All registers can perform linear addressing. Only eight registers can perform circular ad[...]

Addressing Modes 3-31 Instruction Set SPRU733 3.8.2 Circular Addressing Mode Th e BK0 and BK1 fields in AMR specify the block sizes for circular addressing, see section 2.7.3. 3.8.2.1 LD and ST Instructions As with linear address arithmetic, offsetR/cst is shifted left by 3, 2, 1, or 0 according to the data size, and is then added to or subtracted [...]

Addressing Modes Instruction Set 3-32 SPRU733 3.8.2.2 ADDA and SUBA Instructions As with linear address arithmetic, offsetR/cst is shifted left by 3, 2, 1, or 0 according to the data size, and is then added to or subtracted from baseR to produce the final address. Circular addressing modifies this slightly by only allowing bits N through 0 of the r[...]

Addressing Modes 3-33 Instruction Set SPRU733 T able 3 − 10. Indirect Address Generation for Load/Store Addressing T ype No Modification of Address Register Preincrement or Predecrement of Address Register Postincrement or Postdecrement of Address Register Register indirect *R *++R * − − R *R++ *R − − Register relative *+R[ ucst5 ] * − [...]

Instruction Compatibility Instruction Set 3-34 SPRU733 3.9 Instruction Compatibility The C62x, C64x, and C67x DSPs share an instruction set. All of the instruc- tions valid for the C62x DSP are also valid for the C67x DSP . See Appendix A for a list of the instructions that are common to the C62x, C64x, and C67x DSPs. 3.10 Instruction Descriptions [...]

The way each instruction is described Example 3-35 Instruction Set SPRU733 The way each instruction is described. Example Syntax EXAMPLE (.unit) src , dst .unit = .L1, .L2, .S1, .S2, .D1, .D2 src and dst indicate source and destination, respectively . The ( . unit) dictates which fu nctional unit the instruction is mapped to (.L1, .L2, .S1, .S2, .M[...]

Example The way each instruction is described 3-36 Instruction Set SPRU733 T able 3 − 12. Relationships Between Operands, Operand Size, Signed/Unsigned, Functional Units, and Opfields for Example Instruction (ADD) Opcode map field used... For operand type... Unit Opfield src1 src2 dst sint xsint sint .L1, .L2 000 001 1 src1 src2 dst sint xsint sl[...]

The way each instruction is described Example 3-37 Instruction Set SPRU733 Compatibility The C62x, C64x, and C67x DSPs share an instruction set. All of the instructions valid for the C62x DSP are also valid for the C67x DSP . This section identifies which DSP family the instruction is valid. Description Instruction execution and its effect on the r[...]

ABS Absolute V alue With Saturation 3-38 Instruction Set SPRU733 Absolute V alue With Saturation ABS Syntax ABS (.unit) src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 1 1 5 4 3 2 1 0 creg z dst src2 00000x op 1 1 0 s p 3 1 5 5 1 7 1 1 Opcode map field used... For operand type... Unit[...]

Absolute V alue With Saturation ABS 3-39 Instruction Set SPRU733 Instruction T ype Single-cycle Delay Slots 0 See Also ABSDP , ABSSP Example 1 ABS .L1 A1,A5 Before instruction 1 cycle after instruction A1 8000 4E3Dh − 2147463619 A1 8000 4E3Dh − 2147463619 A5 xxxx xxxxh A5 7FFF B1C3h 2147463619 Example 2 ABS .L1 A1,A5 Before instruction 1 cycle [...]

ABSDP Absolute V alue, Double-Precision Floating-Point 3-40 Instruction Set SPRU733 Absolute V alue, Double-Precision Floating-Point ABSDP Syntax ABSDP (.unit) src2 , dst .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 1 1 6 5 4 3 2 1 0 creg z dst src2 reserved x 1 0 1 1 0 0 1 0 0 0 s p 3 1 5 5 1 1 1 Opcode [...]

Absolute V alue, Double-Precision Floating-Point ABSDP 3-41 Instruction Set SPRU733 Pipeline Stage E1 E2 Read src2_l src2_h Written dst_l dst_h Unit in use .S If dst is used as the source for the ADDDP , CMPEQDP , CMPL TDP , CMPGTDP , MPYDP , or SUBDP instruction, the number of delay slots can be reduced by one, because these instructions read the [...]

ABSSP Absolute V alue, Single-Precision Floating-Point 3-42 Instruction Set SPRU733 Absolute V alue, Single-Precision Floating-Point ABSSP Syntax ABSSP (.unit) src2 , dst .unit = . S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 1 1 6 5 4 3 2 1 0 creg z dst src2 0 0 0 0 0 x 1 1 1 1 0 0 1 0 0 0 s p 3 1 5 5 1 1 1 Opcod[...]

Absolute V alue, Single-Precision Floating-Point ABSSP 3-43 Instruction Set SPRU733 Pipeline Stage E1 Read src2 Written dst Unit in use .S Instruction T ype Single-cycle Delay Slots 0 Functional Unit Latency 1 See Also ABS, ABSDP Example ABSSP .S1X B1,A5 Before instruction 1 cycle after instruction B1 c020 0000h − 2.5 B1 c020 0000h − 2.5 A5 xxx[...]

ADD Add T wo Signed Integers Without Saturation 3-44 Instruction Set SPRU733 Add T wo Signed Integers Without Saturation ADD Syntax ADD (.unit) src1 , src2 , dst or ADD (.D1 or .D2) src2 , src1 , dst .unit = .L1, .L2, .S1, .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode .L unit 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 s[...]

Add T wo Signed Integers Without Saturation ADD 3-45 Instruction Set SPRU733 Opcode .S unit 31 29 28 27 23 22 18 17 13 12 1 1 6 5 4 3 2 1 0 creg z dst src2 src1 x op 1 0 0 0 s p 3 1 5 5 5 1 6 1 1 Opcode map field used... For operand type... Unit Opfield src1 src2 dst sint xsint sint .S1, .S2 00 01 1 1 src1 src2 dst scst5 xsint sint .S1, .S2 00 01 1[...]

ADD Add T wo Signed Integers Without Saturation 3-46 Instruction Set SPRU733 Opcode .D unit 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 76543210 creg z dst src2 src1 op 10000 s p 3 1 5 5 5 6 1 1 Opcode map field used... For operand type... Unit Opfield src2 src1 dst sint sint sint .D1, .D2 01 0000 src2 src1 dst sint ucst5 sint .D1, .D2 01 0010 Descript[...]

Add T wo Signed Integers Without Saturation ADD 3-47 Instruction Set SPRU733 Example 1 ADD .L2X A1,B1,B2 Before instruction 1 cycle after instruction A1 0000 325Ah 12890 A1 0000 325Ah B1 FFFF FF12h − 238 B1 FFFF FF12h B2 xxxx xxxxh B2 0000 316Ch 12652 Example 2 ADD .L1 A1,A3:A2,A5:A4 Before instruction 1 cycle after instruction A1 0000 325Ah 1289[...]

ADDAB Add Using Byte Addressing Mode 3-48 Instruction Set SPRU733 Add Using Byte Addressing Mode ADDAB Syntax ADDAB (.unit) src2 , src1 , dst .unit = .D1 or .D2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 76543210 creg z dst src2 src1 op 10000 s p 3 1 5 5 5 6 1 1 Opcode map field used... For operand [...]

Add Using Byte Addressing Mode ADDAB 3-49 Instruction Set SPRU733 Example 1 ADDAB .D1 A4,A2,A4 Before instruction 1 cycle after instruction A2 0000 000Bh A2 0000 000Bh A4 0000 0100h A4 0000 0103h AMR 0002 0001h AMR 0002 0001h BK0 = 2 → size = 8 A4 in circular addressing mode using BK0 Example 2 ADDAB .D1X B14,42h,A4 Before instruction 1 cycle aft[...]

ADDAD Add Using Doubleword Addressing Mode 3-50 Instruction Set SPRU733 Add Using Doubleword Addressing Mode ADDAD Syntax ADDAD (.unit) src2 , src1 , dst .unit = . D1 or .D2 Compatibility C67x and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 76543210 creg z dst src2 src1 op 10000 s p 3 1 5 5 5 6 1 1 Opcode map field used... For operand [...]

Add Using Doubleword Addressing Mode ADDAD 3-51 Instruction Set SPRU733 Instruction T ype Single-cycle Delay Slots 0 Functional Unit Latency 1 See Also ADD, ADDAB, ADDAH, ADDA W Example ADDAD .D1 A1,A2,A3 Before instruction 1 cycle after instruction A1 0000 1234h 4660 A1 0000 1234h 4660 A2 0000 0002h 2 A2 0000 0002h 2 A3 xxxx xxxxh A3 0000 1244h 46[...]

ADDAH Add Using Halfword Addressing Mode 3-52 Instruction Set SPRU733 Add Using Halfword Addressing Mode ADDAH Syntax ADDAH (.unit) src2 , src1 , dst .unit = .D1 or .D2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 76543210 creg z dst src2 src1 op 10000 s p 3 1 5 5 5 6 1 1 Opcode map field used... For [...]

Add Using Halfword Addressing Mode ADDAH 3-53 Instruction Set SPRU733 Example 1 ADDAH .D1 A4,A2,A4 Before instruction 1 cycle after instruction A2 0000 000Bh A2 0000 000Bh A4 0000 0100h A4 0000 0106h AMR 0002 0001h AMR 0002 0001h BK0 = 2 → size = 8 A4 in circular addressing mode using BK0 Example 2 ADDAH .D1X B14,42h,A4 Before instruction 1 cycle[...]

ADDA W Add Using Word Addressing Mode 3-54 Instruction Set SPRU733 Add Using Word Addressing Mode ADDA W Syntax ADDA W (.unit) src2 , src1 , dst .unit = .D1 or .D2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 76543210 creg z dst src2 src1 op 10000 s p 3 1 5 5 5 6 1 1 Opcode map field used... For opera[...]

Add Using Word Addressing Mode ADDA W 3-55 Instruction Set SPRU733 Example 1 ADDAW .D1 A4,2,A4 Before instruction 1 cycle after instruction A4 0002 0000h A4 0002 0000h AMR 0002 0001h AMR 0002 0001h BK0 = 2 → size = 8 A4 in circular addressing mode using BK0 Example 2 ADDAW .D1X B14,42h,A4 Before instruction 1 cycle after instruction B14 0020 1000[...]

ADDDP Add T wo Double-Precision Floating-Point V alues 3-56 Instruction Set SPRU733 Add T wo Double-Precision Floating-Point V alues ADDDP Syntax ADDDP (.unit) src1 , src2 , dst (C67x and C67x+ CPU) .unit = .L1 or .L2 or ADDDP (.unit) src1 , src2 , dst (C67x+ CPU only) .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 [...]

Add T wo Double-Precision Floating-Point V alues ADDDP 3-57 Instruction Set SPRU733 Notes: 1) This instruction takes the rounding mode from and sets the warning bits in F ADCR, not F AUCR as for other .S unit instructions. 2) If rounding is performed, the INEX bit is set. 3) If one source is SNaN or QNaN, the result is NaN_out. If either source is [...]

ADDDP Add T wo Double-Precision Floating-Point V alues 3-58 Instruction Set SPRU733 Pipeline Stage E1 E2 E3 E4 E5 E6 E7 Read src1_l src2_l src1_h src2_h Written dst _ l dst _ h Unit in use .L or .S .L or .S For the C67x CPU, if dst is used as the source for the ADDDP , CMPEQDP , CMPL TDP , CMPGTDP , MPYDP , or SUBDP instruction, the number of delay[...]

Add Signed 16-Bit Constant to Register ADDK 3-59 Instruction Set SPRU733 Add Signed 16-Bit Constant to Register ADDK Syntax ADDK (.unit) cst , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 76543210 creg z dst cst16 10100 s p 3 1 5 16 1 1 Opcode map field used... For operand type... Unit cst16 dst scst[...]

ADDSP Add T wo Single-Precision Floating-Point V alues 3-60 Instruction Set SPRU733 Add T wo Single-Precision Floating-Point V alues ADDSP Syntax ADDSP (.unit) src1 , src2 , dst (C67x and C67x+ CPU) .unit = .L1 or .L2 or ADDSP (.unit) src1 , src2 , dst (C67x+ CPU only) .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 [...]

Add T wo Single-Precision Floating-Point V alues ADDSP 3-61 Instruction Set SPRU733 Notes: 1) This instruction takes the rounding mode from and sets the warning bits in F ADCR, not F AUCR as for other .S unit instructions. 2) If rounding is performed, the INEX bit is set. 3) If one source is SNaN or QNaN, the result is NaN_out. If either source is [...]

ADDSP Add T wo Single-Precision Floating-Point V alues 3-62 Instruction Set SPRU733 Pipeline Stage E1 E2 E3 E4 Read src1 src2 Written dst Unit in use .L or .S Instruction T ype 4-cycle Delay Slots 3 Functional Unit Latency 1 See Also ADD, ADDDP , ADDU, SUBSP Example ADDSP .L1 A1,A2,A3 Before instruction 4 cycles after instruction A1 C020 0000h − [...]

Add T wo Unsigned Integers Without Saturation ADDU 3-63 Instruction Set SPRU733 Add T wo Unsigned Integers Without Saturation ADDU Syntax ADDU (.unit) src1 , src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src1 x op 1 1 0 s p 3 1 5 5 5 1 7 1 1 Opcode map[...]

ADDU Add T wo Unsigned Integers Without Saturation 3-64 Instruction Set SPRU733 Example 1 ADDU .L1 A1,A2,A5:A4 Before instruction 1 cycle after instruction A1 0000 325Ah 12890 † A1 0000 325Ah A2 FFFF FF12h 4294967058 † A2 FFFF FF12h A5:A4 xxxx xxxxh A5:A4 0000 0001h 0000 316Ch 4294979948 ‡ † Unsigned 32-bit integer ‡ Unsigned 40-bit (long[...]

Add T wo 16-Bit Integers on Upper and Lower Register Halves ADD2 3-65 Instruction Set SPRU733 Add T wo 16-Bit Integers on Upper and Lower Register Halves ADD2 Syntax ADD2 (.unit) src1 , src2 , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 654321 0 creg z dst src2 src1 x 0 0 000 1[...]

ADD2 Add T wo 16-Bit Integers on Upper and Lower Register Halves 3-66 Instruction Set SPRU733 Execution if (cond) { msb16( src1 ) + msb16( src2 ) → msb16( dst ); lsb16( src1 ) + lsb16( src2 ) → lsb16( dst ); } else nop Pipeline Stage E1 Read src1, src2 Written dst Unit in use .S Instruction T ype Single-cycle Delay Slots 0 See Also ADD, ADDU, S[...]

Bitwise AND AND 3-67 Instruction Set SPRU733 Bitwise AND AND Syntax AND (.unit) src1 , src2 , dst .unit = .L1, .L2, .S1, .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode .L unit 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 543210 creg z dst src2 src1 x op 110 s p 3 1 5 5 5 1 7 1 1 Opcode map field used... For operand type... Unit Opfield src[...]

AND Bitwise AND 3-68 Instruction Set SPRU733 Pipeline Stage E1 Read src1, src2 Written dst Unit in use .L or .S Instruction T ype Single-cycle Delay Slots 0 See Also OR, XOR Example 1 AND .L1X A1,B1,A2 Before instruction 1 cycle after instruction A1 F7A1 302Ah A1 F7A1 302Ah A 2 xxxx xxxxh A 2 02A0 2020h B1 02B6 E724h B1 02B6 E724h Example 2 AND .L1[...]

Branch Using a Displacement B 3-69 Instruction Set SPRU733 Branch Using a Displacement B Syntax B (.unit) label .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 76543210 creg z cst21 00100 s p 3 1 21 1 1 Opcode map field used... For operand type... Unit cst21 scst21 .S1, .S2 Description A 21-bit signed constant, c[...]

B Branch Using a Displacement 3-70 Instruction Set SPRU733 T arget Instruction Pipeline Stage E1 PS PW PR DP DC E1 Read Written Branch T aken  Unit in use .S Instruction T ype Branch Delay Slots 5 Example T able 3 − 13 gives the program counter values and actions for the following code example. 0000 0000 B .S1 LOOP 0000 0004 ADD .L1 A1, A2, A3[...]

Branch Using a Register B 3-71 Instruction Set SPRU733 Branch Using a Register B Syntax B (.unit) src2 .unit = .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 1 1 6 5 4 3 2 1 0 creg z 0 0 0 0 0 src2 0 0 0 0 0 x 0 0 1 1 0 1 1 0 0 0 s p 3 1 5 1 1 1 Opcode map field used... For operand type... Unit src2 xuint .S2[...]

B Branch Using a Register 3-72 Instruction Set SPRU733 T arget Instruction Pipeline Stage E1 PS PW PR DP DC E1 Read src2 Written Branch T aken  Unit in use .S2 Instruction T ype Branch Delay Slots 5 Example T able 3 − 14 gives the program counter values and actions for the following code example. In this example, the B10 register holds the val[...]

Branch Using an Interrupt Return Pointer B IRP 3-73 Instruction Set SPRU733 Branch Using an Interrupt Return Pointer B IRP Syntax B (.unit) IRP .unit = .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 1 1 6 5 4 3 2 1 0 creg z dst 0 0 1 1 0 0 0 0 0 0 x 0 0 0 0 1 1 1 0 0 0 s p 3 1 5 1 1 1 Opcode map field used...[...]

B IRP Branch Using an Interrupt Return Pointer 3-74 Instruction Set SPRU733 T arget Instruction Pipeline Stage E1 PS PW PR DP DC E1 Read IRP Written Branch T aken  Unit in use .S2 Instruction T ype Branch Delay Slots 5 Example T able 3 − 15 gives the program counter values and actions for the following code example. Given that an interrupt occ[...]

Branch Using NMI Return Pointer B NRP 3-75 Instruction Set SPRU733 Branch Using NMI Return Pointer B NRP Syntax B (.unit) NRP .unit = .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 1 1 6 5 4 3 2 1 0 creg z dst 0 0 1 1 1 0 0 0 0 0 x 0 0 0 0 1 1 1 0 0 0 s p 3 1 5 1 1 1 Opcode map field used... For operand type.[...]

B NRP Branch Using NMI Return Pointer 3-76 Instruction Set SPRU733 T arget Instruction Pipeline Stage E1 PS PW PR DP DC E1 Read NRP Written Branch T aken  Unit in use .S2 Instruction T ype Branch Delay Slots 5 Example T able 3 − 16 gives the program counter values and actions for the following code example. Given that an interrupt occurred at [...]

Clear a Bit Field CLR 3-77 Instruction Set SPRU733 Clear a Bit Field CLR Syntax CLR (.unit) src2 , csta , cstb , dst or CLR (.unit) src2 , src1 , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode Constant form 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 876543210 creg z dst src2 csta cstb 100010 s p 3 1 5 5 5 5 1 1 Opcode map [...]

CLR Clear a Bit Field 3-78 Instruction Set SPRU733 Description The field in src2 , specified by csta and cstb , is cleared to zero. csta and cstb may be specified as constants or as the ten LSBs of the src1 registers, with cstb being bits 0 − 4 and csta bits 5 − 9. csta signifies the bit location of the LSB in the field and cstb signifies the b[...]

Clear a Bit Field CLR 3-79 Instruction Set SPRU733 Example 1 CLR .S1 A1,4,19,A2 Before instruction 1 cycle after instruction A1 07A4 3F2Ah A1 07A4 3F2Ah A 2 xxxx xxxxh A 2 07A0 000Ah Example 2 CLR .S2 B1,B3,B2 Before instruction 1 cycle after instruction B1 03B6 E7D5h B1 03B6 E7D5h B 2 xxxx xxxxh B2 03B0 0001h B3 0000 0052h B3 0000 0052h[...]

CMPEQ Compare for Equality , Signed Integers 3-80 Instruction Set SPRU733 Compare for Equality , Signed Integers CMPEQ Syntax CMPEQ (.unit) src1 , src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src1 x op 1 1 0 s p 3 1 5 5 5 1 7 1 1 Opcode map field used[...]

Compare for Equality , Signed Integers CMPEQ 3-81 Instruction Set SPRU733 Pipeline Stage E1 Read src1, src2 Written dst Unit in use .L Instruction T ype Single-cycle Delay Slots 0 See Also CMPEQDP , CMPEQSP , CMPGT , CMPL T Example 1 CMPEQ .L1X A1,B1,A2 Before instruction 1 cycle after instruction A1 0000 04B8h 1208 A1 0000 04B8h A 2 xxxx xxxxh A 2[...]

CMPEQDP Compare for Equality , Double-Precision Floating-Point V alues 3-82 Instruction Set SPRU733 Compare for Equality , Double-Precision Floating-Point Values CMPEQDP Syntax CMPEQDP (.unit) src1 , src2 , dst .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 1 1 6 5 4 3 2 1 0 creg z dst src2 src1 x 1 0 10001[...]

Compare for Equality , Double-Precision Floating-Point V alues CMPEQDP 3-83 Instruction Set SPRU733 Notes: 1) In the case of NaN compared with itself, the result is false. 2) No configuration bits besides those in the preceding table are set, except the NaNn and DENn bits when appropriate. Pipeline Stage E1 E2 Read src1_l src2_l src1_h src2_h Writt[...]

CMPEQSP Compare for Equality , Single-Precision Floating-Point V alues 3-84 Instruction Set SPRU733 Compare for Equality , Single-Precision Floating-Point Values CMPEQSP Syntax CMPEQSP (.unit) src1 , src2 , dst .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 1 1 6 5 4 3 2 1 0 creg z dst src2 src1 x 1 1 10001[...]

Compare for Equality , Single-Precision Floating-Point V alues CMPEQSP 3-85 Instruction Set SPRU733 Notes: 1) In the case of NaN compared with itself, the result is false. 2) No configuration bits besides those shown in the preceding table are set, except for the NaNn and DENn bits when appropriate. Pipeline Stage E1 Read src1 src2 Written dst Unit[...]

CMPGT Compare for Greater Than, Signed Integers 3-86 Instruction Set SPRU733 Compare for Greater Than, Signed Integers CMPGT Syntax CMPGT (.unit) src1 , src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src1 x op 1 1 0 s p 3 1 5 5 5 1 7 1 1 Opcode map fiel[...]

Compare for Greater Than, Signed Integers CMPGT 3-87 Instruction Set SPRU733 Description Performs a signed comparison of src1 to src2 . If src1 is greater than src2 , then a 1 is written to dst ; otherwise, a 0 is written to dst . Note: The CMPGT instruction allows using a 5-bit constant as src1. If src2 is a 5-bit constant, as in CMPGT .L1 A4, 5, [...]

CMPGT Compare for Greater Than, Signed Integers 3-88 Instruction Set SPRU733 Example 1 CMPGT .L1X A1,B1,A2 Before instruction 1 cycle after instruction A1 0000 01B6h 438 A1 0000 01B6h A 2 xxxx xxxxh A 2 0000 0000h false B1 0000 08BDh 2237 B1 0000 08BDh Example 2 CMPGT .L1X A1,B1,A2 Before instruction 1 cycle after instruction A1 FFFF FE91h − 367 [...]

Compare for Greater Than, Double-Precision Floating-Point V alues CMPGTDP 3-89 Instruction Set SPRU733 Compare for Greater Than, Double-Precision Floating-Point V alues CMPGTDP Syntax CMPGTDP (.unit) src1 , src2 , dst .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 1 1 6 5 4 3 2 1 0 creg z dst src2 src1 x 1 [...]

CMPGTDP Compare for Greater Than, Double-Precision Floating-Point V alues (C67x CPU) 3-90 Instruction Set SPRU733 Note: No configuration bits other than those shown above are set, except the NaNn and DENn bits when appropriate. Pipeline Stage E1 E2 Read src1_l src2_l src1_h src2_h Written dst Unit in use .S .S Instruction T ype DP compare Delay Slo[...]

Compare for Greater Than, Single-Precision Floating-Point V alues CMPGTSP 3-91 Instruction Set SPRU733 Compare for Greater Than, Single-Precision Floating-Point V alues CMPGTSP Syntax CMPGTSP (.unit) src1 , src2 , dst .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 1 1 6 5 4 3 2 1 0 creg z dst src2 src1 x 1 [...]

CMPGTSP Compare for Greater Than, Single-Precision Floating-Point V alues 3-92 Instruction Set SPRU733 Note: No configuration bits other than those shown above are set, except for the NaNn and DENn bits when appropriate. Pipeline Stage E1 Read src1 src2 Written dst Unit in use .S Instruction T ype Single-cycle Delay Slots 0 Functional Unit Latency [...]

Compare for Greater Than, Unsigned Integers CMPGTU 3-93 Instruction Set SPRU733 Compare for Greater Than, Unsigned Integers CMPGTU Syntax CMPGTU (.unit) src1 , src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src1 x op 1 1 0 s p 3 1 5 5 5 1 7 1 1 Opcode m[...]

CMPGTU Compare for Greater Than, Unsigned Integers 3-94 Instruction Set SPRU733 Pipeline Stage E1 Read src1, src2 Written dst Unit in use .L Instruction T ype Single-cycle Delay Slots 0 See Also CMPGT , CMPGTDP , CMPGTSP , CMPL TU Example 1 CMPGTU .L1 A1,A2,A3 Before instruction 1 cycle after instruction A1 0000 0128h 296 † A1 0000 0128h A 2 FFFF[...]

Compare for Less Than, Signed Integers CMPL T 3-95 Instruction Set SPRU733 Compare for Less Than, Signed Integers CMPL T Syntax CMPL T (.unit) src1 , src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src1 x op 1 1 0 s p 3 1 5 5 5 1 7 1 1 Opcode map field u[...]

CMPL T Compare for Less Than, Signed Integers 3-96 Instruction Set SPRU733 Description Performs a signed comparison of src1 to src2 . If src1 is less than src2 , then 1 is written to dst ; otherwise, 0 is written to dst . Note: The CMPL T instruction allows using a 5-bit constant as src1. If src2 is a 5-bit constant, as in CMPLT .L1 A4, 5, A0 Then [...]

Compare for Less Than, Signed Integers CMPL T 3-97 Instruction Set SPRU733 Example 1 CMPLT .L1 A1,A2,A3 Before instruction 1 cycle after instruction A1 0000 07E2h 2018 A1 0000 07E2h A 2 0000 0F6Bh 3947 A 2 0000 0F6Bh A3 xxxx xxxxh A3 0000 0001h true Example 2 CMPLT .L1 A1,A2,A3 Before instruction 1 cycle after instruction A1 FFFF FED6h − 298 A1 F[...]

CMPL TDP Compare for Less Than, Double-Precision Floating-Point Values 3-98 Instruction Set SPRU733 Compare for Less Than, Double-Precision Floating-Point V alues CMPL TDP Syntax CMPL TDP (.unit) src1 , src2 , dst .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 1 1 6 5 4 3 2 1 0 creg z dst src2 src1 x 1 0 10[...]

Compare for Less Than, Double-Precision Floating-Point V alues CMPL TDP 3-99 Instruction Set SPRU733 Note: No configuration bits other than those above are set, except for the NaNn and DENn bits when appropriate. Pipeline Stage E1 E2 Read src1_l src2_l src1_h src2_h Written dst Unit in use .S .S Instruction T ype DP compare Delay Slots 1 Functional[...]

CMPL TSP Compare for Less Than, Single-Precision Floating-Point Values 3-100 Instruction Set SPRU733 Compare for Less Than, Single-Precision Floating-Point V alues CMPL TSP Syntax CMPL TSP (.unit) src1 , src2 , dst .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 1 1 6 5 4 3 2 1 0 creg z dst src2 src1 x 1 1 1[...]

Compare for Less Than, Single-Precision Floating-Point V alues CMPL TSP 3-101 Instruction Set SPRU733 Note: No configuration bits other than those above are set, except for the NaNn and DENn bits when appropriate. Pipeline Stage E1 Read src1 src2 Written dst Unit in use .S Instruction T ype Single-cycle Delay Slots 0 Functional Unit Latency 1 See A[...]

CMPL TU Compare for Less Than, Unsigned Integers 3-102 Instruction Set SPRU733 Compare for Less Than, Unsigned Integers CMPL TU Syntax CMPL TU (.unit) src1 , src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src1 x op 1 1 0 s p 3 1 5 5 5 1 7 1 1 Opcode map[...]

Compare for Less Than, Unsigned Integers CMPL TU 3-103 Instruction Set SPRU733 Pipeline Stage E1 Read src1, src2 Written dst Unit in use .L Instruction T ype Single-cycle Delay Slots 0 See Also CMPGTU, CMPL T , CMPL TDP , CMPL TSP Example 1 CMPLTU .L1 A1,A2,A3 Before instruction 1 cycle after instruction A1 0000 289Ah 10394 † A1 0000 289Ah A 2 FF[...]

DPINT Convert Double-Precision Floating-Point V alue to Integer 3-104 Instruction Set SPRU733 Convert Double-Precision Floating-Point V alue to Integer DPINT Syntax DPINT (.unit) src2 , dst .unit = .L1 or .L2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 0 0 0 0 0 x 0 0 0 1 0 0 0 1 1 0 s p 3 1 [...]

Convert Double-Precision Floating-Point V alue to Integer DPINT 3-105 Instruction Set SPRU733 Pipeline Stage E1 E2 E3 E4 Read src2_l src2_h Written dst Unit in use .L Instruction T ype 4-cycle Delay Slots 3 Functional Unit Latency 1 See Also DPSP , DPTRUNC, INTDP , SPINT Example DPINT .L1 A1:A0,A4 Before instruction 4 cycles after instruction A1:A0[...]

DPSP Convert Double-Precision Floating-Point V alue to Single-Precision Floating-Point Value 3-106 Instruction Set SPRU733 Convert Double-Precision Floating-Point V alue to Single-Precision Floating-Point V alue DPSP Syntax DPSP (.unit) src2 , dst .unit = .L1 or .L2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 [...]

Convert Double-Precision Floating-Point V alue to Single-Precision Floating-Point Value DPSP 3-107 Instruction Set SPRU733 7) If underflow occurs, the INEX and UNDER bits are set and the results are set as follows (SPFN is the smallest floating-point number): Underflow Output Rounding Mode Result Sign Nearest Even Zero +Infinity − Infinity + +0 +[...]

DPTRUNC Convert Double-Precision Floating-Point V alue to Integer With T runcation 3-108 Instruction Set SPRU733 Convert Double-Precision Floating-Point V alue to Integer With T runcation DPTRUNC Syntax DPTRUNC (.unit) src2 , dst .unit = .L1 or .L2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 [...]

Convert Double-Precision Floating-Point V alue to Integer With T runcation DPTRUNC 3-109 Instruction Set SPRU733 Pipeline Stage E1 E2 E3 E4 Read src2_l src2_h Written dst Unit in use .L Instruction T ype 4-cycle Delay Slots 3 Functional Unit Latency 1 See Also DPINT , DPSP , SPTRUNC Example DPTRUNC .L1 A1:A0,A4 Before instruction 4 cycles after ins[...]

EXT Extract and Sign-Extend a Bit Field 3-1 10 Instruction Set SPRU733 Extract and Sign-Extend a Bit Field EXT Syntax EXT (.unit) src2 , csta , cstb , dst or EXT (.unit) src2 , src1 , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode Constant form 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 876543210 creg z dst src2 csta cstb [...]

Extract and Sign-Extend a Bit Field EXT 3-1 1 1 Instruction Set SPRU733 Description The field in src2 , specified by csta and cstb , is extracted and sign-extended to 32 bits. The extract is performed by a shift left followed by a signed shift right. csta and cstb are the shift left amount and shift right amount, respectively . This c an be thought[...]

EXT Extract and Sign-Extend a Bit Field 3-1 12 Instruction Set SPRU733 Instruction T ype Single-cycle Delay Slots 0 See Also EXTU Example 1 EXT .S1 A1,10,19,A2 Before instruction 1 cycle after instruction A1 07A4 3F2Ah A1 07A4 3F2Ah A 2 xxxx xxxxh A2 FFFF F21Fh Example 2 EXT .S1 A1,A2,A3 Before instruction 1 cycle after instruction A1 03B6 E7D5h A1[...]

Extract and Zero-Extend a Bit Field EXTU 3-1 13 Instruction Set SPRU733 Extract and Zero-Extend a Bit Field EXTU Syntax EXTU (.unit) src2 , csta , cstb , dst or EXTU (.unit) src2 , src1 , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode Constant width and offset form: 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 876543210 creg[...]

EXTU Extract and Zero-Extend a Bit Field 3-1 14 Instruction Set SPRU733 Description The field in src2 , specified by csta and cstb , is extracted and zero extended to 32 bits. The extract is performed by a shift left followed by an unsigned shift right. csta and cstb are the amounts to shift left and shift right, respectively . This can be thought [...]

Extract and Zero-Extend a Bit Field EXTU 3-1 15 Instruction Set SPRU733 Instruction T ype Single-cycle Delay Slots 0 See Also EXT Example 1 EXTU .S1 A1,10,19,A2 Before instruction 1 cycle after instruction A1 07A4 3F2Ah A1 07A4 3F2Ah A2 xxxx xxxxh A2 0000 121Fh Example 2 EXTU .S1 A1,A2,A3 Before instruction 1 cycle after instruction A1 03B6 E7D5h A[...]

IDLE Multicycle NOP With No T ermination Until Interrupt 3-1 16 Instruction Set SPRU733 Multicycle NOP With No T ermination Until Interrupt IDLE Syntax IDLE .unit = none Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 18 17 16 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 1 0 Reserved 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 s p 14 1 1 Description Performs an [...]

Convert Signed Integer to Double-Precision Floating-Point V alue INTDP 3-1 17 Instruction Set SPRU733 Convert Signed Integer to Double-Precision Floating-Point V alue INTDP Syntax INTDP (.unit) src2 , dst .unit = .L1 or .L2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 0 0 0 0 0 x 0 1 1 1 0 0 1[...]

INTDP Convert Signed Integer to Double-Precision Floating-Point V alue 3-1 18 Instruction Set SPRU733 Example INTDP .L1x B4,A1:A0 Before instruction 5 cycles after instruction B4 1965 1127h 426053927 B4 1965 1127h 426053927 A1:A0 xxxx xxxxh xxxx xxxxh A1:A0 41B9 6511h 2700 0000h 4.2605393 E08[...]

Convert Unsigned Integer to Double-Precision Floating-Point V alue INTDPU 3-1 19 Instruction Set SPRU733 Convert Unsigned Integer to Double-Precision Floating-Point V alue INTDPU Syntax INTDPU (.unit) src2 , dst .unit = .L1 or .L2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 0 0 0 0 0 x 0 1 1 [...]

INTDPU Convert Unsigned Integer to Double-Precision Floating-Point V alue 3-120 Instruction Set SPRU733 Example INTDPU .L1 A4,A1:A0 Before instruction 5 cycles after instruction A4 FFFF FFDEh 4294967262 A4 FFFF FFDEh 4294967262 A1:A0 xxxx xxxxh xxxx xxxxh A1:A0 41EF FFFFh FBC0 0000h 4.2949673 E09[...]

Convert Signed Integer to Single-Precision Floating-Point V alue INTSP 3-121 Instruction Set SPRU733 Convert Signed Integer to Single-Precision Floating-Point V alue INTSP Syntax INTSP (.unit) src2 , dst .unit = .L1 or .L2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 0 0 0 0 0 x 1 0 0 1 0 1 0 [...]

INTSPU Convert Unsigned Integer to Single-Precision Floating-Point V alue 3-122 Instruction Set SPRU733 Convert Unsigned Integer to Single-Precision Floating-Point V alue INTSPU Syntax INTSPU (.unit) src2 , dst .unit = .L1 or .L2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 0 0 0 0 0 x 1 0 0 1[...]

Load Byte From Memory With a 5-Bit Unsigned Constant Offset or Register Offset LDB(U) 3-123 Instruction Set SPRU733 Load Byte From Memory With a 5-Bit Unsigned Constant Offset or Register Offset LDB(U) Syntax Register Offset LDB (.unit) *+ baseR[offsetR] , dst or LDBU (.unit) *+ baseR[offsetR] , dst Unsigned Constant Offset LDB (.unit) *+ baseR[ucs[...]

LDB(U) Load Byte From Memory With a 5-Bit Unsigned Constant Offset or Register Offset 3-124 Instruction Set SPRU733 The addressing arithmetic that performs the additions and subtractions defaults to linear mode. However , for A4 − A7 and for B4 − B7, the mode can be changed to circular mode by writing the appropriate value to the AMR (see secti[...]

Load Byte From Memory With a 5-Bit Unsigned Constant Offset or Register Offset LDB(U) 3-125 Instruction Set SPRU733 Example LDB .D1 * − A5[4],A7 Before LDB 1 cycle after LDB 5 cycles after LDB A5 0000 0204h A5 0000 0204h A5 0000 0204h A7 1951 1970h A7 1951 1970h A7 FFFF FFE1h AMR 0000 0000h AMR 0000 0000h AMR 0000 0000h mem 200h E1h mem 200h E1h [...]

LDB(U) Load Byte From Memory With a 15-Bit Unsigned Constant Offset 3-126 Instruction Set SPRU733 Load Byte From Memory With a 15-Bit Unsigned Constant Offset LDB(U) Syntax LDB (.unit) *+B14/B15[ ucst15 ], dst or LDBU (.unit) *+B14/B15[ ucst15 ], dst .unit = .D2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 9 8 [...]

Load Byte From Memory With a 15-Bit Unsigned Constant Offset LDB(U) 3-127 Instruction Set SPRU733 Execution if (cond) mem → dst else nop Note: This instruction executes only on the B side (.D2). Pipeline Stage E1 E2 E3 E4 E5 Read B14 / B15 Written dst Unit in use .D2 Instruction T ype Load Delay Slots 4 See Also LDH, LDW Example LDB .D2 *+B14[36][...]

LDDW Load Doubleword From Memory With an Unsigned Constant Offset or Register Offset 3-128 Instruction Set SPRU733 Load Doubleword From Memory With an Unsigned Constant Offset or Register Offset LDDW Syntax Register Offset LDDW (.unit) *+ baseR[offsetR] , dst Unsigned Constant Offset LDDW (.unit) *+ baseR[ucst5] , dst .unit = .D1 or .D2 Compatibili[...]

Load Doubleword From Memory With an Unsigned Constant Offset or Register Offset LDDW 3-129 Instruction Set SPRU733 Increments and decrements default to 1 and offsets default to 0 when no bracketed register , bracketed constant, or constant enclosed in parentheses is specified. Square brackets, [ ], indicate that ucst5 is left shifted by 3. Parenthe[...]

LDDW Load Doubleword From Memory With an Unsigned Constant Offset or Register Offset 3-130 Instruction Set SPRU733 Delay Slots 4 Functional Unit Latency 1 See Also LDB, LDH, LDW Example 1 LDDW .D2 *+B10[1],A1:A0 Before instruction 5 cycles after instruction A1:A0 xxxx xxxxh xxxx xxxxh A1:A0 4021 3333h 3333 3333h B 1 0 0000 0010h 16 B10 0000 0010h 1[...]

Load Halfword From Memory With a 5-Bit Unsigned Constant Offset or Register Offset LDH(U) 3-131 Instruction Set SPRU733 Load Halfword From Memory With a 5-Bit Unsigned Constant Offset or Register Offset LDH(U) Syntax Register Offset LDH (.unit) *+ baseR[offsetR] , dst or LDHU (.unit) *+ baseR[offsetR] , dst Unsigned Constant Offset LDH (.unit) *+ b[...]

LDH(U) Load Halfword From Memory With a 5-Bit Unsigned Constant Offset or Register Offset 3-132 Instruction Set SPRU733 The addressing arithmetic that performs the additions and subtractions defaults to linear mode. However , for A4 − A7 and for B4 − B7, the mode can be changed to circular mode by writing the appropriate value to the AMR (see s[...]

Load Halfword From Memory With a 5-Bit Unsigned Constant Offset or Register Offset LDH(U) 3-133 Instruction Set SPRU733 Example LDH .D1 *++A4[A1],A8 Before LDH 1 cycle after LDH 5 cycles after LDH A1 0000 0002h A1 0000 0002h A1 0000 0002h A4 0000 0020h A4 0000 0024h A4 0000 0024h A8 1103 51FFh A8 1103 51FFh A8 FFFF A21Fh AMR 0000 0000h AMR 0000 000[...]

LDH(U) Load Halfword From Memory With a 15-Bit Unsigned Constant Offset 3-134 Instruction Set SPRU733 Load Halfword From Memory With a 15-Bit Unsigned Constant Offset LDH(U) Syntax LDH (.unit) *+B14/B15[ ucst15 ], dst or LDHU (.unit) *+B14/B15[ ucst15 ], dst .unit = .D2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13[...]

Load Halfword From Memory With a 15-Bit Unsigned Constant Offset LDH(U) 3-135 Instruction Set SPRU733 T able 3 − 20. Data T ypes Supported by LDH(U) Instruction (15-Bit Offset) Mnemonic op Field Load Data T ype SIze Left Shift of Offset LDH 100 Load halfword 16 1 bit LDHU 000 Load halfword unsigned 16 1 bit Execution if (cond) mem → dst else no[...]

LDW Load Word From Memory With a 5-Bit Unsigned Constant Offset or Register Offset 3-136 Instruction Set SPRU733 Load Word From Memory With a 5-Bit Unsigned Constant Offset or Register Offset LDW Syntax Register Offset LDW (.unit) *+ baseR[offsetR] , dst Unsigned Constant Offset LDW (.unit) *+ baseR[ucst5] , dst .unit = .D1 or .D2 Compatibility C62[...]

Load Word From Memory With a 5-Bit Unsigned Constant Offset or Register Offset LDW 3-137 Instruction Set SPRU733 Increments and decrements default to 1 and offsets default to 0 when no bracketed register or constant is specified. Loads that do no modification to the baseR can use the syntax *R. Square brackets, [ ], indicate that the ucst5 o f fset[...]

LDW Load Word From Memory With a 5-Bit Unsigned Constant Offset or Register Offset 3-138 Instruction Set SPRU733 Example 1 LDW .D1 *A10,B1 Before LDW 1 cycle after LDW 5 cycles after LDW B1 0000 0000h B1 0000 0000h B1 21F3 1996h A10 0000 0100h A10 0000 0100h A10 0000 0100h mem 100h 21F3 1996h mem 100h 21F3 1996h mem 100h 21F3 1996h Example 2 LDW .D[...]

Load Word From Memory With a 15-Bit Unsigned Constant Offset LDW 3-139 Instruction Set SPRU733 Load Word From Memory With a 15-Bit Unsigned Constant Offset LDW Syntax LDW (.unit) *+B14/B15[ ucst15 ], dst .unit = .D2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 9 8 7 6 4 3 2 1 0 creg z dst ucst15 y 11011 s p 3 1[...]

LDW Load Word From Memory With a 15-Bit Unsigned Constant Offset 3-140 Instruction Set SPRU733 Pipeline Stage E1 E2 E3 E4 E5 Read B14 / B15 Written dst Unit in use .D2 Instruction T ype Load Delay Slots 4 See Also LDB, LDH Pipeline[...]

Leftmost Bit Detection LMBD 3-141 Instruction Set SPRU733 Leftmost Bit Detection LMBD Syntax LMBD (.unit) src1 , src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src1/cst5 x op 1 1 0 s p 3 1 5 5 5 1 7 1 1 Opcode map field used... For operand type... Unit [...]

LMBD Leftmost Bit Detection 3-142 Instruction Set SPRU733 Execution if (cond) { if ( src1 0 == 0) lmb0( src2 ) → dst if ( src1 0 == 1) lmb1( src2 ) → dst } else nop Pipeline Stage E1 Read src1, src2 Written dst Unit in use .L Instruction T ype Single-cycle Delay Slots 0 Example LMBD .L1 A1,A2,A3 Before instruction 1 cycle after instruction A1 0[...]

Multiply Signed 16 LSB x Signed 16 LSB MPY 3-143 Instruction Set SPRU733 Multiply Signed 16 LSB  Signed 16 LSB MPY Syntax MPY (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 76543210 creg z dst src2 src1 x op 00000 s p 3 1 5 5 5 1 5 1 1 Opcode map field[...]

MPY Multiply Signed 16 LSB x Signed 16 LSB 3-144 Instruction Set SPRU733 Example 1 MPY .M1 A1,A2,A3 Before instruction 2 cycles after instruction A1 0000 0123h 291 † A1 0000 0123h A 2 01E0 FA81h − 1407 † A 2 01E0 FA81h A3 xxxx xxxxh A3 FFF9 C0A3 − 409437 † Signed 16-LSB integer Example 2 MPY .M1 13,A1,A2 Before instruction 2 cycles after [...]

Multiply T wo Double-Precision Floating-Point V alues MPYDP 3-145 Instruction Set SPRU733 Multiply T wo Double-Precision Floating-Point V alues MPYDP Syntax MPYDP (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C67x and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 76543210 creg z dst src2 src1 x 0 1 11000000 s p 3 1 5 5 5[...]

MPYDP Multiply T wo Double-Precision Floating-Point V alues 3-146 Instruction Set SPRU733 Pipeline Stage E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 Read src1_l src2_l src1_l src2_h src1_h src2_l src1_h src2_h Written dst_l dst_h Unit in use .M .M .M .M If dst is used as the source for the ADDDP , CMPEQDP , CMPL TDP , CMPGTDP , MPYDP , or SUBDP instruction, the[...]

Multiply Signed 16 MSB x Signed 16 MSB MPYH 3-147 Instruction Set SPRU733 Multiply Signed 16 MSB  Signed 16 MSB MPYH Syntax MPYH (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 76543210 creg z dst src2 src1 x 0 0 00100000 s p 3 1 5 5 5 1 1 1 Opcode map [...]

MPYH Multiply Signed 16 MSB x Signed 16 MSB 3-148 Instruction Set SPRU733 Example MPYH .M1 A1,A2,A3 Before instruction 2 cycles after instruction A1 0023 0000h 35 † A1 0023 0000h A 2 FFA7 1234h − 89 † A 2 FFA7 1234h A3 xxxx xxxxh A3 FFFF F3D5h − 3115 † Signed 16-MSB integer[...]

Multiply Signed 16 MSB x Signed 16 LSB MPYHL 3-149 Instruction Set SPRU733 Multiply Signed 16 MSB  Signed 16 LSB MPYHL Syntax MPYHL (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 76543210 creg z dst src2 src1 x 0 1 00100000 s p 3 1 5 5 5 1 1 1 Opcode m[...]

MPYHL Multiply Signed 16 MSB x Signed 16 LSB 3-150 Instruction Set SPRU733 Example MPYHL .M1 A1,A2,A3 Before instruction 2 cycles after instruction A1 008A 003Eh 138 † A1 008A 003Eh A 2 21FF 00A7h 167 ‡ A 2 21FF 00A7h A3 xxxx xxxxh A3 0000 5A06h 23046 † Signed 16-MSB integer ‡ Signed 16-LSB integer[...]

Multiply Unsigned 16 MSB x Unsigned 16 LSB MPYHLU 3-151 Instruction Set SPRU733 Multiply Unsigned 16 MSB  Unsigned 16 LSB MPYHLU Syntax MPYHLU (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 76543210 creg z dst src2 src1 x 0 1 11100000 s p 3 1 5 5 5 1 1[...]

MPYHSLU Multiply Signed 16 MSB x Unsigned 16 LSB 3-152 Instruction Set SPRU733 Multiply Signed 16 MSB  Unsigned 16 LSB MPYHSLU Syntax MPYHSLU (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 76543210 creg z dst src2 src1 x 0 1 01100000 s p 3 1 5 5 5 1 1 [...]

Multiply Signed 16 MSB x Unsigned 16 MSB MPYHSU 3-153 Instruction Set SPRU733 Multiply Signed 16 MSB  Unsigned 16 MSB MPYHSU Syntax MPYHSU (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 76543210 creg z dst src2 src1 x 0 0 01100000 s p 3 1 5 5 5 1 1 1 O[...]

MPYHU Multiply Unsigned 16 MSB x Unsigned 16 MSB 3-154 Instruction Set SPRU733 Multiply Unsigned 16 MSB  Unsigned 16 MSB MPYHU Syntax MPYHU (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 76543210 creg z dst src2 src1 x 0 0 11100000 s p 3 1 5 5 5 1 1 1 [...]

Multiply Unsigned 16 MSB x Signed 16 LSB MPYHULS 3-155 Instruction Set SPRU733 Multiply Unsigned 16 MSB  Signed 16 LSB MPYHULS Syntax MPYHULS (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 76543210 creg z dst src2 src1 x 0 1 10100000 s p 3 1 5 5 5 1 1 [...]

MPYHUS Multiply Unsigned 16 MSB x Signed 16 MSB 3-156 Instruction Set SPRU733 Multiply Unsigned 16 MSB  Signed 16 MSB MPYHUS Syntax MPYHUS (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 76543210 creg z dst src2 src1 x 0 0 10100000 s p 3 1 5 5 5 1 1 1 O[...]

Multiply 32-Bit x 32-Bit Into 32-Bit Result MPYI 3-157 Instruction Set SPRU733 Multiply 32-Bit  32-Bit Into 32-Bit Result MPYI Syntax MPYI (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C67x and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 76543210 creg z dst src2 src1 x op 00000 s p 3 1 5 5 5 1 5 1 1 Opcode map field[...]

MPYI Multiply 32-Bit x 32-Bit Into 32-Bit Result 3-158 Instruction Set SPRU733 Functional Unit Latency 4 See Also MPYID Example MPYI .M1X A1,B2,A3 Before instruction 9 cycles after instruction A1 0034 5678h 3430008 A1 0034 5678h 3430008 B2 0011 2765h 1124197 B2 0011 2765h 1124197 A3 xxxx xxxxh A3 CBCA 6558h − 875928232[...]

Multiply 32-Bit x 32-Bit Into 64-Bit Result MPYID 3-159 Instruction Set SPRU733 Multiply 32-Bit  32-Bit Into 64-Bit Result MPYID Syntax MPYID (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C67x and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 76543210 creg z dst src2 src1 x op 00000 s p 3 1 5 5 5 1 5 1 1 Opcode map fi[...]

MPYID Multiply 32-Bit x 32-Bit Into 64-Bit Result 3-160 Instruction Set SPRU733 Functional Unit Latency 4 See Also MPYI Example MPYID .M1 A1,A2,A5:A4 Before instruction 10 cycles after instruction A1 0034 5678h 3430008 A1 0034 5678h 3430008 A2 0011 2765h 1124197 A2 0011 2765h 1124197 A5:A4 xxxx xxxxh xxxx xxxxh A5:A4 0000 0381h CBCA 6558h 385600470[...]

Multiply Signed 16 LSB x Signed 16 MSB MPYLH 3-161 Instruction Set SPRU733 Multiply Signed 16 LSB  Signed 16 MSB MPYLH Syntax MPYLH (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 76543210 creg z dst src2 src1 x 1 0 00100000 s p 3 1 5 5 5 1 1 1 Opcode m[...]

MPYLH Multiply Signed 16 LSB x Signed 16 MSB 3-162 Instruction Set SPRU733 Example MPYLH .M1 A1,A2,A3 Before instruction 2 cycles after instruction A1 0900 000Eh 14 † A1 0900 000Eh A 2 0029 00A7h 41 ‡ A 2 0029 00A7h A3 xxxx xxxxh A3 0000 023Eh 574 † Signed 16-LSB integer ‡ Signed 16-MSB integer[...]

Multiply Unsigned 16 LSB x Unsigned 16 MSB MPYLHU 3-163 Instruction Set SPRU733 Multiply Unsigned 16 LSB  Unsigned 16 MSB MPYLHU Syntax MPYLHU (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 76543210 creg z dst src2 src1 x 1 0 11100000 s p 3 1 5 5 5 1 1[...]

MPYLSHU Multiply Signed 16 LSB x Unsigned 16 MSB 3-164 Instruction Set SPRU733 Multiply Signed 16 LSB  Unsigned 16 MSB MPYLSHU Syntax MPYLSHU (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 76543210 creg z dst src2 src1 x 1 0 01100000 s p 3 1 5 5 5 1 1 [...]

Multiply Unsigned 16 LSB x Signed 16 MSB MPYLUHS 3-165 Instruction Set SPRU733 Multiply Unsigned 16 LSB  Signed 16 MSB MPYLUHS Syntax MPYLUHS (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 76543210 creg z dst src2 src1 x 1 0 10100000 s p 3 1 5 5 5 1 1 [...]

MPYSP Multiply T wo Single-Precision Floating-Point V alues 3-166 Instruction Set SPRU733 Multiply T wo Single-Precision Floating-Point V alues MPYSP Syntax MPYSP (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C67x and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 76543210 creg z dst src2 src1 x 1 1 10000000 s p 3 1 5 5 5[...]

Multiply T wo Single-Precision Floating-Point V alues MPYSP 3-167 Instruction Set SPRU733 Pipeline Stage E1 E2 E3 E4 Read src1 src2 Written dst Unit in use .M If dst is used as the source for the ADDDP , CMPEQDP , CMPL TDP , CMPGTDP , MPYDP , or SUBDP instruction, the number of delay slots can be reduced by one, because these instructions read the [...]

MPYSPDP Multiply Single-Precision V alue x Double-Precision Value (C67x+ CPU) 3-168 Instruction Set SPRU733 Multiply Single-Precision Floating-Point V alue  Double-Precision Floating-Point V alue MPYSPDP Syntax MPYSPDP (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C67x+ CPU only Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 765[...]

Multiply Single-Precision V alue x Double-Precision Value (C67x+ CPU) MPYSPDP 3-169 Instruction Set SPRU733 Pipeline Stage E1 E2 E3 E4 E5 E6 E7 Read src1 src2_l src1 src2_h Written dst_l dst_h Unit in use .M .M The low half of the result is written out one cycle earlier than the high half. If dst is used as the source for the ADDDP , CMPEQDP , CMPL[...]

MPYSP2DP Multiply T wo Single-Precision Floating-Point V alues for Double-Precision Result (C67x+ CPU) 3-170 Instruction Set SPRU733 Multiply T wo Single-Precision Floating-Point V alues for Double-Precision Result MPYSP2DP Syntax MPYSP2DP (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C67x+ CPU only Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1[...]

Multiply T wo Single-Precision Floating-Point V alues for Double-Precision Result (C67x+ CPU) MPYSP2DP 3-171 Instruction Set SPRU733 Pipeline Stage E1 E2 E3 E4 E5 Read src1 src2 Written dst_l dst_h Unit in use .M The low half of the result is written out one cycle earlier than the high half. If dst is used as the source for the ADDDP , CMPEQDP , CM[...]

MPYSU Multiply Signed 16 LSB x Unsigned 16 LSB 3-172 Instruction Set SPRU733 Multiply Signed 16 LSB  Unsigned 16 LSB MPYSU Syntax MPYSU (.unit) src1, src2, dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 76543210 creg z dst src2 src1 x op 00000 s p 3 1 5 5 5 1 5 1 1 Opcode m[...]

Multiply Signed 16 LSB x Unsigned 16 LSB MPYSU 3-173 Instruction Set SPRU733 See Also MPY , MPYU, MPYUS Example MPYSU .M1 13,A1,A2 Before instruction 2 cycles after instruction A1 3497 FFF3h 65523 ‡ A1 3497 FFF3h A2 xxxx xxxxh A 2 000C FF57h 851779 ‡ Unsigned 16-LSB integer[...]

MPYU Multiply Unsigned 16 LSB x Unsigned 16 LSB 3-174 Instruction Set SPRU733 Multiply Unsigned 16 LSB  Unsigned 16 LSB MPYU Syntax MPYU (.unit) src1, src2, dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 76543210 creg z dst src2 src1 x 1 1 11100000 s p 3 1 5 5 5 1 1 1 Opcod[...]

Multiply Unsigned 16 LSB x Unsigned 16 LSB MPYU 3-175 Instruction Set SPRU733 Example MPYU .M1 A1,A2,A3 Before instruction 2 cycles after instruction A1 0000 0123h 291 ‡ A1 0000 0123h A 2 0F12 FA81h 64129 ‡ A 2 0F12 FA81h A3 xxxx xxxxh A3 011C C0A3 18661539 § ‡ Unsigned 16-LSB integer[...]

MPYUS Multiply Unsigned 16 LSB x Signed 16 LSB 3-176 Instruction Set SPRU733 Multiply Unsigned 16 LSB  Signed 16 LSB MPYUS Syntax MPYUS (.unit) src1, src2, dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 76543210 creg z dst src2 src1 x 1 1 10100000 s p 3 1 5 5 5 1 1 1 Opcode[...]

Multiply Unsigned 16 LSB x Signed 16 LSB MPYUS 3-177 Instruction Set SPRU733 Example MPYUS .M1 A1,A2,A3 Before instruction 2 cycles after instruction A1 1234 FFA1h 65441 ‡ A1 1234 FFA1h A2 1234 FFA1h − 95 † A2 1234 FFA1h A3 xxxx xxxxh A3 FFA1 2341h − 6216895 † Signed 16-LSB integer ‡ Unsigned 16-LSB integer[...]

MV Move From Register to Register 3-178 Instruction Set SPRU733 Move From Register to Register MV Syntax MV (.unit) src2, dst .unit = .L1, .L2, .S1, .S2, .D1, .D2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode .L unit 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 0 0 0 0 0 x op 1 1 0 s p 3 1 5 5 1 7 1 1 Opcode map field used...[...]

Move From Register to Register MV 3-179 Instruction Set SPRU733 Opcode .D unit 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 76543210 creg z dst src2 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 s p 3 1 5 5 1 1 Opcode map field used... For operand type... Unit src 2 dst sint sint .D1, .D2 Description The MV pseudo-operation moves a value from one register to another [...]

MVC Move Between Control File and Register File 3-180 Instruction Set SPRU733 Move Between Control File and Register File MVC Syntax MVC (.unit) src2 , dst .unit = .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0 creg z dst src2 00000x op 1000 s p 3 1 5 5 1 6 1 1 Operands when moving from the c[...]

Move Between Control File and Register File MVC 3-181 Instruction Set SPRU733 Execution if (cond) src2 → dst else nop Note: The MVC instruction executes only on the B side (.S2). Refer to the individual control register descriptions for specific behaviors and restrictions in accesses via the MVC instruction. Pipeline Stage E1 Read src2 Written ds[...]

MVC Move Between Control File and Register File 3-182 Instruction Set SPRU733 T able 3 − 21. Register Addresses for Accessing the Control Registers Acronym Register Name Address Read/ Write AMR Addressing mode register 00000 R, W CSR Control status register 00001 R, W F ADCR Floating-point adder configuration 10010 R, W F AUCR Floating-point auxi[...]

Move Signed Constant Into Register and Sign Extend MVK 3-183 Instruction Set SPRU733 Move Signed Constant Into Register and Sign Extend MVK Syntax MVK (.unit) cst , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 7 654321 0 creg z dst cst16 01010 s p 3 1 5 16 1 1 Opcode map field used... For operand typ[...]

MVK Move Signed Constant Into Register and Sign Extend 3-184 Instruction Set SPRU733 Instruction T ype Single cycle Delay Slots 0 See Also MVKH, MVKL, MVKLH Example 1 MVK .L2 − 5,B8 Before instruction 1 cycle after instruction B8 xxxx xxxxh B8 FFFF FFFBh Example 2 MVK .D2 14,B8 Before instruction 1 cycle after instruction B8 xxxx xxxxh B8 0000 00[...]

Move 16-Bit Constant Into Upper Bits of Register MVKH/MVKLH 3-185 Instruction Set SPRU733 Move 16-Bit Constant Into Upper Bits of Register MVKH/MVKLH Syntax MVKH (.unit) cst , dst or MVKLH (.unit) cst , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 76543210 creg z dst cst16 11010 s p 3 1 5 16 1 1 Opco[...]

MVKH/MVKLH Move 16-Bit Constant Into Upper Bits of Register 3-186 Instruction Set SPRU733 Instruction T ype Single-cycle Delay Slots 0 Note: Us e the MVK instruction (page 3-183 ) to load 16-bit constants. The assem- bler generates a warning for any constant over 16 bits. T o load 32-bit constants, such as 1234 5678h, use the following pair of inst[...]

Move Signed Constant Into Register and Sign Extend − Used with MVKH MVKL 3-187 Instruction Set SPRU733 Move Signed Constant Into Register and Sign Extend MVKL Syntax MVKL (.unit) cst , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 7 654321 0 creg z dst cst16 01010 s p 3 1 5 16 1 1 Opcode map field u[...]

MVKL Move Signed Constant Into Register and Sign Extend − Used with MVKH 3-188 Instruction Set SPRU733 Pipeline Stage E1 Read Written dst Unit in use .S Instruction T ype Single cycle Delay Slots 0 See Also MVK, MVKH, MVKLH Example 1 MVKL .S1 5678h,A8 Before instruction 1 cycle after instruction A8 xxxx xxxxh A8 0000 5678h Example 2 MVKL .S1 0C67[...]

Negate NEG 3-189 Instruction Set SPRU733 Negate NEG Syntax NEG (.unit) src2, dst .unit = .L1, .L2, .S1, .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode .S unit 31 29 28 27 23 22 18 17 13 12 1 1 6 5 4 3 2 1 0 creg z dst src2 0 0 0 0 0 x 0 1 0 1 1 0 1 0 0 0 s p 3 1 5 5 1 1 1 Opcode map field used... For operand type... Unit src 2 dst xsint s[...]

NOP No Operation 3-190 Instruction Set SPRU733 No Operation NOP Syntax NOP [ count ] .unit = none Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 18 17 16 13 12 1 1 10 9 8 7 6 5 4 3 2 1 0 Reserved 0 src 0 0 0 0 0 0 0 0 0 0 0 0 p 14 4 1 Opcode map field used... For operand type... Unit src ucst4 none Description src is encoded as count − 1[...]

No Operation NOP 3-191 Instruction Set SPRU733 Example 1 NOP MVK .S1 125h,A1 Before NOP 1 cycle after NOP (No operation executes) 1 cycle after MVK A1 1234 5678h A1 1234 5678h A1 0000 0125h Example 2 MVK .S1 1,A1 MVKLH .S1 0,A1 NOP 5 ADD .L1 A1,A2,A1 Before NOP 5 1 cycle after ADD instruction (6 cycles after NOP 5) A1 0000 0001h A1 0000 0004h A2 00[...]

NORM Normalize Integer 3-192 Instruction Set SPRU733 Normalize Integer NORM Syntax NORM (.unit) src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 00000x op 110 s p 3 1 5 5 1 7 1 1 Opcode map field used... For operand type... Unit Opfield src2 dst xsint uin[...]

Normalize Integer NORM 3-193 Instruction Set SPRU733 Execution if (cond) norm( src ) → dst else nop Pipeline Stage E1 Read src2 Written dst Unit in use .L Instruction T ype Single-cycle Delay Slots 0 Example 1 NORM .L1 A1,A2 Before instruction 1 cycle after instruction A1 02A3 469Fh A1 02A3 469Fh A2 xxxx xxxxh A2 0000 0005h 5 Example 2 NORM .L1 A[...]

NOT Bitwise NOT 3-194 Instruction Set SPRU733 Bitwise NOT NOT Syntax NOT (.unit) src2, dst .unit = .L1, .L2, .S1, .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode .L unit 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 543210 creg z dst src2 1 1 1 1 1 x 1 1 0 1 1 1 0 1 1 0 s p 3 1 5 5 1 1 1 Opcode map field used... For operand type... Unit src [...]

Bitwise OR OR 3-195 Instruction Set SPRU733 Bitwise OR OR Syntax OR (.unit) src1 , src2 , dst .unit = .L1, .L2, .S1, .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode .L unit 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 543210 creg z dst src2 src1 x op 110 s p 3 1 5 5 5 1 7 1 1 Opcode map field used... For operand type... Unit Opfield src1 sr[...]

OR Bitwise OR 3-196 Instruction Set SPRU733 Execution if (cond) src1 OR src2 → dst else nop Pipeline Stage E1 Read src1, src2 Written dst Unit in use .L or .S Instruction T ype Single-cycle Delay Slots 0 See Also AND, XOR Example 1 OR .S1 A3,A4,A5 Before instruction 1 cycle after instruction A3 08A3 A49Fh A3 08A3 A49Fh A4 00FF 375Ah A4 00FF 375Ah[...]

Double-Precision Floating-Point Reciprocal Approximation RCPDP 3-197 Instruction Set SPRU733 Double-Precision Floating-Point Reciprocal Approximation RCPDP Syntax RCPDP (.unit) src2 , dst .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 1 1 6 5 4 3 2 1 0 creg z dst src2 reserved x 1 0 11011000 s p 3 1 5 5 5 1[...]

RCPDP Double-Precision Floating-Point Reciprocal Approximation 3-198 Instruction Set SPRU733 Note: 1) If src2 is SNaN, NaN_out is placed in dst and the INV AL and NAN2 bits are set. 2) If src2 is QNaN, NaN_out is placed in dst and the NAN2 bit is set. 3) If src2 is a signed denormalized number , signed infinity is placed in dst and the DIV0, INFO, [...]

Single-Precision Floating-Point Reciprocal Approximation RCPSP 3-199 Instruction Set SPRU733 Single-Precision Floating-Point Reciprocal Approximation RCPSP Syntax RCPSP (.unit) src2 , dst .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 1 1 6 5 4 3 2 1 0 creg z dst src2 0 0 0 0 0 x 1 1 1 1 0 1 1 0 0 0 s p 3 1[...]

RCPSP Single-Precision Floating-Point Reciprocal Approximation 3-200 Instruction Set SPRU733 Notes: 1) If src2 is SNaN, NaN_out is placed in dst and the INV AL and NAN2 bits are set. 2) If src2 is QNaN, NaN_out is placed in dst and the NAN2 bit is set. 3) If src2 is a signed denormalized number , signed infinity is placed in dst and the DIV0, INFO,[...]

Double-Precision Floating-Point Square-Root Reciprocal Approximation RSQRDP 3-201 Instruction Set SPRU733 Double-Precision Floating-Point Square-Root Reciprocal Approximation RSQRDP Syntax RSQRDP (.unit) src2 , dst .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 1 1 6 5 4 3 2 1 0 creg z dst src2 reserved x 1[...]

RSQRDP Double-Precision Floating-Point Square-Root Reciprocal Approximation 3-202 Instruction Set SPRU733 Notes: 1) If src2 is SNaN, NaN_out is placed in dst and the INV AL and NAN2 bits are set. 2) If src2 is QNaN, NaN_out is placed in dst and the NAN2 bit is set. 3) If src2 is a negative, nonzero, nondenormalized number , NaN_out is placed in dst[...]

Single-Precision Floating-Point Square-Root Reciprocal Approximation RSQRSP 3-203 Instruction Set SPRU733 Single-Precision Floating-Point Square-Root Reciprocal Approximation RSQRSP Syntax RSQRSP (.unit) src2 , dst .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 1 1 6 5 4 3 2 1 0 creg z dst src2 0 0 0 0 0 x [...]

RSQRSP Single-Precision Floating-Point Square-Root Reciprocal Approximation 3-204 Instruction Set SPRU733 Note: 1) If src2 is SNaN, NaN_out is placed in dst and the INV AL and NAN2 bits are set. 2) If src2 is QNaN, NaN_out is placed in dst and the NAN2 bit is set. 3) If src2 is a negative, nonzero, nondenormalized number , NaN_out is placed in dst [...]

Add T wo Signed Integers With Saturation SADD 3-205 Instruction Set SPRU733 Add T wo Signed Integers With Saturation SADD Syntax SADD (.unit) src1 , src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src1 x op 1 1 0 s p 3 1 5 5 5 1 7 1 1 Opcode map field us[...]

SADD Add T wo Signed Integers With Saturation 3-206 Instruction Set SPRU733 Pipeline Stage E1 Read src1, src2 Written dst Unit in use .L Instruction T ype Single-cycle Delay Slots 0 See Also ADD, SSUB Example 1 SADD .L1 A1,A2,A3 Before instruction 1 cycle after instruction 2 cycles after instruction A1 5A2E 51A3h 1512984995 A1 5A2E 51A3h A1 5A2E 51[...]

Add T wo Signed Integers With Saturation SADD 3-207 Instruction Set SPRU733 Example 3 SADD .L1X B2,A5:A4,A7:A6 Before instruction 1 cycle after instruction A5:A4 0000 0000h 7C83 39B1h 1922644401 † A5:A4 0000 0000h 7C83 39B1h A7:A6 xxxx xxxxh xxxx xxxxh A7:A6 0000 0000h 8DAD 7953h 2376956243 † B2 112A 3FA2h 287981474 B2 112A 3FA2h CSR 0001 0100h[...]

SA T Saturate a 40-Bit Integer to a 32-Bit Integer 3-208 Instruction Set SPRU733 Saturate a 40-Bit Integer to a 32-Bit Integer SA T Syntax SA T (.unit) src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 0 0 0 0 0 x 1 0 0 0 0 0 0 1 1 0 s p 3 1 5 5 1 1 1 Opco[...]

Saturate a 40-Bit Integer to a 32-Bit Integer SA T 3-209 Instruction Set SPRU733 Example 1 SAT .L2 B1:B0,B5 Before instruction 1 cycle after instruction 2 cycles after instruction B1:B0 0000 001Fh 3413 539Ah B1:B0 0000 001Fh 3413 539Ah B1:B0 0000 001Fh 3413 539Ah B5 xxxx xxxxh B5 7FFF FFFFh B5 7FFF FFFFh CSR 0001 0100h CSR 0001 0100h CSR 0001 0300h[...]

SET Set a Bit Field 3-210 Instruction Set SPRU733 Set a Bit Field SET Syntax SET (.unit) src2 , csta , cstb , dst or SET (.unit) src2 , src1 , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode Constant form: 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 876543210 creg z dst src2 csta cstb 100010 s p 3 1 5 5 5 5 1 1 Opcode map fi[...]

Set a Bit Field SET 3-21 1 Instruction Set SPRU733 Description The field in src2 , specified by csta and cstb , is set to all 1s. The csta and cstb operands may be specified as constants or in the ten LSBs of the src1 register , with cstb being bits 0 − 4 and csta bits 5 − 9. csta signifies the bit location of the L S B of the field and cstb si[...]

SET Set a Bit Field 3-212 Instruction Set SPRU733 Example 1 SET .S1 A0,7,21,A1 Before instruction 1 cycle after instruction A0 4B13 4A1Eh A0 4B13 4A1Eh A 1 xxxx xxxxh A1 4B3F FF9Eh Example 2 SET .S2 B0,B1,B2 Before instruction 1 cycle after instruction B0 9ED3 1A31h B0 9ED3 1A31h B1 0000 C197h B1 0000 C197h B2 xxxx xxxxh B2 9EFF FA31h[...]

Arithmetic Shift Left SHL 3-213 Instruction Set SPRU733 Arithmetic Shift Left SHL Syntax SHL (.unit) src2 , src1 , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 1 1 6 5 4 3 2 1 0 creg z dst src2 src1 x op 1 0 0 0 s p 3 1 5 5 5 1 6 1 1 Opcode map field used... For operand type... Unit Opfie[...]

SHL Arithmetic Shift Left 3-214 Instruction Set SPRU733 Pipeline Stage E1 Read src1, src2 Written dst Unit in use .S Instruction T ype Single-cycle Delay Slots 0 See Also SHR, SSHL Example 1 SHL .S1 A0,4,A1 Before instruction 1 cycle after instruction A0 29E3 D31Ch A0 29E3 D31Ch A 1 xxxx xxxxh A1 9E3D 31C0h Example 2 SHL .S2 B0,B1,B2 Before instruc[...]

Arithmetic Shift Right SHR 3-215 Instruction Set SPRU733 Arithmetic Shift Right SHR Syntax SHR (.unit) src2 , src1 , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 1 1 6 5 4 3 2 1 0 creg z dst src2 src1 x op 1 0 0 0 s p 3 1 5 5 5 1 6 1 1 Opcode map field used... For operand type... Unit Opf[...]

SHR Arithmetic Shift Right 3-216 Instruction Set SPRU733 Pipeline Stage E1 Read src1, src2 Written dst Unit in use .S Instruction T ype Single-cycle Delay Slots 0 See Also SHL, SHRU Example 1 SHR .S1 A0,8,A1 Before instruction 1 cycle after instruction A0 F123 63D1h A0 F123 63D1h A 1 xxxx xxxxh A1 FFF1 2363h Example 2 SHR .S2 B0,B1,B2 Before instru[...]

Logical Shift Right SHRU 3-217 Instruction Set SPRU733 Logical Shift Right SHRU Syntax SHRU (.unit) src2 , src1 , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 1 1 6 5 4 3 2 1 0 creg z dst src2 src1 x op 1 0 0 0 s p 3 1 5 5 5 1 6 1 1 Opcode map field used... For operand type... Unit Opfiel[...]

SHRU Logical Shift Right 3-218 Instruction Set SPRU733 Pipeline Stage E1 Read src1, src2 Written dst Unit in use .S Instruction T ype Single-cycle Delay Slots 0 See Also SHL, SHR Example SHRU .S1 A0,8,A1 Before instruction 1 cycle after instruction A0 F123 63D1h A0 F123 63D1h A 1 xxxx xxxxh A1 00F1 2363h Pipeline[...]

Multiply Signed 16 LSB x Signed 16 LSB With Left Shift and Saturation SMPY 3-219 Instruction Set SPRU733 Multiply Signed 16 LSB  Signed 16 LSB With Left Shift and Saturation SMPY Syntax SMPY (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 76543210 creg [...]

SMPY Multiply Signed 16 LSB x Signed 16 LSB With Left Shift and Saturation 3-220 Instruction Set SPRU733 Example SMPY .M1 A1,A2,A3 Before instruction 2 cycle after instruction A1 0000 0123h 291 ‡ A1 0000 0123h A2 01E0 FA81h − 1407 ‡ A2 01E0 FA81h A3 xxxx xxxxh A3 FFF3 8146h − 818874 CSR 0001 0100h CSR 0001 0100h Not saturated ‡ Signed 16-[...]

Multiply Signed 16 MSB x Signed 16 MSB With Left Shift and Saturation SMPYH 3-221 Instruction Set SPRU733 Multiply Signed 16 MSB  Signed 16 MSB With Left Shift and Saturation SMPYH Syntax SMPYH (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 76543210 cr[...]

SMPYHL Multiply Signed 16 MSB x Signed 16 LSB With Left Shift and Saturation 3-222 Instruction Set SPRU733 Multiply Signed 16 MSB  Signed 16 LSB With Left Shift and Saturation SMPYHL Syntax SMPYHL (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 76543210[...]

Multiply Signed 16 MSB x Signed 16 LSB With Left Shift and Saturation SMPYHL 3-223 Instruction Set SPRU733 Example SMPYHL .M1 A1,A2,A3 Before instruction 2 cycles after instruction A1 008A 0000h 138 † A1 008A 0000h A2 0000 00A7h 167 ‡ A2 0000 00A7h A3 xxxx xxxxh A3 0000 B40Ch 46092 CSR 0001 0100h CSR 0001 0100h Not saturated † Signed 16-MSB i[...]

SMPYLH Multiply Signed 16 LSB x Signed 16 MSB With Left Shift and Saturation 3-224 Instruction Set SPRU733 Multiply Signed 16 LSB  Signed 16 MSB With Left Shift and Saturation SMPYLH Syntax SMPYLH (.unit) src1 , src2 , dst .unit = .M1 or .M2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 76543210[...]

Multiply Signed 16 LSB x Signed 16 MSB With Left Shift and Saturation SMPYLH 3-225 Instruction Set SPRU733 Example SMPYLH .M1 A1,A2,A3 Before instruction 2 cycles after instruction A1 0000 8000h − 32768 ‡ A1 0000 8000h A2 8000 0000h − 32768 † A2 8000 0000h A3 xxxx xxxxh A3 7FFF FFFFh 2147483647 CSR 0001 0100h CSR 0001 0300h Saturated † Si[...]

SPDP Convert Single-Precision Floating-Point V alue to Double-Precision Floating-Point Value 3-226 Instruction Set SPRU733 Convert Single-Precision Floating-Point V alue to Double-Precision Floating-Point V alue SPDP Syntax SPDP (.unit) src2 , dst .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 1 1 6 5 4 3 2[...]

Convert Single-Precision Floating-Point V alue to Double-Precision Floating-Point Value SPDP 3-227 Instruction Set SPRU733 Pipeline Stage E1 E2 Read src2 Written dst_l dst_h Unit in use .S If dst is used as the source for the ADDDP , CMPEQDP , CMPL TDP , CMPGTDP , MPYDP , or SUBDP instruction, the number of delay slots can be reduced by one, becaus[...]

SPINT Convert Single-Precision Floating-Point V alue to Integer 3-228 Instruction Set SPRU733 Convert Single-Precision Floating-Point V alue to Integer SPINT Syntax SPINT (.unit) src2 , dst .unit = .L1 or .L2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 0 0 0 0 0 x 0 0 0 1 0 1 0 1 1 0 s p 3 1 [...]

Convert Single-Precision Floating-Point V alue to Integer SPINT 3-229 Instruction Set SPRU733 Pipeline Stage E1 E2 E3 E4 Read src2 Written dst Unit in use .L Instruction T ype 4-cycle Delay Slots 3 Functional Unit Latency 1 See Also DPINT , INTSP , SPDP , SPTRUNC Example SPINT .L1 A1,A2 Before instruction 4 cycles after instruction A1 4109 9999Ah 8[...]

SPTRUNC Convert Single-Precision Floating-Point V alue to Integer With T runcation 3-230 Instruction Set SPRU733 Convert Single-Precision Floating-Point V alue to Integer With T r uncation SPTRUNC Syntax SPTRUNC (.unit) src2 , dst .unit = .L1 or .L2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2[...]

Convert Single-Precision Floating-Point V alue to Integer With T runcation SPTRUNC 3-231 Instruction Set SPRU733 Pipeline Stage E1 E2 E3 E4 Read src2 Written dst Unit in use .L Instruction T ype 4-cycle Delay Slots 3 Functional Unit Latency 1 See Also DPTRUNC, SPDP , SPINT Example SPTRUNC .L1X B1,A2 Before instruction 4 cycles after instruction B1 [...]

SSHL Shift Left With Saturation 3-232 Instruction Set SPRU733 Shift Left With Saturation SSHL Syntax SSHL (.unit) src2 , src1 , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 1 1 6 5 4 3 2 1 0 creg z dst src2 src1 x op 1 0 0 0 s p 3 1 5 5 5 1 6 1 1 Opcode map field used... For operand type.[...]

Shift Left With Saturation SSHL 3-233 Instruction Set SPRU733 Pipeline Stage E1 Read src1, src2 Written dst Unit in use .S Instruction T ype Single-cycle Delay Slots 0 See Also SHL, SHR Example 1 SSHL .S1 A0,2,A1 Before instruction 1 cycle after instruction 2 cycles after instruction A0 02E3 031Ch A0 02E3 031Ch A0 02E3 031Ch A1 xxxx xxxxh A1 0B8C 0[...]

SSUB Subtract T wo Signed Integers With Saturation 3-234 Instruction Set SPRU733 Subtract T wo Signed Integers With Saturation SSUB Syntax SSUB (.unit) src1 , src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src1 x op 1 1 0 s p 3 1 5 5 5 1 7 1 1 Opcode ma[...]

Subtract T wo Signed Integers With Saturation SSUB 3-235 Instruction Set SPRU733 Pipeline Stage E1 Read src1, src2 Written dst Unit in use .L Instruction T ype Single-cycle Delay Slots 0 See Also SUB Example 1 SSUB .L2 B1,B2,B3 Before instruction 1 cycle after instruction 2 cycles after instruction B1 5A2E 51A3h 1512984995 B1 5A2E 51A3h B1 5A2E 51A[...]

STB Store Byte to Memory With a 5-Bit Unsigned Constant Offset or Register Offset 3-236 Instruction Set SPRU733 Store Byte to Memory With a 5-Bit Unsigned Constant Offset or Register Offset STB Syntax Register Offset STB (.unit) src , *+ baseR[offsetR] Unsigned Constant Offset STB (.unit) src , *+ baseR[ucst5] .unit = .D1 or .D2 Compatibility C62x,[...]

Store Byte to Memory With a 5-Bit Unsigned Constant Offset or Register Offset STB 3-237 Instruction Set SPRU733 Increments and decrements default to 1 and offsets default to zero when no bracketed register or constant is specified. Stores that do no modification to the baseR can use the syntax *R. Square brackets, [ ], indicate that the ucst 5 offs[...]

STB Store Byte to Memory With a 15-Bit Unsigned Constant Offset 3-238 Instruction Set SPRU733 Store Byte to Memory With a 15-Bit U ns i gned Constant O ffset STB Syntax STB (.unit) src , *+B14/B15[ ucst15 ] .unit = .D2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 876 43210 creg z src ucst15 y 01111 s p 3 1 5 15 1 1 1 Descr[...]

Store Byte to Memory With a 15-Bit Unsigned Constant Offset STB 3-239 Instruction Set SPRU733 Pipeline Stage E1 Read B14 / B15 , src Written Unit in use .D2 Instruction T ype Store Delay Slots 0 See Also STH, STW Example STB .D2 B1,*+B14[40] Before instruction 1 cycle after instruction 3 cycles after instruction B1 1234 5678h B1 1234 5678h B1 1234 [...]

STH Store Halfword to Memory With a 5-Bit Unsigned Constant Offset or Register Offset 3-240 Instruction Set SPRU733 Store Halfword to Memory With a 5-Bit Unsigned Constant Offset or Register Offset STH Syntax Register Offset STH (.unit) src , *+ baseR[offsetR] Unsigned Constant Offset STH (.unit) src , *+ baseR[ucst5] .unit = .D1 or .D2 Compatibili[...]

Store Halfword to Memory With a 5-Bit Unsigned Constant Offset or Register Offset STH 3-241 Instruction Set SPRU733 Increments and decrements default to 1 and offsets default to zero when no bracketed register or constant is specified. Stores that do no modification to the baseR can use the syntax *R. Square brackets, [ ], indicate that the ucst 5 [...]

STH Store Halfword to Memory With a 5-Bit Unsigned Constant Offset or Register Offset 3-242 Instruction Set SPRU733 Example 2 STH .D1 A1,*A10 −− [A11] Before instruction 1 cycle after instruction 3 cycles after instruction A1 9A32 2634h A1 9A32 2634h A1 9A32 2634h A10 0000 0100h A10 0000 00F8h A10 0000 00F8h A11 0000 0004h A11 0000 0004h A11 00[...]

Store Halfword to Memory With a 15-Bit Unsigned Constant Offset STH 3-243 Instruction Set SPRU733 Store Halfword to Memory With a 15-Bit U ns i gned Constant O ffset STH Syntax STH (.unit) src , *+B14/B15[ ucst15 ] .unit = .D2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 876 43210 creg z src ucst15 y 10111 s p 3 1 5 15 1 1[...]

STH Store Halfword to Memory With a 15-Bit Unsigned Constant Offset 3-244 Instruction Set SPRU733 Pipeline Stage E1 Read B14 / B15 , src Written Unit in use .D2 Instruction T ype Store Delay Slots 0 See Also STB, STW Pipeline[...]

Store Word to Memory With a 5-Bit Unsigned Constant Offset or Register Offset STW 3-245 Instruction Set SPRU733 Store Word to Memory With a 5-Bit Unsigned Constant Offset or Register Offset STW Syntax Register Offset STW (.unit) src , *+ baseR[offsetR] Unsigned Constant Offset STW (.unit) src , *+ baseR[ucst5] .unit = .D1 or .D2 Compatibility C62x,[...]

STW Store Word to Memory With a 5-Bit Unsigned Constant Offset or Register Offset 3-246 Instruction Set SPRU733 Increments and decrements default to 1 and offsets default to zero when no bracketed register or constant is specified. Stores that do no modification to the baseR can use the syntax *R. Square brackets, [ ], indicate that the ucst 5 offs[...]

Store Word to Memory With a 15-Bit Unsigned Constant Offset STW 3-247 Instruction Set SPRU733 Store Word to Memory With a 15-Bit U ns i gned Constant O ffset STW Syntax STW (.unit) src , *+B14/B15[ ucst15 ] .unit = .D2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 876 43210 creg z src ucst15 y 11111 s p 3 1 5 15 1 1 1 Descr[...]

STW Store Word to Memory With a 15-Bit Unsigned Constant Offset 3-248 Instruction Set SPRU733 Pipeline Stage E1 Read B14 / B15 , src Written Unit in use .D2 Instruction T ype Store Delay Slots 0 See Also STB, STH Pipeline[...]

Subtract T wo Signed Integers Without Saturation SUB 3-249 Instruction Set SPRU733 Subtract T wo Signed Integers Without Saturation SUB Syntax SUB (.unit) src1 , src2 , dst or SUB (.D1 or .D2) src2 , src1 , dst .unit = .L1, .L2, .S1, .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode .L unit 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z[...]

SUB Subtract T wo Signed Integers Without Saturation 3-250 Instruction Set SPRU733 Opcode .S unit 31 29 28 27 23 22 18 17 13 12 1 1 6 5 4 3 2 1 0 creg z dst src2 src1 x op 1 0 0 0 s p 3 1 5 5 5 1 6 1 1 Opcode map field used... For operand type... Unit Opfield src1 src2 dst sint xsint sint .S1, .S2 01 01 1 1 src1 src2 dst scst5 xsint sint .S1, .S2 0[...]

Subtract T wo Signed Integers Without Saturation SUB 3-251 Instruction Set SPRU733 Opcode .D unit 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 76543210 creg z dst src2 src1 op 10000 s p 3 1 5 5 5 6 1 1 Opcode map field used... For operand type... Unit Opfield src2 src1 dst sint sint sint .D1, .D2 01 0001 src2 src1 dst sint ucst 5 sint .D1, .D2 01 001 1 [...]

SUB Subtract T wo Signed Integers Without Saturation 3-252 Instruction Set SPRU733 Instruction T ype Single-cycle Delay Slots 0 See Also ADD, SSUB, SUBC, SUBDP , SUBSP , SUBU, SUB2 Example SUB .L1 A1,A2,A3 Before instruction 1 cycle after instruction A1 0000 325Ah 12810 A1 0000 325Ah A2 FFFF FF12h − 238 A2 FFFF FF12h A3 xxxx xxxxh A3 0000 3348h 1[...]

Subtract Using Byte Addressing Mode SUBAB 3-253 Instruction Set SPRU733 Subtract Using Byte Addressing Mode SUBAB Syntax SUBAB (.unit) src2 , src1 , dst .unit = .D1 or .D2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 76543210 creg z dst src2 src1 op 10000 s p 3 1 5 5 5 6 1 1 Opcode map field used... F[...]

SUBAB Subtract Using Byte Addressing Mode 3-254 Instruction Set SPRU733 Example SUBAB .D1 A5,A0,A5 Before instruction 1 cycle after instruction A0 0000 0004h A0 0000 0004h A5 0000 4000h A5 0000 400Ch AMR 0003 0004h AMR 0003 0004h BK0 = 3 → size = 16 A5 in circular addressing mode using BK0[...]

Subtract Using Halfword Addressing Mode SUBAH 3-255 Instruction Set SPRU733 Subtract Using Halfword Addressing Mode SUBAH Syntax SUBAH (.unit) src2 , src1 , dst .unit = .D1 or .D2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 76543210 creg z dst src2 src1 op 10000 s p 3 1 5 5 5 6 1 1 Opcode map field u[...]

SUBA W Subtract Using Word Addressing Mode 3-256 Instruction Set SPRU733 Subtract Using Word Addressing Mode SUBA W Syntax SUBA W (.unit) src2 , src1 , dst .unit = .D1 or .D2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 76543210 creg z dst src2 src1 op 10000 s p 3 1 5 5 5 6 1 1 Opcode map field used..[...]

Subtract Using Word Addressing Mode SUBA W 3-257 Instruction Set SPRU733 Example SUBAW .D1 A5,2,A3 Before instruction 1 cycle after instruction A3 xxxx xxxxh A3 0000 0108h A5 0000 0100h A5 0000 0100h AMR 0003 0004h AMR 0003 0004h BK0 = 3 → size = 16 A5 in circular addressing mode using BK0[...]

SUBC Subtract Conditionally and Shift − Used for Division 3-258 Instruction Set SPRU733 Subtract Conditionally and Shift—Used for Division SUBC Syntax SUBC (.unit) src1 , src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src1 x 1 0 01011110 s p 3 1 5 5[...]

Subtract Conditionally and Shift − Used for Division SUBC 3-259 Instruction Set SPRU733 Example 1 SUBC .L1 A0,A1,A0 Before instruction 1 cycle after instruction A0 0000 125Ah 4698 A0 0000 024B4h 9396 A1 0000 1F12h 7954 A1 0000 1F12h Example 2 SUBC .L1 A0,A1,A0 Before instruction 1 cycle after instruction A0 0002 1A31h 137777 A0 0000 47E5h 18405 A[...]

SUBDP Subtract T wo Double-Precision Floating-Point V alues 3-260 Instruction Set SPRU733 Subtract T wo Double-Precision Floating-Point V alues SUBDP Syntax SUBDP (.unit) src1 , src2 , dst (C67x and C67x+ CPU) .unit = .L1 or .L2 or SUBDP (.unit) src1 , src2 , dst (C67x+ CPU only) .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 2[...]

Subtract T wo Double-Precision Floating-Point V alues SUBDP 3-261 Instruction Set SPRU733 Notes: 1) This instruction takes the rounding mode from and sets the warning bits in F ADCR, not F AUCR as for other .S unit instructions. 2) The source specific warning bits set in F ADCR are set according to the registers sources in the actual machine instru[...]

SUBDP Subtract T wo Double-Precision Floating-Point V alues 3-262 Instruction Set SPRU733 Pipeline Stage E1 E2 E3 E4 E5 E6 E7 Read src1_l src2_l src1_h src2_h Written dst_l dst_h Unit in use .L or .S .L or .S For the C67x CPU, if dst is used as the source for the ADDDP , CMPEQDP , CMPL TDP , CMPGTDP , MPYDP , or SUBDP instruction, the number of del[...]

Subtract T wo Single-Precision Floating-Point V alues SUBSP 3-263 Instruction Set SPRU733 Subtract T wo Single-Precision Floating-Point V alues SUBSP Syntax SUBSP (.unit) src1 , src2 , dst (C67x and C67x+ CPU) .unit = .L1 or .L2 or SUBSP (.unit) src1 , src2 , dst (C67x+ CPU only) .unit = .S1 or .S2 Compatibility C67x and C67x+ CPU Opcode 31 29 28 2[...]

SUBSP Subtract T wo Single-Precision Floating-Point V alues 3-264 Instruction Set SPRU733 Notes: 1) This instruction takes the rounding mode from and sets the warning bits in F ADCR, not F AUCR as for other .S unit instructions. 2) The source specific warning bits set in F ADCR are set according to the registers sources in the actual machine instru[...]

Subtract T wo Single-Precision Floating-Point V alues SUBSP 3-265 Instruction Set SPRU733 Pipeline Stage E1 E2 E3 E4 Read src1 src2 Written dst Unit in use .L Instruction T ype 4-cycle Delay Slots 3 Functional Unit Latency 1 See Also ADDSP , SUB, SUBDP , SUBU Example SUBSP .L1X A2,B1,A3 Before instruction 4 cycles after instruction A2 4109 999Ah A2[...]

SUBU Subtract T wo Unsigned Integers Without Saturation 3-266 Instruction Set SPRU733 Subtract T wo Unsigned Integers Without Saturation SUBU Syntax SUBU (.unit) src1 , src2 , dst .unit = .L1 or .L2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src1 x op 1 1 0 s p 3 1 5 5 5 1 7 1 1[...]

Subtract T wo Unsigned Integers Without Saturation SUBU 3-267 Instruction Set SPRU733 Example SUBU .L1 A1,A2,A5:A4 Before instruction 1 cycle after instruction A1 0000 325Ah 12810 † A1 0000 325Ah A2 FFFF FF12h 4294967058 † A2 FFFF FF12h A5:A4 xxxx xxxxh xxxx xxxxh A5:A4 0000 00FFh 0000 3348h − 4294954168 ‡ † Unsigned 32-bit integer ‡ Si[...]

SUB2 Subtract T wo 16-Bit Integers on Upper and Lower Register Halves 3-268 Instruction Set SPRU733 Subtract T wo 16-Bit Integers on Upper and Lower Register Halves SUB2 Syntax SUB2 (.unit) src1 , src2 , dst .unit = .S1 or .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 6543210 creg z dst src2 sr[...]

Subtract T wo 16-Bit Integers on Upper and Lower Register Halves SUB2 3-269 Instruction Set SPRU733 Execution if (cond) { (lsb16( src1 ) − lsb16( src2 )) → lsb16( dst ); (msb16( src1 ) − msb16( src2 )) → msb16( dst ); } else nop Pipeline Stage E1 Read src1, src2 Written dst Unit in use .S Instruction T ype Single-cycle Delay Slots 0 See Als[...]

XOR Bitwise Exclusive OR 3-270 Instruction Set SPRU733 Bitwise Exclusive OR XOR Syntax XOR (.unit) src1 , src2 , dst .unit = .L1, .L2, .S1, .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode .L unit 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 1 1 543210 creg z dst src2 src1 x op 110 s p 3 1 5 5 5 1 7 1 1 Opcode map field used... For operand type.[...]

Bitwise Exclusive OR XOR 3-271 Instruction Set SPRU733 Execution if (cond) src1 XOR src2 → dst else nop Pipeline Stage E1 Read src1, src2 Written dst Unit in use .L or .S Instruction T ype Single-cycle Delay Slots 0 See Also AND, OR Example 1 XOR .S1 A3, A4, A5 Before instruction 1 cycle after instruction A3 0721 325Ah A3 0721 325Ah A4 0019 0F12h[...]

ZERO Zero a Register 3-272 Instruction Set SPRU733 Zero a Register ZERO Syntax ZERO (.unit) dst .unit = .L1, .L2, .D1, .D2, .S1, .S2 Compatibility C62x, C64x, C67x, and C67x+ CPU Opcode Opcode map field used... For operand type... Unit Opfield dst sint .L1, .L2 001 01 1 1 dst slong .L1, .L2 01 1 01 1 1 dst sint .D1, .D2 01 0001 dst sint .S1, .S2 01[...]

4-1 Pipeline SPRU733 Pipeline The C67x DSP pipeline provides flexibility to simplify programming and improve performance. T wo factors provide this flexibility:  Control of the pipeline is simplified by eliminating pipeline interlocks.  Increased pipelining eliminates traditional architectural bottlenecks in program fetch, data access, and mu[...]

Pipeline Operation Overview Pipeline 4-2 SPRU733 4.1 Pipeline Operation Overview The pipeline phases are divided into three stages:  Fetch  Decode  Execute Al l instructions in the C67x DSP instruction set flow through the fetch, decode, and execute stages of the pipeline. The fetch stage of the pipeline has four phases for all instruction[...]

Pipeline Operation Overview 4-3 Pipeline SPRU733 Figure 4 − 2. Fetch Phases of the Pipeline PR PW PS PG PW Memory PS PR PG Registers units Functional (a) (b) CPU PR PW PS PG 256 MVK LDW LDW SHL ADD MVK LDW LDW NOP MVK MV B SADD SMPYH SADD SHR SMPY SHR SMPYH LDW LDW LDW LDW MVK B SMPY SMPYH MV MVKLH LDW LDW Fetch SMPYH Decode (c) 4.1.2 Decode The [...]

Pipeline Operation Overview Pipeline 4-4 SPRU733 Figure 4 − 3(a) shows the decode phases in sequential order from left to right. Figure 4 − 3(b ) shows a fetch packet that contains two execute packets as they are processed through the decode stage of the pipeline. The last six instruc- tions of the fetch packet (FP) are parallel and form an exe[...]

Pipeline Operation Overview 4-5 Pipeline SPRU733 4.1.3 Execute The execute portion of the pipeline is subdivided into ten phases (E1 − E10), as compared to the five phases in a fixed-point pipeline. Different types of instructions require different numbers of these phases to complete their execution. These phases of the pipeline play an important[...]

Pipeline Operation Overview Pipeline 4-6 SPRU733 4.1.4 Pipeline Operation Summary Figure 4 − 5 shows all the phases in each stage of the C67x DSP pipeline in sequential order , from left to right. Figure 4 − 5. Pipeline Phases Fetch Execute Decode PG PS PW PR DP DC E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 Figure 4 − 6 shows an example of the pipeline f[...]

Pipeline Operation Overview 4-7 Pipeline SPRU733 T able 4 − 1. Operations Occurring During Pipeline Phases Stage Phase Symbol During This Phase Instruction T ype Completed Program fetch Program address generation PG The address of the fetch packet is determined. Program address sent PS Th e address of the fetch packet is sent to the memory . Prog[...]

Pipeline Operation Overview Pipeline 4-8 SPRU733 T able 4 − 1. Operations Occurring During Pipeline Phases (Continued) Stage Instruction T ype Completed During This Phase Symbol Phase Execute 2 E2 For load instructions, the address is sent to memory . For store instructions, the address and data are sent to memory . † Single-cycle instructions [...]

Pipeline Operation Overview 4-9 Pipeline SPRU733 T able 4 − 1. Operations Occurring During Pipeline Phases (Continued) Stage Instruction T ype Completed During This Phase Symbol Phase Execute 5 E5 For load instructions, data is written into a register file. † For INTDP and MPYSP2DP instructions, the upper 32 bits of the result are written to a [...]

Pipeline Operation Overview Pipeline 4-10 SPRU733 Registers used by the instructions in E1 are shaded in Figure 4 − 7. The multi- plexers used for the input operands to the functional units are also shaded in th e figure. The bold crosspaths are used by the MPY and SUBSP instructions. Figure 4 − 7. Pipeline Phases Block Diagram CMPL TSP DP PR P[...]

Pipeline Operation Overview 4-1 1 Pipeline SPRU733 Many C67x DSP instructions are single-cycle instructions, which means they have only one execution phase (E1). The other instructions require more than one execute phase. The types of instructions, each of which require dif ferent numbers of execute phases, are described in section 4.2. Example 4 ?[...]

Pipeline Execution of Instruction T ypes Pipeline 4-12 SPRU733 4.2 Pipeline Execution of Instruction T ypes The pipeline operation of the C67x DSP instructions can be categorized into fourteen instruction types. Thirteen of these are shown in T able 4 − 2 ( NOP is not included in the table), which is a mapping of operations occurring in each exec[...]

Pipeline Execution of Instruction T ypes 4-13 Pipeline SPRU733 T able 4 − 2. Execution Stage Length Description for Each Instruction T ype (Continued) Instruction T ype Execution phases 2-Cycle DP 4-Cycle INTDP DP Compare E1 Compute the lower results and write to register Read sources and start computation Read sources and start computation Read [...]

Pipeline Execution of Instruction T ypes Pipeline 4-14 SPRU733 T able 4 − 2. Execution Stage Length Description for Each Instruction T ype (Continued) Instruction T ype Execution phases ADDDP/SUBDP MPYI MPYID MPYDP E1 Read lower sources and start computation Read sources and start computation Read sources and start computation Read lower sources [...]

Pipeline Execution of Instruction T ypes 4-15 Pipeline SPRU733 T able 4 − 2. Execution Stage Length Description for Each Instruction T ype (Continued) Instruction T ype Execution phases MPYSPDP MPYSP2DP E1 Read src1 and lower src2 and start computation Read sources and start computation E2 Read src1 and upper src2 and continue computation Continu[...]

Pipeline Execution of Instruction T ypes Pipeline 4-16 SPRU733 4.2.1 Single-Cycle Instructions Single-cycle in structions complete execution during the E1 phase of the pipe- line (see T able 4 − 3). Figure 4 − 8 shows the fetch, decode, and execute phases of the pipeline that single-cycle instructions use. Figure 4 − 9 shows the single-cycle [...]

Pipeline Execution of Instruction T ypes 4-17 Pipeline SPRU733 4.2.2 16 y 16-Bit Multiply Instructions The 16 × 16-bit multiply instructions use both the E1 and E2 phases of the pipeline to complete their operations (see T able 4 − 4). Figure 4 − 10 shows the fetch, decode, and execute phases of the pipeline that the multiply instructions use.[...]

Pipeline Execution of Instruction T ypes Pipeline 4-18 SPRU733 4.2.3 Store Instructions Store instructions require phases E1 through E3 of the pipeline to complete their operations (see T able 4 − 5). Figure 4 − 12 shows the fetch, decode, and execute phases of the pipeline that the store instructions use. Figure 4 − 13 shows the operations o[...]

Pipeline Execution of Instruction T ypes 4-19 Pipeline SPRU733 Figure 4 − 13. Store Instruction Execution Block Diagram Memory E2 E3 Memory controller Register file E1 .D Data E2 Address Functional unit When you perform a load and a store to the same memory location, these rules apply ( i = cycle):  When a load is executed before a store, the [...]

Pipeline Execution of Instruction T ypes Pipeline 4-20 SPRU733 4.2.4 Load Instructions Data loads require five, E1 − E5, of the pipeline execute phases to complete their operations (see T able 4 − 6). Figure 4 − 14 shows the fetch, decode, and execute phases of the pipeline that the load instructions use. Figure 4 − 15 shows the operations [...]

Pipeline Execution of Instruction T ypes 4-21 Pipeline SPRU733 Figure 4 − 15. Load Instruction Execution Block Diagram E5 Address E3 Memory E2 E4 Memory controller Register file E1 .D Functional unit Data In t he E 4 stage of a load, the d ata i s r eceived at the CPU c ore b oundary . F inally , in the E5 phase, the data is loaded into a registe[...]

Pipeline Execution of Instruction T ypes Pipeline 4-22 SPRU733 4.2.5 Branch Instructions Although branch takes one execute phase, there are five delay slots between the execution of the branch and execution of the target code (see T able 4 − 7). Figure 4 − 16 shows the pipeline phases used by the branch instruction and branch target code. The d[...]

Pipeline Execution of Instruction T ypes 4-23 Pipeline SPRU733 Figure 4 − 17. Branch Instruction Execution Block Diagram DP PR PW PS PG 32 32 32 32 32 32 32 32 256 NOP MV SMPYH SMPYH SHR SHR LDW LDW B LDW SUB LDW SMPY SMPYH SMPYH SMPYH SADD SHR SADD SHR STH SADD STH SADD B SUB SMPY SMPYH SADD SADD STH STH MVK B SADD SADD SMPY SMPYH DC LDW LDW E1 [...]

Pipeline Execution of Instruction T ypes Pipeline 4-24 SPRU733 4.2.6 T wo-Cycle DP Instructions T wo-cycle DP instructions use both the E1 and E2 phases of the pipeline to complete their operations (see T able 4 − 8). The following instructions are two-cycle DP instructions:  ABSDP  RCPDP  RSQDP  SPDP The lower and upper 32 bits of th[...]

Pipeline Execution of Instruction T ypes 4-25 Pipeline SPRU733 4.2.7 Four-Cycle Instructions Four-cycle instructions use the E1 through E4 phases of the pipeline to complete their operations (see T able 4 − 9). The following instructions are four-cycle instructions:  ADDSP  DPINT  DPSP  DPTRUNC  INTSP  MPYSP  SPINT  SPTRUN[...]

Pipeline Execution of Instruction T ypes Pipeline 4-26 SPRU733 4.2.8 INTDP Instruction The INTDP instruction uses the E1 through E5 phases of the pipeline to complete its operations (see T able 4 − 1 0). src2 is read on E1, the lower 32 bits of the result are written on E4, and the upper 32 bits of the result are written on E5. The INTDP instruct[...]

Pipeline Execution of Instruction T ypes 4-27 Pipeline SPRU733 4.2.9 DP Compare Instructions The DP compare instructions use the E1 and E2 phases of the pipeline to complete their operations (see T able 4 − 1 1). The lower 32 bits of the sources ar e read on E1, the upper 32 bits of the sources are read on E2, and the results are written on E2. T[...]

Pipeline Execution of Instruction T ypes Pipeline 4-28 SPRU733 4.2.10 ADDDP/SUBDP Instructions Th e ADDDP/SUBDP instructions use the E1 through E7 phases of the pipeline to complete their operations (see T able 4 − 12). The lower 32 bits of the result are written on E6, and the upper 32 bits of the result are written on E7. The ADDDP/SUBDP instru[...]

Pipeline Execution of Instruction T ypes 4-29 Pipeline SPRU733 4.2.1 1 MPYI Instruction The MPYI instruction uses the E1 through E9 phases of the pipeline to complete its operations (see T able 4 − 13). The sources are read on cycles E1 through E4 and the result is written on E9. The MPYI instruction is executed on the .M unit. The functional uni[...]

Pipeline Execution of Instruction T ypes Pipeline 4-30 SPRU733 4.2.12 MPYID Instruction The MPYID instruction uses the E1 through E10 phases of the pipeline to complete its operations (see T able 4 − 14). The sources are read on cycles E1 through E4, the lower 32 bits of the result are written on E9, and the upper 32 bits of the result are writte[...]

Pipeline Execution of Instruction T ypes 4-31 Pipeline SPRU733 4.2.13 MPYDP Instruction The MPYDP instruction uses the E1 through E10 phases of the pipeline to complete its operations (see T able 4 − 15). The lower 32 bits of src1 are read on E1 and E2, and the upper 32 bits of src1 are read on E3 and E4. The lower 32 bits of src2 are read on E1 [...]

Pipeline Execution of Instruction T ypes Pipeline 4-32 SPRU733 4.2.14 MPYSPDP Instruction The MPYSPDP instruction uses the E1 through E7 phases of the pipeline to complete its operations (see T able 4 − 1 6 ). src1 is read on E1 and E2. The lower 32 bits of src2 are read on E1, and the upper 32 bits of src2 are read on E2. The lower 32 bits of th[...]

Functional Unit Constraints 4-33 Pipeline SPRU733 4.2.15 MPYSP2DP Instruction The MPYSP2DP instruction uses the E1 through E5 phases of the pipeline to complete its operations (see T able 4 − 17). src1 and src2 are read on E1. The lower 32 bits of the result are written on E4, and the upper 32 bits of the result are written on E5. The MPYSP2DP in[...]

Functional Unit Constraints Pipeline 4-34 SPRU733 4.3.1 .S-Unit Constraints T able 4 − 18 shows the instruction constraints for single-cycle instructions executing on the .S unit. T able 4 − 18. Single-Cycle .S-Unit Instruction Constraints Instruction Execution Cycle 1 2 Single-cycle RW Instruction T ype Subsequent Same-Unit Instruction Executa[...]

Functional Unit Constraints 4-35 Pipeline SPRU733 T able 4 − 19 shows the instruction constraints for DP compare instructions executing on the .S unit. T able 4 − 19. DP Compare .S-Unit Instruction Constraints Instruction Execution Cycle 1 2 3 DP compare R RW Instruction T ype Subsequent Same-Unit Instruction Executable Single-cycle Xrw  DP [...]

Functional Unit Constraints Pipeline 4-36 SPRU733 T able 4 − 20 shows the instruction constraints for 2-cycle DP instructions exe- cuting on the .S unit. T able 4 − 20. 2-Cycle DP .S-Unit Instruction Constraints Instruction Execution Cycle 1 2 3 2-cycle RW W Instruction T ype Subsequent Same-Unit Instruction Executable Single-cycle Xw  DP co[...]

Functional Unit Constraints 4-37 Pipeline SPRU733 T able 4 − 21 shows the instruction constraints for ADDSP/SUBSP instructions executing on the .S unit. T able 4 − 21. ADDSP/SUBSP .S-Unit Instruction Constraints Instruction Execution Cycle 1 2 3 4 ADDSP/SUBSP R W Instruction T ype Subsequent Same-Unit Instruction Executable Single-cycle  [...]

Functional Unit Constraints Pipeline 4-38 SPRU733 T able 4 − 22 shows the instruction constraints for ADDDP/SUBDP instructions executing on the .S unit. T able 4 − 22. ADDDP/SUBDP .S-Unit Instruction Constraints Instruction Execution Cycle 1 2 3 4 5 6 7 ADDDP/SUBDP R R W W Instruction T ype Subsequent Same-Unit Instruction Executable Single-cyc[...]

Functional Unit Constraints 4-39 Pipeline SPRU733 T able 4 − 23 shows the instruction constraints for branch instructions executing on the .S unit. T able 4 − 23. Branch .S-Unit Instruction Constraints Instruction Execution Cycle 1 2 3 4 5 6 7 8 Branch † R Instruction T ype Subsequent Same-Unit Instruction Executable Single-cycle    [...]

Functional Unit Constraints Pipeline 4-40 SPRU733 4.3.2 .M-Unit Constraints T able 4 − 24 shows the instruction constraints for 16 × 16 multiply instructions executing on the .M unit. T able 4 − 24. 16  16 Multiply .M-Unit Instruction Constraints Instruction Execution Cycle 1 2 3 16 × 16 multiply R W Instruction T ype Subsequent Same-Unit [...]

Functional Unit Constraints 4-41 Pipeline SPRU733 T able 4 − 25 shows the instruction constraints for 4-cycle instructions executing on the .M unit. T able 4 − 25. 4-Cycle .M-Unit Instruction Constraints Instruction Execution Cycle 1 2 3 4 5 4-cycle R W Instruction T ype Subsequent Same-Unit Instruction Executable 16 × 16 multiply  Xw  ?[...]

Functional Unit Constraints Pipeline 4-42 SPRU733 T able 4 − 26 shows the instruction constraints for MPYI instructions executing on the .M unit. T able 4 − 26. MPYI .M-Unit Instruction Constraints Instruction Execution Cycle 1 2 3 4 5 6 7 8 9 10 MPYI R R R R W Instruction T ype Subsequent Same-Unit Instruction Executable 16 × 16 multiply Xr X[...]

Functional Unit Constraints 4-43 Pipeline SPRU733 T able 4 − 27 shows the instruction constraints for MPYID instructions executing on the .M unit. T able 4 − 27. MPYID .M-Unit Instruction Constraints Instruction Execution Cycle 1 2 3 4 5 6 7 8 9 10 1 1 MPYID R R R R W W Instruction T ype Subsequent Same-Unit Instruction Executable 16 × 16 mult[...]

Functional Unit Constraints Pipeline 4-44 SPRU733 T able 4 − 28 shows the instruction constraints for MPYDP instructions executing on the .M unit. T able 4 − 28. MPYDP .M-Unit Instruction Constraints Instruction Execution Cycle 1 2 3 4 5 6 7 8 9 10 1 1 MPYDP R R R R W W Instruction T ype Subsequent Same-Unit Instruction Executable 16 × 16 mult[...]

Functional Unit Constraints 4-45 Pipeline SPRU733 T able 4 − 29 shows the instruction constraints for MPYSP instructions executing on the .M unit. T able 4 − 29. MPYSP .M-Unit Instruction Constraints Instruction Execution Cycle 1 2 3 4 MPYSP R W Instruction T ype Subsequent Same-Unit Instruction Executable MPYSPDP  MPYSP2DP  I[...]

Functional Unit Constraints Pipeline 4-46 SPRU733 T able 4 − 30 shows the instruction constraints for MPYSPDP instructions executing on the .M unit. T able 4 − 30. MPYSPDP .M-Unit Instruction Constraints Instruction Execution Cycle 1 2 3 4 5 6 7 MPYSPDP R R W W Instruction T ype Subsequent Same-Unit Instruction Executable 16 × 16 multiply Xr ?[...]

Functional Unit Constraints 4-47 Pipeline SPRU733 T able 4 − 31 shows the instruction constraints for MPYSP2DP instructions executing on the .M unit. T able 4 − 31. MPYSP2DP .M-Unit Instruction Constraints Instruction Execution Cycle 1 2 3 4 5 MPYSP2DP R R W W Instruction T ype Subsequent Same-Unit Instruction Executable 16 × 16 multiply  X[...]

Functional Unit Constraints Pipeline 4-48 SPRU733 4.3.3 .L-Unit Constraints T able 4 − 32 shows the instruction constraints for single-cycle instructions executing on the .L unit. T able 4 − 32. Single-Cycle .L-Unit Instruction Constraints Instruction Execution Cycle 1 2 Single-cycle RW Instruction T ype Subsequent Same-Unit Instruction Executa[...]

Functional Unit Constraints 4-49 Pipeline SPRU733 T able 4 − 33 shows the instruction constraints for 4-cycle instructions executing on the .L unit. T able 4 − 33. 4-Cycle .L-Unit Instruction Constraints Instruction Execution Cycle 1 2 3 4 5 4-cycle R W Instruction T ype Subsequent Same-Unit Instruction Executable Single-cycle   Xw  4-[...]

Functional Unit Constraints Pipeline 4-50 SPRU733 T able 4 − 34 shows the instruction constraints for INTDP instructions executing on the .L unit. T able 4 − 34. INTDP .L-Unit Instruction Constraints Instruction Execution Cycle 1 2 3 4 5 6 INTDP R W W Instruction T ype Subsequent Same-Unit Instruction Executable Single-cycle   Xw Xw  4[...]

Functional Unit Constraints 4-51 Pipeline SPRU733 T able 4 − 35 shows the instruction constraints for ADDDP/SUBDP instructions executing on the .L unit. T able 4 − 35. ADDDP/SUBDP .L-Unit Instruction Constraints Instruction Execution Cycle 1 2 3 4 5 6 7 8 ADDDP/SUBDP R R W W Instruction T ype Subsequent Same-Unit Instruction Executable Single-c[...]

Functional Unit Constraints Pipeline 4-52 SPRU733 4.3.4 .D-Unit Instruction Constraints T able 4 − 36 shows the instruction constraints for load instructions executing on the .D unit. T able 4 − 36. Load .D-Unit Instruction Constraints Instruction Execution Cycle 1 2 3 4 5 6 Load R W W Instruction T ype Subsequent Same-Unit Instruction Executab[...]

Functional Unit Constraints 4-53 Pipeline SPRU733 T able 4 − 37 shows the instruction constraints for store instructions executing on the .D unit. T able 4 − 37. Store .D-Unit Instruction Constraints Instruction Execution Cycle 1 2 3 4 Store RW Instruction T ype Subsequent Same-Unit Instruction Executable Single-cycle    Load [...]

Functional Unit Constraints Pipeline 4-54 SPRU733 T able 4 − 38 shows the instruction constraints for single-cycle instructions executing on the .D unit. T able 4 − 38. Single-Cycle .D-Unit Instruction Constraints Instruction Execution Cycle 1 2 Single-cycle RW Instruction T ype Subsequent Same-Unit Instruction Executable Single-cycle  Load [...]

Functional Unit Constraints 4-55 Pipeline SPRU733 T able 4 − 39 shows the instruction constraints for LDDW instructions executing on the .D unit. T able 4 − 39. LDDW Instruction With Long Write Instruction Constraints Instruction Execution Cycle 1 2 3 4 5 6 LDDW RW W Instruction T ype Subsequent Same-Unit Instruction Executable Instruction with[...]

Performance Considerations Pipeline 4-56 SPRU733 4.4 Performance Considerations Th e C67x DSP pipeline is most effective when it is kept as full as the algorithms in the program allow it to be. It is useful to consider some situations that can affect pipeline performance. A fetch packet (FP) is a grouping of eight instructions. Each FP can be split[...]

Performance Considerations 4-57 Pipeline SPRU733 Figure 4 − 28 . Pipeline Operation: Fetch Packets With Different Numbers of Execute Packets Clock cycle Fetch packet (FP) Execute packet (EP) 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 17 nk PG PS PW PR DP DC E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 n k+1 DP DC E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 n k+2 DP DC E1 E2 E[...]

Performance Considerations Pipeline 4-58 SPRU733 4.4.2 Multicycle NOPs The NOP instruction has an optional operand, count , that allows you to issue a single instruction for multicycle NOP s. A NOP 2, for example, fills in extra delay slots for the instructions in its execute packet and for all previous execute packets. If a NOP 2 is in parallel wi[...]

Performance Considerations 4-59 Pipeline SPRU733 Figure 4 − 30 shows how a multicycle NOP can be af fected by a branch. If the delay slots of a branch finish while a multicycle NOP is still dispatching NOP s into the pipeline, the branch overrides the multicycle NOP and the branch target begins execution five delay slots after the branch was issu[...]

Performance Considerations Pipeline 4-60 SPRU733 4.4.3 Memory Considerations The C67x DSP has a memory configuration with program memory in one physical space and data memory in another physical space. Data loads and program fetches have the same operation in the pipeline, they just use differ- ent phases to complete their operations. With both dat[...]

Performance Considerations 4-61 Pipeline SPRU733 Depending on the type of memory and the time required to complete an access, the pipeline may stall to ensure proper coordination of data and instructions. This is discussed in section 4.4.3.1. In the instance where multiple accesses are made to a single ported memory , th e pipeline will stall to al[...]

Performance Considerations Pipeline 4-62 SPRU733 4.4.3.2 Memory Bank Hits Most C67x devices use an interleaved memory bank scheme, as shown in Figure 4 − 33. Each number in the diagram represents a byte address. A load byte ( LDB ) instruction from address 0 loads byte 0 in bank 0. A load halfword ( LDH ) instruction from address 0 loads the half[...]

Performance Considerations 4-63 Pipeline SPRU733 T able 4 − 41. Loads in Pipeline from Example 4 − 2 i i + 1 i + 2 i + 3 i + 4 i + 5 LDW .D1 Bank 0 E1 E2 E3 − E4 E5 LDW .D2 Bank 0 E1 E2 − E3 E4 E5 For devices that have more than one memory space (see Figure 4 − 34), an access to bank 0 in one space does not interfere with an access to ban[...]

5-1 Interrupts SPRU733 9 Interrupts This chapter describes CPU interrupts, including reset and the nonmaskable interrupt ( NMI). It details the related CPU control registers and their functions in controlling interrupts. It also describes interrupt processing, the method the CPU uses to detect automatically the presence of interrupts and divert pro[...]

Overview Interrupts 5-2 SPRU733 5.1 Overview T ypically , DSPs work in an environment that contains multiple external asynchronous events. These events require tasks to be performed by the DSP when they occur . An interrupt is an event that stops the current process in the CPU so that the CPU can attend to the task needing completion because of the[...]

Overview 5-3 Interrupts SPRU733 T able 5 − 1. Interrupt Priorities Priority Interrupt Name Interrupt T ype Highest Reset Reset NMI Nonmaskable INT4 Maskable INT5 Maskable INT6 Maskable INT7 Maskable INT8 Maskable INT9 Maskable INT10 Maskable INT1 1 Maskable INT12 Maskable INT13 Maskable INT14 Maskable Lowest INT15 Maskable 5.1.1.1 Reset (RESET ) [...]

Overview Interrupts 5-4 SPRU733 5.1.1.2 Nonmaskable Interrupt (NMI) NMI is the second-highest priority interrupt and is generally used to alert the CPU of a serious hardware problem such as imminent power failure. For NMI processing to occur , the nonmaskable interrupt enable (NMIE) bit in th e interrupt enable register must be set to 1. If NMIE is[...]

Overview 5-5 Interrupts SPRU733 5.1.1.4 Interrupt Acknowledgment (IACK) and Interrupt Number (INUM n ) The IACK and INUM n signals alert hardware external to the C6000 that an interrupt has occurred and is being processed. The IACK signal indicates that the CPU has begun processing an interrupt. The INUM n signal (INUM3 − INUM0) indicates the num[...]

Overview Interrupts 5-6 SPRU733 5.1.2 Interrupt Service T able (IST) When the CPU begins processing an interrupt, it references the interrupt service table (IST). The IST is a table of fetch packets that contain code for servicing the interrupts. The IST consists of 16 consecutive fetch packets. Each interrupt service fetch packet (ISFP) contains e[...]

Overview 5-7 Interrupts SPRU733 5.1.2.1 Interrupt Service Fetch Packet (ISFP) An ISFP is a fetch packet used to service an interrupt. Figure 5 − 2 shows an ISFP that contains an interrupt service routine small enough to fit in a single fetch packet (FP). T o branch back to the main program, the FP contains a branch to the interrupt return pointer[...]

Overview Interrupts 5-8 SPRU733 If the interrupt service routine for an interrupt is too large to fit in a single fetch packet, a branch to the location of additional interrupt service routine code is required. Figure 5 − 3 shows that the interrupt service routine for INT4 was too large for a single fetch packet, and a branch to memory location 1[...]

Overview 5-9 Interrupts SPRU733 5.1.2.2 Interrupt Service T able Pointer (ISTP) Th e reset fetch packet must be located at address 0, but the rest of the IST can be at any program memory location that is on a 256-word boundary . The location of the IST is determined by the interrupt service table base (ISTB) field of the interrupt service table poi[...]

Overview Interrupts 5-10 SPRU733 5.1.3 Summary of Interrupt Control Registers T able 5 − 2 lists the interrupt control registers on the C67x CPU. T able 5 − 2. Interrupt Control Registers Acronym Register Name Description Page CSR Control status register Allows you to globally set or disable interrupts 2-13 ICR Interrupt clear register Allows y[...]

Globally Enabling and Disabling Interrupts 5-1 1 Interrupts SPRU733 5.2 Globally Enabling and Disabling Interrupts The control status register (CSR) contains two fields that control interrupts: GIE and PGIE, as shown in Figure 2 − 4 (page 2-13) and described in T able 2 − 7 (page 2-14). The global interrupt enable (GIE) allows you to enable or [...]

Globally Enabling and Disabling Interrupts Interrupts 5-12 SPRU733 Example 5 − 2. Code Sequence to Disable Maskable Interrupts Globally MVC CSR,B0 ; get CSR AND -2,B0,B0 ; get ready to clear GIE MVC B0,CSR ; clear GIE Example 5 − 3. Code Sequence to Enable Maskable Interrupts Globally MVC CSR,B0 ; get CSR OR 1,B0,B0 ; get ready to set GIE MVC B[...]

Individual Interrupt Control 5-13 Interrupts SPRU733 5.3 Individual Interrupt Control Servicing interrupts effectively requires individual control of all three types of interrupts: reset, nonmaskable, and maskable. Enabling and disabling individ- ual interrupts is done with the interrupt enable register (IER). The status of pending interrupts is st[...]

Individual Interrupt Control Interrupts 5-14 SPRU733 5.3.2 Status of Interrupts The interrupt flag register (IFR) contains the status of INT4 − INT15 and NMI. Each interrupt’s corresponding bit in IFR is set to 1 when that interrupt occurs; otherwise, the bits have a value of 0. If you want to check the status of inter- rupts, use the MVC instr[...]

Individual Interrupt Control 5-15 Interrupts SPRU733 5.3.4 Returning From Interrupt Servicing After RESET goes high, the control registers are brought to a known value and program execution begins at address 0h. After nonmaskable and maskable interrupt servicing, use a branch to the corresponding return pointer register to continue the previous pro[...]

Interrupt Detection and Processing Interrupts 5-16 SPRU733 5.4 Interrupt Detection and Processing When an interrupt occurs, it sets a flag in the interrupt flag register (IFR). Depending on certain conditions, the interrupt may or may not be processed. This section discusses the mechanics of setting the flag bit, the conditions for processing an in[...]

Interrupt Detection and Processing 5-17 Interrupts SPRU733 Any pending interrupt will be taken as soon as pending branches are completed. Figure 5 − 4. Nonreset Interrupt Detection and Processing: Pipeline Operation 21 22 20 19 17 18 16 15 14 0 0 0 0 0 0 0 0 0 E10 22 21 20 19 ‡ 18 17 16 15 E1 DC 14 12 11 10 89 7 6 † 4 5 3 0 0 0 0 0 E10 E10 E9[...]

Interrupt Detection and Processing Interrupts 5-18 SPRU733 5.4.3 Actions T aken During Nonreset Interrupt Processing During CPU cycles 6 through 14 of Figure 5 − 4, the following interrupt proces- sing actions occur:  Processing of subsequent nonreset interrupts is disabled.  For all interrupts except NMI, the PGIE bit is set to the value o[...]

Interrupt Detection and Processing 5-19 Interrupts SPRU733 5.4.4 Setting the RESET Interrupt Flag RESET must be held low for a minimum of 10 clock cycles. Four clock cycles after RESET goes high, processing of the reset vector begins. The flag for RESET (IF0) in the IFR is set by the low-to-high transition of the RESET signal on the CPU boundary . [...]

Interrupt Detection and Processing Interrupts 5-20 SPRU733 5.4.5 Actions T aken During RESET Interrupt Processing A low signal on the RESET pin is the only requirement to process a reset. Once RESET makes a high-to-low transition, the pipeline is flushed and CPU regis- ters are returned to their reset values. GIE, NMIE, and the ISTB in the ISTP are[...]

Performance Considerations 5-21 Interrupts SPRU733 5.5 Performance Considerations The interaction of the C6000 CPU and sources of interrupts present perfor- mance issues for you to consider when you are developing your code. 5.5.1 General Performance  Overhead . Overhead for all CPU interrupts is 9 cycles. Y ou can see this in Figure 5 − 4, wh[...]

Programming Considerations Interrupts 5-22 SPRU733 5.6 Programming Considerations Th e interaction of the C6000 CPUs and sources of interrupts present program- ming issues for you to consider when you are developing your code. 5.6.1 Single Assignment Programming Using the same register to store different variables (called here: multiple assignment)[...]

Programming Considerations 5-23 Interrupts SPRU733 Example 5 − 1 1. Code Using Single Assignment LDW .D1 *A0,A6 ADD .L1 A1,A2,A3 NOP 3 MPY .M1 A6,A4,A5 ; uses A6 5.6.2 Nested Interrupts Generally , when the CPU enters an interrupt service routine, interrupts are disabled. However , when the interrupt service routine is for one of the maskable int[...]

Programming Considerations Interrupts 5-24 SPRU733 Example 5 − 13 shows a C-based interrupt handler that allows nested interrupts. The steps are similar , although the compiler takes care of allocating th e stack and saving CPU registers. For more information on using C to access control registers and write interrupt handlers, see the TMS320C6000[...]

Programming Considerations 5-25 Interrupts SPRU733 Example 5 − 13. C Interrupt Service Routine That Allows Nested Interrupts /* c6x.h contains declarations of the C6x control registers */ #include <c6x.h> interrupt void isr(void) { unsigned old_csr; unsigned old_irp; old_irp = IRP ;/* Save IRP */ old_csr = CSR ;/* Save CSR (and thus PGIE) *[...]

Programming Considerations Interrupts 5-26 SPRU733 5.6.4 T raps A trap behaves like an interrupt, but is created and controlled with software. The trap condition can be stored in any one of the conditional registers: A1, A2, B0, B1, or B2. If the trap condition is valid, a branch to the trap handler routine processes the trap and the return. Exampl[...]

A-1 Instruction Compatibility SPRU733 Appendix A Instruction Compatibility The C62x, C64x, and C67x DSPs share an instruction set. All of the instruc- tions valid for the C62x DSP are also valid for the C67x and C67x+ DSPs. The C67x DSP adds specific instructions for 32-bit integer multiply , doubleword load, and floating-point operations. T able A[...]

Instruction Compatibility Instruction Compatibility A-2 SPRU733 T able A − 1. Instruction Compatibility Between C62x, C64x, C67x, and C67x+ DSPs (Continued) Instruction C67x+ DSP C67x DSP C64x DSP C62x DSP Page B displacement 3-69     B register 3-71  B IRP 3-73  B NRP 3-75  CLR 3-77  CM[...]

Instruction Compatibility A-3 Instruction Compatibility SPRU733 T able A − 1. Instruction Compatibility Between C62x, C64x, C67x, and C67x+ DSPs (Continued) Instruction C67x+ DSP C67x DSP C64x DSP C62x DSP Page INTSP 3-121   INTSPU 3-122  LDB memory 3-123  LDB memory (15-bit offset) 3-126  LDBU memory 3-123 [...]

Instruction Compatibility Instruction Compatibility A-4 SPRU733 T able A − 1. Instruction Compatibility Between C62x, C64x, C67x, and C67x+ DSPs (Continued) Instruction C67x+ DSP C67x DSP C64x DSP C62x DSP Page MPYI 3-157   MPYID 3-159  MPYLH 3-161  MPYLHU 3-163  MPYLSHU 3-164  MPYLUHS 3-165 ?[...]

Instruction Compatibility A-5 Instruction Compatibility SPRU733 T able A − 1. Instruction Compatibility Between C62x, C64x, C67x, and C67x+ DSPs (Continued) Instruction C67x+ DSP C67x DSP C64x DSP C62x DSP Page RSQRDP 3-201   RSQRSP 3-203  SADD 3-205  SA T 3-208  SET 3-210  SHL 3-213  SH[...]

Instruction Compatibility Instruction Compatibility A-6 SPRU733 T able A − 1. Instruction Compatibility Between C62x, C64x, C67x, and C67x+ DSPs (Continued) Instruction C67x+ DSP C67x DSP C64x DSP C62x DSP Page SUB 3-249     SUBAB 3-253  SUBAH 3-255  SUBA W 3-256  SUBC 3-258  SUBDP 3-260[...]

B-1 Mapping Between Instruction and Functional Unit SPRU733 Appendix A Mapping Between Instruction and Functional Unit T able B − 1 lists the instructions that execute on each functional unit. T able B − 1. Functional Unit to Instruction Mapping Functional Unit Instruction .L Unit .M Unit .S Unit .D Unit ABS  ABSDP  ABSSP  ADD  ?[...]

Mapping Between Instruction and Functional Unit Mapping Between Instruction and Functional Unit B-2 SPRU733 T able B − 1. Functional Unit to Instruction Mapping (Continued) Instruction Functional Unit Instruction .D Unit .S Unit .M Unit .L Unit B displacement  B register  † B IRP  † B NRP  † CLR  CMPEQ  CMPEQDP  CMPEQSP[...]

Mapping Between Instruction and Functional Unit B-3 Mapping Between Instruction and Functional Unit SPRU733 T able B − 1. Functional Unit to Instruction Mapping (Continued) Instruction Functional Unit Instruction .D Unit .S Unit .M Unit .L Unit INTDP  INTDPU  INTSP  INTSPU  LDB memory  LDB memory (15-bit offset)  ‡ LDBU memory[...]

Mapping Between Instruction and Functional Unit Mapping Between Instruction and Functional Unit B-4 SPRU733 T able B − 1. Functional Unit to Instruction Mapping (Continued) Instruction Functional Unit Instruction .D Unit .S Unit .M Unit .L Unit MPYHU  MPYHULS  MPYHUS  MPYI  MPYID  MPYLH  MPYLHU  MPYLSHU  MPYLUHS  MPYSP [...]

Mapping Between Instruction and Functional Unit B-5 Mapping Between Instruction and Functional Unit SPRU733 T able B − 1. Functional Unit to Instruction Mapping (Continued) Instruction Functional Unit Instruction .D Unit .S Unit .M Unit .L Unit NORM  NOT  OR  RCPDP  RCPSP  RSQRDP  RSQRSP  SADD  SA T  SET  SHL ?[...]

Mapping Between Instruction and Functional Unit Mapping Between Instruction and Functional Unit B-6 SPRU733 T able B − 1. Functional Unit to Instruction Mapping (Continued) Instruction Functional Unit Instruction .D Unit .S Unit .M Unit .L Unit STB memory (15-bit offset)  ‡ STH memory  STH memory (15-bit offset)  ‡ STW memory  STW[...]

C-1 .D Unit Instructions and Opcode Maps SPRU733 Appendix A .D Unit Instructions and Opcode Maps This appendix lists the instructions that execute in the .D functional unit and illustrates the opcode maps for these instructions. T opic Page C.1 Instructions Executing in the .D Functional Unit C-2 . . . . . . . . . . . . . . . . . C.2 Opcode Map Sym[...]

Instructions Executing in the .D Functional Unit .D Unit Instructions and Opcode Maps C-2 SPRU733 C.1 Instructions Executing in the .D Functional Unit T able C − 1 lists the instructions that execute in the .D functional unit. T able C − 1. Instructions Executing in the .D Functional Unit Instruction Instruction ADD LDW memory ADDAB LDW memory [...]

Opcode Map Symbols and Meanings C-3 .D Unit Instructions and Opcode Maps SPRU733 C.2 Opcode Map Symbols and Meanings T able C − 2 lists the symbols and meanings used in the opcode maps. T able C − 2. .D Unit Opcode Map Symbol Definitions Symbol Meaning baseR base address register creg 3-bit field specifying a conditional register dst destinatio[...]

Opcode Map Symbols and Meanings .D Unit Instructions and Opcode Maps C-4 SPRU733 T able C − 3. Address Generator Options for Load/Store mode Field Syntax Modification Performed 0 0 0 0 * − R[ ucst5 ] Negative offset 0 0 0 1 *+R[ ucst5 ] Positive offset 010 0 * − R[ offsetR ] Negative of fset 0 1 0 1 *+R[ offsetR ] Positive offset 100 0 * − [...]

32-Bit Opcode Maps C-5 .D Unit Instructions and Opcode Maps SPRU733 C.3 32-Bit Opcode Maps The C67x CPU 32-bit opcodes used in the .D unit are mapped in Figure C − 1 through Figure C − 4. Figure C − 1. 1 or 2 Sources Instruction Format 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 3 1 2 76543210 creg z dst src2 src1 op 10000 s p 3 1 5 5 5 6 1 1 Figure C [...]

D-1 .L Unit Instructions and Opcode Maps SPRU733 Appendix A .L Unit Instructions and Opcode Maps This appendix lists the instructions that execute in the .L functional unit and illustrates the opcode maps for these instructions. T opic Page D.1 Instructions Executing in the .L Functional Unit D-2 . . . . . . . . . . . . . . . . . D.2 Opcode Map Sym[...]

Instructions Executing in the .L Functional Unit .L Unit Instructions and Opcode Maps D-2 SPRU733 D.1 Instructions Executing in the .L Functional Unit T able D − 1 lists the instructions that execute in the .L functional unit. T able D − 1. Instructions Executing in the .L Functional Unit Instruction Instruction ABS LMBD ADD MV ADDDP NEG ADDSP [...]

Opcode Map Symbols and Meanings D-3 .L Unit Instructions and Opcode Maps SPRU733 D.2 Opcode Map Symbols and Meanings T able D − 2 lists the symbols and meanings used in the opcode maps. T able D − 2. .L Unit Opcode Map Symbol Definitions Symbol Meaning creg 3-bit field specifying a conditional register dst destination op opfield; field within o[...]

32-Bit Opcode Maps .L Unit Instructions and Opcode Maps D-4 SPRU733 D.3 32-Bit Opcode Maps The C67x CPU 32-bit opcodes used in the .L unit are mapped in Figure D − 1 through Figure D − 3. Figure D − 1. 1 or 2 Sources Instruction Format 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src1 x op 1 1 0 s p 3 1 5 5 5 1 7 1 1 Figure D [...]

E-1 .M Unit Instructions and Opcode Maps SPRU733 Appendix A .M Unit Instructions and Opcode Maps This appendix lists the instructions that execute in the .M functional unit and illustrates the opcode maps for these instructions. T opic Page E.1 Instructions Executing in the .M Functional Unit E-2 . . . . . . . . . . . . . . . . . E.2 Opcode Map Sym[...]

Instructions Executing in the .M Functional Unit .M Unit Instructions and Opcode Maps E-2 SPRU733 E.1 Instructions Executing in the .M Functional Unit T able E − 1 lists the instructions that execute in the .M functional unit. T able E − 1. Instructions Executing in the .M Functional Unit Instruction Instruction MPY MPYLHU MPYDP MPYLSHU MPYH MP[...]

Opcode Map Symbols and Meanings E-3 .M Unit Instructions and Opcode Maps SPRU733 E.2 Opcode Map Symbols and Meanings T able E − 2 lists the symbols and meanings used in the opcode maps. T able E − 2. .M Unit Opcode Map Symbol Definitions Symbol Meaning creg 3-bit field specifying a conditional register dst destination op opfield; field within o[...]

32-Bit Opcode Maps .M Unit Instructions and Opcode Maps E-4 SPRU733 E.3 32-Bit Opcode Maps The C67x CPU 32-bit opcodes used in the .M unit are mapped in Figure E − 1 through Figure E − 3. Figure E − 1. Extended M-Unit with Compound Operations 31 29 28 27 23 22 18 17 13 12 1 1 10 6 5 4 3 2 1 0 creg z dst src2 src1 x 0 op 1 1 0 0 s p 3 1 5 5 5 [...]

F-1 .S Unit Instructions and Opcode Maps SPRU733 Appendix A .S Unit Instructions and Opcode Maps This appendix lists the instructions that execute in the .S functional unit and illustrates the opcode maps for these instructions. T opic Page F .1 Instructions Executing in the .S Functional Unit F-2 . . . . . . . . . . . . . . . . . F .2 Opcode Map S[...]

Instructions Executing in the .S Functional Unit .S Unit Instructions and Opcode Maps F-2 SPRU733 F .1 Instructions Executing in the .S Functional Unit T able F − 1 lists the instructions that execute in the .S functional unit. T able F − 1. Instructions Executing in the .S Functional Unit Instruction Instruction ABSDP MVKH ABSSP MVKL ADD MVKLH[...]

Opcode Map Symbols and Meanings F-3 .S Unit Instructions and Opcode Maps SPRU733 F .2 Opcode Map Symbols and Meanings T able F − 2 lists the symbols and meanings used in the opcode maps. T able F − 2. .S Unit Opcode Map Symbol Definitions Symbol Meaning creg 3-bit field specifying a conditional register csta constant a cstb constant b cstn n-bi[...]

32-Bit Opcode Maps .S Unit Instructions and Opcode Maps F-4 SPRU733 F .3 32-Bit Opcode Maps The C67x CPU 32-bit opcodes used in the .S unit are mapped in Figure F − 1 through Figure F − 11 . Figure F − 1. 1 or 2 Sources Instruction Format 31 29 28 27 23 22 18 17 13 12 1 1 6 5 4 3 2 1 0 creg z dst src2 src1 x op 1 0 0 0 s p 3 1 5 5 5 1 6 1 1 F[...]

32-Bit Opcode Maps F-5 .S Unit Instructions and Opcode Maps SPRU733 Figure F − 6. Call Unconditional, Immediate with Implied NOP 5 Instruction Format 31 29 28 27 76543210 0 0 0 z cst21 00100 s p 1 21 1 1 Figure F − 7. Branch with NOP Constant Instruction Format 31 29 28 27 16 15 13 12 1 1 6 5 4 3 2 1 0 creg z src2 src1 0 0 0 0 1 0 0 1 0 0 0 s p[...]

G-1 No Unit Specified Ins tructions and Opc ode Maps SPRU733 Appendix A No Unit Specified Instructions and Opcode Map s This appendix lists the instructions that execute with no unit specified and illustrates the opcode maps for these instructions. For a list of the instructions that execute in the .D functional unit, see Appendix C. For a list of [...]

Instructions Executing With No Unit Specified No Unit Specified Instructions and Opc ode Maps G-2 SPRU733 G.1 Instructions Executing With No Unit Specified T able G − 1 lists the instructions that execute with no unit specified. T able G − 1. Instructions Executing With No Unit Specified Instruction IDLE NOP G.2 Opcode Map Symbols and Meanings [...]

32-Bit Opcode Maps G-3 No Unit Specified Instructions and Opc ode Maps SPRU733 G.3 32-Bit Opcode Maps The C67x CPU 32-bit opcodes used in the no unit instructions are mapped in Figure G − 1 through Figure G − 3. Figure G − 1. Loop Buffer Instruction Format 3 1 2 9 2 8 2 7 2 3 2 2 1 8 1 7 1 6 1 3 1 2 1 1 1 0 9876543210 creg z cstb csta 1 op 0 [...]

Index Index-1 SPRU733 Index 1X and 2X paths 2-6 2-cycle DP instructions, .S-unit instruction constraints 4-36 4-cycle instructions .L-unit instruction constraints 4-49 .M-unit instruction constraints 4-41 A A4 MODE bits 2-10 A5 MODE bits 2-10 A6 MODE bits 2-10 A7 MODE bits 2-10 ABS instruction 3-38 ABSDP instruction 3-40 absolute value floating-poi[...]

Index Index-2 SPRU733 B B instruction using a displacement 3-69 using a register 3-71 B IRP instruction 3-73 B NRP instruction 3-75 B4 MODE bits 2-10 B5 MODE bits 2-10 B6 MODE bits 2-10 B7 MODE bits 2-10 bit field clear (CLR) 3-77 extract and sign-extend a bit field (EXT) 3-1 10 extract and zero-extend a bit field (EXTU) 3-1 13 set (SET) 3-210 bitw[...]

Index Index-3 SPRU733 compare for equality floating-point double-precision values (CMPEQDP) 3-82 single-precision values (CMPEQSP) 3-84 signed integers (CMPEQ) 3-80 compare for greater than floating-point double-precision values (CMPGTDP) 3-89 single-precision values (CMPGTSP) 3-91 signed integers (CMPGT) 3-86 unsigned integers (CMPGTU) 3-93 compar[...]

Index Index-4 SPRU733 cross paths 2-6 CSR 2-13 D DA1 and DA2 2-7 data address paths 2-7 DC pipeline phase 4-3 DCC bits 2-13 decoding instructions 4-3 delay slots 3-14 DEN1 bit in F ADCR 2-24 in F AUCR 2-27 in FMCR 2-31 DEN2 bit in F ADCR 2-24 in F AUCR 2-27 in FMCR 2-31 detection and processing, interrupts 5-16 disabling an individual interrupt 5-1[...]

Index Index-5 SPRU733 IEn bit 2-17 IER 2-17 IFn bit 2-18 IFR 2-18 INEX bit in F ADCR 2-24 in F AUCR 2-27 in FMCR 2-31 INFO bit in F ADCR 2-24 in F AUCR 2-27 in FMCR 2-31 instruction compatibility 3-34, A-1 instruction descriptions 3-34 instruction execution .D unit C-2 .L unit D-2 .M unit E-2 .S unit F-2 no unit instructions G-2 instruction operati[...]

Index Index-6 SPRU733 INTSPU instruction 3-122 INV AL bit in F ADCR 2-24 in F AUCR 2-27 in FMCR 2-31 IRP 2-19 ISn bit 2-20 ISR 2-20 ISTB bits 2-21 ISTP 2-21 L latency 3-14 LDB instruction 5-bit unsigned constant offset or register offset 3-123 15-bit unsigned constant offset 3-126 LDBU instruction 5-bit unsigned constant offset or register offset 3[...]

Index Index-7 SPRU733 move 16-bit constant into upper bits of register (MVKH and MVKLH) 3-185 between control file and register file (MVC) 3-180 from register to register (MV) 3-178 signed constant into register and sign extend (MVK) 3-183 signed constant into register and sign extend (MVKL) 3-187 MPY instruction 3-143 MPYDP instruction 3-145 .M-un[...]

Index Index-8 SPRU733 multiply (continued) unsigned by unsigned unsigned 16 LSB by unsigned 16 LSB (MPYU) 3-174 unsigned 16 LSB by unsigned 16 MSB (MPYLHU) 3-163 unsigned 16 MSB by unsigned 16 LSB (MPYHLU) 3-151 unsigned 16 MSB by unsigned 16 MSB (MPYHU) 3-154 multiply instructions .M-unit instruction constraints 4-40 block diagram 4-17 pipeline op[...]

Index Index-9 SPRU733 PGIE bit 2-13 pipeline decode stage 4-3 execute stage 4-5 execution 4-12 factors that provide programming flexibility 4-1 fetch stage 4-2 functional unit constraints 4-33 overview 4-2 performance considerations 4-56 phases 4-2 stages 4-2 summary 4-6 pipeline execution 4-12 pipeline operation ADDDP instruction 4-28 branch instr[...]

Index Index-10 SPRU733 returning from interrupt servicing 5-15 REVISION ID bits 2-13 RMODE bits in F ADCR 2-24 in FMCR 2-31 RSQRDP instruction 3-201 RSQRSP instruction 3-203 S SADD instruction 3-205 SA T bit 2-13 SA T instruction 3-208 saturate a 40-bit integer to a 32-bit integer (SA T) 3-208 serial fetch packets 3-17 set a bit field (SET) 3-210 s[...]

Index Index-1 1 SPRU733 SUBC instruction 3-258 SUBDP instruction 3-260 .L-unit instruction constraints 4-51 .S-unit instruction constraints 4-38 pipeline operation 4-28 SUBSP instruction 3-263 .S-unit instruction constraints 4-37 subtract conditionally and shift (SUBC) 3-258 floating-point double-precision (SUBDP) 3-260 single-precision (SUBSP) 3-2[...]