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Cypress CY14B101NA manual

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Table of contents for the manual

  • Page 1

    PRELIMINARY CY14B101LA, CY14B101NA 1 Mbit (128K x 8/64K x 16) nvSRAM Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 001-42879 Rev . *B Revised January 29, 2009 Features ■ 20 ns, 25 ns, and 45 ns Access Times ■ Internally organized as 128K x 8 (CY14B101LA) or 64K x 16 (CY14B101[...]

  • Page 2

    PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev . *B Page 2 of 25 Pinout s Figure 1. Pin Diagram - 48 FBG A Figure 2. Pin Diag ram - 44 Pin TSOP II WE V CC A 11 A 10 V CAP A 6 A 0 A 3 CE NC NC DQ 0 A 4 A 5 NC DQ 2 DQ 3 NC V SS A 9 A 8 OE V SS A 7 NC NC NC NC A 2 A 1 NC V CC DQ 4 NC DQ 5 DQ 6 NC DQ 7 NC A 15 A 14 A 13 A 12 HSB 3 2 6 5 4[...]

  • Page 3

    PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev . *B Page 3 of 25 Figure 3. Pin Diagram - 48-Pin SSOP and 32-Pin SOIC T able 1. Pin Definitions Pin Name I/O T ype Description A 0 – A 16 Input Address Inputs Used to Select one of the 131,072 bytes of the nvSRAM for x8 Config uration. A 0 – A 15 Address Inputs Used to Select one of t[...]

  • Page 4

    PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev . *B Page 4 of 25 Device Operation The CY14B101LA/CY14B101NA nvSRAM is made up o f two functional components paired in the same physical cell. They are an SRAM memory cell and a nonvola tile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is[...]

  • Page 5

    PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev . *B Page 5 of 25 During any STORE operation, rega rdless of how it is initiated, the CY14B101LA/CY14B101NA continues to drive the HSB pin LOW , releasing it onl y when the STORE is complete. Upon completion of the STORE operation, the CY14B101LA/CY14B101NA re mains disabled un til the HS[...]

  • Page 6

    PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev . *B Page 6 of 25 Preventing AutoStore The AutoS tore function is disabled by initiati ng an AutoS t ore disable sequence. A sequence of read ope rations is performed in a manner si milar to the Software STORE initiation. T o initiate the AutoS tore disable sequence, the followi ng sequen[...]

  • Page 7

    PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev . *B Page 7 of 25 Maximum Ratin gs Exceeding maximum ratings may impair the useful life of the device. These user guid elines are not tested. S torage T emperature .................. .............. . –65 ° C to +150 ° C Maximum Accumulated Storage T ime: At 150 ° C Ambient T emperatu[...]

  • Page 8

    PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev . *B Page 8 of 25 AC T est Conditions Input Pulse Levels ....... .............. .............. .............. ... 0V to 3V Input Rise and Fall T imes (10% - 90%)........... ............. < 3 ns Input and Output T iming Reference Levels ........... ......... 1.5V Dat a Retention and End[...]

  • Page 9

    PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev . *B Page 9 of 25 AC Switching Characteristics Parameters Description 20 ns 25 ns 45 ns Unit Cypress Parameters Alt Parameters Min Max Min Max Mi n Max SRAM Read Cycle t ACE t ACS Chip Enable Access Time 20 25 45 ns t RC [15] t RC Read Cycle T i me 20 25 45 ns t AA [16] t AA Address Acces[...]

  • Page 10

    PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev . *B Page 10 of 25 Note 21. CE or WE must be > V IH during address transitions. Figure 7. SRAM Read Cy cle #2: CE and OE Controlled [3, 15, 19] Figure 8. SRAM Write Cycle #1: WE Controlled [3, 18, 19, 21 ] Ad dress V al id Ad dr ess Data Output Ou tput Data Va li d Stand by Acti ve Hig[...]

  • Page 11

    PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev . *B Page 1 1 of 25 Figure 9. SRAM Write Cycle #2: CE Controlled [3, 18, 19, 21] Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled [3, 18, 19, 21] D ata Ou tput Da ta Inpu t Inpu t D ata Va li d High Impedance Addr e ss Val id Ad dr ess t WC t SD t HD BHE , BLE WE CE t SA t SCE t HA [...]

  • Page 12

    PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev . *B Page 12 of 25 AutoStore/Power Up RECALL Parameters Descrip tion 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t HRECALL [27] Power Up RECALL Durati on 20 20 20 ms t STORE [23] ST ORE Cycle Duration 8 8 8 ms t DELA Y [24] T i me Allowed to Complete SRAM Cycle 20 25 25 ns V SWITCH Low[...]

  • Page 13

    PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev . *B Page 13 of 25 Sof tware Controlled ST ORE/RECALL Cycle Parameters [27, 28 ] Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t RC STORE/RECALL Initiation Cycle T ime 20 25 45 ns t SA Address Setup T i me 0 0 0 ns t CW Clock Pulse Width 15 20 30 ns t HA Address Hold T ime 0 [...]

  • Page 14

    PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev . *B Page 14 of 25 Hardware STORE Cycle Parameters Descrip tion 20ns 25ns 45ns Unit Min Max Min Max Min Max t DHSB HSB T o Output Act ive T ime when write latch not set 20 25 25 ns t PHSB Hardware STORE Pulse Wid th 15 15 15 ns t SS [29, 30] Soft Sequence Proc essing T ime 100 100 100 μ [...]

  • Page 15

    PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev . *B Page 15 of 25 T ruth T able For SRAM Operations HSB must remain HIGH for SRAM operations. T ab le 3. T ruth T able for x8 Configuration CE WE OE Inputs/Outputs [2 ] Mode Power H X X High Z Deselect/Power down S tandby L H L Data Out (DQ 0 –DQ 7 ); Read Active L H H High Z Output Di[...]

  • Page 16

    PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev . *B Page 16 of 25 Ordering Information Speed (ns) Ordering Code Package Diagram Package T ype Operating Range 20 CY14B101LA-ZS20XCT 51-85087 44-pin TSOP II Commercial CY14B101LA-ZS20XC 51-85087 44 -pin TSOP II CY14B101LA-BA20XCT 51-85128 48 -ball FBGA CY14B101LA-BA20XC 51-85128 48 -ball [...]

  • Page 17

    PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev . *B Page 17 of 25 25 CY14B101LA-ZS25XCT 51-85087 44-pin TSOP II Commercial CY14B101LA-ZS25XC 51-85087 44 -pin TSOP II CY14B101LA-BA25XCT 51-85128 48 -ball FBGA CY14B101LA-BA25XC 51-85128 48 -ball FBGA CY14B101LA-SP25XCT 51-85 061 48-pin SSOP CY14B101LA-SP25XC 51-85061 48-pin SSOP CY14B10[...]

  • Page 18

    PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev . *B Page 18 of 25 45 CY14B101LA-ZS45XCT 51-85087 44-pin TSOP II Commercial CY14B101LA-ZS45XC 51-85087 44 -pin TSOP II CY14B101LA-BA45XCT 51-85128 48 -ball FBGA CY14B101LA-BA45XC 51-85128 48 -ball FBGA CY14B101LA-SP45XCT 51-85 061 48-pin SSOP CY14B101LA-SP45XC 51-85061 48-pin SSOP CY14B10[...]

  • Page 19

    PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev . *B Page 19 of 25 Part Numbering Nomenclature Option: T - T ape & Reel Blank - S td. S pe ed: 20 - 20 ns 25 - 25 ns Data Bus: L - x8 N - x16 Density: 101 - 1 Mb V oltage: B - 3.0V Cypress CY 14 B 101L A-ZS 20 X C T NVSRAM 14 - AutoStore + Software STORE + Hardware STORE T emperature [...]

  • Page 20

    PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev . *B Page 20 of 25 Package Diagrams Figure 16. 44-Pin TSOP II (51-85087) MAX MIN. DIMENSION IN MM (INCH) 11.938 (0.470) PLANE SEATING PIN 1 I.D. 44 1 18.517 (0.729) 0.800 BSC 0° -5° 0.400(0.016) 0.300 (0.012) EJECTOR PIN R G O K E A X S 11.735 (0.462) 10.058 (0.396) 10.262 (0.404) 1.194[...]

  • Page 21

    PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev . *B Page 21 of 25 Figure 17. 48 -Ball FBGA - 6 mm x 10 m m x 1.2 mm (51 -85128) Package Diagrams (continued) A 1 A1 CORNER 0.75 0.75 Ø0.30±0.05(48X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.21±0.05 1.20 MAX C SEATING PLANE 0.53±0.05 0.25 C 0.15 C A1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 [...]

  • Page 22

    PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev . *B Page 22 of 25 Figure 18. 48-Pin SSOP (51-85061) Package Diagrams (continued) 51-85061 *C [+] Feedback[...]

  • Page 23

    PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev . *B Page 23 of 25 Figure 19. 32-Pin SOIC (51-85127) Package Diagrams (continued) [+] Feedback[...]

  • Page 24

    PRELIMINARY CY14B101LA, CY14B101NA Document #: 001-42879 Rev . *B Page 24 of 25 Document History Page Document Title: CY14B101LA/CY14B101NA 1 Mbit (128K x 8 /64K x 16) nvSRA M Document Number: 001-42879 Rev . ECN No. Submission Date Orig. of Change Description of Cha nge ** 2050747 See ECN UNC/PYRS New Data Sheet *A 2607447 1 1/14/2008 GVCH/AESA Re[...]

  • Page 25

    Document #: 001-42879 Rev . *B Revised January 29, 20 09 Page 25 of 25 AutoS tore and QuantumT rap are registe red trademarks of C ypress Semicondu ctor Corporation . All product s and company na mes mentio ned in this document are the tradem arks of thei r respective holders. PRELIMINARY CY14B101LA, CY14B101NA © Cypress Semicondu ctor Corporati o[...]