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Cypress CY14B101Q3 manual

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Table of contents for the manual

  • Page 1

    PRELIMINARY 1 Mbit (128K x 8) Serial SPI nvSRAM CY14B101Q1 CY14B101Q2 CY14B101Q3 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 001-50091 Rev . *A Revised February 2, 2009 Features ■ 1 Mbit NonV ola tile SRAM ❐ Internally organize d as 128K x 8 ❐ STORE to QuantumTrap ® nonv[...]

  • Page 2

    PRELIMINARY CY14B101Q1 CY14B101Q2 CY14B101Q3 Document #: 001-50091 Rev . *A Page 2 of 22 Pinout s Figure 1. Pin Diagr am - 8-Pin DFN [1, 2, 3] Figure 2. Pin Diagram - 16-Pin SOIC T able 1. Pin Definitions Pin Name I/O T ype Description CS Input Chip Select . Activates the device when pulled LOW . Driving this pin high puts the device in low power s[...]

  • Page 3

    PRELIMINARY CY14B101Q1 CY14B101Q2 CY14B101Q3 Document #: 001-50091 Rev . *A Page 3 of 22 Device Operation CY14B101Q1/CY14B101Q2/CY14 B101Q3 is 1 Mbit nvSRAM memory with a nonvolatile element in each memory cell. All the reads and writes to nvSRAM happen to th e SRAM which gives nvSRAM the un ique capability to handle in finite writes to the memory [...]

  • Page 4

    PRELIMINARY CY14B101Q1 CY14B101Q2 CY14B101Q3 Document #: 001-50091 Rev . *A Page 4 of 22 capacitor (V CAP ) and enables the device to sa fely STORE the data in the nonvolatile memory when power goes down. During normal operation, the device draws current from V CC to charge the capacitor connected to the V CAP pin. When the voltage on the V CC pin [...]

  • Page 5

    PRELIMINARY CY14B101Q1 CY14B101Q2 CY14B101Q3 Document #: 001-50091 Rev . *A Page 5 of 22 Note CY14B101Q2/CY14B101 Q3 has AutoS t ore Enabled fro m the factory . In CY14 B101Q1, V CAP pin is not present and AutoS tore opti on is not available. The Autosto re Enable and Disable instructio ns to CY14B101Q1 are ignored. Note If AutoS tore is disabled a[...]

  • Page 6

    PRELIMINARY CY14B101Q1 CY14B101Q2 CY14B101Q3 Document #: 001-50091 Rev . *A Page 6 of 22 SPI Modes CY14B101Q1/CY14B101Q2/CY14 B101Q3 may be driven by a microcontroller with its SPI periph eral running in either of the following two modes: ■ SPI Mode 0 (CPOL=0, CPHA=0) ■ SPI Mode 3 (CPOL=1, CPHA=1) For both these modes, inpu t data is latched-in[...]

  • Page 7

    PRELIMINARY CY14B101Q1 CY14B101Q2 CY14B101Q3 Document #: 001-50091 Rev . *A Page 7 of 22 SPI Operating Features Power Up Power up is defined as the co ndition when the power supply i s turned on and V CC crosses Vswitch voltage. During this time, the Chip Select (CS ) must be allow ed to follow the V CC voltage. Therefore, CS must be co nnected to [...]

  • Page 8

    PRELIMINARY CY14B101Q1 CY14B101Q2 CY14B101Q3 Document #: 001-50091 Rev . *A Page 8 of 22 St atus Register The status register bits are listed in Ta b l e 3 . T he status register consists of Ready bit (RDY ) and data protection bits BP1, BP0, WEN, and WPEN. The RDY bit can be polled to check the Re ady or Busy status while a nvSRAM STORE cycle is i[...]

  • Page 9

    PRELIMINARY CY14B101Q1 CY14B101Q2 CY14B101Q3 Document #: 001-50091 Rev . *A Page 9 of 22 Write Protection and Block Protection CY14B101Q1/CY14B101 Q2/CY1 4B101Q3 provides features for both software and hardware write protection using WRDI instruction and WP . Additionally , this device also provides block protection mechanism through BP0 and BP1 pi[...]

  • Page 10

    PRELIMINARY CY14B101Q1 CY14B101Q2 CY14B101Q3 Document #: 001-50091 Rev . *A Page 10 of 22 Writ e Protect (WP ) Pin The write protect pin (WP ) is used to provide hardware wri te protecti on. WP pin enables all normal read and write operations when held HIGH. When the WP pin is brought LOW and WPEN bit is “1”, all write opera tions to the status[...]

  • Page 11

    PRELIMINARY CY14B101Q1 CY14B101Q2 CY14B101Q3 Document #: 001-50091 Rev . *A Page 1 1 of 22 nvSRAM Special Instructions CY14B101Q1/CY14B101 Q2/CY14B101Q3 provides four special instructions which enables access to four nvSRAM specific functions: ST ORE, RECALL, ASDISB, and ASENB. Ta b l e 8 lists these instructions. Sof tware STORE When a STORE instr[...]

  • Page 12

    PRELIMINARY CY14B101Q1 CY14B101Q2 CY14B101Q3 Document #: 001-50091 Rev . *A Page 12 of 22 bit is cleared on the positive ed ge of CS following the STORE instruction . Sof tware RECALL When a RECALL instruction is executed, nvSRAM performs a Software RECALL operation. T o i s sue this instruction, the device must be write enabled (WEN = ‘1’). Th[...]

  • Page 13

    PRELIMINARY CY14B101Q1 CY14B101Q2 CY14B101Q3 Document #: 001-50091 Rev . *A Page 13 of 22 Maximum Ratin gs Exceeding maximum ratings may shorten the useful life of the device. These user guid elines are not tested. S torage T emperature .................. ............... –65 ° C to +150 ° C Maximum Accumulated Storage T ime At 150 ° C Ambient [...]

  • Page 14

    PRELIMINARY CY14B101Q1 CY14B101Q2 CY14B101Q3 Document #: 001-50091 Rev . *A Page 14 of 22 AC T est Conditions Input Pulse Levels .................. .............. .................... 0V to 3V Input Rise and Fall T imes (10% - 90%) .... .............. ..... < 3 ns Input and Output T iming Refer ence Levels ................... ..1.5V Dat a Retent[...]

  • Page 15

    PRELIMINARY CY14B101Q1 CY14B101Q2 CY14B101Q3 Document #: 001-50091 Rev . *A Page 15 of 22 AC Switching Characteristics Cypress Parameter Alt. Parameter Description 40MHz Unit Min Max f SCK f SCK Clock Frequency , SCK 40 MHz t CL t WL Clock Pulse Width Low 1 1 ns t CH t WH Clock Pulse Width High 1 1 ns t CS t CE CS High T ime 20 ns t CSS t CES CS Se[...]

  • Page 16

    PRELIMINARY CY14B101Q1 CY14B101Q2 CY14B101Q3 Document #: 001-50091 Rev . *A Page 16 of 22 AutoS tore or Power Up RECALL Parameters Description CY‘4B101QxA Unit Min Max t FA [7] Power Up RECALL Durati on 20 ms t STORE [8] ST ORE Cycle Duration 8m s t DELA Y [9] T ime Allowed to Comp lete SRAM Cycle 25 ns V SWITCH Low V o ltage T rigger Level 2.65 [...]

  • Page 17

    PRELIMINARY CY14B101Q1 CY14B101Q2 CY14B101Q3 Document #: 001-50091 Rev . *A Page 17 of 22 Sof tware Controlled STORE and RECALL Cycles Parameter Des cription CY14B101Q1 Unit Min Max t RECALL RECALL Duration 200 μ s t SS [12, 13] Soft Sequence Processing T ime 100 μ s Switching W aveforms Figure 24. Soft ware STORE Cycle [1 2] Figure 25. Software [...]

  • Page 18

    PRELIMINARY CY14B101Q1 CY14B101Q2 CY14B101Q3 Document #: 001-50091 Rev . *A Page 18 of 22 Hardware STORE Cycle Parameter Description CY14B101Q1 Unit Min Max t DHSB HSB T o Ou tput Active T ime when write latch not set 25 ns t PHSB Hardware STORE Pulse Wid th 15 ns Switching W aveforms Figure 26. Hardware ST ORE Cycle [8] ~ ~ ~ ~ HSB (IN) HSB (OUT) [...]

  • Page 19

    PRELIMINARY CY14B101Q1 CY14B101Q2 CY14B101Q3 Document #: 001-50091 Rev . *A Page 19 of 22 Ordering Information Ordering Co de Package Diagram Package T ype Operating Range CY14B101Q1-LHXIT 001- 50671 8 DFN (with WP ) Industrial CY14B101Q1-LHXI 001-50 671 8 D FN (with WP ) CY14B101Q1-LHXCT 001-50671 8 DFN (with WP ) Commercial CY14B101Q1-LHXC 001-50[...]

  • Page 20

    PRELIMINARY CY14B101Q1 CY14B101Q2 CY14B101Q3 Document #: 001-50091 Rev . *A Page 20 of 22 Package Diagrams Figure 27. 8-Pin (300 mil) DFN Package (001-50671) 1. ALL DIMEN SIONS ARE IN MILLIMETERS 3. BASED ON REF JEDEC # MO- 240 EXCEPT DIMENSIONS (L) and (b) NOTES: 2. PACKAGE WEIGHT: TBD 001-50671 *A [+] Feedback[...]

  • Page 21

    PRELIMINARY CY14B101Q1 CY14B101Q2 CY14B101Q3 Document #: 001-50091 Rev . *A Page 21 of 22 Figure 28. 16-Pin (300 mil) SOIC (51-85022 ) Package Diagrams (continued) 51-85022 *B [+] Feedback[...]

  • Page 22

    Document #: 001-50091 Rev . *A Revised February 2, 2009 Page 22 of 22 AutoStore and Quantum Trap are trademarks of Cypress Semico nductor Corp . All products an d company names ment ioned in this d ocume nt ar e the trad emarks of their respe ctive ho lders. PRELIMINARY CY14B101Q1 CY14B101Q2 CY14B101Q3 © Cypress Semicondu ctor Corporati on, 2008-2[...]