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Cypress CY14B104NA manual

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  • Page 1

    PRELIMINARY CY14B104LA, CY14B104NA 4 Mbit (512K x 8/256K x 16) nvSRAM Cypress Semiconducto r Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 001-49918 Rev . *A Revised March 1 1, 2009 Features ■ 20 ns, 25 ns, and 45 ns acce ss times ■ Internally organized as 512K x 8 (CY14B104L A) or 256K x 16 (CY14B[...]

  • Page 2

    PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev . *A Page 2 of 23 Pinout s Figure 1. Pin Diagram - 48 FBGA Figure 2. Pi n Diagram - 44 Pin TSOP II WE V CC A 11 A 10 V CAP A 6 A 0 A 3 CE NC NC DQ 0 A 4 A 5 NC DQ 2 DQ 3 NC V SS A 9 A 8 OE V SS A 7 NC NC NC A 17 A 2 A 1 NC V CC DQ 4 NC DQ 5 DQ 6 NC DQ 7 NC A 15 A 14 A 13 A 12 HSB 3 2 6 5 [...]

  • Page 3

    PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev . *A Page 3 of 23 Figure 3. Pin Diagram - 54 Pin TSOP II (x16) Pin Definitions Pin Name I/O T ype Description A 0 – A 18 Input Address Inputs Used to Select one of the 524,2 88 by tes of the nvSRAM for x8 Configuratio n . A 0 – A 17 Address Inputs Used to Select one of the 262,1 44 wo[...]

  • Page 4

    PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev . *A Page 4 of 23 Device Operation The CY14B104LA/CY14B104NA nvSRAM is made up o f two functional components paired in the same physical cell. They are a SRAM memory cell and a n onvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is [...]

  • Page 5

    PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev . *A Page 5 of 23 remains disabled until the HSB pin returns HIGH. Lea ve the HSB unconnected if it is not used. Hardware RECALL (Power Up) During power up or after any low power condition (V CC <V SWITCH ), an internal RECALL re quest is latched. When V CC again exceeds the sense volt[...]

  • Page 6

    PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev . *A Page 6 of 23 Preventing AutoStore The AutoS t ore function is disab led by initia ting an AutoS tore disable sequence. A sequence of read ope rations is performed in a manner similar to the software STORE initiation. T o initiate the AutoS tore disa ble sequence, the following sequen[...]

  • Page 7

    PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev . *A Page 7 of 23 Best Practices nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of t he product’s m ain system values, experience gained worki ng with hundreds of applic ations has resulted in the following suggestion s as be st practices: ■ The[...]

  • Page 8

    PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev . *A Page 8 of 23 Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These us er guidelines are not teste d . S torage T emperature ..................... ... ... ....... –65 ° C to +150 ° C Maximum Accumulated S torage Time At 150 ° C Ambient T empera[...]

  • Page 9

    PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev . *A Page 9 of 23 AC T est Conditions Input Pulse Levels ..................... .............. .............. ... 0V to 3V Input Rise and Fall T imes (10% - 90%) .............. .......... < 3 ns Input and Output T iming Reference Levels .................... 1.5V Dat a Retention and Endu[...]

  • Page 10

    PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev . *A Page 10 of 23 AC Switching Characteristics Parameters Description 20 ns 25 ns 45 ns Unit Cypress Parameters Alt Parameters Min Max Min Max Min Max SRAM Read Cy cle t ACE t ACS Chip Enable Access Time 20 25 45 ns t RC [13] t RC Read Cycle T ime 20 25 45 ns t AA [14] t AA Address Acces[...]

  • Page 11

    PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev . *A Page 1 1 of 23 Figure 7. SRAM Read Cycle #2: CE and OE Controlled [3, 13, 17] Figure 8. SRAM Write Cycle #1: WE Cont ro lled [3, 16, 17, 1 8] Ad dress V alid Ad dre ss Data Output Ou tput Data Vali d Stand by Acti ve High Impedance CE OE BHE, BLE I CC t HZCE t RC t ACE t AA t LZC E t[...]

  • Page 12

    PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev . *A Page 12 of 23 Figure 9. SRAM Write C ycle #2: CE Controlled [3, 16, 17, 1 8] Figure 10. SRAM W rite Cycle #3: BHE and BLE Cont rolled [3, 16, 17, 18] D ata Ou tput Da ta Inpu t Inpu t D ata Va li d High Impedance Ad d res s Va lid Ad dre ss t WC t SD t HD BHE , BLE WE CE t SA t SCE t[...]

  • Page 13

    PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev . *A Page 13 of 23 AutoStore/Power Up RECALL Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t HRECALL [19] Power Up RECALL Duration 20 20 20 ms t STORE [20] STORE Cycle Duration 8 8 8 ms t DELA Y [21] T ime Allowed to Complete SRAM Cycle 20 25 25 ns V SWITCH Low V o[...]

  • Page 14

    PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev . *A Page 14 of 23 Sof tware Controlled STORE/RECALL Cycle In the following table, the software controlled STORE and RECALL cycle parameters are listed. [24, 25] Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t RC STORE/RECALL Initiation Cycle T ime 20 25 45 ns t SA[...]

  • Page 15

    PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev . *A Page 15 of 23 Hardware STORE Cycle Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t DHSB HSB T o Outp ut Active Time when write latch not set 20 25 25 ns t PHSB Hardware STORE Pulse Wid th 15 15 15 ns t SS [26, 27] Soft Sequence Processing T ime 100 100 100 μ [...]

  • Page 16

    PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev . *A Page 16 of 23 T ruth T able For SRAM Operations HSB should remain HIGH for SRAM Operations. For x8 Configuration CE WE OE Input s/Output s [2] Mode Power H X X High Z Deselect/Power down S tandby L H L Data Out (DQ 0 –DQ 7 ); Read Active L H H High Z Output Disabled Active L L X Da[...]

  • Page 17

    PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev . *A Page 17 of 23 Ordering Information Speed (ns) Ordering Code Package Diagram Package T ype Operating Range 20 CY14B104LA-ZS20XCT 51-85087 44-pin TSOP II Commercial CY14B104LA-ZS20XC 51-85087 44-pin TSOP II CY14B104LA-ZS20XIT 51-85087 44-p in TSO P II Industrial CY14B104LA-ZS20XI 51-85[...]

  • Page 18

    PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev . *A Page 18 of 23 45 CY14B104LA-ZS45XCT 51-85087 44-pin TSOP II Commercial CY14B104LA-ZS45XC 51-85087 44-pin TSOP II CY14B104LA-ZS45XIT 51-85087 44-p in TSO P II Industrial CY14B104LA-ZS45XI 51-85087 44-pin TSOP II CY14B104LA-BA45XCT 51-85128 48-ball FBGA Commercial CY14B104LA-BA45XC 51-[...]

  • Page 19

    PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev . *A Page 19 of 23 Part Numbering Nomenclature Option: T - T ape & Reel Blank - S td. S peed: 20 - 20 ns 25 - 25 ns Data Bus: L - x8 N - x16 Densit y: 104 - 4 Mb V olt age: B - 3.0V Cypress CY 14 B 104 L A -ZS P 20 X C T NVSRAM 14 - Auto Store + Software Store + Hardware Store T emper[...]

  • Page 20

    PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev . *A Page 20 of 23 Package Diagrams Figure 16. 44-Pin TSOP II (51-85087) MAX MIN. DIMENSION IN MM (INCH) 11.938 (0.470) PLANE SEATING PIN 1 I.D. 44 1 18.517 (0.729) 0.800 BSC 0° -5° 0.400(0.016) 0.300 (0.012) EJECTOR PIN R G O K E A X S 11.735 (0.462) 10.058 (0.396) 10.262 (0.404) 1.194[...]

  • Page 21

    PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev . *A Page 21 of 23 Figure 17. 48 -Ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128) Package Diagrams (continued) A 1 A1 CORNER 0.75 0.75 Ø0.30±0.05(48X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.21±0.05 1.20 MAX C SEATING PLANE 0.53±0.05 0.25 C 0.15 C A1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 3.[...]

  • Page 22

    PRELIMINARY CY14B104LA, CY14B104NA Document #: 001-49918 Rev . *A Page 22 of 23 Figure 18. 54-Pin TSOP II (51-85160) Package Diagrams (continued) 51-85160 -** [+] Feedback[...]

  • Page 23

    Document #: 001-49918 Rev . *A Revised March 1 1, 2009 Page 23 of 23 AutoS tore and QuantumT rap are registered trademarks o f Cypress Se miconductors. All other pro ducts a nd compan y names mention ed i n this document a re the tradem arks of the ir respectiv e holders. PRELIMINARY CY14B104LA, CY14B104NA © Cypress Semicondu ctor Corpor ation, 20[...]