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Cypress CY14B108K manual

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Table of contents for the manual

  • Page 1

    PRELIMINARY CY14B108K, CY14B108M 8 Mbit (1024K x 8/512K x 16) nvSRAM with Real T ime Clock Cypress Semiconducto r Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 001-47378 Rev . ** Revised April 01 , 20 0 9 Features ■ 20 ns, 25 ns, and 45 ns acce ss times ■ Internally organized as 1024K x 8 (CY14B108[...]

  • Page 2

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 2 of 29 Pinout s Figure 1. Pin Di a gr am : 44 -PI n and 54-Pin TSOP II T able 1. Pin Definitions Pin Name I/O T ype Description A 0 – A 19 Input Address Inputs Used to Select one of the 1,048,576 by tes of the nvSRAM for x8 Configuration . A 0 – A 18 Address Inputs Used to Se[...]

  • Page 3

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 3 of 29 Device Operation The CY14B108K/CY14B108M nvSRAM is made u p of two functional components paired in the same physical cell. These are a SRAM memory cell and a nonvolatile Qua ntumT rap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is tr[...]

  • Page 4

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 4 of 29 power-on-recall, the MPU must be active or the WE held inactive until the MPU come s out of reset. T o re duce unnecessary nonvolatile STOREs, AutoS tore, and Hardware STORE operations are ignored unless at least one write operation has taken place since th e most recent S[...]

  • Page 5

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 5 of 29 Preventing AutoStore The AutoS tore function is disab led by initiati ng an AutoS tore disable sequence. A sequence of read ope rations is performed in a manner si milar to th e Software STORE initiation. T o initiate the AutoS tore disable sequence, the followi ng sequenc[...]

  • Page 6

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 6 of 29 Dat a Protection The CY14B108K/CY14B108M prot ects data from corruption during low voltage conditio ns b y inhibi ti ng all external ly initiated STORE and write operations. The low voltage condition is detected w hen V CC is less than V SWITCH . If the CY14B108K/ CY14B108[...]

  • Page 7

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 7 of 29 Real Time Clock Operation nvTime Operation The CY14B108K/CY14B108 M offers internal registers that contain clock, alarm, watchdog, interrupt, and control functions. RTC registers use the last 16 address locations of the SRAM. Internal double buffering of the clock and time[...]

  • Page 8

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 8 of 29 calibration registers and the OSCEN bit are not affected by the ‘oscillator failed’ con dition. The value of OSCF must be reset to ‘0’ when the time reg isters are writ ten for t he first ti me. This in itialize s the st ate of t his bit which may have become set w[...]

  • Page 9

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 9 of 29 Figure 3. W atchdog Timer Block Diagram . Power Monitor The CY14B108K provides a power manage ment scheme with power fail interrupt capability . It also controls the internal switch to backup power for the clock and protects the memory from low V CC access. The power monit[...]

  • Page 10

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 10 of 29 Figure 4. RTC Recommended Component Configuration Figure 5. Interrupt Block Diagram Recommended V alues Y 1 = 32.768 KHz (6 pF) C 1 = 21 pF C 2 = 21 pF Note: The recommende d values for C1 and C2 include board trace cap acitance . X out X in Y1 C2 C1 W atchdog T imer Powe[...]

  • Page 11

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 1 1 of 29 T able 4. RTC Register Map [7] Register BCD Format Data [8] Function/Range CY14B108K CY14B108M D7 D6 D5 D4 D3 D2 D1 D0 0xFFFFF 0x7FFFF 10s Y ears Y ears Y ears: 00–99 0xFFFFE 0x7FFFE 0 0 0 10s Months Months Months: 01 –12 0xFFFFD 0x7FFFD 0 0 10s Day of Month D ay Of [...]

  • Page 12

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 12 of 29 T able 5. Register Map Detail Register Description CY14B108K CY14B108M 0xFFFFF 0x7FFFF Time Keeping - Y ears D7 D6 D5 D4 D3 D2 D1 D0 10s Y ears Y ears Contains the lower two BCD di gits of the year . Lo wer nibble (four bits) contains the value for years; upper nibble (fo[...]

  • Page 13

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 13 of 29 Register Description CY14B108K CY14B108M 0xFFFF8 0x 7FFF8 Calibration/Con trol D7 D6 D5 D4 D3 D2 D1 D0 OSCEN 0 Calibrat ion Sign Calibration OSCEN O scillator Enable. When set to 1, the oscillator is stopped. When set to 0, the oscillator runs. Disabling the oscillato r s[...]

  • Page 14

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 14 of 29 Register Description CY14B108K CY14B108M 0xFFFF4 0x 7FFF4 Alarm - Hours D7 D6 D5 D4 D3 D2 D1 D0 M 10s Alarm Hours Alarm Hours Contains the alarm value for the hours and the mask bi t to select or deselect the hours value. M Match. When this bit is set to 0, the hours valu[...]

  • Page 15

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 15 of 29 Maximum Ratin gs Exceeding maximum ratings may impair the useful life of the device. These user g uidelines are not tested. S t orage T emperature ............. ... .. ... ............ –65 ° C to +150 ° C Maximum Accumulated Storage T ime At 150 ° C Ambient T emperat[...]

  • Page 16

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 16 of 29 AC T est Conditions Input Pulse Levels ....................... ............ ........... ...... 0V to 3V Input Rise and Fall T imes (10% - 90%) ........ ................ < 3 ns Input and Output T iming Reference Levels ................ .... 1.5V Dat a Retention and Endu[...]

  • Page 17

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 17 of 29 T able 6. RTC Characteristics Parameters Description T est Conditions Min Ty p Max Units I BAK [14] RTC Backup Current Room T e mperature (25 o C) 300 nA Hot T emperature (85 o C) 4 50 nA V RTC ba t RTC Battery Pin V oltage 1.8 3.0 3.3 V V RTC ca p RTC Capacitor Pin V olt[...]

  • Page 18

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 18 of 29 AC Switching Characteristics Parameters Descriptio n 20 ns 25 ns 45 ns Unit Cypress Parameters Alt Parameter s Min Max Min Max Min Max SRAM Read Cycle t ACE t ACS Chip Enable Access Time 20 25 45 ns t RC [15] t RC Read Cyc le T ime 20 25 45 ns t AA [16] t AA Address Acces[...]

  • Page 19

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 19 of 29 Switching W aveforms Figure 8. SRAM Read Cycle 2: CE Controlled [3, 15, 1 9] Figure 9. SRAM W rite Cycle 1: WE Controll ed [3, 18, 19, 2 0] Ad dr es s Val id Ad dr e ss Data Output Ou tput Data Vali d Stand by Acti ve High Impedance CE OE BHE, BLE I CC t HZCE t RC t ACE t[...]

  • Page 20

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 20 of 29 Switching W aveforms Figure 10. SRAM Write Cycle 2: CE Controll ed [3, 18, 19, 2 0] Figure 1 1 . SR AM Write Cycle 3: BHE and BLE Contro lled [5, 18, 19, 20, 21] D ata Ou tput Da ta Inpu t Inpu t D ata Va li d High Impedance Addr e ss Val id Ad dr e ss t WC t SD t HD BHE [...]

  • Page 21

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 21 of 29 AutoStore/Power Up RECALL Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t HRECALL [22] Power Up RECALL Duration 20 20 20 ms t STORE [23] STORE Cycle Duration 8 8 8 ms t DELA Y [24] T ime Allowed to Complete SRAM Cycle 20 25 25 ns V SWITCH Low V olt[...]

  • Page 22

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 22 of 29 Sof tware Controlled ST ORE and RECALL Cycle In the following table, the software controlled STORE and RECALL cycle parameters are listed. [27, 28] Parameters Descrip tion 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t RC STORE/RECALL Initiation Cycle T ime 20 25 45 ns [...]

  • Page 23

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 23 of 29 Hardware STORE Cycle Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max t DHSB HSB T o Outp ut Active Time when write latch not set 20 25 25 ns t PHSB Hardware STORE Pulse Wid th 15 15 15 ns Switching W aveforms Figure 15. Hardware STORE Cycle [23] Figu[...]

  • Page 24

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 24 of 29 T ruth T able For SRAM Operations HSB should remain HIGH for SRAM Operations. For x8 Configuration CE WE OE Input s and Outputs [2] Mode Power H X X High Z Deselect/Power Down S tandby L H L Data Out (DQ 0 –DQ 7 ); Read Active L H H High Z Output Disabled Active L L X D[...]

  • Page 25

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 25 of 29 Part Numbering Nomenclature Option: T - T ap e & Reel Blank - S t d. S peed: 20 - 20 ns 25 - 25 ns Data Bus: K - x8 + RT C M - x16 + RTC Density: 108 - 8 Mb V oltage: B - 3.0V Cypress CY14 B 108 K ZS P 20 X C T NVSRAM 14 - AutoStore + Software STORE + Hardware STORE T[...]

  • Page 26

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 26 of 29 Ordering Information Spee d (ns) Ordering Code Pac kage Diagram Package T yp e Operating Range 20 CY14B108K-ZS20XCT 51-85087 44-pin TSOPII Commercial CY14B108K-ZS20XC 51-85 087 44-pin TSOPII CY14B108K-ZS20XIT 51-85087 44-pin TSOPII Industrial CY14B108K-ZS20XI 51-85087 44-[...]

  • Page 27

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 27 of 29 Package Diagrams Figure 17. 44-Pin TSOP II (51-85087) MAX MIN. DIMENSION IN MM (INCH) 11.938 (0.470) PLANE SEATING PIN 1 I.D. 44 1 18.517 (0.729) 0.800 BSC 0° -5° 0.400(0.016) 0.300 (0.012) EJECTOR PIN R G O K E A X S 11.735 (0.462) 10.058 (0.396) 10.262 (0.404) 1.194 ([...]

  • Page 28

    PRELIMINARY CY14B108K, CY14B108M Document #: 001-47378 Rev . ** Page 28 of 29 Figure 18. 54-Pin TSOP II (51-85160) Package Diagrams (continued) 51-85160 ** [+] Feedback[...]

  • Page 29

    Document #: 001-47378 Rev . ** Revised April 01, 2009 Page 29 of 29 AutoS tore and QuantumT rap are re gistered trad emarks of Cypress Semi conductor Corpo ration. All prod ucts and com pany names menti o ned in this documen t are the trad emark s of th eir resp ectiv e holders. PRELIMINARY CY14B108K, CY14B108M © Cypress Semiconducto r Corporatio [...]