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A good user manual
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Table of contents for the manual
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Page 1
4-Mbit (256K x 16) S t atic RAM CY62146DV30 Cypress Semiconductor Corpora tion • 3901 North First S treet • San Jose , CA 95134 • 408-9 43-2600 Document #: 38-05339 Rev . *A Revised February 2, 2005 Features • V ery high speed: 45 ns • Wide volt age range: 2.20V–3.6 0V • Pin-compatible with CY62146CV30 • Ultra-low active power — T[...]
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Page 2
CY62146DV30 Document #: 38-05339 Rev . *A Page 2 of 1 1 Notes: 2. NC pins are not internally connected on the die. 3. DNU pins have to be left floati ng or tied to V SS to ensure proper application. 4. Pins H1, G2, and H6 in the BGA package are address exp ansion pins for 8 Mb, 16 Mb, and 32 Mb, respectively . 5. T ypical values are included for re[...]
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Page 3
CY62146DV30 Document #: 38-05339 Rev . *A Page 3 of 1 1 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. .............. ...... –65°C to +150°C Ambient T emperature with Power Applied ........... ............................ ...... –55°C to +125°C Supply V o[...]
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Page 4
CY62146DV30 Document #: 38-05339 Rev . *A Page 4 of 1 1 Cap acitance (for all packages) [9] Parameter Description T est Conditions Max. Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V CC = V CC(typ) 10 pF C OUT Output Capacitance 10 pF Thermal Resist ance [9] Parameter Description T est Conditions BGA TSOP II Un it Θ JA Thermal Resistance (J[...]
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Page 5
CY62146DV30 Document #: 38-05339 Rev . *A Page 5 of 1 1 Switching Characteristics Over the Operating Range [12] Parameter Description 45 ns [10] 55 ns 70 ns Unit Min. Max. Min. Max. Min. Max. Read Cycle t RC Read Cycle T ime 45 55 70 ns t AA Address to D ata V alid 45 55 70 ns t OHA Dat a Hold f rom Addres s Change 10 10 1 0 ns t ACE CE LOW to Data[...]
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Page 6
CY62146DV30 Document #: 38-05339 Rev . *A Page 6 of 1 1 Switching W aveforms Read Cycle 1 (Add ress T ransition Controlled) [16, 17] Read Cycle No. 2 (OE Controlled) [17, 18] Notes: 16. The device is contin uously selected . OE , CE = V IL , BHE and/or BLE = V IL . 17. WE is HIGH for read cycle. 18. Address valid prior to or coincident with C E and[...]
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Page 7
CY62146DV30 Document #: 38-05339 Rev . *A Page 7 of 1 1 Write Cycle No. 1 (WE Controlled) [15, 19, 20] Write Cycle No. 2 (CE Controlled) [15, 19, 20] Notes: 19. Data I/O is high impedance if OE = V IH . 20. If CE goes HIGH simulta neously with WE = V IH , the output rema ins in a high-imp edance stat e. 21. During this period, the I/Os are in outpu[...]
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Page 8
CY62146DV30 Document #: 38-05339 Rev . *A Page 8 of 1 1 Write Cycle No. 3 (WE Controlled, OE LOW) [20] Write Cycle No. 4 (BHE /BLE Controlled, OE LOW) [20] Switching W aveforms (continued) DATA IN t HD t SD t LZWE t PWE t SA t HA t AW t SCE t WC t HZWE CE ADDRESS WE DATA I/O NOTE 21 t BW BHE /BLE DATA I/O ADDRESS t SD t SA t HA t AW t WC CE WE DATA[...]
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Page 9
CY62146DV30 Document #: 38-05339 Rev . *A Page 9 of 1 1 T ruth T able CE WE OE BHE BLE Inputs/Outputs Mode Power H X X X X High Z Deselect/Power-D own S tandby (I SB ) L X X H H High Z Output Disabled Active (I CC ) L H L L L Data Out (I/O O –I/O 15 ) Read Active (I CC ) L H L H L Data Out (I/O O –I/O 7 ); I/O 8 –I/O 15 in High Z Read Active [...]
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Page 10
CY62146DV30 Document #: 38-05339 Rev . *A Page 10 of 1 1 © Cypress Semi conductor Corpora tion, 2005. The information con tained herein is subject to change wit hout notice. Cypr ess Semic onductor Corpo ration assumes no responsibility for th e use of any circuitry o ther than circuitry embodied i n a Cypress prod uct. Nor does it convey or imply[...]
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Page 11
CY62146DV30 Document #: 38-05339 Rev . *A Page 1 1 of 1 1 Document History Page Document Title:CY62146DV30 MoBL ® 4-Mbit (256K x 16) St atic RAM Document Number: 38-05339 REV . ECN NO. Issue Date Orig. of Change Des cription of Change ** 213251 See ECN AJU New Data Sheet *A 316039 See ECN PCI Added 45-ns S peed Bin in AC, DC and Ordering Informati[...]