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Cypress CY7C1330AV25 manual

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  • Page 1

    PRELIMINARY 18-Mbit (512K x 36/1Mbit x 18) Pipelined Register-Register Late W rite CY7C1330A V25 CY7C1332A V25 Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document No : 001-0784 4 Rev . *A Revised September 20, 2006 Features • Fast clock speed: 250, 200 MHz • Fast access time: 2.0, [...]

  • Page 2

    PRELIMINARY CY7C1330A V25 CY7C1332A V25 Document No: 001-07844 Rev . *A Page 2 of 19 Selection Guide CY7C1330A V2 5-250 CY7C1332A V2 5-250 CY7C1330A V25-200 CY7C1332A V25- 200 Unit Maximum Access T i me 2.0 2.25 ns Maximum Operating Curren t 600 550 mA Maximum CMOS S tandby Current 280 260 mA Pin Configurations 234 5 6 7 1 A B C D E F G H J K L M N[...]

  • Page 3

    PRELIMINARY CY7C1330A V25 CY7C1332A V25 Document No: 001-07844 Rev . *A Page 3 of 19 Pin Definitions Name I/O T ype Descriptio n A Input- Synchronous Address Inp uts used to select one of the address locations . Sampled at the risi ng edge of the K. BWS a BWS b BWS c BWS d Input- Synchronous Byte Write Select Inputs, active LOW . Qualified with WE [...]

  • Page 4

    PRELIMINARY CY7C1330A V25 CY7C1332A V25 Document No: 001-07844 Rev . *A Page 4 of 19 Introduction Functional Overview The CY7C1330A V25 an d CY7C1332A V25 are synchronous- pipelined Late Write SRAMs running at speeds up to 250 MHz. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass [...]

  • Page 5

    PRELIMINARY CY7C1330A V25 CY7C1332A V25 Document No: 001-07844 Rev . *A Page 5 of 19 guaranteed. The d evice must be deselecte d prior to entering the “sleep” mode. CE must remain inactive for the duration of t ZZREC after the ZZ input returns LOW . Cycle Description T ruth T able [1, 2, 3, 4, 5] Operation Address Used CE WE BWS x CLK ZZ Commen[...]

  • Page 6

    PRELIMINARY CY7C1330A V25 CY7C1332A V25 Document No: 001-07844 Rev . *A Page 6 of 19 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial bo undary scan test access port (T AP) in the FBGA package. This port operates in accor- dance with IEEE S tand ard 1 149.1-1900 but does not have the set of functions require d for full 1 1[...]

  • Page 7

    PRELIMINARY CY7C1330A V25 CY7C1332A V25 Document No: 001-07844 Rev . *A Page 7 of 19 EXTEST EXTEST is a mandatory 1 149.1 instruction which is to be executed whenever the instru cti on register is loaded with all 0s. EXTEST is not implemented in this SRAM T AP controller, and therefore this device is not co mpliant to 1 149.1. The T AP controller d[...]

  • Page 8

    PRELIMINARY CY7C1330A V25 CY7C1332A V25 Document No: 001-07844 Rev . *A Page 8 of 19 Note: 6. The 0/1 next to each state re present s the value at TMS at the rising edge of TCK. T AP Controller St ate Diagram [6] TEST -LOGIC RESET TEST -LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT -DR EXIT1-DR P A USE-DR EXIT2-DR UPDA TE-DR SELECT IR-SCAN CAPTURE-IR[...]

  • Page 9

    PRELIMINARY CY7C1330A V25 CY7C1332A V25 Document No: 001-07844 Rev . *A Page 9 of 19 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [7, 8, 9] Parameter Description T est Conditio ns Min. Max. Unit V OH1 Output HIGH V oltage I OH = − 2.0 mA 1.7 V V OH2 Output HIGH V oltage I OH = − 100 µ A2 . 1 V V OL1 Ou[...]

  • Page 10

    PRELIMINARY CY7C1330A V25 CY7C1332A V25 Document No: 001-07844 Rev . *A Page 10 of 19 t CH Capture Hold after Clock Rise 5 ns Output Times t TDOV TCK Clock LOW to TDO V alid 10 ns t TDOX TCK Clock LOW to TDO Invalid 0 ns T AP T iming and T est Conditions [1 1] T AP AC Switching Characteristics Over the Operating Range (continued) [10, 1 1] Paramete[...]

  • Page 11

    PRELIMINARY CY7C1330A V25 CY7C1332A V25 Document No: 001-07844 Rev . *A Page 1 1 of 19 Scan Register Sizes Register Name Bit Size—CY7C1330A V25 Bit Size—CY7C1332A V25 Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan 70 51 Instruction Codes Instruction Code Description EXTEST 000 Captures the Inpu t/Output ring contents. IDCODE 001 Loads the ID[...]

  • Page 12

    PRELIMINARY CY7C1330A V25 CY7C1332A V25 Document No: 001-07844 Rev . *A Page 12 of 19 Boundary Scan Order (512K x 36) Bit # Bump ID Bit # Bump ID Bit # Bump ID 15 R 2 5 6 F 4 9 2 H 24 P 2 6 7 E 5 0 1 H 34 T 2 7 6 E 5 13 G 46 R 2 8 7 D 5 2 4 D 55 T 2 9 6 D 5 3 4 E 67 T 3 0 6 A 5 44 G 76 P 3 1 6 C 5 5 4 H 87 P 3 2 5 C 5 6 4 M 96 N 3 3 5 A 5 7 3 L 10 [...]

  • Page 13

    PRELIMINARY CY7C1330A V25 CY7C1332A V25 Document No: 001-07844 Rev . *A Page 13 of 19 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. .............. ...... –65°C to +150°C Ambient T emperature with Power Applied ................. ...... ..... ............... ?[...]

  • Page 14

    PRELIMINARY CY7C1330A V25 CY7C1332A V25 Document No: 001-07844 Rev . *A Page 14 of 19 AC T est Loads and W aveforms Notes: 17. T ested initially and after any design or proc ess change that may aff ect these parameters. 18. Unless otherwise noted, test conditions a ssume signal tran siti on time of 2 V/ns, timing referen ce levels of 0.75V , V REF [...]

  • Page 15

    PRELIMINARY CY7C1330A V25 CY7C1332A V25 Document No: 001-07844 Rev . *A Page 15 of 19 Switching Characteristics [18, 19, 20, 21] Parameter Descrip tion 250 200 Unit Min. Max. M in. Max. t Power V CC (typical) to the First Access Read or Write [22] 11 m s Clock t CYC Clock Cycle Time 4.0 5.0 ns F MAX Maximum Operating Frequency 250 200 MHz t CH Cloc[...]

  • Page 16

    PRELIMINARY CY7C1330A V25 CY7C1332A V25 Document No: 001-07844 Rev . *A Page 16 of 19 Switching W aveforms READ/WRITE/DESELECT Sequence (OE Controlled) [23, 24, 25, 26] Notes: 23. The combination of WE and BWS x (x = a, b, c, d for x36 and x = a, b for x18) define a write cycle (see Write Cycle Description table). 24. All chip enables need to be ac[...]

  • Page 17

    PRELIMINARY CY7C1330A V25 CY7C1332A V25 Document No: 001-07844 Rev . *A Page 17 of 19 READ/WRITE/DESELECT Sequence (CE Controlled) Switching W aveforms (continued) CLK CE t CYC t CH t CL t CES t CEH = DON’T CARE = UNDEFINED READ WRITE READ DESELECT WRITE Deselect READ WRITE WRITE DESELECT ADDRESS WE Data In/Out RA1 t AH t AS t WES t WEH t CO Q1 O[...]

  • Page 18

    PRELIMINARY CY7C1330A V25 CY7C1332A V25 Document No: 001-07844 Rev . *A Page 18 of 19 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change withou t notice. Cypress S em ic on duct or Corpo ration assu mes no resp onsib ility for th e us e of any circuitry o ther than circuitr y embodied [...]

  • Page 19

    PRELIMINARY CY7C1330A V25 CY7C1332A V25 Document No: 001-07844 Rev . *A Page 19 of 19 Document History Page Document Title: CY7C1330A V25/CY7C1332A V25 18-Mbit (512K x 36/1Mbit x 18) Pipelined Regi ster-Register Late Write SRAM Document Numb er: 001-0784 4 REV . ECN No. Issue Date Orig. of Change Description of Chan ge ** 46981 1 See ECN NXR New da[...]