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Cypress CY7C1333H manual

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Table of contents for the manual

  • Page 1

    PRELIMINARY 2-Mbit (64K x 32) Flow-Through SRAM with NoBL™ Architecture CY7C1333H Cypress Semiconductor Corpora tion • 3901 North First S treet • San Jose , CA 95134 • 408-943-26 00 Document #: 001-00209 Rev . ** Revised April 1 1, 2005 Features • Can support up to 133 -MHz bus operations with zero wait st ates. — Data is transferred on[...]

  • Page 2

    PRELIMINARY CY7C1333H Document #: 001-00209 Rev . ** Page 2 of 12 Selection Guide CY7C1333H-133 CY7C1333H-100 Unit Maximum Access T i me 6.5 8.0 ns Maximum Operating Current 225 205 mA Maximum CMOS S tandby Current 40 40 mA Shaded area cont ains advance inf ormation. Plea se con tact your local Cypr ess sales repr esent ative for availability of th[...]

  • Page 3

    PRELIMINARY CY7C1333H Document #: 001-00209 Rev . ** Page 3 of 12 Pin Definitions (100-pin TQFP Package) Name I/O Descriptio n A 0 , A 1 , A Input- Synchronous Address Inputs used to s elect one of the 64K address locations . Sampled at the rising edge of the CLK. A [1:0] are fed to the two-bit burst counter . BW [A:D] Input- Synchronous Byte Wr it[...]

  • Page 4

    PRELIMINARY CY7C1333H Document #: 001-00209 Rev . ** Page 4 of 12 Functional Overview The CY7C1333H is a synchronous flow-through burst SRAM designed specifically to el iminate wait states during Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with[...]

  • Page 5

    PRELIMINARY CY7C1333H Document #: 001-00209 Rev . ** Page 5 of 12 Linear Burst Address T able (MODE = GND) First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 10 1 1 01 10 1 1 00 10 1 1 00 01 1 1 00 01 10 Interleaved Burst Sequence First Address Second Address Third Address Fourth Address A1, A0 A1, A0 A1, A0[...]

  • Page 6

    PRELIMINARY CY7C1333H Document #: 001-00209 Rev . ** Page 6 of 12 T ruth T able for Read/Write [2, 3] Function WE BW A BW B BW C BW D R e a d H XXXX W r i t e N o B y t e s W r i t t e n L HHHH Wri t e B y t e A – (D Q A ) L L HHH Write Byte B – (DQ B )L H L H H Wri t e By t e C – ( DQ C )L H H L H Wri t e By t e D – ( DQ D ) L HHH L Write [...]

  • Page 7

    PRELIMINARY CY7C1333H Document #: 001-00209 Rev . ** Page 7 of 12 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. .............. ...... –65°C to +150°C Ambient T emp erature with Power Applied ........... ............................ ...... –55°C to +125°C[...]

  • Page 8

    PRELIMINARY CY7C1333H Document #: 001-00209 Rev . ** Page 8 of 12 Cap acit ance [1 1] Parameter Description T est Condition s 100 TQFP Package Unit C IN Input Capacitance T A = 25° C, f = 1 MHz, V DD = 3.3V V DDQ =3.3V 5p F C CLOCK Clock Input Capacitance 5 p F C I/O I/O Capacit ance 5 p F AC T est Loads and W aveforms Switching Characteristics Ov[...]

  • Page 9

    PRELIMINARY CY7C1333H Document #: 001-00209 Rev . ** Page 9 of 12 Hold Times t AH Address Hold after CLK Rise 0.5 0.5 ns t ALH ADV/LD Hold after CLK Rise 0.5 0.5 ns t WEH WE , BW [A:D] Hold after CLK Rise 0.5 0.5 ns t CENH CEN Hold after CLK Rise 0.5 0.5 ns t DH Data Input Hold af ter CLK Rise 0.5 0.5 ns t CEH Chip Enable Hold after CLK Rise 0.5 0.[...]

  • Page 10

    PRELIMINARY CY7C1333H Document #: 001-00209 Rev . ** Page 10 of 12 NOP , ST ALL and DESELECT Cycles [18, 19 , 21 ] ZZ Mode T iming [22, 23] Switching W aveforms (continued) READ Q(A3) 456789 1 0 A3 A4 A5 D(A4) 123 CLK CE WE CEN BW [A:B] ADV/LD ADDRESS DQ C OMMAND WRITE D(A4) STALL WRITE D(A1) READ Q(A2) STALL NOP READ Q(A5) DESELECT CONTINUE DESELE[...]

  • Page 11

    PRELIMINARY CY7C1333H Document #: 001-00209 Rev . ** Page 1 1 of 12 © Cypress Semi con duct or Cor po rati on , 20 04 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress pr[...]

  • Page 12

    PRELIMINARY CY7C1333H Document #: 001-00209 Rev . ** Page 12 of 12 Document History Page Document Title: CY7C1333H 2-Mbit (64K x 32 ) Fl ow-Through SRAM with NoBL™ A rchitecture Document Numb er: 001-00209 REV . ECN NO. Issue Date Orig. of Change Description of Cha ng e ** 347377 See ECN PCI New Datasheet [+] Feedback[...]