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Cypress CY7C1355C manual

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Table of contents for the manual

  • Page 1

    9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture CY7C1355C CY7C1357C Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05539 Rev . *E Revised September 14, 2006 Features • No Bus Latency™ (NoBL™) architec ture eliminates dead cycles betwe en write [...]

  • Page 2

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 2 of 28 1 2 C MODE BW A BW B WE CE1 CE2 CE3 OE READ LOGIC DQs DQP A DQP B DQP C DQP D MEMORY ARRAY E INPUT REGISTER BW C BW D ADDRESS REGISTER WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BURST LOGIC A0' A1' D1 D0 Q1 Q0 A0 A1 ADV/LD CE ADV/LD C C LK C EN WRITE DRIVERS D A T A S T E[...]

  • Page 3

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 3 of 28 Pin Configurations 100-Pin TQFP Pinout A A A A A1 A0 NC/288M NC/144M V SS V DD NC/36M A A A A A A DQP B DQ B DQ B V DDQ V SS DQ B DQ B DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD DQ A DQ A V DDQ V SS DQ A DQ A DQ A DQ A V SS V DDQ DQ A DQ A DQP A DQP C DQ C DQ C V DDQ V SS DQ C DQ C DQ [...]

  • Page 4

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 4 of 28 Pin Configurations (continued) 100-Pin TQFP Pinout A A A A A1 A0 NC/288M NC/144M V SS V DD NC/36M A A A A A A A NC NC V DDQ V SS NC DQP A DQ A DQ A V SS V DDQ DQ A DQ A V SS NC V DD DQ A DQ A V DDQ V SS DQ A DQ A NC NC V SS V DDQ NC NC NC NC NC NC V DDQ V SS NC NC DQ B DQ B V SS V DDQ D[...]

  • Page 5

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 5 of 28 Pin Configurations (continued) 234 5 67 1 A B C D E F G H J K L M N P R T U V DDQ NC/576M NC/1G DQP C DQ C DQ D DQ C DQ D AA A A NC/18M V DDQ CE 2 A DQ C V DDQ DQ C V DDQ V DDQ V DDQ DQ D DQ D NC/144M NC V DDQ V DD CLK V DD V SS V SS V SS V SS V SS V SS V SS V SS NC NC NC NC TDO TCK TDI[...]

  • Page 6

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 6 of 28 Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip enable with JT AG) CY7C1355C (256K x 36 ) 234 56 7 1 A B C D E F G H J K L M N P R TDO NC/576M NC/1G DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C CEN A CE2 DQ C DQ D DQ D MODE NC DQ C DQ C DQ D DQ D DQ D NC/36M NC/72M V DDQ BW [...]

  • Page 7

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 7 of 28 Pin Definitions Name I/O Description A 0 , A 1 , A Input- Synchronous Address In puts used to select one of the addres s locations . Sampled at the rising edge of the CLK. A [1:0] are fed to the two-bit burst counter . BW A , BW B BW C , BW D Input- Synchronous Byte Write Inputs, active[...]

  • Page 8

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 8 of 28 Functional Overview The CY7C1355C/CY7C1357C is a synch ronous flow-through burst SRAM designed specifically to eliminate wait states during Write-Read transitions. All synchronous inputs pass through input registers contro lled by the rising edge of the clock. The clock signal is quali [...]

  • Page 9

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 9 of 28 precautio n, DQ s and DQP X ar e automat ically tri -stat ed during the data portion of a write cycle, regardless of the state of OE . Burst Write Accesses The CY7C1355C/CY7C13 57C has an on-chip burst counter that allows the user the ability to supply a sing le address and conduct up t[...]

  • Page 10

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 10 of 28 NOP/WRITE ABORT (Begin Burs t) None L H L L L L H X L L->H Tri-S tate WRITE ABORT (Continue Burst) Next X X X L H X H X L L->H Tri- St ate IGNORE CLOCK EDGE (S tall) Current X X X L X X X X H L->H – SLEEP MODE None X X X H X X X X X X T ri-St ate Partial T ruth T able for Re[...]

  • Page 11

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 1 1 of 28 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1355C/CY7C1357C incorpora tes a serial boundary scan test access port (T AP) in the BGA package only . The TQFP package does not offer this functionality . This part operates in accordance with IEEE S t andard 1 149.1-1900, but doesn?[...]

  • Page 12

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 12 of 28 Diagram. Upon power-up, the instruction register is loaded with the IDCODE in struction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in th e pre v i o us section. When the T AP controller is in th e Capture-IR state, the two l[...]

  • Page 13

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 13 of 28 T AP Timing T AP AC Switching Characteristics Over the Operating Range [10, 1 1] Parameter Description Min. Max. Unit Clock t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH Time 20 ns t TL TCK Clock LOW Time 20 ns Output Times t TDOV TCK Clock LOW t[...]

  • Page 14

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 14 of 28 3.3V T AP AC T est Conditions Input pulse levels ......... .............. ......................... V SS to 3.3V Input rise and fall times ......... .............. ...................... ... ... 1 ns Input timing referenc e levels ... .............. ..........................1.5V Outpu[...]

  • Page 15

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 15 of 28 Scan Register Sizes Register Name Bit Size (x36) Bit Size (x18) Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order (1 19-ball BGA package) 69 69 Boundary Scan Order (165-ball FBGA package) 69 69 Identification Codes Instruction Code Description EXTEST 000 Captures I/O ring conte n[...]

  • Page 16

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 16 of 28 1 19-ball BGA Boundary Scan Order CY7C1355C (256K x 36) CY7C1357C (512K x 18) Bit# ball ID Signal Name Bit# ball ID Signal Name Bit# ball Id Signal Name Bit# ball Id Signal Name 1 K4 CLK 37 R6 A 1 K4 CLK 37 R6 A 2H 4 W E 38 T5 A 2 H4 WE 38 T5 A 3M 4 C E N 39 T3 A 3 M4 CEN 39 T3 A 4F 4 [...]

  • Page 17

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 17 of 28 165-ball FBGA Boundary Scan Order CY7C1355C (256K x 36) CY7C1357C (512K x 18) Bit# ball ID Signal Name Bit# ball ID Signal Name Bit# ball ID Signal Name Bit# ball ID Signal Name 1 B6 CLK 37 R4 A 1 B6 CLK 37 R4 A 2B 7 W E 38 P4 A 2 B7 WE 38 P4 A 3A 7C E N 39 R3 A 3 A7 CEN 39 R3 A 4B 8 O[...]

  • Page 18

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 18 of 28 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. .............. ...... –65°C to +150°C Ambient T emp erature with Power Applied ........... ............................ ...... –55°C to + 125°C [...]

  • Page 19

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 19 of 28 Cap acit ance [15] Parameter Description T est Conditions 100 TQFP Max. 11 9 B G A Max. 165 FBGA Max. Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V DD = 3.3V . V DDQ = 2.5V 55 5 p F C CLK Clock Input Capacitance 5 5 5 pF C I/O Input/Output Capacitance 5 7 7 pF Thermal Resist an[...]

  • Page 20

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 20 of 28 Switching Characteristics Over the Operating Range [16, 17] Parameter D escription –133 –100 Unit Min. Max. Min. Max. t POWER V DD (T ypical) to the First Access [18] 11 m s Clock t CYC Clock Cycle T ime 7.5 10 ns t CH Clock HIGH 3.0 4.0 ns t CL Clock LOW 3.0 4.0 ns Output Times t [...]

  • Page 21

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 21 of 28 Switching W aveforms Read/Write W aveforms [22, 23, 24] Notes: 22. For this waveform ZZ is tied LOW . 23. When CE is LOW , CE 1 is LOW, CE 2 is HIGH and CE 3 is LOW . When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. 24. Order of t he Burst sequence is determined by the st [...]

  • Page 22

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 22 of 28 NOP , ST ALL and DESELECT Cycles [22, 23 , 25 ] Note: 25. The IGNORE CLOCK EDGE or ST ALL cycle (Clock 3) illustrates CEN being used to create a pau se. A write is not performed durin g this cycle . Switching W aveforms (continued) WRITE D(A1) 123456789 CLK t CYC t CL t CH 10 CE t CEH [...]

  • Page 23

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 23 of 28 ZZ Mode T iming [26, 27] Notes: 26. Device must be deselected when entering ZZ mode. See tru th ta ble for all possible signal conditions to deselect t he device. 27. DQs are in high-Z when e xiting ZZ sleep mode. Switching W aveforms (continued) t ZZ I SUPPLY CLK ZZ t ZZREC A LL INPUT[...]

  • Page 24

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 24 of 28 Ordering Information Not all of the speed, package and temperature ranges are available. Please co ntact your local sales representative or visit www .cypress .com for actua l produc t s offered. Speed (MHz) Ordering Code Pac kage Diagram Part and Package T ype Operating Range 133 CY7C[...]

  • Page 25

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 25 of 28 Package Diagrams NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMAT[...]

  • Page 26

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 26 of 28 Package Diagrams (continued) 1.27 20.32 2 16 5 4 37 L E A B D C H G F K J U P N M T R 12.00 19.50 30° TYP. 2.40 MAX. A1 CORNER 0.70 REF. U T R P N M L K J H G F E D C A B 21 43 65 7 Ø1.00(3X) REF. 7.62 22.00±0.20 14.00±0.20 1.27 0.60±0.10 C 0.15 C B A 0.15(4X) Ø0.05 M C Ø0.75±0[...]

  • Page 27

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 27 of 28 © Cypress Semi con duct or Cor po rati on , 20 06 . The information contained he re i n is su bj ect to ch ange withou t n oti ce. C ypr ess S em ic on duct or Corporation assumes no responsib ility f or the u se of any circuitry o ther than circui try embodied i n a Cypress prod uct.[...]

  • Page 28

    CY7C1355C CY7C1357C Document #: 38-05539 Rev . *E Page 28 of 28 Document History Page Document Title: CY7C1355C/CY7C1357C 9-Mbit (256 K x 36/512 K x 18) Flow-Through S RAM with NoBL™ Architecture Document Number: 38-05539 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 24 2032 See ECN RKF New data sheet *A 332059 See ECN PCI Cha[...]