English dropdown-ico

Cypress CY7C1382D manual

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

Go to page of

Similar user manuals

A good user manual

The rules should oblige the seller to give the purchaser an operating instrucion of Cypress CY7C1382D, along with an item. The lack of an instruction or false information given to customer shall constitute grounds to apply for a complaint because of nonconformity of goods with the contract. In accordance with the law, a customer can receive an instruction in non-paper form; lately graphic and electronic forms of the manuals, as well as instructional videos have been majorly used. A necessary precondition for this is the unmistakable, legible character of an instruction.

What is an instruction?

The term originates from the Latin word „instructio”, which means organizing. Therefore, in an instruction of Cypress CY7C1382D one could find a process description. An instruction's purpose is to teach, to ease the start-up and an item's use or performance of certain activities. An instruction is a compilation of information about an item/a service, it is a clue.

Unfortunately, only a few customers devote their time to read an instruction of Cypress CY7C1382D. A good user manual introduces us to a number of additional functionalities of the purchased item, and also helps us to avoid the formation of most of the defects.

What should a perfect user manual contain?

First and foremost, an user manual of Cypress CY7C1382D should contain:
- informations concerning technical data of Cypress CY7C1382D
- name of the manufacturer and a year of construction of the Cypress CY7C1382D item
- rules of operation, control and maintenance of the Cypress CY7C1382D item
- safety signs and mark certificates which confirm compatibility with appropriate standards

Why don't we read the manuals?

Usually it results from the lack of time and certainty about functionalities of purchased items. Unfortunately, networking and start-up of Cypress CY7C1382D alone are not enough. An instruction contains a number of clues concerning respective functionalities, safety rules, maintenance methods (what means should be used), eventual defects of Cypress CY7C1382D, and methods of problem resolution. Eventually, when one still can't find the answer to his problems, he will be directed to the Cypress service. Lately animated manuals and instructional videos are quite popular among customers. These kinds of user manuals are effective; they assure that a customer will familiarize himself with the whole material, and won't skip complicated, technical information of Cypress CY7C1382D.

Why one should read the manuals?

It is mostly in the manuals where we will find the details concerning construction and possibility of the Cypress CY7C1382D item, and its use of respective accessory, as well as information concerning all the functions and facilities.

After a successful purchase of an item one should find a moment and get to know with every part of an instruction. Currently the manuals are carefully prearranged and translated, so they could be fully understood by its users. The manuals will serve as an informational aid.

Table of contents for the manual

  • Page 1

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 18-Mbit (512K x 36/1M x 18) Pipelined SRAM Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-05543 Rev . *F Revised January 12, 2009 Features ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■[...]

  • Page 2

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 2 of 34 Logic Block Diagram – CY7C1380D/CY7C1380F [3] (512K x 36) Logic Block Diagram – CY7C1382D/CY7C1382F [3] (1M x 18) ADDRESS REGISTER ADV CLK BURST COUNTER AND LOGIC CLR Q1 Q0 ADSP ADSC MODE BWE GW CE 1 CE 2 CE 3 OE ENABLE REGISTER OUTPUT REGISTERS SENSE AMPS OUTP[...]

  • Page 3

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 3 of 34 Pin Configurations 100-Pin TQFP Pinout (3-Chip Enable) Figure 1. CY7C1380D, CY7C1380F(51 2K X 36) F igure 2. CY7C1382D, CY7C1382F (1M X 18) [+] Feedback[...]

  • Page 4

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 4 of 34 1 19-Ball BGA Pinout Figure 3. CY7C1380F (512K X 36) Figure 4. CY7C1382F (1M X 18) 234 5 6 7 1 A B C D E F G H J K L M N P R T U V DDQ NC/288M NC/144M DQP C DQ C DQ D DQ C DQ D AA A A ADSP V DDQ AA DQ C V DDQ DQ C V DDQ V DDQ V DDQ DQ D DQ D NC NC V DDQ V DD CLK V [...]

  • Page 5

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 5 of 34 165-Ball FBGA Pinout (3-Chip Enable) Figure 5. CY7C1380D/CY7C1380F (512 K x 36) Figure 6. CY7C1382D/CY7C1382F (1M x 18) 234 56 7 1 A B C D E F G H J K L M N P R TDO NC/28 8M NC/14 4M DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE A CE2 DQ C DQ D DQ D MODE NC DQ C[...]

  • Page 6

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 6 of 34 T able 1. Pin Definitions Name I/O Description A 0 , A 1 , A Input- Synchronous Address inputs used to select one o f the address locations . Samp led at the rising edge of the CLK if ADSP or ADSC is active L OW , and CE 1 , CE 2 , and CE 3 [2] are sampled active. [...]

  • Page 7

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 7 of 34 MODE Input-S tatic Selects burst order . When tied to GND selects linear burst sequence. When tied to V DD or left floating selects interleaved burst sequence. This i s a strap pin a nd must remain static during device operation. Mode p in has an internal pu ll up.[...]

  • Page 8

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 8 of 34 Functional Overview All synchronous inputs pass through input registe rs controlled by the rising edge of the clock. All data outputs pass through output registers controlled by th e ri sing ed ge of the clock. Maximum access delay from the clock rise (t CO ) is 2.[...]

  • Page 9

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 9 of 34 Burst Sequence s The CY7C1380D/CY7C1382D/C Y7C1380F/CY7C138 2F provides a two-bit wraparound counter , fed by A1: A0, that imple- ments an interleaved or a linear burst sequence. The interleaved burst sequence is designed spe cifically to support Intel Pentiu m app[...]

  • Page 10

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 10 of 34 T ruth T able The T ruth T able for this data sheet follows. [4, 5, 6, 7, 8] Operation Add. Us ed CE 1 CE 2 CE 3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselect Cycle, Power Down None H X X L X L X X X L-H T ri-S tate Deselect Cycle, Power Down None L L X L L X X X X L [...]

  • Page 11

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 1 1 of 34 T ruth T able for Read/Write [4, 9] Function (CY7C1380D/CY7C13 80F) GW BWE BW D BW C BW B BW A R e a d H HXXXX R e a d H L HHHH Write Byte A – (DQ A and DQP A ) H L HHH L Write Byte B – (DQ B and DQP B )H L H H L H Write Bytes B, A H L H H L L Write Byte C ?[...]

  • Page 12

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 12 of 34 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1380D/CY7C1382D incorpora tes a serial boundary scan test access port (T AP).Thi s part is fully compliant wi th 1 149.1. The T AP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels. The CY7C1380D/CY7C1382[...]

  • Page 13

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 13 of 34 When the T AP controller is in the Capture-IR state, the two least significant bits are loade d with a binary ‘ 01’ pattern to enable fau lt isolation of the board-level serial te st data path. Byp ass Register T o save time when serial ly shifting data throug[...]

  • Page 14

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 14 of 34 when the EXTEST is entered as the current instruction. When HIGH, it enables the output b uffers to drive the output bus. When LOW , this bit pl aces the output bus into a High-Z conditi on. This bit can be set by entering the SAMPLE/PRELOAD o r EXTEST command, an[...]

  • Page 15

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 15 of 34 3.3V T AP AC T est Conditions Input pulse levels .............. .............. .............. ....... V SS t o 3.3V Input rise and fall tim es. ............. ................................ ......1 ns Input timing reference levels...... ............. .. .........[...]

  • Page 16

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 16 of 34 Identification Regi ster Definitions Instruction Field CY7C1380D/CY7C1380F (512K x 36) CY7C1382D/CY7C1382F (1 Mbit x 18) Description Revision Number (31:29) 000 000 Describes the version number . Device Dept h (28:24) [13] 0101 1 0101 1 Reserved for interna l use.[...]

  • Page 17

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 17 of 34 1 19-Ball BGA Bounda ry Scan Order [14, 15] Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 H4 23 F6 45 G4 67 L1 2 T 42 4 E 74 6 A 46 8 M 2 3T 5 2 5 D 7 4 7 G 3 6 9 N 1 4 T 62 6 H 74 8 C 37 0 P 1 5R 5 2 7 G 6 4 9 B 2 7 1 K 1 6 L 5 2 8 E 65 0 B 37 2 L 2 7[...]

  • Page 18

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 18 of 34 165-Ball BGA Bounda ry Scan Order [14, 16] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2N 7 3 2 C 1 1 6 2 D 2 3 N10 33 A1 1 63 E2 4P 1 1 3 4 B 1 1 6 4 F 2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7R 9 3 7 A 9 6 7 H 3 8P 9 3 8 B 9 6 8 J 1 9 P 10 39 C10 6[...]

  • Page 19

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 19 of 34 Maximum Ratin gs Exceeding the maximu m ratings may impair the usefu l life of the device. For user guidelines, n ot tested. S torage T emperature ................ .............. ... –65°C to +150°C Ambient T emperature with Power Applied ............ ........[...]

  • Page 20

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 20 of 34 Cap acitance [19] Parameter Description T est C onditions 100 TQFP Package 1 19 BGA Package 165 FBGA Package Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V DD = 3.3V . V DDQ = 2.5V 58 9 p F C CLK Clock Input Capacitance 5 8 9 pF C IO Input/Output Capacitanc[...]

  • Page 21

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 21 of 34 Figure 9. AC T est Loads and Waveforms OUTPUT R = 317 Ω R = 351 Ω 5p F INCLUDING JIG AND SCOPE (a) (b) OUTPUT R L = 50 Ω Z 0 = 50 Ω V T = 1.5V 3.3V ALL INPUT PULSES V DDQ GND 90% 10% 90% 10% ≤ 1 ns ≤ 1 ns (c) OUTPUT R = 1667 Ω R = 1538 Ω 5p F INCLUDING J[...]

  • Page 22

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 22 of 34 Switching Characteristics Over the Operating Range [20, 21] Parameter Description 25 0 MHz 200 MHz 167 MHz Unit Min Max Min Max Min Max t POWER V DD (T ypical) to the first Access [22] 1 11 ms Clock t CYC Clock Cycle T ime 4.0 56 ns t CH Clock HIGH 1.7 2.0 2.2 ns [...]

  • Page 23

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 23 of 34 Switching W aveforms Figure 10. Read Cycle Timing [26] t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t CEH t CES GW, BWE, BWx Data Out (Q) High-Z t CLZ t DOH t CO ADV t OEHZ t CO Single READ BURST READ t OEV t OELZ t CHZ ADV suspends burst. [...]

  • Page 24

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 24 of 34 Figure 1 1 . Write Cycle Timing [26, 27] Switching W aveforms (continued ) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t CEH t CES BWE, BW X ata Out (Q) High-Z ADV BURST READ BURST WRITE D(A2) D(A2 + 1) D(A2 + 1) D(A1) D(A3) D(A3 + 1) D(A3[...]

  • Page 25

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 25 of 34 Figure 12. Read/Write Cycle Timing [26, 28, 29] Switching W aveforms (continued ) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A2 t CEH t CES BWE, BW X Data Out (Q) High-Z ADV Single WRITE D(A3) A4 A5 A6 D(A5) D(A6) Data In (D) BURST READ Back[...]

  • Page 26

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 26 of 34 Figure 13. ZZ Mode T iming [30, 31] Switching W aveforms (continued ) t ZZ I SUPPLY CLK ZZ t ZZREC ALL INPUTS (except ZZ) DON’T CARE I DDZZ t ZZI t RZZI Outputs (Q) High-Z DESELECT or READ Only Notes 30. Device must be deselected when entering ZZ mode. See “T [...]

  • Page 27

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 27 of 34 Ordering Information The follow ing t able list s all speed, pac kage and temp erature ra ng e options. Please note tha t some options listed belo w may not be available for order entry . T o verify the availability of a specific option, visit the Cypress website [...]

  • Page 28

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 28 of 34 Speed (MHz) Ordering Code Package Diagram Part and Packa ge T ype Operating Range 200 CY7C1380D-200AXC 51-8 5050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial CY7C1382D-200AXC CY7C1380F-200AXC CY7C1382F-200AXC CY7C1380F-200BGC 51-851 15 1 19-ba[...]

  • Page 29

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 29 of 34 Speed (MHz) Ordering Code Package Diagram Part and Packa ge T ype Operating Range 167 CY7C1380D-167AXC 51-8 5050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial CY7C1382D-167AXC CY7C1380F-167AXC CY7C1382F-167AXC CY7C1380F-167BGC 51-851 15 1 19-ba[...]

  • Page 30

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 30 of 34 Package Diagrams Figure 14. 100-Pin Thin Plastic Quad Flat Pack (14 x 20 x 1.4 mm) (51-85050) NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE [...]

  • Page 31

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 31 of 34 Figure 15. 1 19-Ba ll BGA ( 14 x 22 x 2.4 mm) (51-851 15) Package Diagrams (continued) 51-851 15-*B [+] Feedback[...]

  • Page 32

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 32 of 34 Figure 16. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180) Package Diagrams (continued) A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø 0 . 2 5MCAB Ø0.05 M C B A 0.15(4X) 0.35±0.06 SEATING PLANE 0.53±0.05 0.25 C 0.15 C PIN 1 CORNER TOP VIEW BOTT[...]

  • Page 33

    CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document #: 38-05543 Rev . *F Page 33 of 34 Document History Page Document Title: CY7C1380D/CY7C13 82D/CY7C1380F/CY7C1 382F , 18-Mbit (512K x 36/1M x 18) Pipelined SRAM Document Number: 38-05543 REV . ECN NO. Submission Date Orig. of Change Description of Chan ge ** 254515 See ECN RKF New data sheet *A 2885[...]

  • Page 34

    Document #: 38-05543 Rev . *F Revised January 12, 20 09 Page 34 of 34 All product s and comp any names me ntioned in this document may be the t rademarks of the ir respecti ve holders. CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F © Cypress Semicondu ctor Corporati on, 2006-2009. The information cont ained herein is subject to change without no tice. [...]