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Cypress CY7C1441AV33 manual

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  • Page 1

    36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-05357 Rev . *G Revised May 09, 2008 Features ■ Supports 133-MHz bus operations ■ 1M x 36/2M x 18/512K x 72 common IO ■ 3.3V core [...]

  • Page 2

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 2 of 31 Logic Block Diagram – CY7C1441A V33 (1M x 36) Logic Block Diagram – CY7C1443A V33 (2Mx 18) ADDRESS REGISTER BURST COUNTER AND LOGIC CLR Q1 Q0 ENABLE REGISTER SENSE AMPS OUTPUT BUFFERS INPUT REGISTERS MEMORY ARRAY MODE A [1:0] ZZ DQ s DQP A DQP B DQP C DQP D A 0[...]

  • Page 3

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 3 of 31 Logic Block Diagram – CY7C1447A V33 (512K x 72) BW D BW C BW B BW A BWE GW CE1 CE2 CE3 OE ENABLE REGISTER ADDRESS REGISTER ADV CLK BURST COUNTER AND LOGIC CLR Q1 Q0 ADSP ADSC MODE A 0, A1,A A[1:0] BW F BW E BW H BW G OUTPUT BUFFERS DQ A , DQP A WRITE DRIVER DQ B [...]

  • Page 4

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 4 of 31 Pin Configurations Figure 1. 100-Pin TQF P Pinout A A A A A 1 A 0 NC/72M A V SS V DD A A A A A A A A DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP A DQP C DQ[...]

  • Page 5

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 5 of 31 Pin Configurations (continued) 165-ball FBGA (15 x 17 x 1.4 m m) Pinout CY7C1441A V33 (1M x 36) 234 567 1 A B C D E F G H J K L M N P R TDO NC/288M NC/144M DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE A CE 2 DQ C DQ D DQ D MODE NC DQ C DQ C DQ D DQ D DQ D A NC/[...]

  • Page 6

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 6 of 31 Pin Configurations (continued) A B C D E F G H J K L M N P R T U V W 123456789 1 1 10 DQ G DQ G DQ G DQ G DQ G DQ G DQ G DQ G DQ C DQ C DQ C DQ C NC DQP G DQ H DQ H DQ H DQ H DQ D DQ D DQ D DQ D DQP D DQP C DQ C DQ C DQ C DQ C NC DQ H DQ H DQ H DQ H DQP H DQ D DQ D[...]

  • Page 7

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 7 of 31 Pin Definitions Name IO Description A 0 , A 1 , A Input- Synchronous Address Inputs Used to Select One o f the Address Lo cation s. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW , and CE 1 , CE 2 , and CE 3 are sampled active. A [1:0] feed the[...]

  • Page 8

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 8 of 31 DQ s IO- Synchronous Bidirectional Dat a IO lines . As inputs, they feed into an on-chip data register that is triggered by the rising edge of CL K. As outp uts, they deliver the data contained in the memory location sp ecif ied by the addresses p resented during t[...]

  • Page 9

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 9 of 31 Functional Overview All synchronous inputs pass through input registe rs controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CDV ) is 6.5 ns (133-MHz device). The CY7C1441A V33/CY7C1443A V33/CY7C14 47A V33 supports secondary cach[...]

  • Page 10

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 10 of 31 ZZ Mode Electrical Characteristics Parameter Description T est Condition s Min. Max. Unit I DDZZ Sleep mode standby current ZZ > V DD – 0.2V 100 mA t ZZS Device operation to ZZ ZZ > V DD – 0.2V 2t CYC ns t ZZREC ZZ recovery time ZZ < 0.2V 2t CYC ns t [...]

  • Page 11

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 1 1 of 31 Partial T ruth T able for Read/Write Function (CY7C1441 A V33) [2, 7] GW BWE BW D BW C BW B BW A R e a d H HXXXX R e a d H L HHHH Write Byte A (DQ A , DQP A ) H L HHH L Write Byte B(DQ B , DQP B )H L H H L H Write Bytes A, B (DQ A , DQ B , DQP A , DQP B )H L H H [...]

  • Page 12

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 12 of 31 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1441A V33/CY7C1443A V33/CY7C1447A V33 inco r- porates a serial bou ndary scan test access port (T AP). This part is fully compliant with 1 149.1. The T AP operates using JEDEC-standard 3.3V or 2.5V IO logic levels.[...]

  • Page 13

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 13 of 31 Instruction Register Three-bit ins tructions can be seri ally loaded into the instruction register . T his register is loaded when it is place d between the TDI and TDO balls as shown in the T ap Controller Block Diagram. Upon power up, the instruction register is[...]

  • Page 14

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 14 of 31 EXTEST The EXTEST instruction drives the preloade d dat a out through the system output pins. This in struction also connects the boundary scan register fo r serial access between the TDI and TDO in the shift-DR controller state. EXTEST OUTPUT BUS TRI-ST A T E IEE[...]

  • Page 15

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 15 of 31 T AP AC Switchi ng Characteristics Over the Operatin g Range [9, 10] Parameter Description Min. Max. Unit Clock t TCYC TCK Clock Cycle T ime 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH time 20 ns t TL TCK Clock LOW time 20 ns Output Times t TDOV TCK [...]

  • Page 16

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 16 of 31 3.3V T AP AC T est Conditions Input pulse levels .................... .............. .............. .V SS t o 3.3V Input rise and fall tim es. ........................ .............. ........... .. 1 ns Input timing reference levels...... .............. ..........[...]

  • Page 17

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 17 of 31 Identification Regi ster Definitions Instruction Field CY7C1441A V33 (1M x 36) CY7C1443A V33 (2M x 18) CY7C1447A V33 (512K x 72) Description Revision Number (31:29) 000 000 000 Describes the version number . Device Depth (28:24) 0101 1 0101 1 0101 1 Reserved for I[...]

  • Page 18

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 18 of 31 165-ball FBGA Boundary Scan Order [13,14] CY7C1441A V33 (1M x 36), CY7C1443A V33 (2M x 18) Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 26 E1 1 51 A3 76 N1 2 N7 27 D1 1 52 A2 77 N2 3N 1 0 2 8 G 1 0 5 3B 2 7 8P 1 4P 1 1 2 9 F 1 0 5 4 C 2 7 9 R 1 5 P[...]

  • Page 19

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 19 of 31 Maximum Ratin gs Exceeding maximum ratings may shorten the useful life of the device. User gui d el i ne s are not tested. S torage T emperature .................. ... ... ... ... ... –65 ° C to +150 ° C Ambient T emperature with Power Applied ................[...]

  • Page 20

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 20 of 31 Cap acit ance Parameter [17] Description T est Conditions 100 TQFP Max. 165 FBGA Max. 209 FBGA Max. Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 3.3V V DDQ = 2.5V 6.5 7 5 pF C CLK Clock Input Capacitance 3 7 5 pF C IO Input/Output Capacitance 5.5 6[...]

  • Page 21

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 21 of 31 Switching Characteristics Over the Operatin g Range [22, 23 ] Parameter Description – 133 –100 Unit Min. Max. Min. Max. t POWER V DD (T ypical) to the first Access [18] 11 m s Clock t CYC Clock Cycle T ime 7.5 10 ns t CH Clock HIGH 2.5 3.0 ns t CL Clock LOW 2.[...]

  • Page 22

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 22 of 31 Timing Diagrams Figure 3. Read Cycle Ti ming [24] . t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A1 t CEH t CES Data Out (Q) High-Z t CLZ t DOH t CDV t OEHZ t CDV Single READ BURST READ t OEV t OELZ t CHZ Burst wraps around to its initial state t ADVH t ADVS [...]

  • Page 23

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 23 of 31 Figure 4. W r ite Cycle Timing [24, 25] . Timing Diagrams (continued) t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A1 t CEH t CES High-Z BURST READ BURST WRITE D(A2) D(A2 + 1) D(A2 + 1) D(A1) D(A3) D(A3 + 1) D(A3 + 2) D(A2 + 3) A2 A3 Extended BURST WRITE D(A2[...]

  • Page 24

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 24 of 31 Figure 5. Read/Write Cycle Timing [24, 26, 27] . Timing Diagrams (continued) t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A2 t CEH t CES Single WRITE D(A3) A3 A4 BURST READ Back-to-Back READs High-Z Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) t WEH t WES t OEHZ t DH [...]

  • Page 25

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 25 of 31 Figure 6. ZZ Mode Timing [28, 29] Timing Diagrams (continued) t ZZ I SUPPLY CLK ZZ t ZZREC A LL INPUTS (except ZZ) DON’T CARE I DDZZ t ZZI t RZZI Outputs (Q) High-Z DESELECT or READ Only Note 28. Device must be deselected when entering ZZ mode. See Cycle De scri[...]

  • Page 26

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 26 of 31 Ordering Information Not all of the speed, package and temper ature ranges are avail abl e. Please c ontact your local sales representative or visit www .cypress.com for actual products of fered. Spee d (MHz) Ordering Code Package Diagram Part and Package T ype Op[...]

  • Page 27

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 27 of 31 Package Diagrams Figure 1. 100-pi n TQF P (14 x 20 x 1.4 mm) (51-85050) NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIMENSIONS IN MILLI[...]

  • Page 28

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 28 of 31 Figure 2. 165-ball FBGA (15 x 17 x 1.4 mm) (51-85165) Package Diagrams (continued) A 1 PIN 1 CORNER 17.00±0.10 15.00±0.10 7.00 1.00 Ø0.45±0.05(165X) Ø0.25 M C A B Ø 0 . 0 5MC B A 0.15(4X) 0.35 1.40 MAX. SEATING PLANE 0.53±0.05 0.25 C 0.15 C P I N1C O R N E [...]

  • Page 29

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 29 of 31 Figure 3. 209-ball FBGA (14 x 22 x1.76 mm) (51-851 67) Package Diagrams (continued) 51-85167-** [+] Feedback[...]

  • Page 30

    CY7C1441A V33 CY7C1443A V33,CY7C1447A V33 Document #: 38-05357 Rev . *G Page 30 of 31 Document History Page Document Title: CY7C1441A V33/CY7C1443A V33/CY7C1447A V33 36-Mbit (1M x 36/2M x 18/512K x 72) Flo w-Through SRAM Document Number: 38-05357 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 124459 03/06/03 CJM New Data Sheet *A[...]

  • Page 31

    Document #: 38-05357 Rev . *G Revised May 09, 2008 Page 31 of 31 i486 is a trade mark, and Intel a nd Pentium are r egistered trad emarks of Intel C orporation. Po werPC is a tradem ark of IBM Corpor ation. All pro duct and comp any names ment ioned in this do cument are the tr ad emarks of their respe ctive holder s. CY7C1441A V33 CY7C1443A V33,CY[...]