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Cypress CY7C1486V25 manual

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  • Page 1

    72-Mbit (2M x 36 /4M x 18/1M x 72) Pipelined Sync SRAM CY7C1480V25 CY7C1482V25 CY7C1486V25 Cypress Semiconductor Corpora tion • 198 Champion Court • San J ose , CA 95134-1709 • 408-943-2600 Document #: 38-05282 Rev . *H Revised April 23, 2007 Features • Supports bus operation up to 250 MH z • Available speed grades are 250, 200, and 167 M[...]

  • Page 2

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 2 of 32 Logic Block Diagram – CY7C1480V25 (2 M x 36) Logic Block Diagram – CY7C1482V25 (4 M x 18) ADDRESS REGISTER ADV CLK BURST COUNTER AND LOGIC CLR Q1 Q0 ADSP ADSC MODE BWE GW CE 1 CE 2 CE 3 OE ENABLE REGISTER OUTPUT REGISTERS SENSE AMPS OUTPUT BUFFERS E PIPELINED ENABLE [...]

  • Page 3

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 3 of 32 Logic Block Diagram – CY7C1486V25 (1 M x 72) BW D BW C BW B BW A BWE GW CE1 CE2 CE3 OE ENABLE REGISTER PIPELINED ENABLE ADDRESS REGISTER ADV CLK BINARY COUNTER CLR Q1 Q0 ADSP ADSC MODE A 0, A1,A A[1:0] BW F BW E BW H BW G DQs DQP A DQP B DQP C DQP D DQP E DQP F DQP G D[...]

  • Page 4

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 4 of 32 Pin Configurations 100-Pin TQFP Pinout DQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP A DQP C DQ C DQc V DDQ V SSQ DQ C DQ C DQ C DQ C V SSQ V DDQ DQ C DQ C V DD NC[...]

  • Page 5

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 5 of 32 Pin Configurations (continued) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1480V25 (2M x 36) CY7C1482V25 (4M x 18) 234 5 67 1 A B C D E F G H J K L M N P R TDO NC/288M NC/144M DQP C DQ C DQP D NC DQ D CE 1 BW B CE 3 BW C BWE A CE2 DQ C DQ D DQ D MODE NC DQ C DQ C DQ D DQ[...]

  • Page 6

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 6 of 32 Pin Configurations (continued) CY7C1486V25 (1M × 72) 209-Ball FBGA (14 x 22 x 1.76 mm) Pi nout A B C D E F G H J K L M N P R T U V W 123456789 1 1 10 DQ G DQ G DQ G DQ G DQ G DQ G DQ G DQ G DQ C DQ C DQ C DQ C NC DQP G DQ H DQ H DQ H DQ H DQ D DQ D DQ D DQ D DQP D DQP C[...]

  • Page 7

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 7 of 32 Pin Definitions Pin Name I/O Description A 0 , A 1 , A Input- Synchronous Address Inputs used to select one of the address locatio ns . Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW , and CE 1 , CE 2 , and CE 3 are sampled active. A1: A0 are fed to [...]

  • Page 8

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 8 of 32 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CO ) is 3.0 ns (250 [...]

  • Page 9

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 9 of 32 DQs are automatically tri-stat ed whenever a write cycle is detected, regardless of the state of OE . Single Write Accesses Initiated by ADSC ADSC Write accesses are initiated when the following condi- tions are satisfied: (1) ADSC is asserted LOW , (2) ADSP is deasserte[...]

  • Page 10

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 10 of 32 Notes 3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW . 4. WRITE = L when any one or more Byte Write Enab le signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE , GW = H. 5. The DQ pins are controlled by the current cycle and the[...]

  • Page 11

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 1 1 of 32 T ruth T able for Read/Write The read/write truth table for the CY7C1480V25 follows. [5] Function GW BWE BW D BW C BW B BW A R e a d H HXXXX R e a d H L HHHH Wri t e B yt e A – (D Q A and DQP A ) H L HHH L Write Byte B – (DQ B and DQP B )H L H H L H Write Bytes B, [...]

  • Page 12

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 12 of 32 IEEE 1 149.1 Serial Boundary Scan (JT AG) The CY7C1480V25/CY7C148 2V25/CY7C1486V25 incorpo- rates a serial boundary scan test access port (T AP). This port operates in accordance with IEEE S tandard 1 149.1-1990 but does not have the set of functions required fo r full [...]

  • Page 13

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 13 of 32 Instruction Register Three-bit instructions can be serially loaded into the instruction register . This register is loaded w hen it is placed betwe en the TDI and TDO balls as shown in the “T AP Controller Block Diagram” on page 12 . At power up, the instructi on re[...]

  • Page 14

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 14 of 32 The SRAM clock input might no t be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If th is is an issue, it is still possible to capture all other signals an d simply ignore the value of the CLK captured[...]

  • Page 15

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 15 of 32 2.5V T AP AC T est Conditions Input pulse levels ...... .............. ............ .............. .. V SS to 2.5V Input rise and fall time ........... ........... .............. ........... ...... 1 ns Input timing referenc e levels ....................... ............[...]

  • Page 16

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 16 of 32 Scan Register Sizes Register Name Bit Size (x36) Bit Size (x18) Bit Size (x72) Instruction 3 3 3 Bypass 1 1 1 ID 32 32 32 Boundary Scan Order – 165 FBGA 73 54 - Boundary Scan Order – 209 BGA - - 1 12 Identification Codes Instruction Co de Description EXTEST 000 Capt[...]

  • Page 17

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 17 of 32 Boundary Scan Exit Order (4M x 18) Bit # 165-Ball ID Bit # 165-Ba ll ID Bit # 165-Ball ID 1D 2 1 9 R 8 3 7 C 1 1 2E 2 2 0 P 3 3 8 A 1 1 3F 2 2 1 P 4 3 9 A 1 0 4G 2 2 2 P 8 4 0 B 1 0 5J 1 2 3 P 9 4 1 A 9 6 K1 24 P10 42 B9 7L 1 2 5 R 9 4 3 A 8 8M 1 2 6 R 1 0 4 4 B 8 9N 1 [...]

  • Page 18

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 18 of 32 Boundary Scan Exit Order (1M x 72) Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID 1 A1 29 T 1 57 V10 85 C1 1 2A 2 3 0 T 2 5 8 U 1 1 8 6 C 1 0 3 B1 31 U1 59 U10 87 B1 1 4B 2 3 2 U 2 6 0 T 1 1 8 8 B 1 0 5 C1 33 V1 61 T10 89 A1 1 6C 2 3 4 V 2 6 2 R[...]

  • Page 19

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 19 of 32 Maximum Ratings Exceeding the maximum rati ngs may impair the useful life of the device. The se user guid elines are no t tested. S torage T emperature .. .............. ................. –65 ° C to +150 ° C Ambient T e mperature with Power Applied .................[...]

  • Page 20

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 20 of 32 Cap acit ance [14] Parameter Description T est Conditions 100 TQFP Package 165 FBGA Package 209 FBGA Package Unit C ADDRESS Address Input Capa citance T A = 25 ° C, f = 1 MHz, V DD = 2.5V V DDQ = 2.5V 66 6 p F C DA T A Data Input Capacitance 5 5 5 pF C CTRL Control Inp[...]

  • Page 21

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 21 of 32 Notes 15. T iming reference level is 1.25V when V DDQ = 2.5V and is 0.9V w hen V DD Q = 1.8V . 16. T est conditions shown in (a) of “AC T est Loads and W aveforms” on pa ge 20 unless otherwise not ed. 17. This part has a volt age regulator internally; t POWER is the[...]

  • Page 22

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 22 of 32 Switching W aveforms Read Cycle Timing [21] t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t CEH t CES GW, BWE, BWx D ata Out (Q) High-Z t CLZ t DOH t CO ADV t OEHZ t CO Single READ BURST READ t OEV t OELZ t CHZ ADV suspends burst. Burst wraps arou[...]

  • Page 23

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 23 of 32 Write Cycle T iming [21, 22] Switching W aveforms (continued) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A1 t CEH t CES BWE, BW X D ata Out (Q) High-Z ADV BURST READ BURST WRITE D(A2) D(A2 + 1) D(A2 + 1) D(A1) D(A3) D(A3 + 1) D(A3 + 2) D(A2 + 3) A[...]

  • Page 24

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 24 of 32 Read/Write Cycle Timing [21, 23, 24 ] Switching W aveforms (continued) t CYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE t AH t AS A2 t CEH t CES D ata Out (Q) High-Z ADV Single WRITE D(A3) A4 A5 A6 D(A5) D(A6) Data In (D) BURST READ Back-to-Back READs High-Z Q(A2[...]

  • Page 25

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 25 of 32 ZZ Mode T iming [25, 26] Switching W aveforms (continued) t ZZ I SUPPLY CLK ZZ t ZZREC A LL INPUTS (except ZZ) DON’T CARE I DDZZ t ZZI t RZZI Outputs (Q) High-Z DESELECT or READ Only Notes 25. Device must be deselected whe n entering ZZ mode. See “T ruth T able” o[...]

  • Page 26

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 26 of 32 Ordering Information Not all of the speed, package and temperature ranges are available. Please co ntact your local sales represe ntative or visit www .cypress .com for a ctual prod ucts offered. Spee d (MHz) Ordering Co de Package Diagram Part and Packag e T ype Operat[...]

  • Page 27

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 27 of 32 250 CY7C1480 V25-250AXC 51-85050 100-Pin Thin Quad F lat Pack (14 x 20 x 1.4 mm) Lead-Free Commercia l CY7C1482V25-250AXC CY7C1480V25-250BZC 51-85165 165-ball Fine-Pitc h Ball Grid Array (15 x 17 x 1.4 mm) CY7C1482V25-250BZC CY7C1480V25-250BZXC 51-85165 165-ball Fine-Pi[...]

  • Page 28

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 28 of 32 Package Diagrams Figure 1. 100-Pin Thin Plastic Quad Fl atpack (14 x 20 x 1.4 mm), 51-8 5050 NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE 3. DIME[...]

  • Page 29

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 29 of 32 Figure 2. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165 Package Diagrams (continued) A 1 PIN 1 CORNER 17.00±0.10 15.00±0.10 7.00 1.00 Ø0.45±0.05(165X) Ø0.25 M C A B Ø0.05 M C B A 0.15(4X) 0.35 1.40 MAX. SEATING PLANE 0.53±0.05 0.25 C 0.15 C PIN 1 CORNER TOP VIEW BOT[...]

  • Page 30

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 30 of 32 © Cypress Semico nductor Corpor ation, 2002- 2007. The inform ation contai ned herein is sub ject to change wi thout notice. Cypr ess S emiconduct or Corporation a ssumes no responsi bility for the use of any circuitr y other than circui try embodied in a Cy press prod[...]

  • Page 31

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 31 of 32 Document History Page Document Title: CY7C1480V25/CY7C1482V25 /CY7C1486V25 72 -Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sy nc SRAM Document Number: 38-05282 REV . ECN NO. Issue Date Orig. of Change Description of Chan ge ** 1 14670 08/06/02 PKS New Data Sheet *A 1 18281[...]

  • Page 32

    CY7C1480V25 CY7C1482V25 CY7C1486V25 Document #: 38-05282 Rev . *H Page 32 of 32 *G 4866 90 See ECN VKN Corrected the typo in the 209-Ball FBGA pinout. (Corrected the ball name H9 to V SS from V SSQ ). *H 102 6720 See ECN VKN/KKVTMP Added footnote #2 related to V SSQ Document Title: CY7C1480V25/CY7C1482V25 /CY7C1486V25 72 -Mbit (2M x 36/4M x 18/1M x[...]