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Cypress STK14CA8 manual

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Table of contents for the manual

  • Page 1

    STK14CA8 128Kx8 AutoS tore ™ nvSRAM Cypress Semiconducto r Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-51592 Rev . ** Revised March 04, 2009 Features ■ 25, 35, 45 ns Read Access and Read/Write Cycle Time ■ Unlimited Read/Write Endurance ■ Automatic No nvolatile STORE on Power Loss ?[...]

  • Page 2

    STK14CA8 Document Number: 001-51592 Rev . ** Page 2 of 16 Pinout s Figure 1. 48-Pin SSOP Figure 2. 32-Pin SOIC Figure 3. Relative PCB Area Usage [1] Pin Descriptions V SS A 14 A 12 A 7 A 6 DQ 0 DQ 1 V CC DQ 2 A 3 A 2 A 1 V CAP A 13 A 8 A 9 A 11 A 10 DQ 7 DQ 6 V SS A 0 NC 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 [...]

  • Page 3

    STK14CA8 Document Number: 001-51592 Rev . ** Page 3 of 16 Absolute Maximum Ratings V oltage on Input Relati ve to Ground ................. –0.5V to 4.1V V oltage on Input Relative to V SS ...........–0.5V to (V CC + 0.5V) V oltage on DQ 0-7 or HSB .............. ... ..... –0.5V to (V CC + 0.5V) T emperature under Bias .................... ...[...]

  • Page 4

    STK14CA8 Document Number: 001-51592 Rev . ** Page 4 of 16 AC T est Conditions Input Pulse Levels ..................... ...................... ......... 0V to 3V Input Rise and Fall Times ... ......... ........... ......... ........... ...... ≤ 5 ns Input and Output T iming Reference Levels ................ .... 1.5V Output Load .............. ...[...]

  • Page 5

    STK14CA8 Document Number: 001-51592 Rev . ** Page 5 of 16 SRAM READ Cycles #1 and #2 Figure 6. SRAM READ Cycle #1: Address Controlled [3, 4, 6] Figure 7. SRAM READ Cycle #2: E and G Controlled [3, 6] NO. Symbols Parameter STK14CA8-25 STK14CA8-35 STK14CA8-45 Unit s #1 #2 Alt. Min Max Min Max Min Max 1 t ELQV t ACS Chip Enable Access T ime 25 35 45 n[...]

  • Page 6

    STK14CA8 Document Number: 001-51592 Rev . ** Page 6 of 16 SRAM WRITE Cycles #1 and #2 Figure 8. SRAM WRITE Cycle #1: W Controlled [7,8] Figure 9. SRAM WRITE Cycle #2: E Controll ed [7,8] NO. Symbols Parameter STK14CA8-25 STK14 CA8-35 STK14CA8-45 Unit s #1 #2 Alt. Min Max Min Max Min Max 12 t AVAV t AVAV t WC Write Cycle T ime 25 3 5 45 ns 13 t WL W[...]

  • Page 7

    STK14CA8 Document Number: 001-51592 Rev . ** Page 7 of 16 AutoS tore/POWER UP RECALL t Figure 10. AutoStore/POWER UP RECALL Note Read and Write cycles are ignored during STORE, RECALL, and while V CC is below V SWITCH. NO. Symbols Parameter STK14CA8 Units Notes Stan da r d Alternate Min Max 22 t HRECALL Power up RECALL Duration 20 ms 9 23 t STORE t[...]

  • Page 8

    STK14CA8 Document Number: 001-51592 Rev . ** Page 8 of 16 Sof tware Controlled ST ORE/RECALL Cycle Figure 1 1. Sof tware STORE/RECALL CYCLE: E Controlled [13] Figure 12. Software STORE/RECALL CYCLE: G Co n t ro lled [13] NO. Symbols Parameter [12,13] STK14CA8-35 STK14CA8-35 STK14CA8-45 Units Notes E Cont G Cont Alt Min Max Min Max Min Max 26 t AVAV[...]

  • Page 9

    STK14CA8 Document Number: 001-51592 Rev . ** Page 9 of 16 Hardware STORE Cycle Figure 13. Hardware STORE Cycle Sof t Sequence Commands Figure 14. Software Sequence Commands NO. Symbols Parameter STK14CA8 Units Notes St andard Alte rnate Min Max 31 t DELA Y t HLQZ Hardware STORE to SRAM Disabled 1 70 μ s 1 4 32 t HLHX Hardware STORE Pulse Wid th 15[...]

  • Page 10

    STK14CA8 Document Number: 001-51592 Rev . ** Page 10 of 16 Mode Selection E W G A 16 -A 0 Mode I/O Power Notes H X X X Not Selected Output High Z S tandby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L H L 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F 0x08B45 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoS tore Disabl[...]

  • Page 11

    STK14CA8 Document Number: 001-51592 Rev . ** Page 1 1 of 16 nvSRAM Operation nvSRAM The STK14CA8 nvSRAM has two functional compone nts paired in the same physical cell. T hese are the SRAM memory ce ll and a nonvolatile QuantumTrap cell. The SRAM memory cell operates similar to a standard fast static RAM. Dat a in th e SRAM can be transferred to th[...]

  • Page 12

    STK14CA8 Document Number: 001-51592 Rev . ** Page 12 of 16 Sof tware ST ORE Data can be transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK14CA8 software STORE cycle is initia ted by executin g sequential E controlled or G controlled READ cycles from six specific addre ss locations in exact order . During the[...]

  • Page 13

    STK14CA8 Document Number: 001-51592 Rev . ** Page 13 of 16 Low A verage Active Po wer CMOS technology provide s the STK14CA8 with the benefit of power supply current that scales with cycle time . Less c urrent is drawn as the memory cycle time becomes longer th an 50 ns. Figure 16 shows the relationship between I CC and READ/WRITE cycle time. Worst[...]

  • Page 14

    STK14CA8 Document Number: 001-51592 Rev . ** Page 14 of 16 Ordering Information Ordering Codes Packing Option Blank=T ube TR=T ape and Reel T em perature Range Blank=Commercial (0 to +70 C ) I= Industrial (-45 to +85 C) Access Time 25=25 ns 35=35 ns 45=45 ns Lead Fini sh F=100% Sn (Matte Tin) RoHS Compliant Package N=Plastic 32-pin 300 mi l SOIC (5[...]

  • Page 15

    STK14CA8 Document Number: 001-51592 Rev . ** Page 15 of 16 Package Diagrams Figure 17. 32-Pin 300 mil SOIC (51-85127) Figure 18. 48-Pin 300 mil SSOP (51-85061) 51-85127 *A 51-85061 *C [+] Feedback[...]

  • Page 16

    Document Number: 001-51592 Rev . ** Revised March 04, 2009 Page 16 of 16 AutoStore and Quant umTrap are regis tered tradem arks of Cypres s Semico nduct or Corpo ration. All oth er prod ucts and company name s mentioned in this docu ment may be the trademarks of their respecti ve holders . STK14CA8 © Cypress Semiconducto r Corporation, 2009. The i[...]