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Cypress CYV15G0404DXB manual

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  • Page 1

    CYV15G0404DXB Independent Clock Quad HOTLink II™ T ransceiver with Reclocker Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-02097 Rev . *B Revised December 14, 2007 Features ■ Quad channel tra nsceiver for 195 to 1 500 MBaud serial signaling rate ❐ Aggregate throughput of[...]

  • Page 2

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 2 of 44 The CYV15G0404DXB satisfies the SMPTE-259M and SMPTE-292M compliance according to SMPTE EG34-1999 Pathological T est Requireme nts. As a second generation HOTLink d evice, the CYV15G0404DXB extends the HOTLink fa mily with enhan ced levels of integra tion and faster data rates, while maintain[...]

  • Page 3

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 3 of 44 Shifter TXLBA TXLBC T ransmit Path Block Diagram TXRA TEA Input Register Phase-Align Buff er Encoder BIST LFSR SPDSELA REFCLKA+ REFCLKA– T ransmit PLL Clock Multiplier TXCLKA Bit-Rate Clock Character-Rate Clock A OUT A1+ OUT A1– OUT A2+ OUT A2– 8 TXRA TEB Input Register Phase-Alig n Buf[...]

  • Page 4

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 4 of 44 INA1+ INA1– INA2+ INA2– INSELA INB1+ INB1– INB2+ INB2– INSELB INC1+ INC1– INC2+ INC2– INSELC IND1+ IND1– IND2+ IND2– INSELD Clock & Data Recovery PLL Shifter Clock & Data Recovery PLL Shifter Clock & Data Recovery PLL Shifter Clock & Dat a Recovery PLL Shifter [...]

  • Page 5

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 5 of 44 WREN ADDR[3:0] DA T A[7:0] Device Configuration and Control Block = Internal Signal RXRA TE[A..D] FRAMCHAR[A..D] RFEN[A..D] RXCKSEL[A. .D] RFMODE[A..D ][1:0] RXBIST[A.. D] DECMODE[A..D] DECBYP[A..D] SDASEL[A.. D][1:0] RXPLLPD[A..D ] TXRA TE[A..D] TXCKSEL[A..D] TXBIST[A..D ] OE[A..D][2..1 ] P [...]

  • Page 6

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 6 of 44 Pin Configuration (T op View) 123456789 10 11 12 13 14 15 16 17 18 19 20 A IN C1– OUT C1– IN C2– OUT C2– V CC IN D1– OUT D1– GND IN D2– OUT D2– IN A1– OUT A1– GND IN A2– OUT A2– V CC IN B1– OUT B1– IN B2– OUT B2– B IN C1+ OUT C1+ IN C2+ OUT C2+ V CC IN D1+ OUT [...]

  • Page 7

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 7 of 44 Pin Configuration (Bottom View) 20 19 18 17 16 15 14 13 12 11 10 987654321 A OUT B2– IN B2– OUT B1– IN B1– V CC OUT A2– IN A2– GND OUT A1– IN A1– OUT D2– IN D2– GND OUT D1– IN D1– V CC OUT C2– IN C2– OUT C1– IN C1– B OUT B2+ IN B2+ OUT B1+ IN B1+ V CC OUT A2+ I[...]

  • Page 8

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 8 of 44 Pin Definitions CYV15G0404DXB Quad HO TLink II T ransceiver Name I/O Characteristics Signal Description T ransmit Path Dat a and St atus Signals TXDA[7:0] TXDB[7:0] TXDC[7:0] TXDD[7:0] L VTTL Input, synchronous, sample d by the associated TXCLKx ↑ or REFCLKx ↑ [2] T ransmit D at a Inpu t [...]

  • Page 9

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 9 of 44 TXCLKOA TXCLKOB TXCLKOC TXCLKOD LV T T L O u t p u t T ransmit Cl ock Outp ut . TXCLKOx output clock is syn thesized by each channel’s transmit PLL and operates synchronous to the internal tran smit character clock. TXCLKOx operates at either th e same freq uency as REF CLKx± (TXRA TE = 0)[...]

  • Page 10

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 10 of 44 LDTDEN L VTTL Input, internal pull up Level Detect T ran sition Density Enable . When LDTDEN is HIGH , the signal le ve l detector , range controller , and transition den si ty detector are al l enabled to determin e if the RXPLL tracks REFCLKx± or the selected input serial data stream. If [...]

  • Page 11

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 1 1 of 44 LFIA LFIB LFIC LFID L VTTL Output, asynchronous Link Fault I ndication O utput . LFIx is an output status indicator sign al. LFIx is the logical OR of five internal cond itions. LFIx is asserted LOW wh en any of these condi- tions are true: ■ Received serial data rate outside expected ran[...]

  • Page 12

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 12 of 44 CYV15G0404DXB HOTLi nk II Operation The CYV15G0404DXB is a hig hly configurable, independe nt clocking, quad-channel transceiver designe d to support reliable transfer of large quantities of data, using high spee d serial lin ks from multiple sources to multiple destinations. This device sup[...]

  • Page 13

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 13 of 44 Once initialized, TXCLKx is allo wed to drift in phase as much a s ±180 degrees. If the input pha se of TXCLKx drifts beyond the handling capacity of the phase align buffer , TXERRx is asserted to indicate the l oss of data, and remains asserted until the p hase align buffer is initialized.[...]

  • Page 14

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 14 of 44 T ransmit Modes Encoder Bypass When the Encoder is bypassed, the character captured from the TXDx[7:0] and T XCTx[1:0] input regi s t e r i s p a s s e d d i r e c t l y t o t h e transmit shifter without modification. With the encod er bypassed, the TXCTx[1:0] inputs are consider ed part of[...]

  • Page 15

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 15 of 44 The REFCLKx± inputs are differential inputs with each inp ut internally biased to 1.4V . If th e REFCLKx+ input is connecte d to a TTL, L VTTL, or L VCMOS clock source, the inpu t signal is recognized when it passes through the internally biased reference point. When driven by a single-ende[...]

  • Page 16

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 16 of 44 T ransition Density The transition detection lo gic checks for the absen ce of transi- tions spanning greater than six transmission characters (60 bits). If no transitions are present in the da ta received, the detection logic for that channel asserts LFIx . Range Controls The CDR circuit in[...]

  • Page 17

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 17 of 44 through the FRAMCHARx latche s through the configuration interfac e. The specific bit combinations of these framing characters are listed in T able 6 . When the sp ecific bi t combinatio n of the selected framing ch aracter is detected b y the framer , the bound- aries of the characters pres[...]

  • Page 18

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 18 of 44 Code rule violations or running d isparity errors that occur as part of the BIST loop do not cause an error indication. RXSTx[2:0] indicates 010b or 10 0b for one character period p er BIST loop to indicate loop co mpletion. This status can be used to check test pattern progress. These same [...]

  • Page 19

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 19 of 44 When the 10B/8B decode r is bypa ssed, the framed 10 -b i t val u e is presented to th e associated output register , along with a status output signal indicating if the ch aracter i n the output register is one of the selected framing ch aracters. The bit usage and mapping of the external s[...]

  • Page 20

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 20 of 44 12, 13, and 14 con sist of global configuration bits and the last latch bank (15) is the mask latch bank that can be configured to perform bit-by-bit config uration . Global Enable Function The global enable function, controlled by th e GLENx bits, is a feature that is used to reduce the num[...]

  • Page 21

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 21 of 44 RXCKSELA RXCKSELB RXCKSELC RXCKSELD Receive Clock Select . The initialization value of the R XCKSELx latch = 1. RXCKSELx selects the receive clock source used to transfer data to the Output Regi sters and the clock source for the RXCLK ± outpu t. When RXCKSELx = 1, the associated Output Reg[...]

  • Page 22

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 22 of 44 TXRA TEA TXRA TEB TXRA TEC TXRA TED T ransmit PL L Clock Rate Select . Th e initializati on value of the TXRA TEx latch = 0. TX RA TEx is used to select the clock multiplier for the Transmit PLL. When TXRA TE x = 0, ea ch transmit PLL multiples the associated REFCLKx± input by 10 to generat[...]

  • Page 23

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 23 of 44 Device Configuration Strategy The following is a se ries of ordered events needed to load the configuration latches on a per channel basis: 1. Pulse RESET Low after device power up. This operation resets all four channels. Initialize the JT AG state machine to its reset state as detailed in [...]

  • Page 24

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 24 of 44 3-Level Sele ct Input s Each 3-Level select inputs reports as two bits in the scan register . These bits report the LOW , MID, and HIGH state of the associated input as 00, 10, and 1 1 respectively . JT AG ID The JT AG device ID for the CYV15G0404DXB is ‘0C81 1069’x . Receive Character S[...]

  • Page 25

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 25 of 44 Figure 2. Receive BIST St ate Machine Receive BIST Detected LOW Monitor Data Received RXSTx = BIST_ST ART (101) No RX PLL Out of Lock Y es, RXSTx = BIST_DA T A_COMP AR E (000) / BIST_COMMAND_COMP ARE (001) Compa re Next Character Auto-Abort Condition Mismatch End-of-BIST St a t e Y es, RXSTx[...]

  • Page 26

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 26 of 44 Maximum Ratin gs Exceeding maximum ratings may im pair the useful life of device. These user g uid elines ar e no t te ste d . S torage T emperature ................. .............. ... –65 °C to +150°C Ambient T emperature with Power Applied ............ ............................. ..[...]

  • Page 27

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 27 of 44 Differential CML Serial Output s: OUT A1 ± , OUT A2 ± , OUTB1 ± , OUTB2 ±, OUT C1 ± , OUTC2 ± , OUTD1 ± , OUTD2 ± V OHC Output HIGH V oltage (V cc Referenced) 100 Ω differential loa d V CC – 0.5 V CC – 0.2 V 150 Ω differential load V CC – 0.5 V CC – 0.2 V V OLC Output LOW V[...]

  • Page 28

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 28 of 44 CYV15G0404DXB AC Electr ical Characteristics Parameter Description Min. Max Unit CYV15G0404DXB T ransmitter L VTTL Switching Characteristics Over the Operating Range f TS TXCLKx Clock Cycle Frequency 19.5 150 MHz t TXCLK TXCLKx Period=1/f TS 6.66 51.28 ns t TXCLKH [ 20] TXCLKx HIGH Time 2.2 [...]

  • Page 29

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 29 of 44 t TREFDS T ransmit Data Set-up T ime to REFCLKx - Full Rate (TXRA TEx = 0, TXCKSELx = 1) 2.4 ns T ransmit Dat a Set-up T ime to REFCLKx - Half Rate (TXRA TEx = 1, TXCKSELx = 1) 2.3 ns t TREFDH T ra nsmit Data Hold T ime from REFCLKx - Full Rate (TXRA TEx = 0, TXCKSELx = 1) 1.0 ns T ransmit D[...]

  • Page 30

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 30 of 44 t RISE [20] CML Output Rise T ime 20 − 80% (CML T est Lo ad) SPDSELx = HIGH 60 270 ps SPDSELx = MID 100 500 ps SPDSELx =LOW 180 1000 ps t FA L L [20] CML Output Fall T ime 80 − 20% (CML T est Load) SPDSELx = HIGH 60 270 p s SPDSELx = MID 100 500 ps SPDSELx =LOW 180 1000 ps t DJ [20, 29, [...]

  • Page 31

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 31 of 44 Note 33. When REFCLKx± is configured for half rate opera tion (TXRA TE = 1) and dat a is captured using REFCLKx instead of a TXCLKx cloc k. Data is capt ured using both the rising and falling ed ges of REFCLKx. CYV15G0404DXB HOTLink II T ran smitter Switching W aveforms (continued) t TREFDH[...]

  • Page 32

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 32 of 44 Switching W aveforms for the CY V15G0404DXB HOTLink II Receiver Notes 34. The TXCLK Ox output remains at the characte r rate regardless of the st ate of TXRA TE and does not follow t he duty cycle of REF CLKx±. 35. The rising edge of TXCLKOx outpu t has no dire ct phase relati onship t o th[...]

  • Page 33

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 33 of 44 Note 37. When operated with a half rate REFCLKx±, the setup and ho ld specifications for dat a relative to RXCLKx are relative to bot h rising and falling edg es of the respective clock out put Switching W aveforms for the CY V15G0404DXB HOTLink II Receiver RXCLKx+ RXDx[7:0], RXSTx[2:0] t R[...]

  • Page 34

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 34 of 44 T able 1 1. Package Coordinate Signal Allocation Ball ID Signal Name Signal T ype Ball ID Signal Name Signal T ype Ball ID Signal Name Signal T ype A01 INC1– CML IN C07 ULCC L VTTL IN PU F17 RCLKENA L VTTL IN PD A02 OU TC1– CML OUT C08 GND GROUND F18 RXSTB[1] L VTTL OUT A03 INC2– CML I[...]

  • Page 35

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 35 of 44 C04 INSELB L VTTL IN F02 RXDC[7] L VTTL OUT L20 TXDB[6] L VTTL IN C05 VCC POWER F03 TXDC[0] L VTT L IN M01 RXDC[4] L VTT L OUT C06 U LCD L VTTL IN PU F04 RCLKEND L VTTL IN PD M02 RXDC[5] L VTTL OUT M03 R CLKENC L VTTL IN PD U03 TXDD[2] L VTTL IN W03 LFID LV T T L O U T M04 TXERRC L VTTL OUT [...]

  • Page 36

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 36 of 44 X3.230 Codes and Not ation Conventions Information transmitted over a serial link is encode d eight bits at a time into a 1 0-bit T ransmission Character a nd then sent serially , bit-by-bit. Information received over a serial link i s collected ten bits at a time, and those transmission cha[...]

  • Page 37

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 37 of 44 mission of any transmission charac ter , the transmit ter selects the proper version of the transmission character base d on the current running disparity value, and the transmitter calculates a new value for its running disparity based on the co ntents of the transmitted character . S pecia[...]

  • Page 38

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 38 of 44 T a b l e 1 4 . Val i d D a ta C h a r a c t e r s ( T X C T x [ 0 ] = 0, RXSTx[2:0] = 000) Data Byte Name Bit s Current RD − Current RD+ Data Byte Name Bits Current RD − Current RD+ HGF EDCBA abcd ei fghj abcd ei fghj HGF EDCBA abcdei fg hj abcdei fg hj D0.0 000 00000 100111 0100 011000[...]

  • Page 39

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 39 of 44 D0.2 010 00000 100111 0101 011000 0101 D0.3 011 00000 100111 0011 011000 1100 D1.2 010 00001 011101 0101 100010 0101 D1.3 011 00001 011101 0011 100010 1100 D2.2 010 00010 101101 0101 010010 0101 D2.3 011 00010 101101 0011 010010 1100 D3.2 010 00011 110001 0101 110001 0101 D3.3 011 00011 1100[...]

  • Page 40

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 40 of 44 D0.4 100 00000 100111 0010 011000 1101 D0.5 101 00000 100111 1010 011000 1010 D1.4 100 00001 011101 0010 100010 1101 D1.5 101 00001 011101 1010 100010 1010 D2.4 100 00010 101101 0010 010010 1101 D2.5 101 00010 101101 1010 010010 1010 D3.4 100 00011 110001 1101 110001 0010 D3.5 101 00011 1100[...]

  • Page 41

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 41 of 44 D0.6 110 00000 100111 0110 011000 0110 D0.7 111 00000 100111 0001 011000 1110 D1.6 110 00001 011101 0110 100010 0110 D1.7 111 00001 011101 0001 100010 1110 D2.6 110 00010 101101 0110 010010 0110 D2.7 111 00010 101101 0001 010010 1110 D3.6 110 00011 110001 0110 110001 0110 D3.7 111 00011 1100[...]

  • Page 42

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 42 of 44 T ab l e 1 5 . Val i d Sp e c i a l C h a r a c t e r C o d e s a n d S e q u e n c e s ( T X C T x = special character code or RXSTx[2:0] = 001) [38, 39] S.C. Code Name S.C. Byte Name Current RD − abcdei fghj Current RD+ abcdei fghj Cypress Alternate S.C. Byte Name [40] Bit s HGF EDCBA S.[...]

  • Page 43

    CYV15G0404DXB Document #: 38-02097 Rev . *B Page 43 of 44 Ordering Information Spee d Orderin g Code Packag e Name Package T ype Operating Range S tandard CYV15G0404DXB-BGC BL256 256-Ball Ther ma lly Enhanced Ball Grid Array Commerci al S tandard CYV15G0404DXB-BGI BL256 256-Ball Therma lly Enha nced Ball Grid Array Industrial Package Diagram 256-Le[...]

  • Page 44

    Document #: 38-02097 Rev . *B Revised December 14, 2007 Page 44 of 44 IBM and ESCON are regi stered trademar ks, and FICON is a trademark, of Int ernational Busine ss Machines. HOTLink is a regi stered tradema rk and HOTLink II and MultiFrame are tr ademarks of Cypress Semicond uctor . All product and compan y names mention ed in this docume nt may[...]