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Fujitsu 16LX manual

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Table of contents for the manual

  • Page 1

    FUJITSU M ICRO ELECTRONIC S EUROPE De ve l op ment tool s f or 16 LX Fami l y CPU Board User Guide [...]

  • Page 2

    DEVELOP MENT TO O LS F OR 16 L X F AMILY &38% RDU G8V HU * XL GH[...]

  • Page 3

    7 DEOH RI &RQW HQW What is i n T his Guide .......................................................................................................... ..................................................................................................... 2 Wh at is not i ncl uded i n th is gu ide .............................................[...]

  • Page 4

    W hat you’l l f ind i nside t his g uide and f ew words ab out its organi zation PU Bo ard in i t s inter face to the Devki t 16 Mainboar d i s desig ned in such a wa y t ha t it is p o ss ib le t o us e d iffer e nt C PU bo a r ds ( wit h var io us me mb er s o f t he 16LX f amily) wi t h the sam e Ma i nboard. Thi s gu ide describes how to use [...]

  • Page 5

    P l ease visi t DevKi t16 WEB si t e www.processor ex p ert.com/dev k i t 16 fo r n e w s a nd g iv eawa ys. Yo u can al so register i n order to obt ai n news by mail. For MCUs an d Fuji t su t ech no l o g i es p lease visit FUJIT SU W EB s i t e h tt p://ww.f u j i t su- fm e.com . When y ou need add i t i o nal CPU perso nali t y board please c[...]

  • Page 6

    Th is c h apter int rod uces featu res of CPU bo ard and pro vi des n ecessary tec hnical an d operational information for DevKit16. he CPU boar d was desig n ed as a rep laceable part of the Devki t 16. So, i t co n t ai ns only few features and t he r est i s pro vi ded b y t he Devki t 16 Ma inb o ard. Po si t i on for a P QFP 100 processo r or [...]

  • Page 7

    If the CPU mou nted on th e CPU board ha s a FL ASH mem ory , th e DevKit 16 FLAS H Pro gramming T ool can be used to program it . DevKi t 16 FLASH Programm ing Tool provi d es s tandard o pera t i o n s (ch eck/p rogra m /ve r ify ) f o r CP U In t e rnal FLA SH m em o ry , Main b oard F LA SH or b oth. Wi t h t h e st an da l o ne CPU b o ard, it[...]

  • Page 8

    This chapte r pr ovide s de taile d de s c r ipti on of CP U b oard incl udi ng all DIP sw itches, ju mpers and con necto rs. CPU boar d can w o rk st andal o ne or in co nnect i o n w i th t he Ma inb oard. If t he Ma inb o ar d is i n us e , pl ease s w itc h al l sw itche s on C P U boar d conf igur ation DIP to OF F . CPU b o ard i s des i g n [...]

  • Page 9

    The ser i a l i nt erface connector sh o ul d be used on l y when the CPU board is no t c onnect ed to the m a inb oar d, because m a inb o ard co nn ect s i t s o wn seri a l (RS232) in t erface to the UART0 an d U A RT1 CPU s i g nals. T o be abl e to use t he K 7 co nnecto r, pl ea se refer t o t h e descr ipt i on o f J7, J8, J9 j umpers later [...]

  • Page 10

    A1 6 A1 8 A2 0 A2 2 AL E GND #WR H #HAK 15 CLK 17 SC K0 19 SIN1 21 FVCC 23 SOT 2 2 5 2 A 17 4 A 19 6 A 21 8 A 23 10 #RD 12 #WR L 14 HRQ 16 RDY 18 SO T0 20 SI N0 22 SC K 1 24 SO T1 26 SCK 2 SO T2 25 26 SI N2 INT4 25 26 INT5 INT6 31 ADT G 3 3 AVR+ 35 AVss 37 A N1 39 A N3 41 A N4 43 A N6 45 TIN 0 47 MD 0 49 32 INT7 34 AV CC 36 AV R - 38 A N0 40 A N2 4[...]

  • Page 11

    When SHORT , t h e +5V f ro m t he v o l t age regul at o r i s co nn ect ed to b o a r d VCC. Thi s jumper m ust b e rem o ved wh e n usi ng an external +5V po wer suppl y t o avoi d current fl o wing back to the regul ato r. When SHORT, t h e VCC is co nnected to CPU’s VCC pins. Before r em o ving t hi s jum per, re m o ve t h e J3 (A VCC to CP[...]

  • Page 12

    These jumpers a llow to use Ma inboar d’s I 2 C c o nnecto r/EE PROM m e m o r y e ven in t h e case, wh en CPU i t se l f do es n’ t provi de t he I 2 C i nt erface. When bot h of these jum p er s are SHORT , the CPU’s HRQ si gnal is connect ed to the Ma inb o ar d’s SDA si g nal (via J19) and #HAK s i g n al i s connected to SCL si g n al[...]

  • Page 13

    4: S-R – i f ON, t his swi t c h connects t he RE S pin o f t he K7 co nn ect o r to t he CPU’s #RS T si gn al . 5: S-H – i f ON, t hi s switc h connect s t he RES pin o f t he K7 connecto r to t he CP U’s #HS T si gn al . 6. H-R – i f ON, t he #RST and #HS T si g nals are co nn e ct ed together. 7: AD00, 8:AD01 – if ON, t h e AD00/P00 [...]

  • Page 14

    These ju mpers co me in the SHORT po si t ion as a default facto r y set t ing: J2 : The CPU is connected to t he +5V p o wer supp ly t hro ugh t his jumper J3 : The CPU A VCC supply pin is co nnected +5V po wer suppl y t hro ugh this jum per J4 : The CPU A GND supply p in is co nnect ed to the GND thro ugh t hi s jumper J5 : The CPU AVR+ pin is co[...]

  • Page 15

    CPU bo ard does not c om e with power sup p ly , please ch eck, if you r po wer s upply matc h the req uir e me nts bef ore y ou pl ug it t o the CPU bo ard! Power supply vo l t age: 9V Po wer suppl y current (CPU b oard MB90F543 wi th Main board conn ected) : S in g le chi p CPU mode, no externa l per i p hera l co nnected: 290mA max . Exter nal b[...]

  • Page 16

    To t he max imu m e xten t per mi tted b y applic able law , Fuj itsu Mic roe lec tronic s E uro pe Gmb H rest r ic ts its w arra nties and its liab ility for the DEVKIT16 and all its deliver ables (eg. sof t ware, appl icat io n ex amp les , ta rge t bo ar ds , ev aluatio n bo ar ds , etc .), i ts pe r f ormanc e a n d a n y co nse que n tia l da [...]

  • Page 17

    The foll owi ng b ugs have bee n found with the boar d a nd need t o be observed when wo r king with t h is tool: Date Revisions - Err o rs Revised Version 05.11. 1999 Version 1.2 i s valid for CPU B o ard ver. 1.3 V1.2 13.02.2000 Th e ta bl e “ Dev i c e B us (K 2 ) a n d In ter f ace Bus (K1 ) co nn ect or s p ins ” ( p ag es 16 , 1 7, 18) w [...]

  • Page 18

    Here you will f ind I nterf ace bus a nd De vic e B us des c rip ti on a nd CP U board s c hema tics . DIN Conn. PI N Device Bus Interf ace Bus PIN NO. CPU Pin Nr. Func ti on CPU PIN Nr. SIGNAL 2n d F unct i on A1 18 SOT 0 85 AD00 P0 0 B1 19 SCK0 86 AD01 P01 C1 20 SIN0 87 AD02 P02 A2 24 SOT 1 88 AD03 P0 3 B2 22 SCK1 89 AD04 P04 C2 21 SIN1 90 AD05 P[...]

  • Page 19

    DIN Conn. PI N Device Bus Interf ace Bus PIN NO. CPU Pin Nr. Func ti on CPU PIN Nr. SIGNAL 2n d F unct i on C10 15 HAK P35 A11 47 TI N0 16 RDY P3 6 B11 48 TOT0 17 CL K P37 C11 GND GND GND A12 67 TI N1 18 SOT0 P40 B12 68 TOT1 19 SCK0 P4 1 C12 20 SIN0 P42 A13 24 SOT1 P45 B13 53 IN0 22 SCK1 P44 C13 54 IN1 21 SIN1 P43 A14 55 IN2 25 SOT 2 P46 B14 56 IN[...]

  • Page 20

    DIN Conn. PI N Device Bus Interf ace Bus PIN NO. CPU Pin Nr. Func ti on CPU PIN Nr. SIGNAL 2n d F unct i on A28 73 TX 0 P94 B28 74 RX0 P95 C28 75 TX 1 P96 A29 76 RX1 P97 B29 79 X1AJ C29 80 X0AJ A30 82 X0J B30 83 X1J C30 VCC VCC A31 49 MD0 B31 50 MD1 C31 NC A32 51 MD2 B32 NC C32 GND GND[...]

  • Page 21

    Title Number Revision Siz e A3 Dat e: 8-D ec-1 999 Sheet of File: D:C puboar d13.ddb Dra wn B y: P00/AD0 0 85 P01/AD0 1 86 P02/AD0 2 87 P03/AD0 3 88 P04/AD0 4 89 P05/AD0 5 90 P06/AD0 6 91 P07/AD0 7 92 P10/AD0 8 93 P11/AD0 9 94 P12/AD1 0 95 P13/AD1 1 96 P14/AD1 2 97 P15/AD1 3 98 P16/AD1 4 99 P17/AD1 5 100 P20/A16 1 P21/A17 2 P22/A18 3 P23/A19 4 P24[...]