IBM 272 manual

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The rules should oblige the seller to give the purchaser an operating instrucion of IBM 272, along with an item. The lack of an instruction or false information given to customer shall constitute grounds to apply for a complaint because of nonconformity of goods with the contract. In accordance with the law, a customer can receive an instruction in non-paper form; lately graphic and electronic forms of the manuals, as well as instructional videos have been majorly used. A necessary precondition for this is the unmistakable, legible character of an instruction.

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First and foremost, an user manual of IBM 272 should contain:
- informations concerning technical data of IBM 272
- name of the manufacturer and a year of construction of the IBM 272 item
- rules of operation, control and maintenance of the IBM 272 item
- safety signs and mark certificates which confirm compatibility with appropriate standards

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After a successful purchase of an item one should find a moment and get to know with every part of an instruction. Currently the manuals are carefully prearranged and translated, so they could be fully understood by its users. The manuals will serve as an informational aid.

Table of contents for the manual

  • Page 1

    IBM PC Institute P ers o n al Sy s tems Ref er e nce PC P r o ce s s o r s February 200 4 - V ersio n 2 72 IBM[...]

  • Page 2

    PC Processors (Celeron - Willamette) Code name Micro-architecture MMX ™ / Streaming SIMD SSE2 L1 cache - bus L1 data cache L1 instruction cache L2 cache - size L2 cache - data path Frontside bus Memory addressability Frontside bus - width Execution units Out-of-order instructions Branch prediction Speculative execution Math coprocessor Compatibil[...]

  • Page 3

    PC Processors (Celeron - Northwood) Code name Micro-architecture MMX ™ / Streaming SIMD SSE2 L1 cache - bus L1 data cache L1 instruction cache L2 cache - size L2 cache - data path Frontside bus Memory addressability Frontside bus - width Execution units Out-of-order instructions Branch prediction Speculative execution Math coprocessor Compatibili[...]

  • Page 4

    PC Processors (Mobile Celeron) - Fall 2001 Vendor Positioning Instruction architecture MMX ™ / Streaming SIMD L1 cache - size L1 cache - write policy L1 cache - organization L1 cache - bus L1 cache - parity L2 cache - size L2 cache - data path L2 cache - buffering L2 cache - organization L2 cache - controller L2 cache - write policy L2 cache - ty[...]

  • Page 5

    PC Processors (Mobile Celeron - Northwood) Code name Micro-architecture MMX ™ / Streaming SIMD SSE2 Power mgmt technology L1 cache - bus L1 data cache L1 instruction cache L2 cache - size L2 cache - data path System bus Memory addressability System bus - width Execution units Out-of-order instructions Branch prediction Speculative execution Math [...]

  • Page 6

    PC Processors (Intel Celeron M) Code name Messaging Micro-architecture MMX ™ / Streaming SIMD SSE2 Power mgmt technology L1 cache - bus L1 data cache L1 instruction cache L2 cache - size L2 cache - data path L3 cache System bus Memory addressability System bus - width Execution units Out-of-order instructions Branch prediction Speculative executi[...]

  • Page 7

    PC Processors (Pentium III - Tualatin) Code name Instruction architecture MMX ™ / Streaming SIMD L1 cache - bus L1 cache - size/controller L1 cache - write policy L1 cache - organization L2 cache - size L2 cache - data path L2 cache - buffering L2 cache - organization L2 cache - controller L2 cache - write policy L2 cache - type Frontside bus - s[...]

  • Page 8

    PC Processors (Mobile Intel Pentium III-M) Code name Instruction architecture MMX ™ / Streaming SIMD Technology L1 cache - bus L1 cache - size/controller L1 cache - write policy L1 cache - organization L2 cache - size L2 cache - data path L2 cache - buffering L2 cache - organization L2 cache - write policy Frontside bus - speed Memory addressabil[...]

  • Page 9

    PC Processors (Mobile Intel Pentium 4-M) Code name Micro-architecture MMX ™ / Streaming SIMD SSE2 Hyper-Threading Power mgmt technology L1 cache - bus L1 data cache L1 instruction cache L2 cache - size L2 cache - data path L3 cache System bus Memory addressability System bus - width Execution units Out-of-order instructions Branch prediction Spec[...]

  • Page 10

    PC Processors (Intel Pentium M) Code name Branding Micro-architecture MMX ™ / Streaming SIMD SSE2 Power mgmt technology L1 cache - bus L1 data cache L1 instruction cache L2 cache - size L2 cache - data path L3 cache System bus Memory addressability System bus - width Execution units Out-of-order instructions Branch prediction Speculative executio[...]

  • Page 11

    PC Processors (Pentium 4) Code name Micro-architecture MMX ™ / Streaming SIMD SSE2 L1 cache - bus L1 data cache L1 instruction cache L2 cache - size L2 cache - data path Front Side Bus Memory addressability Front Side Bus - width Execution units Out-of-order instructions Branch prediction Speculative execution Math coprocessor Compatibility Cache[...]

  • Page 12

    PC Processors (Pentium 4 - Northwood) Code name Micro-architecture MMX ™ / Streaming SIMD SSE2 Hyper-Threading L1 cache - bus L1 data cache L1 instruction cache L2 cache - size L2 cache - data path L3 cache System bus Memory addressability Frontside bus - width Execution units Out-of-order instructions Branch prediction Speculative execution Math[...]

  • Page 13

    PC Processors (Pentium 4 - Prescott) Code name Micro-architecture MMX ™ / Streaming SIMD SSE2 SSE3 Hyper-Threading L1 cache - bus L1 data cache L1 instruction cache L2 cache - size L2 cache - data path L3 cache System bus Memory addressability System bus - width Execution units Out-of-order instructions Branch prediction Speculative execution Mat[...]

  • Page 14

    PC Processors (Pentium 4 Extreme Edition) Code name Formal name Micro-architecture MMX ™ / Streaming SIMD SSE2 Hyper-Threading L1 cache - bus L1 data cache L1 instruction cache L2 cache - size L2 cache - data path L3 cache L3 cache - data path System bus Memory addressability Frontside bus - width Execution units Out-of-order instructions Branch [...]

  • Page 15

    This publication could include technical inaccuracies or typographical errors. References herein to IBM products and services do not imply that IBM intends to make them available in other countries. IBM PROVIDES THIS PUBLICATION AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FIT[...]