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Samsung M391B5273DH0 manual

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  • Page 1

    - 1 - M391B5773DH0 M391B5273DH0 Rev . 1.0, Sep. 2010 SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMA TION AND SPECIFICA TIONS WITHOUT NOTI CE. Products and specifications discussed herein are for reference pur poses only . All info rmation discussed herein is provided on an "AS IS" basis, without warra nties of any kind[...]

  • Page 2

    - 2 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM Rev ision History Revision No. History Draft Date Remark Editor 1.0 - First Release Sep. 2010 - S.H.Kim[...]

  • Page 3

    - 3 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM Table Of Contents 240pin Unbuffered DIM M based on 2Gb D-die 1. DDR3L Unbuffered DIMM Ordering In formation ........ .......................................... ............ ........... ......... ........ ................. 4 2. Key Features....................... ................. ...............[...]

  • Page 4

    - 4 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 1. DDR3L Unbuff ered DIMM Ordering Inf ormation NOTE : 1. "##" - F8/H9/K0 2. F8 - 1066Mbps 7-7-7 / H9 - 1333Mbp s 9-9-9 / K0 - 1600Mbps 1 1-1 1-1 1 - DDR3-1600(1 1-1 1-1 1) is backward compatible to DDR3-1333(9-9-9 ), DDR3-1066(7-7-7) - DDR3-1333(9-9-9) is backward compatible to DDR3-1[...]

  • Page 5

    - 5 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 4. x72 DIMM Pin Configurations (F r ont side/Back side) NOTE : NC = No Connect; NU = Not Used; RFU = Reserved Future Use 1. S1 , ODT1, CKE1: Used for dual-r ank UDIMMs; NC on single-rank UDIMMs 2. CK1,NC and CK1 ,NC : Used for dual-rank UDIMMs; not used on single-rank UDIMMs, but terminated 3. T[...]

  • Page 6

    - 6 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 5. Pin Descr iption NOTE : * The V DD and V DDQ pins are tied common to a single power-plane on these designs. ** DM8, DQS8 and DQS 8 are for ECC UDIMM only . 6. SPD and Thermal Sens or fo r ECC UDIMMs On DIMM thermal sensor will provide DRAM tem perature r eadout through a integrated thermal se[...]

  • Page 7

    - 7 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 7. Input /Output F unctional Description NOTE : 1. DM8, DQS8 and DQS 8 are for ECC UDIMM only . Symbol Ty p e Funct ion CK0-CK 1 CK 0-CK 1 SSTL CK and CK are differential clock inputs. All the DDR3 SDRAM addr /cntl inputs are sampled on the crossing of positive edge of CK and negative edge of CK[...]

  • Page 8

    - 8 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 7.1 Address Mirror ing F eature Figure 1. Wiring Differences for Mirrored and No n-Mirrored Addresses There is a via grid located under the DRAMs for wiring the CA sign als (address, bank address, command, and control lines) to th e DRAM pins. The leng th of the traces from the vias to the DRAMs[...]

  • Page 9

    - 9 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 8. F unction Block Diagr am: 8.1 2GB, 256Mx72 ECC Mo dule (Popu lated as 1 rank of x8 DDR3 SDRAMs) S0 DQS0 DQS0 DM0 DM CS DQS DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D0 DQS1 DQS1 DM1 DM CS DQS DQS DQ8 DQ9 DQ10 DQ1 1 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O [...]

  • Page 10

    - 10 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 8.2 4GB, 512Mx72 ECC Modu le (Populat ed as 2 r anks of x8 DDR3 SDRAMs) S0 DQS0 DQS0 DM0 DM CS DQS DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D0 DQS1 DQS1 DM1 DM CS DQS DQS DQ8 DQ9 DQ10 DQ1 1 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 [...]

  • Page 11

    - 11 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 9. Abso lute Maximum Ratings 9.1 Absolute Maximum DC Ratings NOTE : 1. S tresses greater th an those listed under “A bsolute Maximum Rating s” may cause p ermanent damage to the d evice. This is a stre ss rating o nly and functional operation of the device at these or an y other conditions [...]

  • Page 12

    - 12 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 11. AC & DC Input Measurement Levels 11.1 AC & DC Logic Input Leve ls for Single-ended Signals [ T able 2 ] Single Ended AC and DC input leve ls for Command and Ad dress NOTE : 1. For input o nly pins except RESET , V REF = V REFCA (DC) 2. See "Overshoot and Undershoot sp ecificati[...]

  • Page 13

    - 13 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM [ T able 3 ] Single Ended AC and DC input leve ls for DQ and DM NOTE : 1. For input o nly pins except RESET , V REF = V REFDQ (DC) 2. See ’Overshoot/Undershoo t S pecification’ on page 18. 3. The AC peak noise on V REF may not allow V REF to deviate from V REF (DC) by more th an ± 1% V DD [...]

  • Page 14

    - 14 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 11.2 V REF T o lerances The dc-tolerance limits and ac-noise limits for the reference voltages V REFCA and V REFDQ are illustrate in Figure 2. It shows a valid reference voltage V REF (t) as a function of time. (V REF stands for V REFCA and V REFDQ likewis e). V REF (DC) is the linear average o[...]

  • Page 15

    - 15 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 11.3 AC and DC Logic Input Levels f or Diff erential Signals 11.3.1 Diff erential Signa ls Definition Figure 3. Definition of dif ferential ac-swing and "time abo ve ac level" tDV AC 11.3.2 Differential Swing Requirement for Clock (CK - CK ) and Strobe (DQS - DQS ) NOTE : 1. Used to d[...]

  • Page 16

    - 16 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM [ T able 4 ] Allowed time before ringback (tDV AC) for CK - CK and DQS - DQS (1.35V) [ T able 5 ] Allowed time before ringback (tDV AC) for CK - CK and DQS - DQS (1.5V) Slew Rate [V/ns] tDV AC [p s] @ |V IH/Ldiff (AC)| = 320mV tDV AC [ps] @ |V IH/ Ldiff (AC)| = 270mV min max min max > 4.0 TB[...]

  • Page 17

    - 17 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 11.3.3 Single-ended Requirements for Differential Signals Each individual component of a differential signal (CK, DQS, CK , DQS ) has also to comply with cert ain requirements for single-ended signals. CK and CK have to approximately reach V SEH min / V SEL max (approximately equal to the ac-le[...]

  • Page 18

    - 18 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 11.3.4 Different ial Input Cross Poi nt Voltage T o guarantee tight setup and hold times as well a s output skew para meters with respect to clock and strob e, each cross point vo ltage of differential input signals (CK, CK and DQS, DQS ) must meet the req uirements in below table. The differen[...]

  • Page 19

    - 19 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 11.4 Slew Rate Definition for Single Ended Input Signals See "Address / Command Setup, Hold and Dera ting" for si ngle-ended slew rate definitions for addr ess and command signals. See "Data Setup, Hold and Slew Rate Derating" fo r single-ended slew rate definitions for data[...]

  • Page 20

    - 20 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 12.3 Single-ended Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edg es is defined and measured between V OL (AC) and V OH (AC) for single ended signals as shown in below. [ T able 12 ] Single ended Output slew rat e definition NOTE : O[...]

  • Page 21

    - 21 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 12.4 Diff erential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V OLdiff (AC) and V OH- diff (AC) for differential signals as shown in below . [ T able 14 ] Differential Output slew rate defi niti[...]

  • Page 22

    - 22 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 13. IDD specific ation definition Symbol Description IDD0 Operating One Bank Active-Precharge Cur rent CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for d etail p attern ; BL : 8 1) ; AL : 0; CS : High bet ween ACT and PRE; Command, Address, Bank Address Inputs[...]

  • Page 23

    - 23 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM NOTE : 1) Burst Length: BL8 fixed by MRS: set MR0 A[1, 0]=00B 2) Output Buf fer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01 B; R TT_Nom enable: set MR1 A[9,6,2] = 01 1B; RTT_Wr enable: set MR2 A[10,9] = 10B 3) Precharge Power Down Mode: set MR0 A12=0 B for Slow Exit or MR0 A12=1B for Fast E[...]

  • Page 24

    - 24 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 14. IDD SPEC T able M391B5773DH0 : 2GB(256Mx72) Module NOTE : 1. DIMM IDD SPEC is calculated with consid ering de-actived rank(IDLE) is IDD2N. M391B5273DH0 : 4GB(512Mx72) Module NOTE : 1. DIMM IDD SPEC is calculated with consid ering de-actived rank(IDLE) is IDD2N. Symbol DDR3-1066 DDR3-1333 DD[...]

  • Page 25

    - 25 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 15. Input /Output Capacitance [ T able 16 ] Input/Output Capacit ance NOTE : This parameter is Component Input/Output Capacit ance so that is different from Module level Cap acit ance. 1. Although the DM, TDQS and TDQ S pins have different functions, the loading matche s DQ and DQS 2. This para[...]

  • Page 26

    - 26 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 16. E lectric al Char acteristics and AC t iming [0 ° C<T CASE ≤ 95 ° C, V DDQ = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V); V DD = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)] 16.1 Refresh Par ameters by Devic e Density NOTE : 1. Users should refer to the DRAM supplier data sheet and[...]

  • Page 27

    - 27 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM [ T able 18 ] DDR3-1066 Speed Bins [ T able 19 ] DDR3-1333 Speed Bins Speed DDR3-1066 Units NOTE CL-nRCD-nRP 7 - 7 - 7 Parameter Symbol min max Internal read command to first data tAA 13.125 20 ns ACT to internal read or write delay time tRCD 13. 125 - ns PRE command period tRP 13.125 - ns ACT [...]

  • Page 28

    - 28 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM [ T able 20 ] DDR3-1600 Speed Bins 16.3.1 Speed Bin T able Notes Speed DDR3-1600 Units NOTE CL-nRCD-nRP 11-11 -11 Parameter Symbol min max Intermal read command to first data tAA 13.75 (13.125) 8 20 ns ACT to internal read or write delay time tRCD 13.75 (13.125) 8 - ns PRE command period tRP 13[...]

  • Page 29

    - 29 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM Absolute S pecification [T OPER ; V DDQ = V DD = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)]; NOTE : 1. The CL setting and CWL setting result in tCK(A VG).MIN and tCK(A VG).MAX requiremen ts. When making a selection of tCK (A VG), bo th need to be fulfilled: Requi rements from CL setting as w[...]

  • Page 30

    - 30 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 17. T iming P aramet ers by Speed Grade [ T able 21 ] T iming Paramete rs by Speed Bin Speed DDR3-80 0 DDR3-1066 DDR3-13 33 DDR3-1600 Units NOTE Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX Clock Timing Minimum Clock Cycle Time (DL L off mode) tCK(DLL_OF F) 8 - 8 - 8 - 8 - ns 6 Average Cloc[...]

  • Page 31

    - 31 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM [ Table 21 ] Timing Parame ters by Speed Bin (Cont.) Speed DDR3-800 DDR3-1066 DDR3- 1333 DDR3-1600 Units NOTE Parameter Symbol MIN MAX MIN MAX MI N MAX MIN MAX Data Strobe Timing DQS, DQS differenti al READ Preamble tRPRE 0.9 Note 19 0.9 Note 19 0.9 Note 19 0.9 Note 19 tCK 1 3, 19, g DQS, DQS d[...]

  • Page 32

    - 32 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM [ T able 21 ] Timing Parameters by Speed Bin (Cont.) Speed DDR3-80 0 DDR3-10 66 DDR3-1333 DDR3-1600 Units NOTE Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX Reset Timing Exit Reset from CKE HIGH to a va lid command t XPR max(5nCK , tRFC + 10ns) - max(5nCK, tRFC + 10ns) - max(5nCK, tRFC + 10n[...]

  • Page 33

    - 33 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 17.1 Jitter Notes Specific Note a Unit ’tCK(avg)’ repre sents the actual tCK(avg) of the input cl ock under operation. Unit ’nCK’ represents one clock cycle of the input clock, counting the actual clock edges .ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at T[...]

  • Page 34

    - 34 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 17.2 T iming Parameter Notes 1. Actual val ue dependant upon measuremen t level defi nitions whi ch are TBD. 2. Commands requ iring a locked DL L are: READ (and RAP ) and synchron ous ODT commands. 3. The max value s are system dep endent. 4. WR as programmed in mode register 5. Value must b e [...]

  • Page 35

    - 35 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 18. Physical Dimensions 18.1 256Mbx8 based 256Mx72 Modu le (1 Rank) - M391B5773DH0 133.35 ± 0.15 Max 4.0 54.675 Units : Millimeters 9.50 128.95 (2) (4X)3.00 ± 0.1 30.00 ± 0.15 2.30 17.30 The used devi ce is 256M x8 DDR3L SDRAM, FBGA. DDR3 SDRAM Part NO : K4B2G0846D-HY ∗∗ * NOTE : T olera[...]

  • Page 36

    - 36 - datasheet DDR3L SDRAM Rev . 1.0 Unbuffered DIMM 18.2 256Mbx8 based 512Mx72 Modu le (2 Ranks) - M391B5273DH0 133.35 ± 0.15 Max 4.0 54.675 Units : Millimeters 9.50 128.95 (2) (4X)3.00 ± 0.1 30.00 ± 0.15 2.30 17.30 The used devi ce is 256M x8 DDR3L SDRAM, FBGA. DDR3 SDRAM Part NO : K4B2G0846D-HY ∗∗ * NOTE : T olerances on all dimensions [...]