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Texas Instruments TNETX4090 manual

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  • Page 1

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Single-Chip 100-/1000-Mbit/s Device Integrated Physical Coding Sublayer (PCS) Logic Provides Direct Interface to Gigabit T ransceivers Integrated Address-Lookup Engine and T a[...]

  • Page 2

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description (continued) Switching Engine (Queue Manager) Rambus DRAM Controller VLAN 802.1Q and Address-Lookup Engine 2048 CAM 100/1000 MAC GMII/PMA Hardware RMON and Ethersta[...]

  • Page 3

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCS Duplex LED 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RDRAM Interface 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

  • Page 4

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 GGP P ACKAGE (BOTTOM VIEW) A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 26 24 22 20 18 16 14 12 10 8 6 4 2 25 23 21 19 17 15 13 1 1 9 7 5 3 1[...]

  • Page 5

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 T able 1. Signal-to-Ball Mapping (Signal Names Sorted Alphabetically) SIGNAL NAME BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME BALL NO. [...]

  • Page 6

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 T able 2. Signal-to-Ball Mapping (Signal Names Sorted Alphabetically) (Continued) SIGNAL NAME BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME BALL NO. SIGNAL NA[...]

  • Page 7

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 T erminal Functions JT AG interface TERMINAL I/O INTERNAL DESCRIPTION NAME NO. I/O RESISTOR † DESCRIPTION TCLK L24 I Pullup T est clock. Clocks state information and test da[...]

  • Page 8

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 T erminal Functions (Continued) 100-/1000-Mbit/s MAC interface (GMII mode) TERMINAL NAME I/O INTERNAL RESISTOR † DESCRIPTION M08_COL I Pulldown Collision sense. Assertion of[...]

  • Page 9

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 T erminal Functions (Continued) 100-/1000-Mbit/s MAC interface [physical media attachment (PMA) mode] TERMINAL NAME I/O INTERNAL RESISTOR DESCRIPTION M08_COL I Pulldown Receiv[...]

  • Page 10

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 T erminal Functions (Continued) 100-/1000-Mbit/s MAC interface [media-independent interface (MII) mode] TERMINAL NAME I/O INTERNAL RESISTOR DESCRIPTION M08_COL I Pulldown Col[...]

  • Page 11

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 T erminal Functions (Continued) 100-/1000-Mbit/s MAC interface [media-independent interface (MII) mode] (continued) TERMINAL NAME I/O INTERNAL RESISTOR DESCRIPTION M08_TXEN O[...]

  • Page 12

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 T erminal Functions (Continued) 10-/100-Mbit/s MAC interface (MII mode) (ports 0–7) (continued) TERMINAL I/O INTERNAL DESCRIPTION NAME NO. I/O RESISTOR DESCRIPTION M00_RENE[...]

  • Page 13

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 13 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 T erminal Functions (Continued) 10-/100-Mbit/s MAC interface (MII mode) (ports 0–7) (continued) TERMINAL I/O INTERNAL DESCRIPTION NAME NO. I/O RESISTOR DESCRIPTION M00_RXER[...]

  • Page 14

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 T erminal Functions (Continued) 10-/100-Mbit/s MAC interface (MII mode) (ports 0–7) (continued) TERMINAL I/O INTERNAL DESCRIPTION NAME NO. I/O RESISTOR DESCRIPTION M00_TXEN[...]

  • Page 15

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 15 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 T erminal Functions (Continued) RDRAM interface TERMINAL I/O INTERNAL DESCRIPTION NAME NO. I/O RESISTOR DESCRIPTION DBUS_CTL Y26 O None Bus control. Controls signal-to-frame [...]

  • Page 16

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 T erminal Functions (Continued) DIO interface TERMINAL I/O INTERNAL DESCRIPTION NAME NO. I/O RESISTOR DESCRIPTION SAD0 SAD1 AF22 AE22 I Pullup DIO address bus. Selects the in[...]

  • Page 17

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 17 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 T erminal Functions (Continued) LED interface TERMINAL I/O INTERNAL DESCRIPTION NAME NO. I/O RESISTOR DESCRIPTION LED_CLK AD19 O None LED clock. Serial shift clock for the LE[...]

  • Page 18

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DIO interface description The DIO is a general-purpose interface that is used with a range of microprocessor or computer system interfaces. The interface is backward compatib[...]

  • Page 19

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 19 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 T able 2. DIO Internal Register Address Map (Continued) BYTE 3 BYTE 2 BYTE 1 BYTE 0 DIO ADDRESS SysControl StatControl 0x00F8 Reserved (for EEPROM CRC) 0x00FC VLAN0Ports 0x01[...]

  • Page 20

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 T able 2. DIO Internal Register Address Map (Continued) BYTE 3 BYTE 2 BYTE 1 BYTE 0 DIO ADDRESS VLAN40Ports 0x01A0 VLAN41Ports 0x01A4 VLAN42Ports 0x01A8 VLAN43Ports 0x01AC VL[...]

  • Page 21

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 21 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 T able 2. DIO Internal Register Address Map (Continued) BYTE 3 BYTE 2 BYTE 1 BYTE 0 DIO ADDRESS VLAN37QID VLAN36QID 0x0348 VLAN39QID VLAN38QID 0x034C VLAN41QID VLAN40QID 0x03[...]

  • Page 22

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 T able 2. DIO Internal Register Address Map (Continued) BYTE 3 BYTE 2 BYTE 1 BYTE 0 DIO ADDRESS XMultiGroup19 0x054C XMultiGroup20 0x0550 XMultiGroup21 0x0554 XMultiGroup22 0[...]

  • Page 23

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 23 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 T able 2. DIO Internal Register Address Map (Continued) BYTE 3 BYTE 2 BYTE 1 BYTE 0 DIO ADDRESS XMultiGroup61 0x05F4 XMultiGroup62 0x05F8 XMultiGroup63 0x05FC Reserved 0x0600[...]

  • Page 24

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DIO interface description (continued) T able 3 and T able 4 list the least significant byte address for the port-specific statistics. Each statistic is four bytes long. T o d[...]

  • Page 25

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 25 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 T able 3. Port Statistics 1 T AIL PORT NO. HEAD ST A TISTIC EVEN PORTS ODD PORTS 0 0x80xx Receive octet 00 80 1 0x80xx Good receive frames 04 84 2 0x81xx Broadcast receive fr[...]

  • Page 26

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 T able 4. Port Statistics 2 PORT NO. HEAD ST A TISTIC T AIL (ALL PORTS) 0 0x900x Pause transmit frames † 0 1 0x901x Pause receive frames † 4 2 0x902x Security violations [...]

  • Page 27

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 27 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DIO interface description (continued) T able 5. Address-Lookup Statistics PORT NO. HEAD ST A TISTIC N/A 0x9200–0x9FFC Reserved N/A 0xA000 Unknown unicast destination addres[...]

  • Page 28

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 state of DIO signal terminals during hardware reset The CPU can perform a hardware reset by writing to an address in the range of 0x40–0x5F (writes to a DMA address in this[...]

  • Page 29

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 29 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 frame format on the NM port (continued) T o provide a CRC word, which includes the header , the NM port generates a new CRC word as the frame is being read out. It simultaneo[...]

  • Page 30

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 frame format on the NM port (continued) Any device reading frames out of the NM port must expect frames to be in the format shown in Figure 2. Frames received into the switch[...]

  • Page 31

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 31 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 full-duplex NM port The NM port can intermix reception and transmission as desired. It is the direction of the NMData access (i.e., read or write) that determines whether a b[...]

  • Page 32

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAC interface receive control Data received from the PHYs is interpreted and assembled into the TNETX4090 buffer memory . Interpretation involves detection and removal of the[...]

  • Page 33

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 33 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 adaptive performance optimization (APO) Each Ethernet MAC incorporates APO logic. This can be enabled on an individual port basis. When enabled, the MAC uses transmission pac[...]

  • Page 34

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10-/100-Mbit/s MII (ports 0–7) speed, duplex, and flow-control negotiation Each individual port can operate at 10 Mbit/s or 100 Mbit/s in half or full duplex, and can indic[...]

  • Page 35

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 35 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Reserved Reserved Reserved Reserved Reserved Reserved Pause Reserved Speed Reserved Duplex Reserved Reserved Pause Speed Duplex 1200-ms Min 750-ms Min 80-ms Min Link Fail or [...]

  • Page 36

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 100-/1000-Mbit/s PHY interface (port 8) This port is controlled by an IEEE Std 802.3-compliant MAC. speed, duplex, and flow-control negotiation When in PMA mode and autonegot[...]

  • Page 37

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 37 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 speed, duplex, and flow-control negotiation (continued) In 100-Mbit/s mode, M08_RXD4 and M08_RXD5 are reconfigured as open-drain inputs, to allow the port to negotiate with t[...]

  • Page 38

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 pretagging and extended port awareness The TNETX4090 can be incorporated into a hierarchical system, whereby this port is connected to a crossbar matrix with up to 17 1000-Mb[...]

  • Page 39

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 39 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 T able 10. T ransmit Pretag Bit Definitions BIT NAME FUNCTION 31–28 reserved Reserved. These bits always are 0. 27 rxheader Receive header . Indicates whether an IEEE Std 8[...]

  • Page 40

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 T able 12. Directed Format Receive Pretag Bit Definitions BIT NAME FUNCTION 31 1 One. Indicates directed format. The frame is routed to port(s) specified in portvector that a[...]

  • Page 41

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 41 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ring-cascade topology (continued) Frames received on a ring port must have an out-of-band pretag in the clock cycle before Mxx_RXDV is asserted. The contents of the pretag ar[...]

  • Page 42

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 EEPROM interface The EEPROM interface is provided so the system-level manufacturer can produce a CPU-less preconfigured system. This also can be used to change or reconfigure[...]

  • Page 43

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 43 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 EEPROM interface (continued) After the initial start condition, a slave address containing a device address of 000 is output on EDIO, and then EDIO is observed for an acknowl[...]

  • Page 44

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 compatibility with future device revisions All EEPROM locations that correspond to reserved addresses in the memory map, register bits that are read only , and register bits [...]

  • Page 45

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 45 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 T able 17. LED Status Bit Definitions and Shift Order ORDER NAME FUNCTION slast = 0 slast = 1 NAME FUNCTION 1st–12th 1 1th–22nd SW0–SW1 1 Software LEDs 0–1 1. These a[...]

  • Page 46

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TNETX4090 9 DBUS_DA T A8–DBUS_DA T A0 DBUS_CTL DBUS_EN DRX_CLK DTX_CLK BUS_CLK TXCLK RXCLK BUS ENABLE BUS CTRL BUS DA T A (8–0) Concurrent RDRAM 5 13 V REF V DD GND S IN [...]

  • Page 47

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 47 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 JT AG interface The TNETX4090 is fully IEEE Std 1 149.1 compliant. It also includes on-chip pullup resistors on the five JT AG terminals to eliminate the need for external on[...]

  • Page 48

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 frame routing VLAN support The internal routing engine supports the IEEE Std 802.1Q VLANs as shown in Figure 1 1 and described in the following paragraphs. Reset 0x0001 Heade[...]

  • Page 49

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 49 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IEEE Std 802.1Q tags – reception By the time the IALE examines the received frame, it contains an IEEE Std 802.1Q tag header (after the source address). The tag used depend[...]

  • Page 50

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 aging algorithms time-threshold aging When learning addresses, the IALE adds the address to the table and tags it with a time stamp. If another frame is received with this ad[...]

  • Page 51

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 51 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Unknown Multicast Destination Start Known VLAN? Source Port = 1 in. VLANnPorts? Ye s Destination Address Found? Ye s Unkmem Key: interrupt No Ye s N o No UnkVLAN Destination [...]

  • Page 52

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 52 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Source Port Security Violation A B Ye s No new Remove Source Port (and other trunk members) From Port Routing Code Source Address Found? Source Port = 1 in NLearnPorts? No AN[...]

  • Page 53

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 53 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 E Mirr Bit = 1? Remove: – Disabled Ports – Ports Blocked by TxBlockPorts From Port Routing Code Ye s If [(Source Port = MirrorPort or Port Routing Code Includes MirrorPor[...]

  • Page 54

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 removal of source port Normally , the IALE does not route a frame to a port on which it was received. The port routing code is examined to see if the source port is included.[...]

  • Page 55

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 55 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 port trunking example This example shows how to set up the TNETX4090 to support two port trunks. The first trunk group consists of ports 1, 3, 5, and 7 (see T able 21); the s[...]

  • Page 56

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 56 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 flow control The TNETX4090 supports collision-based flow control for ports in half-duplex mode and IEEE Std 802.3x flow control for ports in full-duplex mode. The flow bit in[...]

  • Page 57

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 57 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 other flow-control mechanisms hardware flow control If a port were in MII or GMII mode and full duplex, normally , its Mxx_COL would not be needed. Hardware flow control has [...]

  • Page 58

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 58 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 reading RDRAM Reading from RDRAM memory is accomplished as follows: 1. Write the byte address for the access to ramaddress in RAMAddress. 2. Set rdwrite = 1 and rdram = 1 (th[...]

  • Page 59

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 59 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 internal wrap test (continued) TNETX4090 08 07 06 05 04 03 02 01 00 NM Figure 13. Internal Wrap Example The operational status of the PHYs or external connections to the devi[...]

  • Page 60

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 60 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) † Supply voltage range, V DD(2.5) (see Note 1) –0.5 V to 2.7 V . . . . . . . .[...]

  • Page 61

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 61 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating conditions (unless otherwise noted) P ARAMETER TEST CONDITIONS MIN TYP MAX UNIT V OH High-level output voltage I OH = ra[...]

  • Page 62

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 62 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 physical medium attachment interface (port 8) receive PMA receive (see Figure 16) NO. MIN MAX UNIT 1 t c(Mxx_RBC) Cycle time, receive byte clock 0 and 1 (Mxx_RCLK, Mxx_COL) 1[...]

  • Page 63

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 63 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 transmit PMA transmit (see Figure 17) NO. MIN MAX UNIT 1 t c(Mxx_GTCLK) Cycle time, Mxx_GTCLK 8 † 8 † ns 2,3 t w(Mxx_GTCLK) Pulse duration, Mxx_GTCLK low or high 40% 60% [...]

  • Page 64

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 64 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 GMII (port 8) Figures 18–20 show the timing for the 100-/1000-Mbit/s GMII when operating at 1000 Mbit/s. Both Mxx_CRS and Mxx_COL are driven asynchronously by the PHY . Mxx[...]

  • Page 65

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 65 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PMA and GMII clock (see Figure 20) NO. MIN MAX UNIT 1 t r(Mxx_GCLK) Pulse width low , Mxx_RFCLK 2.5 ns 2 t h(Mxx_GCLK) Pulse width high, Mxx_RFCLK 2.5 ns 3 t w(Mxx_GCLK) Cycl[...]

  • Page 66

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 66 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MII (ports 0–8) Figures 21–23 show the timing for the eight MIIs operating at either 10-Mbit/s or 100-Mbit/s, and the GMII operating at 100-Mbit/s. Mxx_CRS and Mxx_COL ar[...]

  • Page 67

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 67 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MII transmit (see Figure 22) NO. MIN MAX UNIT 1 t d(Mxx_TXD) Delay time, from Mxx_TCLK ↑ to Mxx_TXD3–MxxTXD0 valid 5 15 ns 1 t d(Mxx_TXEN) Delay time, from Mxx_TCLK ↑ t[...]

  • Page 68

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 68 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 RDRAM interface RDRAM (see Figure 24) NO. MIN MAX UNIT 1 t c(DX_CLK) Cycle time DTX_CLK, DRX_CLK 3.33 3.33 ns 2, 3 t w(DX_CLK) Pulse duration, DTX_CLK, DRX_CLK low or high 45[...]

  • Page 69

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 69 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DIO interface The DIO interface is simple and asynchronous to allow easy adaptation to a range of microprocessor devices and computer system interfaces. DIO and DMA writes (s[...]

  • Page 70

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 70 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DIO and DMA reads (see Figure 26) NO. MIN MAX UNIT 1 t w(SCSL) Pulse duration, SCS low 2t c ns 2 t su(SRNW) Setup time, SRNW valid before SCS ↓ 0 ns 3 t su(SAD) Setup time,[...]

  • Page 71

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 71 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 EEPROM interface For further information on EEPROM interface timing, refer to the 24C02 or 24C08 serial EEPROM data sheets. EEPROM writes (see Figure 27) NO. MIN MAX UNIT 1 t[...]

  • Page 72

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 72 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 LED interface LED (see Figure 29) NO. MIN MAX UNIT 1 t c(LED_CLK) Cycle time, LED_CLK 8 t c 2 t w(LED_CLK) Pulse duration, LED_CLK high 4 t c 3 t n(LED_CLK) Number of LED_CLK[...]

  • Page 73

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 73 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 P ARAMETER MEASUREMENT INFORMA TION The following load circuits and voltage waveforms show the conditions used for measuring switching characteristics. T est points are illus[...]

  • Page 74

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 74 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 P ARAMETER MEASUREMENT INFORMA TION 20% 80% 80% 20% 47% 47% t f t r V DD 0 Input 47% t PLH V OH V OL In-Phase Output t PHL 47% 47% V OH V OL Out-of-Phase Output t PHL 47% t P[...]

  • Page 75

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 75 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 P ARAMETER MEASUREMENT INFORMA TION V DD 0 20% 47% 80% Input (active-low enable) Hi-Z Active V OH Hi-Z (forced low) 50% L VCMOS 1.3 V TTL t PZH Output High V OL Hi-Z (forced [...]

  • Page 76

    TNETX4090 ThunderSWITCH II  9-PORT 100-/1000-MBIT/S ETHERNET  SWITCH SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999 76 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DA T A GGP (S-PBGA-N352) PLASTIC BALL GRID ARRA Y (CA VITY DOWN) P ACKAGE 4073223/A 1 1/96 A 1 3 2 F E D C K J H G B P N M W V U T R AC AB AA Y AF AE AD L 5 64 9 8[...]

  • Page 77

    PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) TNETX4090GGP OBSOLETE BGA GGP 352 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device wi[...]

  • Page 78

    IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders[...]