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Xilinx UG129 manual

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  • Page 1

    R PicoBlaz e 8-bit Embed ded Micr ocontr oller User Guide f o r Spar tan-3, Vir te x-II, and Vir tex -II Pr o FPGA s UG129 (v 1.1.2) J une 24, 2008[...]

  • Page 2

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om UG129 (v1.1.2) J u ne 24, 200 8 Xilinx is disclos ing this D ocument and Intell ectual Prop er ty (he reinafter “ the Desig n”) to you for use in the deve lopment of de signs t o op er ate on, or interface with Xilin x FPGAs. Exc ept as st ated herei n, none o f the Desig n may be [...]

  • Page 3

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 3 UG129 (v 1.1.2) J une 24, 200 8 R Pr eface Limitations Limited W arranty and Disclaimer These design s are provided to you “ as-is”. Xilin x and its licens ors make and you receive no warranties or conditions, express, implied, statu tory or otherwise, and Xi linx specifical ly d[...]

  • Page 4

    4 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Preface: Acknow ledgmen ts R Acknowledgments Xilinx tha nks the follow ing individual s fo r their contribution to the PicoBlaze microcont r oller ca use: • Henk van Kamp en, Mediatro nix Developer of the pBlazID E graphical, int egrated developmen t [...]

  • Page 5

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 5 UG129 (v 1.1.2) J une 24, 200 8 Guide Con tents R About This Guide The PicoBlaze™ em bedded micro contro ller is an eff icient, cost-ef fec tive embedded processor cor e for Spartan ® -3, V irtex ® -II, and V irtex-II Pro FPGAs. This user guide describes the capabilit ies, featur[...]

  • Page 6

    6 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Preface: About This Guide R[...]

  • Page 7

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 7 UG129 (v 1.1.2) J une 24, 200 8 Preface: Limitati ons Limited Warranty and Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limitation of Liabil ity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

  • Page 8

    8 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 R Increment/Decrement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Negate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

  • Page 9

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 9 UG129 (v 1.1.2) J une 24, 200 8 R Chapter 8: Performanc e Input Clock Freq uency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Predicting Ex ecuting Perf ormance . . . . . . . . . . . . . . . . . . . . . . . . . . . . .[...]

  • Page 10

    10 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 R Appendix A: R elated Materials and References App endi x B: Example Progr am Te mpla tes KCPSM3 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 pBlazIDE Syntax . . . . [...]

  • Page 11

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 11 UG129 (v 1.1.2) J une 24, 200 8 R Chapter 1 Intr oduction The PicoBlaze™ micro controller is a compact, capable, and cost- effective fully embedded 8-bit RIS C microcontrolle r core optimized for the Sp artan ® -3, V irtex ® -II, and V ir tex- II Pro FPGA families. Th e PicoBlaz[...]

  • Page 12

    12 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 1: Intr oduction R • Byte-wide Arit hmetic Logi c Unit (ALU) with CARR Y and ZERO indicator fl ags • 64-byte interna l scratchpad RAM • 256 in put and 256 output ports for ea sy expans ion an d enhanceme nt • Automatic 31-lo cation CALL[...]

  • Page 13

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 13 UG129 (v 1.1.2) J une 24, 200 8 PicoBlaze Microcontr oller Functional Bloc ks R Other memory organ izations are poss ible to accommodate mor e PicoBlaze contro llers within a single FPG A or to en able intera ctive code updates without recompil ing the FPG A design. See Chapter 7, ?[...]

  • Page 14

    14 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 1: Intr oduction R Progr am Counter (PC) The Program Counter (PC) points to the next instructio n to be executed. By de fault, the PC autom atically increments to the next inst ruction location wh en executing an instruction . Only the JUMP , C[...]

  • Page 15

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 15 UG129 (v 1.1.2) J une 24, 200 8 Why the PicoBla ze Microcontroller ? R The data registers and scratchpad RAM are not affe cted by Reset. See “RESET Even t” in Append ix C for mor e informa tion. Wh y the PicoBlaz e Micr ocontroller? There ar e literally doze ns of 8-bit microcon[...]

  • Page 16

    16 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 1: Intr oduction R performance re quirements. A completely parallel implementation is faster but consumes mo re FP G A res o urc e s. A microcontr oller embedded within the FPGA pr ovides the best of both worlds. The microcontroller implements [...]

  • Page 17

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 17 UG129 (v 1.1.2) J une 24, 200 8 R Chapter 2 PicoBlaze Interface Signals The top-level interface sig nals to the PicoBlaz e™ microcontroller appear in Figure 2-1 and are des cribed in Ta b l e 2 - 1 . F igure 7-1 provides additional detail o n the internal structure of the PicoBlaz[...]

  • Page 18

    18 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapt er 2: PicoBlaz e Interf ace Signal s R PORT_ID[7: 0] Out put Port Address: Th e I/O port address appears o n this port for two CLK cycles during an INPUT or OUTPUT instruction. READ_STROBE Output Re ad S tro be : When asserted High, this sign al [...]

  • Page 19

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 19 UG129 (v 1.1.2) J une 24, 200 8 R Chapter 3 PicoBlaze Instruction Set Ta b l e 3 - 1 sum marizes the en tire PicoBlaze™ processor inst ruction set, which appe ars alphabetica lly . Instructions are listed using the KCPS M3 syntax. If differ ent, the pBlazID E syntax appea rs in pa[...]

  • Page 20

    20 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 3: PicoBlaz e Instruction S et R ENABLE INTERRUP T (EINT) Enable inter rupt input INTERRUPT_ENAB LE Å 1- - Int errupt Even t As ynchronous int errupt inpu t. Prese rve flags and PC. Clear INTERRUPT_ENABLE flag. Jump to interru pt vec tor at [...]

  • Page 21

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 21 UG129 (v 1.1.2) J une 24, 200 8 R RETURNI DISABLE (RETI DISABLE) Return fr om in terr upt servic e r outine . Interru pt rem ains disab led. PC Å TOS ZERO Å Pr eserved ZERO CARR Y Å Pr eserved CARR Y INTERRUPT_ENABLE Å 0 ?? RETURNI ENABLE (RETI ENABLE) Return fr om in terr upt s[...]

  • Page 22

    22 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 3: PicoBlaz e Instruction S et R Address Spaces As show n in Ta b l e 3 - 2 , th e PicoBlaze m icro controller has five distinct address spaces . Specific instr uctions operate on each of the addr ess spaces. TEST sX, kk T est bits in reg ist[...]

  • Page 23

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 23 UG129 (v 1.1.2) J une 24, 200 8 Address Space s R T able 3-2: PicoBl aze Address Sp aces and R elated Inst ructions Address Space Siz e (Depth x Widt h) Addressing Modes Instru ctions that Operate o n Address Space Instruction 1Kx18 Direct • JUMP • CALL • RETURN • RETURNI ?[...]

  • Page 24

    24 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 3: PicoBlaz e Instruction S et R Pr ocessing Data All data processing inst ructions operate on any of the 16 general-purpose registers. Only the data processing instructions mo dify the ZER O or CARR Y flags as appr opria te for the instructi[...]

  • Page 25

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 25 UG129 (v 1.1.2) J une 24, 200 8 Pr ocessing Data R Complement/In v er t Register The PicoBlaze microcontroller does not have a specific instruction to invert individual bits within register sX . However , the XOR sX,FF instruction performs the equivalent operation, as shown in Figur[...]

  • Page 26

    26 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 3: PicoBlaz e Instruction S et R operation. ORi ng register sX with a bit mask sets specific bits, as shown in Figure 3-6 . A ‘1’ in the bit mask sets the corresponding bit in register sX . A ‘0’ in the bit mask leaves the corre spond[...]

  • Page 27

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 27 UG129 (v 1.1.2) J une 24, 200 8 Pr ocessing Data R See als o: • “ADD sX, Operand —Add Operand to Register sX,” page 91 • “ADDCY sX, Oper and —Add Operand to Register s X with Carry ,” page 92 SUB and SUBCY Subtr act Instructions The PicoBlaze microcontroller provides[...]

  • Page 28

    28 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 3: PicoBlaz e Instruction S et R If incre menting or decrementing a multi-r egister value—i.e., a 16- bit value—perform the operation usi ng multiple instruction s. Incre menting or decrementing a multi-by te value requires using the add [...]

  • Page 29

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 29 UG129 (v 1.1.2) J une 24, 200 8 Pr ocessing Data R If multiplicatio n performance is important to the application, connect one of th e FPGA ’s 18x18 hardwar e multipliers the PicoBlaze I/O ports, as shown in Figur e 3-15 . The hardware multiplier computes the 16-bit result in less[...]

  • Page 30

    30 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 3: PicoBlaz e Instruction S et R Division The PicoBlaz e microcon troller cor e does not have a dedicated h ardwar e di vider . However , the PicoBlaz e micr ocontroller performs d ivision using the av ailable arithm etic and shift instructio[...]

  • Page 31

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 31 UG129 (v 1.1.2) J une 24, 200 8 Pr ocessing Data R No Oper ation (NOP) The PicoBlaze i nstruction set does no t have a specific NOP instruction . T ypi cally , a NO P instruction is comp letely benign, does not affect re gister content s or flags, and performs no operation ot her th[...]

  • Page 32

    32 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 3: PicoBlaz e Instruction S et R A similar NOP techniq ue is to simply jump to th e next instruction, which is equiva lent to the default program flow . The JUMP instruction consumes an instruction cycle (two clock cycles) without affecting r[...]

  • Page 33

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 33 UG129 (v 1.1.2) J une 24, 200 8 Pr ocessing Data R Each bit of r egister sX is logically ANDed wit h either the contents of register sY or a lit eral constant, kk . The operation sets the Z ERO flag if the result of all bitwise AND opera tions is zero. If the second operan d contain[...]

  • Page 34

    34 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 3: PicoBlaz e Instruction S et R The example in Figure 3-25 demonstrates how to generate parit y for all eight bits in a reg i st e r . See also “TEST sX, Operand — T est Bit Location in Register sX, Generate Odd Parity ,” page 11 6 . C[...]

  • Page 35

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 35 UG129 (v 1.1.2) J une 24, 200 8 Pr ocessing Data R See als o: • “SL[ 0 | 1 | X | A ] sX — Shif t Left Regi ster sX,” pa ge 109 • “SR[ 0 | 1 | X | A ] sX — Shift Ri ght Regis ter sX,” page 1 10 Rotate The rotate instructions, shown in Ta b l e 3 - 5 , r otate the cont[...]

  • Page 36

    36 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 3: PicoBlaz e Instruction S et R Mo ving Data Data move ment between va rious resources is an essential mi crocontroller function. Figure 3-26 show s th e va riou s Pic oBla ze i n str uct ions to mo ve data . The LOAD sX,sY instruction moves[...]

  • Page 37

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 37 UG129 (v 1.1.2) J une 24, 200 8 Progr am Flow Contr ol R The JUMP , CALL , an d RETURN instructions are all conditio nally executed, dependin g if a condition is specified and specifi cally whether the CAR R Y or ZERO flags are set or cleared. Ta b l e 3 - 6 summarizes the possible [...]

  • Page 38

    38 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 3: PicoBlaz e Instruction S et R The JUMP instruction does not af fect the ZERO and CAR R Y flags. All jumps ar e absolute; there ar e no relative jumps. Likew ise, computed jumps ar e not supported. See als o “JUMP [Conditio n,] Addr ess ?[...]

  • Page 39

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 39 UG129 (v 1.1.2) J une 24, 200 8 Progr am Flow Contr ol R RETURN instructions themselves. If the CALL instruction is not executed, then the flags ar e unaffected. See als o: • “CALL [Condition,] A ddr ess — Call Subr outine at Speci fied Addr ess, Possibly w ith Conditions ,”[...]

  • Page 40

    40 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 3: PicoBlaz e Instruction S et R[...]

  • Page 41

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 41 UG129 (v 1.1.2) J une 24, 200 8 R Chapter 4 Interrupts The Pico Blaz e™ p r oces sor pr o vide s a s ing le in ter ru pt in pu t sig na l. I f the appl ic ation requires multiple interrupt s ignals, co mbine the sign als usin g simple F PGA logic t o form a single INTERRUP T input[...]

  • Page 42

    42 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 4: Interrupts R A special RETURNI command ensur es that the end of an interr upt service routine r estor es the status of the flags and contr ols the enable of futur e interrupts. When the RETURNI instruction is executed, the PC values saved on[...]

  • Page 43

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 43 UG129 (v 1.1.2) J une 24, 200 8 Example Interrupt Flow R 3. The PicoBlaze microcontr oller recognizes the interrupt and pr eempts the ADD s0,s1 instruction. The current PC, which points to the ADD s0 s1 instruction, is pushed onto the CALL/RETURN stack. Likew ise, the ZERO an d CARR[...]

  • Page 44

    44 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 4: Interrupts R Figure 4-3 shows th e same interrupt procedur e but as a timing diagram. W ith the int errupt enabled, the INTERRUPT input is r ecognized a t Step (2), the same clock cycle where the ADDRESS bus changes va lue. The address for t[...]

  • Page 45

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 45 UG129 (v 1.1.2) J une 24, 200 8 R Chapter 5 Scratchpad RAM The PicoBlaz e™ micr ocontr oller contains a 64-byte s cratchpad R AM. T w o ins tructio ns, STORE and FETCH , move data between any data r egister and the scratchpad R AM. Both dir ect and indir ect addr essing are s uppo[...]

  • Page 46

    46 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 5: Scratc hpad RAM R Impl eme nting a Lo ok-U p T ab le The next few exam ples demonstrate both the flexibility of the scratchpad R AM and indirect ad dress ing. The example code in Figure 5-3 uses Scrat chpad RA M as a lo ok-u p table (LUT) [...]

  • Page 47

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 47 UG129 (v 1.1.2) J une 24, 200 8 Stack Operat ions R Stack Operations Although the Pi coBlaze microcontroller has a CALL/RETUR N stack, it does not have a dedicated data st ack. In some controller architectures, r egister values are pr eserved during subroutine calls or interrupts by[...]

  • Page 48

    48 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 5: Scratc hpad RAM R[...]

  • Page 49

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 49 UG129 (v 1.1.2) J une 24, 200 8 R Chapter 6 Input and Output Ports The PicoB laze™ microcontroller sup ports up to 256 input ports an d 256 output ports that can also be combined to create in put/ou tput ports. The interface sig nals from Figure 2-1 involved in INPU T and OUTPUT o[...]

  • Page 50

    50 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 6: Input and Output P orts R INPUT Operatio ns An INPUT operation transfers the data supplie d on the IN_PORT input port t o any on e of the 16 data registers, defined by register sX , as shown in Figure 6-1 . The PORT_ID output port, defined e[...]

  • Page 51

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 51 UG129 (v 1.1.2) J une 24, 200 8 INPUT Operations R In this example, the PicoBlaze mi crocontr oller is r eading data fro m the port addr ess defined by the contents of r egister s7 . The r ead data is captured in r egister s0 . When the instruction executes, the contents of r egiste[...]

  • Page 52

    52 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 6: Input and Output P orts R Failure to include a register any where in the path from POR T_ID to IN_P OR T is the most common reason for decrea sed system clock rates. Consequently , make sure that this path is register ed at some point. Appli[...]

  • Page 53

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 53 UG129 (v 1.1.2) J une 24, 200 8 OUTPUT Operations R OUTPUT Operations As show n in Figure 6-5 , an OUTPUT operation pr esents the contents of any of the 16 registers to the OUT_POR T output po rt. The POR T_ID o utput port, defined either by reg i st e r sY or an 8-bit immediate con[...]

  • Page 54

    54 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 6: Input and Output P orts R Simple Output St ructure f or F e w Output Destinations For eight or less simple output ports, use “o ne-hot” port addr esses and only decode the appropri ate PO R T_ID sign al, as s hown in Fig ure 6-7 . This t[...]

  • Page 55

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 55 UG129 (v 1.1.2) J une 24, 200 8 OUTPUT Operations R As show n in Figure 6-8 , use CONSTANT dire ctives in the program make the code readable and help ensur e that the corre ct ports ar e decoded. Because the POR T_ID addresses use “one-hot” encoding, it is also possi ble to crea[...]

  • Page 56

    56 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 6: Input and Output P orts R Pipel ining f or Maxim um P erf orm ance In most applications, the PicoBlaze micr ocon troller has more than sufficient performance to meet application requir ements. However , PicoBlaze designs attached to multiple[...]

  • Page 57

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 57 UG129 (v 1.1.2) J une 24, 200 8 Pipelining for Maximum P erf ormance R The pipelinin g registers on the OUT_PORT and PORT_ID signals , shaded in Figure 6-9 , are optional. Both OU T_POR T and POR T_ID are valid for two clock cycles. However , pipelining them decreases the initial fa[...]

  • Page 58

    58 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 6: Input and Output P orts R Repar titioning the Design for Maxim u m P erformance Another appr oach to maximizing performance is to re-evaluate the system requir ements. If the number of I/O ports is the bottleneck in the system, ask if all th[...]

  • Page 59

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 59 UG129 (v 1.1.2) J une 24, 200 8 R Chapter 7 Instruction Storage Configurations The PicoBlaze™ micr ocontroller executes code fr om memory resour ces embedded within the FPGA. Fig ur e 7-1 show s that the PicoBlaze microcontroller actually consists of two subfunctions. The KCPSM3 m[...]

  • Page 60

    60 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 7: Instruction Stor age Configurations R Stand ar d Configur atio n with U AR T or JT A G Pr og rammi ng Int erface The second read/ write port on the block RAM provides a convenien t means to update the PicoBlaze instruction store without reco[...]

  • Page 61

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 61 UG129 (v 1.1.2) J une 24, 200 8 T wo PicoBlaz e Microcontrollers with S eparate 512x1 8 Code Images in a Block RAM R T wo PicoBlaze Microcontr oller s with Separate 512x18 Code Images in a Block RAM T wo PicoBlaze micr oco ntr ollers can also shar e a s ingle du al-port RAM but each[...]

  • Page 62

    62 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 7: Instruction Stor age Configurations R T o maintain com patibility wi th block RAM, the dis tributed ROM must have a registered output using CLB flip-flops. The CORE Generator s oftware can cr eate all of the above dis tributed ROM functions [...]

  • Page 63

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 63 UG129 (v 1.1.2) J une 24, 200 8 R Chapter 8 Performance Input Clock Frequency Ta b l e 8 - 1 shows the maximum available perform ance for the PicoBlaze™ microcontr oller using various FPG A families and speed grad es. The V irtex ® -II and V irtex-II Pro FPGA families are optimiz[...]

  • Page 64

    64 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapt er 8: P erf ormance R[...]

  • Page 65

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 65 UG129 (v 1.1.2) J une 24, 200 8 R Chapter 9 PicoBlaze Development T ools There are thr ee primary development environments for cr eatin g PicoBlaze™ pro cessor applicatio n code, as sum marized in Ta b l e 9 - 1 . Xilinx offers two PicoBlaze environments. The PicoBlaze reference d[...]

  • Page 66

    66 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 9: PicoBlaz e Development T ools R Open a DOS b ox and navigate to the wo rking directory . T o assemble the PicoBlaz e program, type: kcpsm3 <filename>[.psm] Assembly Error s The assembler halts as soon as an error is detected. A short m[...]

  • Page 67

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 67 UG129 (v 1.1.2) J une 24, 200 8 Mediatr onix pBlazIDE R The assembler al so produces a log file plus files that sho w the assign ments for va rious labels and consta nts found in the source code. The log file s hows the instruction ad dr ess, the opcode for each instruction , and th[...]

  • Page 68

    68 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 9: PicoBlaz e Development T ools R Impor ting KCPSM3 Code into pBlazIDE The pBlazID E syntax and in structi on mnemo nics ar e dif fer ent than the Xilinx K CPSM3 syntax. The pBlazIDE softwar e provides an import function to convert KCPSM3 code[...]

  • Page 69

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 69 UG129 (v 1.1.2) J une 24, 200 8 Differences Between the K CPSM3 Asse mbler and pBla zIDE R Differences Between the KCPSM3 Assem bler and pBlazIDE Ta b l e 9 - 2 detai ls the diff erences between the KCPSM3 and pBlazID E instruction mnemo nics. Directives Ta b l e 9 - 3 lists the KCP[...]

  • Page 70

    70 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 9: PicoBlaz e Development T ools R[...]

  • Page 71

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 71 UG129 (v 1.1.2) J une 24, 200 8 R Chapter 10 Using the PicoBlaze Micr ocontr oller in an FPGA Design The PicoBlaze ™ microcontr oller is primaril y designed for use in a VHDL desi gn flow . However , both V erilo g and bl ack box in stanti ation ar e al so support ed, as described[...]

  • Page 72

    72 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 10: Usi ng the PicoBlaze Mi cr ocontr oller in an FPGA Design R Connecting the P rogr am R OM The PicoBlaze pr ogram ROM is used w ithin a VHDL design flow . The PicoBlaze assembler generates a VHDL file in which a block RAM and its initial con[...]

  • Page 73

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 73 UG129 (v 1.1.2) J une 24, 200 8 Black Bo x Instan tiation of KCPS M3 using KCP SM3.ngc R Black Bo x Instantiation of KCPSM3 us ing KCPSM3.ngc The Xilinx NGC file included with th e r eferen ce design was g enerated by synthesizing the KCPSM3.vhd file using the Xilin x Synthesis T oo[...]

  • Page 74

    74 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 10: Usi ng the PicoBlaze Mi cr ocontr oller in an FPGA Design R[...]

  • Page 75

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 75 UG129 (v 1.1.2) J une 24, 200 8 R Chapter 1 1 Assembler Dir ectives Both the KCPSM3 and pBlazIDE assemblers include dir ectives that pro vide advanced control. Locating Co de at a Specific Address In some cases, application code m ust be assigned to a specific instructio n address. [...]

  • Page 76

    76 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 11: Assembler Directives R Defining Co nstants Similar to renaming registers, assign names to con stant values. By defin ing names for c o n s t a n t s , i t i s e a s i e r t o u n d e r s t a n d a n d d o c u m e n t t h e P i c o B l a z[...]

  • Page 77

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 77 UG129 (v 1.1.2) J une 24, 200 8 Defining I/O Po r ts (pBlazIDE) R Input P or ts The DSIN directive defines the name and the por t address (or po rt identification number) for a read-only input po rt. The DSIN directive models an inpu t port that only conn ects to the P icoBl aze mic[...]

  • Page 78

    78 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 11: Assembler Directives R specifies a te xt file that records the result of any outp ut operatio ns to this d uring instruction se t simulation. Fi gure 1 1-5 provides an example. The values recor d ed in the optional output file ar e always[...]

  • Page 79

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 79 UG129 (v 1.1.2) J une 24, 200 8 Custom Instruction Op-Codes R Dur ing in str uct ion set s imula tio n, p BlazI DE dis pla ys th e r ead able o utpu t por t as s hown in Figure 1 1-8 . The port value can be modified fro m the graphical interface. Custom Instruction Op -Codes The pBl[...]

  • Page 80

    80 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chap te r 11: Assembler Directives R[...]

  • Page 81

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 81 UG129 (v 1.1.2) J une 24, 200 8 R Chapter 12 Simulating PicoBlaze Code V a rious tools support PicoBlaze code simulation, each with distinct st r engths and weakne sses as des cribed in T able 12-1 . For example, the pBlazIDE Instr uction Set Simulat or (ISS) is best for simulat ing[...]

  • Page 82

    82 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 12: Simulating PicoBlaze Code R Furthermore, the pBlazIDE ISS o f fers full single-step and breakpoint support whi le viewing the PicoBlaze assembly source code. Evaluate the softwar e timing for end applicatio n. Observe code coverage. Simulat[...]

  • Page 83

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 83 UG129 (v 1.1.2) J une 24, 200 8 Instruction Set Sim ulation with pBlazIDE R Sim ulator Control Butt ons Ta b l e 1 2 - 2 shows the vario us pBlazIDE control buttons and describes thei r functions. Figure 12- 1: The pBlazIDE Instr uction Set Simulator (ISS) pBlaze IDE File Ed i t Vie[...]

  • Page 84

    84 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 12: Simulating PicoBlaze Code R Using the pBlazIDE Inst ruction Set Simulator with KCPSM3 Pro gr ams The pBlazIDE so ftware primarily supports on ly a VHDL design flo w , which is su f ficient for many appl ications. The KCP SM3 assemb le r sup[...]

  • Page 85

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 85 UG129 (v 1.1.2) J une 24, 200 8 T urbocharging Sim ulation using FPGAs! R T urboc har ging Sim u latio n usi ng FP GAs! Har dwa r e si mula tor s tr ack r esults with p ico sec ond or na noseco nd res olu tion . In con tras t, the Pico Blaze mi cro contr olle r is o ften empl oyed i[...]

  • Page 86

    86 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter 12: Simulating PicoBlaze Code R[...]

  • Page 87

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 87 UG129 (v 1.1.2) J une 24, 200 8 R Appendix A Related Materials and Refer ences This appendix provides links to a dditional inf ormation relevant to a PicoBlaze™ processor design. 1. PicoBlaze 8 -bit Embedde d Microcontrolle r Download P icoBlaze r efer ence designs and additional [...]

  • Page 88

    88 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Chapter : Re lated Materials and References R[...]

  • Page 89

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 89 UG129 (v 1.1.2) J une 24, 200 8 R Appendix B Example Pr ogram T emplates The following code templates pr ovide the basic r ecommended structur e for PicoBlaze™ processor application programs. Both KCPS M3 and pBlazIDE t emplates are pr ovided . KCPSM3 Syntax Figure B-1 provides a [...]

  • Page 90

    90 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Appendi x : Exampl e Program T emplate s R pBlazIDE Syntax Figure B-2 provides a code template for creating PicoBlaze applica tions using the pBlazI DE ass embler . Figure B- 2: Pic oBlaze Ap plication Progra m T emplate for KCPSM3 Assembler <name&g[...]

  • Page 91

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 91 UG129 (v 1.1.2) J une 24, 200 8 R Appendix C PicoBlaze Instruction Set and Event Refer e nce This appendix provides a detailed o perationa l description of each PicoBl aze™ processor instruction and th e Interrupt and Reset events, inclu ding pseudocod e for each instruction. The [...]

  • Page 92

    92 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R Pseudocode sX Å (sX + Operand) mod 256; always an 8-bit result if ( (sX + Operand) > 255 ) then CARRY Å 1 else CARRY Å 0 endif if ( ((sX + Operand) = 0) or ((sX + Op erand) = 256) ) t[...]

  • Page 93

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 93 UG129 (v 1.1.2) J une 24, 200 8 AND sX, Operand — Logical Bitwise AND Registe r sX with Operand R Pseudocode if (CARRY = 1) then sX Å (sX + Operand + 1) mod 256; always an 8-bit result else sX Å (sX + Operand) mod 256 ; always an 8-bit result end if if ( (sX + Operand + CARRY) &[...]

  • Page 94

    94 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R Examples AND sX, sY ; Logically AND the individua l bits of register sX with ; the corresponding bits in register sY AND sX, kk ; Logically AND the individua l bits of register sX with ; th[...]

  • Page 95

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 95 UG129 (v 1.1.2) J une 24, 200 8 CALL [Condition,] Addr ess — Call Subroutine a t Specified Address, P ossib ly with Conditions R Condition Depending on the specified Con dition, the program calls the subroutine beginni ng at the specified Address. If the specified Co ndition is no[...]

  • Page 96

    96 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R COMP ARE sX, Operand — Compare Operand with Re gister sX The COMPARE inst ruct ion pe rforms an 8-bit comparis on of t wo operan ds, as s hown in Figure C-4 . The first operand, sX , is a[...]

  • Page 97

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 97 UG129 (v 1.1.2) J une 24, 200 8 DISABLE INTERRUPT — Disable External Interrupt Input R DISABLE INTERRUPT — Disable External Interrupt Input The DISABLE INTERRUPT instruction clears the interrupt enable (IE) flag. Consequently , the PicoBlaz e micr ocontroller ignores the IN TERR[...]

  • Page 98

    98 www .xilinx.c om PicoBlaze 8- bit Embedde d Micr oco ntrol ler UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R FETCH sX, Operand — Read Scratchpad RAM Location to Reg ister sX The FETCH instruction r eads s cratchpad RAM location specified by Operand in to register sX , as shown in Figure C-5 . Th[...]

  • Page 99

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 99 UG129 (v 1.1.2) J une 24, 200 8 INPUT sX, O perand — S et PORT_ID to Opera nd, Read v alue on IN_ PORT into Register sX R INPUT sX, Operand — Set POR T_ID to Operand, Read value on IN_POR T into Register sX The INPUT instruction sets the PORT_ID output po rt to either the value [...]

  • Page 100

    100 www .xilinx.com PicoBla ze 8-bit Em bedded M icr ocontr oller UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R INTERR UPT Event, When En abled The interrupt event is not an instructio n but the response of the PicoBlaze microcontroller to an external i nterrupt input. If the INTERRU PT_ENABLE flag i[...]

  • Page 101

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 101 UG129 (v 1.1.2) J une 24, 200 8 JUMP [Condition,] Address — J ump to Specified Addr ess, P ossibl y with Conditions R JUMP [Conditio n,] Address — J ump to Specified Address, P ossibl y with Conditions The JUMP instruction modifies the normal pr ogram execution sequence by jump[...]

  • Page 102

    102 www .xilinx.com PicoBla ze 8-bit Em bedded M icr ocontr oller UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R LO AD sX, Operand — L oad Register sX with Op erand The LOAD instruction load s the contents of any register . The new value is either the contents of a ny other register or a n immediate[...]

  • Page 103

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 103 UG129 (v 1.1.2) J une 24, 200 8 OR sX, Operand — Logical Bitwise OR Register sX with Operand R OR sX, Operand — Logical Bitwise OR R egister sX with Operand The OR instruction performs a bitwise logical OR operation between two operands, as shown in Figure C-6 . The first opera[...]

  • Page 104

    104 www .xilinx.com PicoBla ze 8-bit Em bedded M icr ocontr oller UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R OUTPUT sX, Op erand — Write Register sX V a lue to OUT_PORT , Set POR T_ID to Operand The OUTPUT instruction sets the PO R T_ID port address to the value specif ied by either the reg i st[...]

  • Page 105

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 105 UG129 (v 1.1.2) J une 24, 200 8 RESET Ev ent R RESET Event The reset event is not an instruction but the response of the Pico Blaze microcontroller when the RESET in put is High. A RESET Event restarts the Pico Blaze microcontroller and clears various hardw are elements, as s hown [...]

  • Page 106

    106 www .xilinx.com PicoBla ze 8-bit Em bedded M icr ocontr oller UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R RETURN [Con dition] — Return from Subroutine Call, P os sibl y with Condition s The RETURN instruction is the compl ement to the CALL ins truction. The RETURN instruction is al so conditi[...]

  • Page 107

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 107 UG129 (v 1.1.2) J une 24, 200 8 RETURNI [ENABLE/DISABLE] — Return from Interr upt Service Routine and Enable or Dis able R PBlazIDE Eq uivalent : RET , RET C , RET NC , RET Z , RET NZ RETURNI [ENABLE/D ISABLE] — Return f r om Interrupt Ser vice Routine and Enable or Disable Int[...]

  • Page 108

    108 www .xilinx.com PicoBla ze 8-bit Em bedded M icr ocontr oller UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R RL sX — Rot ate Left Register sX The rotate left instruction operates on any sing le data r egister . Each bit in th e specified register is shifted left by on e bit position, as shown in[...]

  • Page 109

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 109 UG129 (v 1.1.2) J une 24, 200 8 SL[ 0 | 1 | X | A ] sX — S hift Lef t Reg ist er sX R Example RR sX; Rotate right. Bit sX[0] copied into CARRY Pseudocode CARRY Å sX[0] sX Å {sX[0], sX[7:1]} if ( sX = 0 ) then ZERO Å 1 else ZERO Å 0 endif PC Å PC + 1 Registers/Flags Al tered [...]

  • Page 110

    110 www .xilinx.com PicoBla ze 8-bit Em bedded M icr ocontr oller UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R Examples SL0 sX; Shift left. 0 shifts into LSB, MSB shifts into CARRY. SL1 sX; Shift left. 1 shifts into LSB, MSB shifts into CARRY. SLX sX; Shift left. LSB shifts into LS B, MSB shifts int[...]

  • Page 111

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 111 UG129 (v 1.1.2) J une 24, 200 8 SR[ 0 | 1 | X | A ] sX — Shift Ri ght Register sX R The ZERO flag is alwa ys 0 afte r executing th e SR1 instruction beca use re gister sX is never zero. Example SR0 sX; Shift right. 0 shifts into MSB, LSB shifts into CARRY. SR1 sX; Shift right. 1 [...]

  • Page 112

    112 www .xilinx.com PicoBla ze 8-bit Em bedded M icr ocontr oller UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R Registers/Flags Al tered Register s: sX, PC Flags: CARRY , ZERO ST ORE sX, Ope rand — Write Register sX V alue to Scratc hpad RAM Location The STORE instruction writes r egister sX to the[...]

  • Page 113

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 113 UG129 (v 1.1.2) J une 24, 200 8 SUB sX, O perand —Su btract O perand from Regi ster sX R The STORE instruction is only s upported on PicoBlaze mi cr ocontrollers for Spartan -3, V irtex-II, and V irtex-II Pro FPGAs. SUB sX, Operand —Subtract Operand from Register sX The SUB ins[...]

  • Page 114

    114 www .xilinx.com PicoBla ze 8-bit Em bedded M icr ocontr oller UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R Pseudocode sX Å (sX – Operand) mod 256; always an 8-bit result if ( (sX – Operand) < 0 ) then CARRY Å 1 else CARRY Å 0 endif if ( (sX - Operand) = 0 ) then ZERO Å 1 else ZERO Å [...]

  • Page 115

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 115 UG129 (v 1.1.2) J une 24, 200 8 SUBCY sX, Operand —Subtract Operand from Re gister sX with Borro w R Description Operand an d CARR Y flag ar e subtracted fr om r egi ster sX . The Z ERO an d CA RR Y flag s are set appropriately . Pseudocode if (CARRY = 1) then sX Å (sX - Operand[...]

  • Page 116

    116 www .xilinx.com PicoBla ze 8-bit Em bedded M icr ocontr oller UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R TEST sX, Operand — T est Bit Loc ation in Register sX, Ge nerate Odd P arity The TEST inst ruct ion p erfo rms t wo rel ated but separ ate oper atio ns. T he ZE RO fl ag indicates the res[...]

  • Page 117

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 117 UG129 (v 1.1.2) J une 24, 200 8 TEST sX, Operand — T est Bit Location in Register sX, Generate Odd P arity R Pseudocode ; logically AND the corresponding bits in sX and the Operand for (i=0; i<= 7; i=i+1) { AND_TEST(i) Å sX(i) AND Op erand(i) } if (AND_TEST = 0) then ZERO Å [...]

  • Page 118

    118 www .xilinx.com PicoBla ze 8-bit Em bedded M icr ocontr oller UG129 (v 1.1.2) J une 24, 200 8 Appen dix : Pico Blaze In struction S et and Event Reference R XOR sX, Operand — Logical Bitwise XOR Register sX with Operand The XOR instruction performs a bitwise logical XOR operation between two o perands, as shown in Fig ure C-13 . The first op [...]

  • Page 119

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 119 UG129 (v 1.1.2) J une 24, 200 8 R Appendix D Instruction Codes Ta b l e D - 1 provides the 18-bit i nstruction code for every P icoBlaze™ processor instruction. Ta b l e D - 1 : PicoBlaze Instruction Codes Instruction 17 16 15 14 13 12 11 10 987654321 0 ADD sX,kk 0 1 1 0 0 0 x x [...]

  • Page 120

    120 www .xilinx.com PicoBla ze 8-bit Em bedded M icr ocontr oller UG129 (v 1.1.2) J une 24, 200 8 Append ix : Instruction Codes R JUMP Z 11010100aa aaaaaaaa LOAD sX,kk 0 0 0 0 0 0 x x x x k k k k k k k k LOAD sX,sY 0 0 0 0 0 1 x x x x y y y y 0 0 0 0 OR sX,k k 0 0 1 1 0 0 x x x x k k k k k k k k OR sX,s Y 0 0 1 1 0 1 x x x x y y y y 0 0 0 0 OUTPUT [...]

  • Page 121

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 121 UG129 (v 1.1.2) J une 24, 200 8 R XOR sX,kk 0 0 1 1 1 0 x x x x k k k k k k k k XOR sX,sY 0 0 1 1 1 1 x x x x y y y y 0 0 0 0 Ta b l e D - 1 : PicoBlaze Instruction Codes (Continued) Instruction 17 16 15 14 13 12 11 10 987654321 0 a Absolu te instruction address x Register sX y Reg[...]

  • Page 122

    122 www .xilinx.com PicoBla ze 8-bit Em bedded M icr ocontr oller UG129 (v 1.1.2) J une 24, 200 8 Append ix : Instruction Codes R[...]

  • Page 123

    Pico Blaz e 8- bit Em bedded Microco ntrolle r www .xilinx.c om 123 UG129 (v 1.1.2) J une 24, 200 8 R Appendix E Register and Scratc hpad RAM Planning W orksheets This appendix provides worksh eets to plan register assign ment and alloca tion for a PicoBlaz e™ pr ocess or applic ation. A simil ar work sheet is also pr ovide d to plan scratch pad [...]

  • Page 124

    124 www .xilinx.com PicoBla ze 8-bit Em bedded M icr ocontr oller UG129 (v 1.1.2) J une 24, 200 8 Appendi x : Register and Scratc hpad RAM Planning W orksheets R Scratchpad RAM Loc. Description Loc . Description 00 20 01 21 02 22 03 23 04 24 05 25 06 26 07 27 08 28 09 29 0A 2A 0B 2B 0C 2C 0D 2D 0E 2E 0F 2F 10 30 11 3 1 12 32 13 33 14 34 15 35 16 36[...]