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Xilinx UG518 manual

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Table of contents for the manual

  • Page 1

    [Guide Subtitle] [optional] UG518 (v1.1) A ugust 19, 2009 [ optional] SP601 Har d ware User Guide UG518 (v1.1) A ugust 19, 2009[...]

  • Page 2

    SP601 Hard ware Us er Guide www .xilin x.com UG518 (v1.1) A ug ust 19, 2009 Xilinx is disclosing this user gui de, manual, release note , and/or specification (the "Documentation") to y ou solely for use in the de velop ment of designs to operate with Xilinx hardw are devices . Y ou ma y not reproduce, distribu te, republish, do wnload, d[...]

  • Page 3

    UG518 (v1.1) August 19, 2009 www .xilin x.com SP601 Hardware User Guide Revision History The following table shows the revision history for this document. Date V ersion Revision 07/15/2009 1.0 Initial Xilinx release. 08/19/2009 1.1 • Added Appendix C, “VIT A 57.1 FMC Connections.” • Updated Figur e 1- 18 and Figure 1-32 . • Updated Ta b l[...]

  • Page 4

    SP601 Hard ware Us er Guide www .xilin x.com UG518 (v1.1) A ug ust 19, 2009[...]

  • Page 5

    SP601 Hard ware Us er Guide www .xilin x.com 5 UG518 (v1.1) August 19, 2009 Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [...]

  • Page 6

    6 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Appendix A: References Appendix B: Default Jump er and Switch Settings Appendix C: VITA 57.1 FMC Connections Appendix D: SP601 Master UCF[...]

  • Page 7

    SP601 Hard ware Us er Guide www .xilin x.com 7 UG518 (v1.1) August 19, 2009 Pr eface About This Guide This manual accompan ies the Spartan®-6 FP GA SP601 Evaluation Boar d and cont ains information about the SP601 hardwar e and software tools. Guide Contents This manual contains the following chapters: • Chapter 1, “SP601 Evaluation Board,” [...]

  • Page 8

    8 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Pref ace: About This Guide Online Document The following conventions ar e used in this document: Italic font V ariables in a syntax statement for which you must supply values ngdbuild design_name References to other manuals See the User Guide for more information. Emphasis [...]

  • Page 9

    SP601 Hard ware Us er Guide www .xilin x.com 9 UG518 (v1.1) August 19, 2009 Chapter 1 SP601 Evaluation Board Overview The SP601 board enables har dware and software developers to cr eate or evaluate designs targeting the Spartan®-6 XC6SLX16-2 CSG324 FPGA. The SP601 provides boar d features for evaluati ng the Spartan-6 family that are comm on to m[...]

  • Page 10

    10 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board F eatures The SP601 board pr ovides the following features: • 1. Spartan-6 XC6SLX16-2CS G324 FPGA • 2. 128 MB DDR2 Component Memory • 3. SPI x4 Flash • 4. Linear Flash BPI • 5. 10/100/1000 T r i-Speed Ethernet PHY • 7. IIC Bus [...]

  • Page 11

    SP601 Hard ware Us er Guide www .xilin x.com 11 UG518 (v1.1) August 19, 2009 Related Xili nx Documents Bloc k Diagram Figur e 1- 1 shows a high-level block diagram of the SP601 and its peripherals. Related Xilinx Documents Prior to using the SP601 Evaluation Board, user s sh ou ld be f am il iar wi th X il in x res ourc es. See the following locati[...]

  • Page 12

    12 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board Detailed Description Figur e 1-2 shows a board photo with number ed features corresponding to Ta b l e 1 -1 and the section headings in this document. The numbere d features in Figur e 1-2 correlate to the features and not es listed in Ta [...]

  • Page 13

    SP601 Hard ware Us er Guide www .xilin x.com 13 UG518 (v1.1) August 19, 2009 Detailed Des cription 1. Spar tan-6 XC6SLX16-2CSG 3 24 FPGA A Xilinx Spartan-6 XC6SLX16-2CSG324 FPGA is install ed on the Embedded Development Board. Configuration The SP601 supports configuration in the following modes: • Master SPI x4 • Master SPI x4 with of f-board [...]

  • Page 14

    14 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board Ref erences See the Xilinx Spartan-6 FPGA docu mentation for mor e information at http://www .xilinx.com/support/documentation/spartan-6.htm . 2. 128 MB DDR2 Component Memor y There ar e 128 MB of DDR2 memory available on the SP601 board. [...]

  • Page 15

    SP601 Hard ware Us er Guide www .xilin x.com 15 UG518 (v1.1) August 19, 2009 Detailed Des cription Ta b l e 1 - 5 shows the connections and pin numbers for the DDR2 Component Memory . T able 1- 5: DDR2 Component Memory Connections FPGA U1 Schematic Net name Memory U2 Pin Number Name J7 DDR2_A0 M8 A0 J6 DDR2_A1 M3 A1 H5 DDR2_A2 M7 A2 L7 DDR2_A3 N2 A[...]

  • Page 16

    16 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board Figur e 1-3 provides the user constraints file (UCF) for the DDR2 SDRAM address pins, including the I/O pin assignment and the I/O standar d used. F2 DDR2_BA0 L2 BA0 F1 DDR2_BA1 L3 BA1 E1 DDR2_BA2 L1 BA2 E3 DDR2_WE_B K3 WE L5 DDR2_RAS_B K7[...]

  • Page 17

    SP601 Hard ware Us er Guide www .xilin x.com 17 UG518 (v1.1) August 19, 2009 Detailed Des cription Figur e 1-4 provides the UCF constraints for the DDR2 SDRAM d ata pins, including the I/O pin assignment and I/O standard used. Figur e 1-5 provides the UCF constraints for the DDR2 SDRAM contr ol pins, including the I/O pin assignment and the I/O sta[...]

  • Page 18

    18 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board 3 . SPI x4 Flash The Xilinx Spartan-6 FPGA hosts a SPI interfa ce which is visible to the Xili nx iMP ACT configuration tool. The SPI memory device oper ates at 3.0V ; the Spartan-6 FPGA I/Os are 3.3V tolerant and provide electrically comp[...]

  • Page 19

    SP601 Hard ware Us er Guide www .xilin x.com 19 UG518 (v1.1) August 19, 2009 Detailed Des cription X-Ref Target - Figure 1-7 Figure 1- 7: SPI Flash Interface T opology T able 1- 6: SPI x4 Memory Connections FPGA U1 Pin Schematic Netname SPI MEM U17 SPI HDR J12 Pin # Pin Name Pin # Pin Name V2 FPGA_PROG_B 1 V14 FPGA_D2_MISO3 1 IO3_HOLD_B 2 T14 FPGA_[...]

  • Page 20

    20 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board Figur e 1-8 provides the UCF constraint s for the SPI serial flash PR OM. Ref erences See the W inbond Serial Flash specifications for more information at http://www .winbond- usa.com/hq/enu/Pr oductAndS ales/ProductLines/FlashMemory/Seria[...]

  • Page 21

    SP601 Hard ware Us er Guide www .xilin x.com 21 UG518 (v1.1) August 19, 2009 Detailed Des cription H16 FLASH_A6 23 A6 H15 FLASH_A7 22 A7 H14 FLASH_A8 20 A8 H13 FLASH_A9 19 A9 F18 FLASH_A10 18 A10 F17 FLASH_A1 1 17 A1 1 K13 FLASH_A12 13 A12 K12 FLASH_A13 12 A13 E18 FLASH_A14 1 1 A14 E16 FLASH_A15 10 A15 G13 FLASH_A16 8 A16 H12 FLASH_A17 7 A17 D18 FL[...]

  • Page 22

    22 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board Note: Memor y U10 pin 56 address A24 is not connected on the 16 MB device . It is made av ailable f or larg er density de vices. Ref erences See the Numonyx Flash Memory specifications for more information at http://www .nu monyx.com/Docum[...]

  • Page 23

    SP601 Hard ware Us er Guide www .xilin x.com 23 UG518 (v1.1) August 19, 2009 Detailed Des cription 5. 10/100/1000 T ri-Speed Ether net PHY The SP601 uses the onboar d Marvell Alaska P H Y d e v i c e ( 8 8 E 11 11 ) f o r E t h e r n e t communications at 10, 100, or 1000 Mb/s. Th e board supports a GMII/MII interface from the FPGA to the PHY . The[...]

  • Page 24

    24 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board P18 PHY_RXD7 120 A9 PHY_TXC_GTXCLK 14 B9 PHY_TXCLK 10 A8 PHY_TXER 13 B8 PHY_TXCTL_TXEN 16 F8 PHY_TXD0 18 G8 PHY_TXD1 19 A6 PHY_TXD2 20 B6 PHY_TXD3 24 E6 PHY_TXD4 25 F7 PHY_TXD5 26 A5 PHY_TXD6 28 C5 PHY_TXD7 29 X-Ref Target - Figure 1-11 NE[...]

  • Page 25

    SP601 Hard ware Us er Guide www .xilin x.com 25 UG518 (v1.1) August 19, 2009 Detailed Des cription Ref erences See the Marvell Alaska Gigabit Ethernet T ransc eiver product page for mor e information at http://www .marvell.com/products/tr ansceivers/alaska_gigabit/index.jsp . Also, see th e Xilinx T ri-Mod e Ethernet MAC User Gui de at http://www .[...]

  • Page 26

    26 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board Ref erences T echnical information on the Silicon Labs CP2103GM and the VCP drivers can be found on their website at https://www .silabs.com/Pages/default.aspx . In addition, see some of the Xilinx UAR T IP specifications at: • http://ww[...]

  • Page 27

    SP601 Hard ware Us er Guide www .xilin x.com 27 UG518 (v1.1) August 19, 2009 Detailed Des cription 8-Kb NV Memor y The SP601 hosts a 8-Kb ST Microelectroni cs M24C08-WDW6TP IIC parameter storage memory device (U7) . The IIC address of U7 is 0b1010100, and U7 is not write protected (WP pin 7 is tied to GND). Ref erences See the ST Micro M24C08-WDW6T[...]

  • Page 28

    28 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board Oscillator Sock et (Single-Ended, 2.5V or 3 . 3 V) One populated single-ended clock socket (X2) is provided for user applications. The option of 3.3V or 2.5V power may be selected via a 0 ohm r esistor selection. The SP601 board is shipped[...]

  • Page 29

    SP601 Hard ware Us er Guide www .xilin x.com 29 UG518 (v1.1) August 19, 2009 Detailed Des cription T able 1-13: LPC Pinout KJ H G FE D C B A 1 NC NC VREF_A_M2C GND NC NC PG_C2M GND NC NC 2 NC NC PRSNT_M2C_L CLK1_M2C_P NC NC GND DP0_C2M_P NC NC 3 NC NC GND CLK1_M2C_N NC NC GND DP0_C2M_N NC NC 4 NC NC CLK0_M2C_P GND NC NC GBTCLK0_M2C_P GND NC NC 5 NC[...]

  • Page 30

    30 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board 34 NC NC LA30_P LA31_N NC NC TRST_L GA0 NC NC 35 NC NC LA30_N GND NC NC GA1 12P0V NC NC 36 NC NC GND LA33_P NC NC 3P3V GND NC NC 37 NC NC LA32_P LA33_N NC NC GND 12P0V NC NC 38 NC NC LA32_N GND NC NC 3P3V GND NC NC 39 NC NC GND VA D J NC N[...]

  • Page 31

    SP601 Hard ware Us er Guide www .xilin x.com 31 UG518 (v1.1) August 19, 2009 Detailed Des cription X-Ref T arget - Figure 1-18 NET "FMC_CLK0_M2C_N" LOC = "A10"; NET "FMC_CLK0_M2C_P" LOC = "C10"; NET "FMC_CLK1_M2C_N" LOC = "V9"; NET "FMC_CLK1_M2C_P" LOC = "T9"; NET "[...]

  • Page 32

    32 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board 10. Status LEDs Ta b l e 1 - 1 4 defines the status LEDs. T able 1- 14: Status LEDs Reference Designator Signal Name Color Label Description DS1 FMC_PWR_GOOD_ FLASH_RST_B Green PWR GOOD Indicates power available for VIT A 57.1 FMC expansio[...]

  • Page 33

    SP601 Hard ware Us er Guide www .xilin x.com 33 UG518 (v1.1) August 19, 2009 Detailed Des cription 11. FPGA A wak e LED and Suspend Jumper The suspend mode jumper perm its the FP GA to enter an inactive, "su spend" mode. The FPGA A w ake LED DS 8 will go o ut when th e FPGA ent ers this m ode. See the Spartan-6 FPGA Conf iguration Guide f[...]

  • Page 34

    34 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board 12. FPGA INIT and DONE LEDs The typical Xilinx FPGA power up and conf iguration status LEDs are pres ent on the SP601. The INIT LED DS10 comes on after the FPGA powers up and completes its internal power-on pr ocess. The DONE LED DS9 comes[...]

  • Page 35

    SP601 Hard ware Us er Guide www .xilin x.com 35 UG518 (v1.1) August 19, 2009 Detailed Des cription 1 3 . User I/O The SP601 provides the following user and general purpose I/O capabilities: • User LEDs • User DIP switch • Pushbutton switches • CPU Reset pushbutton switch • GPIO male pin header Note: All GPIO location constraints are colle[...]

  • Page 36

    36 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board User DIP s witch The SP601 includes an active high four pole DIP switch, as described in Figur e 1-24 and Ta b l e 1 - 1 8 . DS13 GPIO_LED_2 Gr een C4 DS14 GPIO_LED_3 Gr een A4 T able 1- 17: User LEDs (Cont’ d) Reference Designator Signa[...]

  • Page 37

    SP601 Hard ware Us er Guide www .xilin x.com 37 UG518 (v1.1) August 19, 2009 Detailed Des cription User Pushb utton Switches The SP601 provides five active high pushbu tton switches: SW6, SW4, SW5, SW7 and SW 9. The five pushbuttons all have the same topology as the sample shown in Fi gure 1-25 . Four pushbuttons are assigned as GPIO, and th e fift[...]

  • Page 38

    38 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board GPIO Male Pin Header The SP601 provides a 2X6 GPIO male pin he ader supporting 3.3V power , GND and eight I/Os. Figure 1-26 and Ta b l e 1 - 2 0 describe the J13 GPIO Male Pin Header . X-Ref Target - Figure 1-26 Figure 1- 26: GPIO Male Pin[...]

  • Page 39

    SP601 Hard ware Us er Guide www .xilin x.com 39 UG518 (v1.1) August 19, 2009 Detailed Des cription X-Ref Target - Figure 1-27 NET "GPIO_LED_0" LOC = "E13"; NET "GPIO_LED_1" LOC = "C14"; NET "GPIO_LED_2" LOC = "C4"; NET "GPIO_LED_3" LOC = "A4"; NET "GPIO_SWITCH_0&qu[...]

  • Page 40

    40 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board 14. FPGA_PR OG_B Pushbutton Switch The SP601 provides one dedicated, active low FPGA_PROG_B pushbutton switch, as shown in Figure 1- 28 . P ower Management A C Adapter and 5V Input P ower J ac k/Switch The SP601 is powered from a 5V source[...]

  • Page 41

    SP601 Hard ware Us er Guide www .xilin x.com 41 UG518 (v1.1) August 19, 2009 P ower Management The SP601 uses power solutions fr om L TC. An estimate of the current draw on the var ious power supply rails is shown in Ta b l e 1 - 2 2 . X-Ref Target - Figure 1- 3 0 Figure 1-30 : Po wer Suppl y 5V PWR J a ck D ua l S witcher L TM4616 3. 3V@ 8 A m a x[...]

  • Page 42

    42 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board Configuration Options The FPGA on the SP601 Evaluation Boar d can be configured by the following methods: • “3. SPI x4 Flash,” page 18 • “4. Linear Flash BPI,” page 20 • “JT AG Configuration,” page 42 For more information[...]

  • Page 43

    SP601 Hard ware Us er Guide www .xilin x.com 43 UG518 (v1.1) August 19, 2009 Configuration Options Th e J T A G c h a i n c a n be u s e d t o p ro g r a m t h e F P G A an d ac c e s s t h e F P G A fo r h a rd w a re a n d software debug. The JT AG connector (USB Mini-B J10) allows a host computer to download bitstreams to the FPGA using the iMP [...]

  • Page 44

    44 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Chapter 1: SP601 Evaluation Board[...]

  • Page 45

    SP601 Hard ware Us er Guide www .xilin x.com 45 UG518 (v1.1) August 19, 2009 Appendix A Refer ences This section pr ovides refer ences to docume ntation supporting Spartan-6 FPGAs, tools, and IP . For additional informati on, see www .xilinx.com/support/documentation/index.htm . Documents supporting the SP601 Evaluation Board: 1. UG138 , LogiCORE?[...]

  • Page 46

    46 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Appendix A: Ref erences[...]

  • Page 47

    SP601 Hard ware Us er Guide www .xilin x.com 47 UG518 (v1.1) August 19, 2009 Appendix B Default Jumper and Switch Settings Ta b l e B - 1 shows the default jumper and switch settings f or the SP601. Ta b l e B - 1 : Default J umper and Switch Settings REFDES T ype/F unction Default SW1 SLIDE, POWER ON-OFF OFF SW2 DIP , 2-POLE, MODE 1M 0 O N ( 1 ) 2[...]

  • Page 48

    48 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Appendix B: Default Jumper and Switch Settings[...]

  • Page 49

    SP601 Hard ware Us er Guide www .xilin x.com 49 UG518 (v1.1) August 19, 2009 Appendix C VIT A 57.1 FMC Connections Ta b l e C - 1 shows the VIT A 57.1 FMC LPC connections. T able C- 1: VIT A 57.1 FMC LPC Connections J1 FMC LPC Pin Schematic Netname U1 FPGA Pin J1 FMC LPC Pin Schematic N etname U1 FPGA Pin C10 FMC_LA06_P D12 D1 FMC_PWR_GOOD_FLASH_RS[...]

  • Page 50

    50 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Appendix C: VIT A 57.1 FMC Connections G13 FMC_LA08_N E1 1 H13 FMC_LA07_P E7 G15 FMC_LA12_P D6 H14 FMC_LA07_N E8 G16 FMC_LA12_N C6 H16 FMC_LA1 1_P B12 G18 FMC_LA16_P C7 H17 FMC_LA1 1_N A12 G19 FMC_LA16_N A7 H19 FMC_LA15_P G9 G21 FMC_LA20_P N7 H20 FMC_LA15_N F9 G22 FMC_LA20[...]

  • Page 51

    SP601 Hard ware Us er Guide www .xilin x.com 51 UG518 (v1.1) August 19, 2009 Appendix D SP601 Master UCF The UCF template is pr ovided for designs that target the SP601. Net names pr ovided in the constraints below corr elate with net names on the SP601 r ev . C schematic. On identifying the appropriate pins , the net names below should be replaced[...]

  • Page 52

    52 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Appendix D: SP601 Mast er UCF NET "DDR2_LDQS_P" LOC = "L4"; NET "DDR2_ODT" LOC = "K6"; NET "DDR2_RAS_B" LOC = "L5"; NET "DDR2_UDM" LOC = "K4"; NET "DDR2_UDQS_N" LOC = "P1"; [...]

  • Page 53

    SP601 Hard ware Us er Guide www .xilin x.com 53 UG518 (v1.1) August 19, 2009 NET "FMC_LA07_P" LOC = "E7"; NET "FMC_LA08_N" LOC = "E11"; NET "FMC_LA08_P" LOC = "F11"; NET "FMC_LA09_N" LOC = "F10"; NET "FMC_LA09_P" LOC = "G11"; NET "FMC_LA10_N&quo[...]

  • Page 54

    54 www .xilin x.com SP601 Hardware User Guide UG518 (v1.1) A ugust 19 , 2009 Appendix D: SP601 Mast er UCF NET "FPGA_CMP_MOSI" LOC = "V16"; NET "FPGA_D0_DIN_MISO_MISO1" LOC = "R13"; NET "FPGA_D1_MISO2" LOC = "T14"; NET "FPGA_D2_MISO3" LOC = "V14"; NET "FPGA_DONE&qu[...]

  • Page 55

    SP601 Hard ware Us er Guide www .xilin x.com 55 UG518 (v1.1) August 19, 2009 NET "PHY_TXCTL_TXEN" LOC = "B8"; NET "PHY_TXC_GTXCLK" LOC = "A9"; NET "PHY_TXD0" LOC = "F8"; NET "PHY_TXD1" LOC = "G8"; NET "PHY_TXD2" LOC = "A6"; NET "PHY_TXD3" L[...]