Intel 2 Duo T7500 manual

Intel® Core™2 Duo Processors and Intel® Core™2 Extreme Processors for Platforms Based on Mobile Intel® 965 Express Chipset Family Datasheet January 2008 Document Number: 316745-005[...]

2 Datasheet Legal Lines and Discl aimers INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTE L® PRODUCTS. NO LICENSE, EXPRESS OR IMP LIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTE D BY TH IS DOCUMENT . EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUC H PRODUCTS, INTEL ASSUMES NO L[...]

Datasheet 3 Contents 1I n t r o d u c t i o n ......... ........... ........ ........... .......... ........... .......... ........... .......... ........... ........ 7 1.1 Terminology ........... .......... ........... .......... ........... .......... ........... .......... ........... ........ 8 1.2 Referen ces .... ........... .......... ......[...]

4 Datasheet Figures 1 Core Low Powe r States................ ........... .......... ............. .......... ........... ........... .......... .. 12 2 Package Low Powe r States ........... ........... .......... ........... .......... ............. ........... .......... .. 13 3 Active VCC and ICC Loadline Intel Core 2 Duo Processors - Standard Vo[...]

Datasheet 5 Revision History Document Number Revision Number Description Date 316745 -001 • Initial R elease May 2007 316745 -002 • Updates — Chapter 1 added Intel® Core ™2 Duo processor - Ultra Low V oltage information — Chapter 3 added T able 8 with Intel Core 2 Duo processor - Ultra Low V oltage U7600 and U7500 specifications — Chap[...]

6 Datasheet[...]

Datasheet 7 Introduction 1 Introduction The Intel® Core™2 Duo processor on 65-nm process technology is the next generation high-performance, low-power processor based on the Intel® Core™ microarchitecture. The Intel Core 2 Duo processor supports the Mobile Intel® 965 Express Chipset and Intel® 82801HBM ICH8M Controller Hub Ba sed Systems. T[...]

Introduction 8 Datasheet 1.1 Terminology Term Definition # A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driv en to a low lev el. For example, when RESET# is low , a reset has been requ ested. Con versely , when NMI is high, a nonmaskable interrupt has occurre d. In the case of [...]

Datasheet 9 Introduction 1.2 References Material and concepts available in the fo llowing documents may be beneficial when reading this document. NOTES: 1. Contact your local In tel represent ative fo r the latest revision of this document. § Document Document Number 1,2 Intel® Core™ 2 Duo Proc essors For Intel® Ce ntrino® Duo Processor Techn[...]

Introduction 10 Datasheet[...]

Datasheet 11 Low Power Features 2 Low Power Features 2.1 Clock Control and Low Power States The processor supports low power states both at the individual core leve l and the package level for optimal power management. A core may independently enter th e C1/A utoHAL T , C1/MW AIT , C2, C3, and C4 low power states. When both cores coincide in a comm[...]

Low Power Features 12 Datasheet Figure 1. Core Low Power State s C2 † C0 Stop Gra nt Cor e st at e break P_LVL 2 or MWAIT( C2) C3 † Cor e state break P_LVL 3 or MWAIT( C3) C1/ MWAIT Cor e st at e break MWAIT(C 1) C1/Auto Halt Halt break HLT instruction C4 †‡ Cor e St ate break P_LVL 4 or P_LVL 5 ø or MWAIT(C4 ) STPCLK# de-asserted STPCLK #[...]

Datasheet 13 Low Power Features NOTES: 1. AutoHAL T or MWAIT/C1. 2.1.1 Core Low Po wer State Descrip tions 2.1.1.1 Core C0 St ate This is the normal oper ating state for cores in the processor . 2.1.1.2 Core C1/Auto HALT Powerdo wn State C1/AutoHAL T is a low power state entered when a core executes the HAL T instruction. The processor transitions [...]

Low Power Features 14 Datasheet A System Management Interrupt (SMI) hand ler returns execution to either Normal state or the AutoHAL T Powerdown state. See the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A/3B: System Programmer's Guide for more information. The system can gener ate a STPCLK# while the processor is[...]

Datasheet 15 Low Power Features 2.1.2 Package Low Power State Descriptions 2.1.2.1 Normal State This is the normal oper ating state for the processor . The processor remains in the Normal state when at least one of its core s is in the C0, C1/AutoHAL T , or C1/MWAIT state. 2.1.2.2 Stop-Grant State When the STPCLK# pin is asserted by the chipset, ea[...]

Low Power Features 16 Datasheet In the Sleep state, the processor is incapabl e of responding to snoop transaction s or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep state. Snoop events that occur while in Sleep state or durin[...]

Datasheet 17 Low Power Features Exit from Deeper Sleep or Intel Enhanced Deeper Sleep state is initiated by DPRSTP# deassertion when either core requests a core st ate other than C4 or either core requests a processor performance state ot her than the lowest operating point. 2.1.2.6.1 Intel Enhanced Deeper Sleep Stat e Intel Enhanced Deeper Sleep s[...]

Low Power Features 18 Datasheet 2.2 Enhanced Intel SpeedStep® Technology The processor features Enhanced Intel Sp eedStep T echnology . F ollowing are the key features of Enhanced Intel SpeedStep T echnology: • Multiple voltage and frequency operating po ints provide optimal performance at the lowest power . • V oltage and frequency selection [...]

Datasheet 19 Low Power Features 2.2.1 Dynamic FSB Frequency Switching Dynamic FSB frequency switching effectively reduces the internal bus clock frequency in half to further decrease the minimum processor oper ating frequency from the Enhanced Intel SpeedStep T echnology perf ormance states and achieve the Super Low Frequency Mode (SuperLFM). This [...]

Low Power Features 20 Datasheet The processor implements two software in te rfaces for requesting extended package low power states: MW AIT instruction extensions with sub-state hints and via BIOS by configuring MSR bits to automatically prom ote package low power states to extended package low power states. Extended Stop-Grant and Exte nded Deeper[...]

Datasheet 21 Low Power Features consumption allows for leakage current reduction, which results in platform power savings and extended battery life. There is no platform-level change required to support this feature as long as the VR v endor supports the VID- x feature. 2.6 Processor Power Status Indicator (PSI-2) Signal The processor incorporates [...]

Low Power Features 22 Datasheet[...]

Datasheet 23 Electrical Spec ifications 3 Electrical Specifications 3.1 Power and Ground Pins For clean, on-chip power distribution, the processor has a large number of V CC (power) and V SS (ground) inputs. All power pins must be connected to V CC power planes while all V SS pins must be connected to system ground planes. Use of multiple power and[...]

Electrical Spec ifications 24 Datasheet 0 0 1 0 1 1 0 1.2250 0 0 1 0 1 1 1 1.2125 0 0 1 1 0 0 0 1.2000 0 0 1 1 0 0 1 1.1875 0 0 1 1 0 1 0 1.1750 0 0 1 1 0 1 1 1.1625 0 0 1 1 1 0 0 1.1500 0 0 1 1 1 0 1 1.1375 0 0 1 1 1 1 0 1.1250 0 0 1 1 1 1 1 1.1125 0 1 0 0 0 0 0 1.1000 0 1 0 0 0 0 1 1.0875 0 1 0 0 0 1 0 1.0750 0 1 0 0 0 1 1 1.0625 0 1 0 0 1 0 0 1.[...]

Datasheet 25 Electrical Spec ifications 1 0 0 0 1 0 1 0.6375 1 0 0 0 1 1 0 0.6250 1 0 0 0 1 1 1 0.6125 1 0 0 1 0 0 0 0.6000 1 0 0 1 0 0 1 0.5875 1 0 0 1 0 1 0 0.5750 1 0 0 1 0 1 1 0.5625 1 0 0 1 1 0 0 0.5500 1 0 0 1 1 0 1 0.5375 1 0 0 1 1 1 0 0.5250 1 0 0 1 1 1 1 0.5125 1 0 1 0 0 0 0 0.5000 1 0 1 0 0 0 1 0.4875 1 0 1 0 0 1 0 0.4750 1 0 1 0 0 1 1 0.[...]

Electrical Spec ifications 26 Datasheet 3.4 Catastrophic Thermal Protection The processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures. Even with the activ ation of THERMTRIP#, which halts all processor intern[...]

Datasheet 27 Electrical Spec ifications 3.6 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). These signals should be connected to the clock chip and the appropriate chipset on the platform. The BSEL encoding for BCLK[1:0] is shown in Ta b l e 3 . 3.7 FSB Signal[...]

Electrical Spec ifications 28 Datasheet NOTES: 1. R efer to Chapter 4 for signal descriptions an d termination requirements. 2. In processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer . In system s with the debug port im plemented on the system board, these signals[...]

Datasheet 29 Electrical Spec ifications 3.8 CMOS Signals CMOS input signals are shown in Ta b l e 4 . Legacy output FERR# , IERR# and other non- AGTL+ signals (THERMTRIP# and PROCHOT#) ut ilize Open Drain output buffers. These signals do not have setup or hold time specif ications in relation to BCLK[1:0]. However , all of the CMOS signals are requ[...]

Electrical Spec ifications 30 Datasheet 3.10 Processor DC Specificatio ns The processor DC specifications in this section are define d at the processor core (pads) unless noted otherwise . Se e Ta b l e 4 for the pin signal definitions and signal pin assignments. Ta b l e 6 through Ta b l e 8 list the DC specifications for the processor and are val[...]

Datasheet 31 Electrical Spec ifications NOTES: 1. Each processor is programmed with a maximum valid voltage identifi cation value (VID), which is se t at manufacturing and cannot be altered. Individual maximum VID values ar e calibrated during manufacturing in such a way that two processors at the same frequency may hav e differe nt settings wit hi[...]

Electrical Spec ifications 32 Datasheet NOTES: 1. Each processor is progr ammed with a maximum valid vo ltage ide ntification value (VID), which is set at manufacturing and cannot be altered. Individual maxi mum VID va lues are calibrated during manufacturing such that two processors at the same frequency may hav e different settings within the VID[...]

Datasheet 33 Electrical Spec ifications 2. The voltage specifications are as sumed to be measured across V CC_SENSE and V SS_SENSE p i n s a t s o c k e t w i t h a 100-MHz bandwidth oscill oscope, 1.5- pF maximum pr obe capacitance, and 1-m Ω minimum impedance. The maximum length of ground wire on the probe shou ld be le ss than 5 mm. En sure ex [...]

Electrical Spec ifications 34 Datasheet NOTES: 1. Each processor is progr ammed with a maximum valid vo ltage ide ntification value (VID), which is set at manufacturing and cannot be altered. Individual maxi mum VID va lues are calibrated during manufacturing such that two processors at the same frequency may hav e different settings within the VID[...]

Datasheet 35 Electrical Spec ifications NOTES: 1. Each processor is programmed with a maximum valid voltage identifi cation value (VID), which is se t at manufacturing and cannot be altered. Individual maximum VID values ar e calibrated during manufacturing such that two processors at the sa me frequency may ha ve different sett ings within the VID[...]

Electrical Spec ifications 36 Datasheet Figure 3. Active V CC and I CC Loadline Intel Core 2 Duo Pr ocessors - Standard Voltage, Low Voltage and Ultra Low Voltage an d Intel Core 2 Extreme Processors (PSI# Not Asserted) I CC-COR E max {HFM|LFM} V CC-CORE [V] V CC-CORE nom {HF M|LFM } +/-V CC-CORE Tole rance = VR St. Pt. E rror 1/ V CC-COR E, D C mi[...]

Datasheet 37 Electrical Spec ifications NOTE: Deeper Sleep mode tolera nce depends on VID v alue. Figure 4. Deeper Sleep V CC and I CC Loadline Intel Core 2 Duo Processors - Standard Voltage and Intel Core 2 Extr eme Processors (PSI# Asserted) I CC-CORE max {Deeper Sl eep} V CC-CORE [V ] V CC-CORE nom {Deeper Sleep} +/-V CC-CORE Tolerance = VR St. [...]

Electrical Spec ifications 38 Datasheet NOTE: Deeper Sleep mode toler a nce depends on VID v alue. NOTES: 1. Unless otherwi se noted, all spec ifications in this table apply to al l processo r frequencies. 2. Crossing V oltage is defined as absolute voltag e where rising ed ge of BCLK0 is equal t o the falling edge of BCLK1. 3. For Vin between 0 V [...]

Datasheet 39 Electrical Spec ifications NOTES: 1. Unless otherw ise noted, all s pecificatio ns in this table apply to al l processor fr equencies. 2. V IL is defined as the maxi mum voltage lev el at a receiving agent that is interpreted as a logical low value . 3. V IH is defined as the mini mum voltage level at a receiving agent that is interpre[...]

Electrical Spec ifications 40 Datasheet NOTES: 1. Unless otherwi se noted, all spec ifications in this table apply to al l processo r frequencies. 2. The V CCP referred to in these specificat ions refers to instantaneous V CCP . 3. Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics are included. 4. Measured at 0.[...]

Datasheet 41 Package Mechanical Specifications and Pin Information 4 Package Mechanical Specifications and Pin Information 4.1 Package Mechanical Specifications The processor is available in 4-MB and 2-MB , 478-pin Micro-FCPGA packages as well as 4-MB and 2-MB, 479-ball Micro-FCBGA packag es. The package mechanical dimensions, keep-out zones, proce[...]

Package Mechanical Specifications and Pin Information 42 Datasheet Figure 6. 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) h[...]

Datasheet 43 Package Mechanical Specifications and Pin Information Figure 7. 4-MB and Fused 2-MB Micro-FCPGA Processo r Packag e Drawing (Sheet 2 of 2)[...]

Package Mechanical Specifications and Pin Information 44 Datasheet Figure 8. 2-MB Micro-FCPGA Processor Pack age Drawing (Sheet 1 of 2)[...]

Datasheet 45 Package Mechanical Specifications and Pin Information Figure 9. 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2)[...]

Package Mechanical Specifications and Pin Information 46 Datasheet Figure 10. 4-MB and Fused 2-MB Micro-FCBGA Processor Packag e Drawing (Sheet 1 of 2)[...]

Datasheet 47 Package Mechanical Specifications and Pin Information Figure 11. 4-MB and Fused 2-MB Micro-FCBGA Processor Package Drawing (Sheet 2 of 2)[...]

Package Mechanical Specifications and Pin Information 48 Datasheet Figure 12. 2-MB Micro-FCBGA Processor Package Drawing (Sheet 1 of 2)[...]

Datasheet 49 Package Mechanical Specifications and Pin Information 4.2 Processor Pinout and Pin List Ta b l e 1 4 shows the top view pi nout of the Intel Core 2 Duo mobile processor . The pin list, arranged in two different format s, is shown in the following pages. Figure 13. 2-MB Micro-FC BGA Processor Package Drawing (Sheet 2 of 2)[...]

Package Mechanical Specifications and Pin Information 50 Datasheet Table 14. The Coordinates of the Processor Pi ns as Viewed from the Top of the Package (Sheet 1 of 2) 1 234 5 6789 1 0 1 1 1 2 1 3 A VSS SMI# VSS FERR# A20M# VCC VSS VCC VCC VSS VCC VCC A B RSVD INIT# LINT1 DPSLP# VSS VCC VSS VCC VCC VSS VC C VSS B C R ESET# VSS RSVD IGNNE # VSS LIN[...]

Datasheet 51 Package Mechanical Specifications and Pin Information Table 15. The Coordinates of the Processor Pi ns as Viewed from the Top of the Package (Sheet 2 of 2) 14 15 16 17 18 19 20 21 22 23 24 25 26 A VSS VCC VSS VCC VCC VSS VCC BCLK[1] BCLK[0] VSS THRMDA VSS TEST6 A B VCC VCC VSS VCC VCC VSS VCC VSS B SEL[0] BSEL[1] VSS THR MDC VCCA B C V[...]

Package Mechanical Specifications and Pin Information 52 Datasheet This page is intentionally left blank.[...]

Datasheet 53 Package Mechanical Specifications and Pi n Information Table 16. Pin Listin g by Pin Name (Sheet 1 of 16) Pin Name Pin Number Signal Buffer Type Direction A[3]# J 4 Source Synch Input/ Output A[4]# L5 Source Synch Input/ Output A[5]# L4 Source Synch Input/ Output A[6]# K5 Source Synch Input/ Output A[7]# M3 Source Synch Input/ Output A[...]

Package Mechan ical Specific ations and Pi n Information 54 Datasheet BR0# F1 Common Clock Input/ Output BSEL[0] B22 CMOS Output BSEL[1] B23 CMOS Output BSEL[2] C21 CMOS Output COMP[0] R26 Power/O ther Input/ Output COMP[1] U26 Power/O ther Input/ Output COMP[2] AA1 Power/Other Input/ Output COMP[3] Y1 P ower/Oth er Input/ Output D[0]# E22 Source S[...]

Datasheet 55 Package Mechanical Specifications and Pi n Information D[37]# T22 Source Synch Input/ Output D[38]# U25 Source S ynch Input/ Output D[39]# U23 Source S ynch Input/ Output D[40]# Y25 Source Synch Input/ Output D[41]# W22 Source Synch Input/ Output D[42]# Y23 Source Synch Input/ Output D[43]# W24 Source Synch Input/ Output D[44]# W25 Sou[...]

Package Mechan ical Specific ations and Pi n Information 56 Datasheet DSTBP[3]# AF24 Source Synch Input/ Output FERR# A5 Open Drain Output GTLREF AD26 Power/Other In put HIT# G6 Common Clock Input/ Output HITM# E4 Common Clock Input/ Output IERR# D20 Open Dr ain Output IGNNE# C4 CMOS Input INIT# B3 CMOS Input LINT0 C6 CMOS Input LINT1 B 4 CMOS Inpu[...]

Datasheet 57 Package Mechanical Specifications and Pi n Information VCC AA13 Power/Other VCC AA15 Power/Other VCC AA17 Power/Other VCC AA18 Power/Other VCC AA20 Power/Other VCC AB7 Power/Other VCC AB9 Power/Other VCC AB10 Power/Other VCC AB12 Power/Other VCC AB14 Power/Other VCC AB15 Power/Other VCC AB17 Power/Other VCC AB18 Power/Other VCC AB20 Po[...]

Package Mechan ical Specific ations and Pi n Information 58 Datasheet VCC E12 Power/O ther VCC E13 Power/O ther VCC E15 Power/O ther VCC E17 Power/O ther VCC E18 Power/O ther VCC E20 Power/O ther VCC F7 Power/O ther VCC F9 Power/O ther VCC F10 Po wer/Oth er VCC F12 Po wer/Oth er VCC F14 Po wer/Oth er VCC F15 Po wer/Oth er VCC F17 Po wer/Oth er VCC [...]

Datasheet 59 Package Mechanical Specifications and Pi n Information VSS AC14 Power /Other VSS AC16 Power /Other VSS AC19 Power /Other VSS AC21 Power /Other VSS AC24 Power /Other VSS AD2 Power/Other VSS AD5 Power/Other VSS AD8 Power/Other VSS AD11 Power/Other VSS AD13 Power/Other VSS AD16 Power/Other VSS AD19 Power/Other VSS AD22 Power/Other VSS AD2[...]

Package Mechan ical Specific ations and Pi n Information 60 Datasheet VSS F16 Power/O ther VSS F19 Power/O ther VSS F22 Power/O ther VSS F25 Power/O ther VSS G1 Power/O ther VSS G4 Power/O ther VSS G23 Po wer/Oth er VSS G26 Po wer/Oth er VSS H3 Power /Other VSS H6 Power /Other VSS H21 Power/O ther VSS H24 Power/O ther VSS J2 Power/O ther VSS J5 Pow[...]

Datasheet 61 Package Mechanical Specifications and Pi n Information VSS A8 Power/Other VCC A9 P ower/Other VCC A10 Power/Other VSS A11 Power/Other VCC A12 Power/Other VCC A13 Power/Other VSS A14 Power/Other VCC A15 Power/Other VSS A16 Power/Other VCC A17 Power/Other VCC A18 Power/Other VSS A19 Power/Other VCC A20 Power/Other BCLK[1] A21 Bus Clock I[...]

Package Mechan ical Specific ations and Pi n Information 62 Datasheet D[51]# AB22 Source Synch Input/ Output VSS AB23 Power/Other D[33]# AB24 Source Synch Input/ Output D[47]# AB25 Source Synch Input/ Output VSS AB26 Power/Other PREQ# AC1 Common Clock Input PRDY# A C2 Common Clock Output VSS AC3 Po wer/Ot her BPM[3]# A C4 Common Clock Input/ Output[...]

Datasheet 63 Package Mechanical Specifications and Pi n Information VID[2] AE5 CMOS Output PSI# AE6 CMOS Ou tput VSSSENSE AE7 Power/Other Ou tput VSS AE8 Power/Other VCC AE9 Power/Other VCC AE10 Power/Other VSS AE11 P ower/Other VCC AE12 Power/Other VCC AE13 Power/Other VSS AE14 P ower/Other VCC AE15 Power/Other VSS AE16 P ower/Other VCC AE17 Power[...]

Package Mechan ical Specific ations and Pi n Information 64 Datasheet BSEL[0] B22 CMOS Output BSEL[1] B23 CMOS Output VSS B24 P ower/Othe r THRMDC B2 5 Power/Oth er VCCA B26 Power/Other RESET# C1 Common Clock Input VSS C2 Power/Other RSVD C3 Reserved IGNNE# C4 CMOS Input VSS C5 Power/Other LINT0 C6 CM OS Input THERMTRI P # C7 Open Drain Output VSS [...]

Datasheet 65 Package Mechanical Specifications and Pi n Information VCC E12 Power/Other VCC E13 Power/Other VSS E14 Power/Other VCC E15 Power/Other VSS E16 Power/Other VCC E17 Power/Other VCC E18 Power/Other VSS E19 Power/Other VCC E20 Power/Other VSS E21 Power/Other D[0]# E22 Source Synch Input/ Output D[7]# E23 Source Synch Input/ Output VSS E24 [...]

Package Mechan ical Specific ations and Pi n Information 66 Datasheet VSS H6 Power/Other VSS H21 P ower/Ot her D[12]# H22 Source Synch Input/ Output D[15]# H23 Source Synch Input/ Output VSS H24 P ower/Ot her DINV[0]# H25 Source Synch Input/ Output DSTBP[0]# H26 Sourc e Synch Input/ Output A[9]# J1 Source Syn ch Input/ Output VSS J2 Power/Other REQ[...]

Datasheet 67 Package Mechanical Specifications and Pi n Information DSTBP[1]# M26 Source S ynch Input/ Output VSS N1 Power/Other A[8]# N2 Source Synch Input/ Output A[10]# N3 Source Synch Input/ Output VSS N4 Power/Other RSVD N5 Reserved VCCP N6 Power/Other VCCP N21 Power/Other D[16]# N22 Source Synch Input/ Output VSS N23 Power/Other DINV[1]# N24 [...]

Package Mechan ical Specific ations and Pi n Information 68 Datasheet A[18]# U5 Source Synch Input/ Output VSS U6 P ower/Other VSS U21 Power/Ot her DINV[2]# U22 Source Synch Input/ Output D[39]# U23 Source Synch Input/ Output VSS U24 Power/Ot her D[38]# U25 Source Synch Input/ Output COMP[1] U26 Power/Other Input/ Output ADSTB[ 1]# V1 Source S ynch[...]

Datasheet 69 Package Mechanical Specifications and Pi n Information 4.3 Alphabetical Signals Reference Table 18. Signal Description (Sheet 1 of 7) Name Type Description A[35:3]# Input/ Output A[35:3]# (Address) define a 2 36 -byte physical memory address space. In sub- phase 1 of the address phase, these pins tr ansmit the address of a transaction.[...]

Package Mechan ical Specific ations and Pi n Information 70 Datasheet BSEL[2:0] Output BSEL[2:0] (B us Select) are use d to sele ct the processor input clock frequency . Ta b l e 3 defines the possible combinations of the signals and the frequency associated with ea ch combination. The re quired frequency is determined by the processor , chipset an[...]

Datasheet 71 Package Mechanical Specifications and Pi n Information DINV[3:0]# Input/ Output DINV[3:0]# (Data Bus Inv ersio n) are source synchronous an d indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals are act ivated when the data on the data bus is inverted. The bus agent in verts the data bus signals if more than half the b[...]

Package Mechan ical Specific ations and Pi n Information 72 Datasheet FERR#/PBE# Output FERR# (Floating-point Error )/PBE#(Pending Break Event) is a multiplex ed signal and its meaning is qualified with STPCLK #. When STPCLK# is not asserted, FERR#/ PBE# indicates a floating point when the processor detects an unmasked floating- point error . FERR#[...]

Datasheet 73 Package Mechanical Specifications and Pi n Information LINT[1:0] Input LINT[1:0] (Lo cal APIC Interrupt) must conne ct the appropriate pi ns o f a l l A P I C B u s agents. When th e APIC is disabled, the LINT0 signal becomes INTR, a mask able interrupt request signal, and LINT1 beco mes NMI, a nonmaskable interru pt. INTR and NMI are [...]

Package Mechan ical Specific ations and Pi n Information 74 Datasheet RESET# Input Asserting the RESET# signal resets the pr ocessor to a known state and invalidates its internal cac hes without writin g back any of their contents. F or a power-on Reset, RESET# must stay active for at least two milliseconds after V CC and BCLK have reached their pr[...]

Datasheet 75 Package Mechanical Specifications and Pi n Information § THERMTRIP# Output The processor protects itself from catastrophic ov erhe ating by use of an internal thermal sensor . This sensor is set well abov e the normal oper ating temper ature to ensure that there are n o false trips. The processo r stops all execution when the junction[...]

Package Mechan ical Specific ations and Pi n Information 76 Datasheet[...]

Datasheet 77 Thermal Specifications and Design Co nsiderations 5 Thermal Specifications and Design Considerations Maintaining the proper thermal environmen t is k ey to reliable, long-term system operation. A complete thermal solution in cludes both component and system level thermal management features. The system/processor thermal solution should[...]

Thermal Specifications and Design Considerations 78 Datasheet 5. Processor TDP requirements in Intel Dynamic Ac celera tion T echnology mode is lesser than TDP in HFM. 6. At Tj of 100 o C 7. At Tj of 50 o C 8. At Tj of 35 o C 9. 4-M L2 cache 10. 2-M L2 cache NOTES: 1. The TDP specif ication shoul d be used to design the proc essor thermal solution.[...]

Datasheet 79 Thermal Specifications and Design Co nsiderations NOTES: 1. The TDP specifi cation should be used to design the processor th ermal solution. Th e TDP is not the maximum theoreti cal power the processor can ge nerate. 2. Not 100% tested. These power specifications are det ermined by char acterization of the processo r currents at higher[...]

Thermal Specifications and Design Considerations 80 Datasheet NOTES: 1. The TDP specif ication shoul d be used to design the proc essor thermal solution. The TDP is not the maximum theoreti cal power th e processor can generate. 2. Not 100% tested. These power specifications are det e rmined by characterization of the processor currents at higher t[...]

Datasheet 81 Thermal Specifications and Design Co nsiderations 5.1.1 Thermal Diode The processor incorporates an on-die PNP transistor whose base emitter junction is used as a thermal diode, with its collector shorted to ground. The thermal diode can be read by an off -die analog/digital converter (a thermal sensor) located on the motherboard or a [...]

Thermal Specifications and Design Considerations 82 Datasheet NOTES: 1. Intel does not support or re commend operation of the thermal diode under reverse bias. Intel does not support or recomm end operation of the thermal diode when t he processor power supplies are not within th eir specifie d tolera nce ran ge. 2. Char acterized across a temper a[...]

Datasheet 83 Thermal Specifications and Design Co nsiderations NOTES: 1. Intel does not support or recommend oper ation of the the rmal diode under rev erse bias. 2. Same as I FW in Ta b l e 2 4 . 3. Characterized acro ss a temper ature range of 50-10 0°C. 4. Not 100% tested. Specified by design characterization. 5. The ideality factor , nQ, repre[...]

Thermal Specifications and Design Considerations 84 Datasheet If the n trim value used to calculate the T offse t differs from the n trim valu e used to in a temperature sensing device, the T error(nf ) may not be accurate. If desired, the T offset can be adjusted by calculating n actual and then recalculating the offset using the n trim as defined[...]

Datasheet 85 Thermal Specifications and Design Co nsiderations EMT TM is a processor feature that enhances Intel Thermal Monitor 2 with a processor throttling algorithm known as Adaptiv e Intel Thermal Monitor 2. Adaptive Intel Ther mal Monitor 2 transitions to intermediate operatin g points, r ather than directly to the LFM, once the processor has[...]

Thermal Specifications and Design Considerations 86 Datasheet junction temperature within the m aximum spec ification, the system must initiate an orderly shutdown to prevent damage. If the processor enters one of the above low power states with PROCHO T# already assert ed, PROCHO T# will remain asserted until the processor exits the low power stat[...]