Intel T1700 manual

Intel® Celeron® Mobile Processor Dual-Core on 45-nm Process Datasheet For Platforms Based on Mobile Inte l® 4 Series Express Chipset Family September 2009 Document Number: 321111-003[...]

2 Datasheet Legal Lines and Disc laimers INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTE L® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPER TY RIGHTS IS GRANTED BY THIS DOCUMENT . EXCEPT AS PROVIDED IN INTEL' S TERMS AND CONDITIONS OF SALE FOR SUC H PRODUCTS, INTEL ASSUMES NO LI[...]

Datasheet 3 Contents 1I n t r o d u c t i o n ......... ......... ........ ......... .......... ........ ......... ........ ........... ........ ......... ........ .... 7 1.1 Terminology ........... ........ ........... ........ ........ ........... ........ ......... .......... ......... .......... 8 1.2 Referen ces .. ......... .......... .......[...]

4 Datasheet Figures 1 Package-Level L ow-Power State s ........... .......... ......... .......... ......... .......... ......... .......... .. 11 2 Core Low-Powe r States ....... .......... ......... ........ ......... .......... ......... ........ ........... ........ ....12 3 4-MB and Fused 2-MB Micro-FCP GA Processor Package Drawing (Sheet 1 of[...]

Datasheet 5 Revision History § Document Number Revision Number Description Date 321111 -001 • Initial R e lease November 200 8 321111 -002 • Added T3000, T3100, T3300, and T3500 proc essors June 2009 321111 -003 • Added specifications fo r SFF processor SU2300 • Added C4 state support information for SU 2300 SFF processor • Added Speedst[...]

6 Datasheet[...]

Datasheet 7 Introduction 1 Introduction This document provides electrical, mechanical, and thermal specifications for the Intel® Celeron® Mobile Processor Dual-Core T1x00, Intel(R) Celeron Processors T3x00 and Intel(R) Celeron Dual-core SFF Proces sors. The processor supports the Mobile Intel® 4 Series Express Chipset and Inte l® 82801 IBM (ICH[...]

Introduction 8 Datasheet 1.1 Terminology Term Definition # A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driv en to a low lev el. F or example, when RESET# is low , a reset has been requ ested. Conversely , when NMI is high, a nonmaskable interrupt has occurre d. In the case of [...]

Datasheet 9 Introduction 1.2 References Material and concepts available in the fo llowing documents may be beneficial when reading this document. Document Document Number Intel® Celer on® Dual-Core T1 x00 Processo rs Specification Update for Platforms Based on Mobile Intel® 4 Series Express Chipset Family See http:// www.intel.com/design/ mobile[...]

Introduction 10 Datasheet[...]

Datasheet 11 Low Power Features 2 Low Power Features 2.1 Clock Control and Low Power States The processor supports the C1/AutoHAL T , C1 /MWAIT , C2, C3 and some support the C4 core low-power states, along with their corresponding package-level states for po wer management. Se e Chapter 3 to see if C4 is supported. These package states include Norm[...]

Low Power Features 12 Datasheet 2.1.1 Core Low-Power States 2.1.1.1 C0 State This is the normal operating state of the processor . 2.1.1.2 C1/AutoHALT Powerdown State C1/AutoHAL T is a low-power state entered when the p rocessor core executes the HAL T instruction. The processor core transitions to the C0 state upon the occurrence of SMI#, INIT#, L[...]

Datasheet 13 Low Power Features 2.1.1.3 C1/MWAIT Powerd own State C1/MWAIT is a low -power state entered when the processor core executes the MWAIT instruction. Processor behavior in the C1/M W AIT state is identical to the C1/AutoHAL T state except that there is an additional event that can cause the processor core to return to the C0 state: the M[...]

Low Power Features 14 Datasheet Since the AGTL+ signal pins receive power from the FSB, these pins should not be driven (allowing the level to return to V CCP ) for minimum power dr awn by the termination resistors in this state. In addition, all other input pins on the FSB should be driven to the inactive state. RESET# causes the processor to imme[...]

Datasheet 15 Low Power Features 2.1.2.5 Deep Sle ep State Deep Sleep state is a very low-power state the processor can enter while maintaining context. Deep Sleep state is entered by a sserting the DPSLP# pi n while in the Sleep state. BCLK may be stopped during the Deep Sleep state for additional platform level power savings. BCLK stop/restart tim[...]

Low Power Features 16 Datasheet • The processor controls voltage r amp rates internally to ensure glitch-free transitions. • Low transition latency and large number of tr ansitions possible per second: — Processor core (including L2 cache) is unavailable for u p to 10 μ s during the frequency transition. — The bus protocol (BNR# mechanism)[...]

Datasheet 17 Low Power Features 2.4 Processor Power Status Indicator (PSI#) Signal The PSI# signal is asserted when the processor is in a reduced power consumption state. PSI# can be used to improve light load efficiency of the voltage regulator , resulting in platform power savings and exte nded battery life. The algorithm that the processor uses [...]

Low Power Features 18 Datasheet[...]

Datasheet 19 Electrical Spec ifications 3 Electrical Specifications 3.1 Power and Ground Pins For clean, on-chip power distribution, the processor has a large number of V CC (power) and V SS (ground) inputs. All power pins must be connected to V CC power planes while all V SS pins must be connected to system ground planes. Use of multiple power and[...]

Electrical Spec ifications 20 Datasheet 0 0 1 0 1 1 0 1.2250 0 0 1 0 1 1 1 1.2125 0 0 1 1 0 0 0 1.2000 0 0 1 1 0 0 1 1.1875 0 0 1 1 0 1 0 1.1750 0 0 1 1 0 1 1 1.1625 0 0 1 1 1 0 0 1.1500 0 0 1 1 1 0 1 1.1375 0 0 1 1 1 1 0 1.1250 0 0 1 1 1 1 1 1.1125 0 1 0 0 0 0 0 1.1000 0 1 0 0 0 0 1 1.0875 0 1 0 0 0 1 0 1.0750 0 1 0 0 0 1 1 1.0625 0 1 0 0 1 0 0 1.[...]

Datasheet 21 Electrical Spec ifications 1 0 0 0 1 0 1 0.6375 1 0 0 0 1 1 0 0.6250 1 0 0 0 1 1 1 0.6125 1 0 0 1 0 0 0 0.6000 1 0 0 1 0 0 1 0.5875 1 0 0 1 0 1 0 0.5750 1 0 0 1 0 1 1 0.5625 1 0 0 1 1 0 0 0.5500 1 0 0 1 1 0 1 0.5375 1 0 0 1 1 1 0 0.5250 1 0 0 1 1 1 1 0.5125 1 0 1 0 0 0 0 0.5000 1 0 1 0 0 0 1 0.4875 1 0 1 0 0 1 0 0.4750 1 0 1 0 0 1 1 0.[...]

Electrical Spec ifications 22 Datasheet 3.4 Catastrophic Thermal Protection The processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures. Even with the activ ati on of THERMTRIP#, which halts all processor inter[...]

Datasheet 23 Electrical Spec ifications 3.6 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). These signals should be connected to the clock chip and the appropriate chipset on the platform. The BSEL encoding for BCLK[1:0] is shown in Ta b l e 3 . 3.7 FSB Signal[...]

Electrical Spec ifications 24 Datasheet NOTES: 1. Refer to Chapter 4 for signal descriptions an d termination requirements. 2. In processor systems where t here is no debug port implemented on the system board, these signals are used to support a debug port interposer . In system s with the debug port im plemented on the system board, these signals[...]

Datasheet 25 Electrical Spec ifications 3.8 CMOS Signals CMOS input signals are shown in Ta b l e 4 . Legacy output FERR# , IERR# and other non- AGTL+ signals (THERMTRIP# and PROCHOT#) ut ilize Open Drain output buffers. These signals do not have setup or hold time specif ications in relation to BCLK[1:0]. However , all of the CMOS signals are requ[...]

Electrical Spec ifications 26 Datasheet 3.10 Processor DC Specificatio ns The processor DC specifications in this section are define d at the processor core (pads) unless noted otherwise . Se e Ta b l e 4 for the pin signal definitions and signal pin assignments. Ta b l e 7 through Ta b l e 1 0 list the DC specifications for the processor and are v[...]

Datasheet 27 Electrical Spec ifications NOTES: 1. Each processo r is programmed with a maximum valid voltage identification value (VID), whic h is set at manufacturing and cannot be altered. Individual maximum VID values ar e calibrated during manufacturing in such a way that two processors at the same frequency may hav e differe nt settin gs withi[...]

Electrical Spec ifications 28 Datasheet NOTES: 1. Each processor is programmed with a maximum v alid vo ltage identifi cation value (VID), which is set at manufacturing and cannot be altered. Individual maxi mum VID values are calibr ated during manufacturing in such a way that two processors at the same frequen cy may have different settings withi[...]

Datasheet 29 Electrical Spec ifications T able 8 lists the DC specifications for the processor and are valid only while meeting specifications for junction temperature, clock frequency , and input voltages. The Highest Frequency Mode (HFM) and Lowest Freque ncy Mode (LFM) refer to the highest and lowest core operating frequencies supported on the G[...]

Electrical Spec ifications 30 Datasheet 5. 800-MHz FSB supported 6. Measured at the bulk capacitors on t he motherbo ard. 7. Based on simulati ons and averaged over the durati on of an y change in current. Specified by design/ characterization at nominal V CC . Not 100% tested. 8. This is a power-up peak c urrent specification, which is appl icable[...]

Datasheet 31 Electrical Spec ifications NOTES: 1. Unless ot herwise note d, all specific ations in this table apply to al l processor frequencies. 2. V IL is defined as the maxi mum voltage lev el at a receiving agent that is interpreted as a logical low value . 3. V IH is defined as the mini mum voltage level at a receiving agent that is interpret[...]

Electrical Spec ifications 32 Datasheet NOTES: 1. Unless otherwise no ted, all specifi cations in this table apply to al l processo r frequencies. 2. The V CCP referred to in these specificat ions refers to instantaneous V CCP . 3. Cpad2 includes die capacitance for all other CMOS input signals. No package par asitics are included. 4. Measured at 0[...]

Datasheet 33 Package Mechanical Specifications and Pin Information 4 Package Mechanical Specifications and Pin Information 4.1 Package Mechanical Specifications The processor is available in a 1-MB , 47 8-pin Micro-FCPGA package. The package mechanical dimensions, keep-out zones, processor mass specifications, and package loading specifications are[...]

Package Mechanical Specifications and Pin Information 34 Datasheet Figure 3. 4-MB and Fused 2-MB Mic ro-FCPGA Processor Package Drawing (Sheet 1 of 2) h[...]

Datasheet 35 Package Mechanical Specifications and Pin Information Figure 4. 4-MB and Fused 2-MB Micro-FCPGA Processor Packag e Drawing (Sheet 2 of 2)[...]

Package Mechanical Specifications and Pin Information 36 Datasheet Figure 5. 2-MB Micr o-FCPGA Processor Package Dr awing (Sheet 1 of 2)[...]

Datasheet 37 Package Mechanical Specifications and Pin Information Figure 6. 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2)[...]

Package Mechanical Specifications and Pin Information 38 Datasheet Figure 7. SFF (ULV DC) Die Micro- FCBGA Processor Package Drawing ø 0.14 A A B L C ø 0.04 ø 0.46±0.04 (Metal Diameter) ø 0.39±0.02 (Solder Resist Opening) L[...]

Datasheet 39 Package Mechanical Specifications and Pin Information 4.2 Processor Pinout and Pin List Ta b l e 1 3 shows the top view pinout of the Intel Celeron Dual-Core processor . The pin list, arranged in two different format s, is shown in the following pages. Table 13. The Coordinates of the Processor Pi ns as Viewed from the Top of the Packa[...]

Package Mechanical Specifications and Pin Information 40 Datasheet Table 14. The Coordinates of the Processor Pi ns as Viewed from the Top of the Package (Sheet 2 of 2) 14 15 16 17 18 19 20 21 22 23 24 25 26 A VSS VCC VSS VCC V CC VSS VCC BCLK[ 1] BCLK[0] VSS THRMDA VSS TEST6 A B VCC VCC VSS VCC VCC VSS VCC VSS BSEL[0] BSEL[1] VSS THRMD C VCCA B C [...]

Datasheet 41 Package Mechanical Specifications and Pin Information Table 15. SFF Processor Top View Upper Left Side BD BC BB B A AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC 1 VSS VSS T DO A[35]# A[17]# A[31]# A[30]# A[19]# COMP[ 2] A[16 ]# 2 VSS BPM[3] # PREQ# A[22]# A[34]# A[32]# A[21]# A[23]# COMP[ 3] A[11]# 3 VSS VSS VSS VSS VSS VSS VS[...]

Package Mechanical Specifications and Pin Information 42 Datasheet Table 16. SFF Processor Top View Upper Right Side AB AA Y W V U T R P N M L K J H G F E D C B A 1 A[7 ]# A[5 ]# REQ[2 ] # REQ[0] # LOCK# T RDY# DBSY# VSS VSS 2 A[1 5]# RSVD0 2 RSVD0 1 A[9 ]# A[3] # BR0# RS[ 0 ]# HI T# HI T M# VSS 3 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 4 A[8] # AD[...]

Datasheet 43 Package Mechanical Specifications and Pin Information Table 17. SFF Processor Top View Lower L eft Side BD BC BB B A AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC 23 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 24 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 25 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 26 VCC VCC VCC VCC VCC VC[...]

Package Mechanical Specifications and Pin Information 44 Datasheet Table 18. SFF Processor Top View Lower Right Side AB AA Y W V U T R P N M L K J H G F E D C B A 23 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 24 V C CV C CV C CV C CV C CV C CV C CV C CV C CV C CV C C 25 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 26 V C CV C CV C CV C CV C CV C CV[...]

Datasheet 45 Package Mechanical Specifications and Pi n Information Table 19. Pin Listin g by Pin Name (Sheet 1 of 16) Pin Name Pin Number Signal Buffer Type Direction A[3]# J4 Source Synch Input/ Output A[4]# L5 Source Synch Input/ Output A[5]# L4 Source Synch Input/ Output A[6]# K5 Source Synch Input/ Output A[7]# M3 Source Synch Input/ Output A[[...]

Package Mechan ical Specific ations and Pi n Informati on 46 Datasheet BR0# F1 Common Clock Input/ Output BSEL[0] B22 CMOS Output BSEL[1] B23 CMOS Output BSEL[2] C21 CMOS Output COMP[0] R26 P ower/Other Input/ Output COMP[1] U26 Power/O ther Input/ Output COMP[2] AA1 Power/Other Input/ Output COMP[3] Y1 Power/O ther Input/ Output D[0]# E22 Source S[...]

Datasheet 47 Package Mechanical Specifications and Pi n Information D[37]# T22 Source Synch Input/ Output D[38]# U25 Source Synch Input/ Output D[39]# U23 Source Synch Input/ Output D[40]# Y25 Source Synch Input/ Output D[41]# W22 Source S ynch Input/ Output D[42]# Y23 Source Synch Input/ Output D[43]# W24 Source S ynch Input/ Output D[44]# W25 Sou[...]

Package Mechan ical Specific ations and Pi n Informati on 48 Datasheet DSTBP[3]# AF24 Source S ynch Input/ Output FERR# A5 Open Drain Output GTLREF AD26 Power/Other In put HIT# G6 Common Clock Input/ Output HITM# E4 Common Clock Input/ Output IERR# D20 Open Dr ain Output IGNNE# C4 CMOS In put INIT# B3 CMO S Input LINT0 C6 CMO S Input LINT1 B4 CMOS [...]

Datasheet 49 Package Mechanical Specifications and Pi n Information VCC AA13 Power/Other VCC AA15 Power/Other VCC AA17 Power/Other VCC AA18 Power/Other VCC AA20 Power/Other VCC AB7 Power/Other VCC AB9 Power/Other VCC AB10 Power/Other VCC AB12 Power/Other VCC AB14 Power/Other VCC AB15 Power/Other VCC AB17 Power/Other VCC AB18 Power/Other VCC AB20 Po[...]

Package Mechan ical Specific ations and Pi n Informati on 50 Datasheet VCC E12 P ower/O ther VCC E13 P ower/O ther VCC E15 P ower/O ther VCC E17 P ower/O ther VCC E18 P ower/O ther VCC E20 P ower/O ther VCC F7 P ower/Oth er VCC F9 P ower/Oth er VCC F10 Pow er/Oth er VCC F12 Pow er/Oth er VCC F14 Pow er/Oth er VCC F15 Pow er/Oth er VCC F17 Pow er/Ot[...]

Datasheet 51 Package Mechanical Specifications and Pi n Information VSS AC14 Power/Other VSS AC16 Power/Other VSS AC19 Power/Other VSS AC21 Power/Other VSS AC24 Power/Other VSS AD2 Power/Other VSS AD5 Power/Other VSS AD8 Power/Other VSS AD11 Power/Other VSS AD13 Power/Other VSS AD16 Power/Other VSS AD19 Power/Other VSS AD22 Power/Other VSS AD25 Pow[...]

Package Mechan ical Specific ations and Pi n Informati on 52 Datasheet VSS F16 P ower/O ther VSS F19 P ower/O ther VSS F22 P ower/O ther VSS F25 P ower/O ther VSS G1 P ower/Oth er VSS G4 P ower/Oth er VSS G23 P ower/O ther VSS G26 P ower/O ther VSS H3 Power/O ther VSS H6 Power/O ther VSS H21 Power /Other VSS H24 Power /Other VSS J2 Power/O ther VSS[...]

Datasheet 53 Package Mechanical Specifications and Pi n Information VSS A8 Power/Other VCC A9 Power/Other VCC A10 Power/Other VSS A11 P ower/Oth er VCC A12 Power/Other VCC A13 Power/Other VSS A14 P ower/Oth er VCC A15 Power/Other VSS A16 P ower/Oth er VCC A17 Power/Other VCC A18 Power/Other VSS A19 P ower/Oth er VCC A20 Power/Other BCLK[1] A21 Bus [...]

Package Mechan ical Specific ations and Pi n Informati on 54 Datasheet D[51]# AB22 Source Synch Input/ Output VSS AB23 Power/Other D[33]# AB24 Source Synch Input/ Output D[47]# AB25 Source Synch Input/ Output VSS AB26 Power/Other PREQ# AC1 Common Clock Input PRDY# A C2 Common Clock Output VSS AC3 P ower/Other BPM[3]# AC4 Common Clock Input/ Output [...]

Datasheet 55 Package Mechanical Specifications and Pi n Information VID[2] AE5 CMOS Output PSI# AE6 CMOS Output VSSSENSE AE7 Power/Other Output VSS AE8 P ower/Other VCC AE9 Power/Other VCC AE10 Power/Other VSS A E11 Power/Other VCC AE12 Power/Other VCC AE13 Power/Other VSS A E14 Power/Other VCC AE15 Power/Other VSS A E16 Power/Other VCC AE17 Power/[...]

Package Mechan ical Specific ations and Pi n Informati on 56 Datasheet BSEL[0] B22 CMOS Output BSEL[1] B23 CMOS Output VSS B24 Po wer/Othe r THRMDC B2 5 Power/Other VCCA B26 Power/Other RESET# C1 Common Clock Input VSS C2 Power/Other RSVD C3 Reserved IGNNE# C4 CMOS Inpu t VSS C5 Power/Other LINT0 C6 CMOS Input THERMTRI P # C7 Open Drain Output VSS [...]

Datasheet 57 Package Mechanical Specifications and Pi n Information VCC E12 P ower/Other VCC E13 P ower/Other VSS E14 Power/Other VCC E15 P ower/Other VSS E16 Power/Other VCC E17 P ower/Other VCC E18 P ower/Other VSS E19 Power/Other VCC E20 P ower/Other VSS E21 Power/Other D[0]# E22 Source S ynch Input/ Output D[7]# E23 Source S ynch Input/ Output [...]

Package Mechan ical Specific ations and Pi n Informati on 58 Datasheet VSS H6 Power/Other VSS H21 P ower/Othe r D[12]# H22 Source Synch Input/ Output D[15]# H23 Source Synch Input/ Output VSS H24 P ower/Othe r DINV[0]# H25 Source Synch Input/ Output DSTBP[0]# H26 Sourc e Synch Input/ Output A[9]# J1 Source S ynch Input/ Output VSS J2 Power/Other RE[...]

Datasheet 59 Package Mechanical Specifications and Pi n Information DSTBP[1]# M26 Source Synch Input/ Output VSS N1 Power/Other A[8]# N2 Source Synch Input/ Output A[10]# N3 Source Sync h Input/ Output VSS N4 Power/Other RSVD N5 Reserved VCCP N6 Power/Other VCCP N21 Power/Other D[16]# N22 Source Synch Input/ Output VSS N23 Power/Other DINV[1]# N24 [...]

Package Mechan ical Specific ations and Pi n Informati on 60 Datasheet A[18]# U5 Source Synch Input/ Output VSS U6 Power/Other VSS U21 Pow er/Othe r DINV[2]# U22 Source Synch Input/ Output D[39]# U23 Source S ynch Input/ Output VSS U24 Pow er/Othe r D[38]# U25 Source S ynch Input/ Output COMP[1] U26 Power/Other Input/ Output ADSTB[ 1]# V1 Source S [...]

Datasheet 61 Package Mechanical Specifications and Pi n Information Table 21. SFF Listing by Ball Name Signal Name Ball Number A[3]# P2 A[4]# V4 A[5]# W1 A[6]# T4 A[7]# AA1 A[8]# A B4 A[9]# T2 A[10]# AC5 A[11]# AD2 A[12]# AD4 A[13]# AA5 A[14]# AE5 A[15]# AB2 A[16]# AC1 A[17]# A N1 A[18]# AK4 A[19]# AG1 A[20]# A T 4 A[21]# AK2 A[22]# A T 2 A[23]# AH[...]

Package Mechan ical Specific ations and Pi n Informati on 62 Datasheet D[20]# R41 D[21]# W41 D[22]# N43 D[23]# U41 D[24]# AA41 D[25]# AB40 D[26]# AD40 D[27]# AC41 D[28]# AA43 D[29]# Y40 D[30]# Y44 D[31]# T44 D[32]# AP44 D[33]# AR43 D[34]# AH40 D[35]# AF40 D[36]# AJ43 D[37]# AG41 D[38]# AF44 D[39]# AH44 D[40]# AM44 D[41]# AN43 D[42]# AM40 D[43]# AK4[...]

Datasheet 63 Package Mechanical Specifications and Pi n Information PSI# BD10 PWRGOOD E7 REQ[0]# R1 REQ[1]# R5 REQ[2]# U1 REQ[3]# P4 REQ[4]# W5 RESET# G5 RS[0]# K2 RS[1]# H4 RS[2]# K4 RSVD01 V2 RSVD02 Y2 RSVD03 AG5 RSVD04 AL5 RSVD05 J9 RSVD06 F4 RSVD07 H8 SLP# D10 SMI# E5 STPCLK# F8 TCK AV 4 TDI AW7 TDO AU1 TEST1 E37 TEST2 D40 TEST3 C43 TEST4 AE41 [...]

Package Mechan ical Specific ations and Pi n Informati on 64 Datasheet VCC AJ33 VCC AK16 VCC AK18 VCC AK20 VCC AK22 VCC AK24 VCC AK26 VCC AK28 VCC AK30 VCC AK32 VCC AL33 VCC AM14 VCC AM16 VCC AM18 VCC AM20 VCC AM22 VCC AM24 VCC AM26 VCC AM28 VCC AM30 VCC AM32 VCC AN33 VCC AP14 VCC AP16 VCC AP18 VCC AP20 VCC AP22 VCC AP24 VCC AP26 VCC AP28 VCC AP30 [...]

Datasheet 65 Package Mechanical Specifications and Pi n Information VCC BB20 VCC BB22 VCC BB24 VCC BB26 VCC BB28 VCC BB30 VCC BB32 VCC BD14 VCC BD16 VCC BD18 VCC BD20 VCC BD22 VCC BD24 VCC BD26 VCC BD28 VCC BD30 VCC BD32 VCC D16 VCC D18 VCC D20 VCC D22 VCC D24 VCC D26 VCC D28 VCC D30 VCC F16 VCC F18 VCC F20 VCC F22 VCC F24 VCC F26 VCC F28 VCC F30 V[...]

Package Mechan ical Specific ations and Pi n Informati on 66 Datasheet VCC T18 VCC T20 VCC T22 VCC T24 VCC T26 VCC T28 VCC T30 VCC T32 VCC U33 VCC V16 VCC V18 VCC V20 VCC V22 VCC V24 VCC V26 VCC V28 VCC V30 VCC V32 VCC W33 VCC Y16 VCC Y18 VCC Y20 VCC Y22 VCC Y24 VCC Y26 VCC Y28 VCC Y30 VCC Y32 VCCA B34 VCCA D34 VCCP A13 VCCP A33 VCCP AA7 VCCP AA9 V[...]

Datasheet 67 Package Mechanical Specifications and Pi n Information VCCP AK14 VCCP AK36 VCCP AK38 VCCP AL 7 VCCP AL 9 VCCP AL11 VCCP AL13 VCCP AL35 VCCP AL37 VCCP AN7 VCCP AN9 VCCP AN11 VCCP AN13 VCCP AN35 VCCP AN37 VCCP AP10 VCCP AP12 VCCP AP36 VCCP AP38 VCCP AR7 VCCP AR9 VCCP AR11 VCCP AR13 VCCP AU11 VCCP AU13 VCCP B12 VCCP B14 VCCP B32 VCCP C13 [...]

Package Mechan ical Specific ations and Pi n Informati on 68 Datasheet VCCP R11 VCCP R13 VCCP R35 VCCP R37 VCCP T14 VCCP U7 VCCP U9 VCCP U11 VCCP U13 VCCP U35 VCCP U37 VCCP V10 VCCP V12 VCCP V14 VCCP V36 VCCP V38 VCCP W7 VCCP W9 VCCP W11 VCCP W13 VCCP W35 VCCP W37 VCCP Y14 VCCSENSE BD12 VID[0] BD8 VID[1] BC7 VID[2] BB10 VID[3] BB8 VID[4] BC5 VID[5][...]

Datasheet 69 Package Mechanical Specifications and Pi n Information VSS AD34 VSS AD36 VSS AD38 VSS AD42 VSS AE3 VSS AE15 VSS AE17 VSS AE19 VSS AE21 VSS AE23 VSS AE25 VSS AE27 VSS AE29 VSS AE31 VSS AE39 VSS AF6 VSS AF8 VSS AF34 VSS AF42 VSS AG3 VSS AG15 VSS AG17 VSS AG19 VSS AG21 VSS AG23 VSS AG25 VSS AG27 VSS AG29 VSS AG31 VSS AG39 VSS AH6 VSS AH8 [...]

Package Mechan ical Specific ations and Pi n Informati on 70 Datasheet VSS AN21 VSS AN23 VSS AN25 VSS AN27 VSS AN29 VSS AN31 VSS AN39 VSS AP6 VSS AP8 VSS AP34 VSS AP42 VSS AR3 VSS AR15 VSS AR17 VSS AR19 VSS AR21 VSS AR23 VSS AR25 VSS AR27 VSS AR29 VSS AR31 VSS AR35 VSS AR37 VSS AR39 VSS A T6 VSS A T8 VSS A T10 VSS A T12 VSS A T36 VSS A T38 VSS A T4[...]

Datasheet 71 Package Mechanical Specifications and Pi n Information VSS B6 VSS B36 VSS B42 VSS BA1 VSS BA3 VSS BA9 VSS BA11 VSS BA13 VSS BA15 VSS BA17 VSS BA19 VSS BA21 VSS BA23 VSS BA25 VSS BA27 VSS BA29 VSS BA31 VSS BA33 VSS BA39 VSS BA43 VSS BB2 VSS BB6 VSS BB12 VSS BB36 VSS BB42 VSS BC3 VSS BC9 VSS B C11 VSS B C15 VSS B C17 VSS B C19 VSS B C21 [...]

Package Mechan ical Specific ations and Pi n Informati on 72 Datasheet VSS F44 VSS G1 VSS G3 VSS G9 VSS G15 VSS G17 VSS G19 VSS G21 VSS G23 VSS G25 VSS G27 VSS G29 VSS G31 VSS G37 VSS H6 VSS H10 VSS H34 VSS H38 VSS H42 VSS J3 VSS J15 VSS J17 VSS J19 VSS J21 VSS J23 VSS J25 VSS J27 VSS J29 VSS J31 VSS J39 VSS K6 VSS K8 VSS K34 VSS K42 VSS L3 VSS L15[...]

Datasheet 73 Package Mechanical Specifications and Pi n Information VSS R29 VSS R31 VSS R39 VSS T6 VSS T8 VSS T10 VSS T12 VSS T34 VSS T36 VSS T38 VSS T42 VSS U3 VSS U5 VSS U15 VSS U17 VSS U19 VSS U21 VSS U23 VSS U25 VSS U27 VSS U29 VSS U31 VSS U39 VSS V6 VSS V8 VSS V34 VSS V42 VSS W3 VSS W15 VSS W17 VSS W19 VSS W21 VSS W23 VSS W25 VSS W27 VSS W29 V[...]

Package Mechan ical Specific ations and Pi n Informati on 74 Datasheet[...]

Datasheet 75 Package Mechanical Specifications and Pi n Information 4.3 Alphabetical Signals Reference Table 22. Signal Description (Sheet 1 of 7) Name Type Description A[35:3]# Input/ Output A[35:3]# (Address) define a 2 36 -byte physical memory address space. In sub- phase 1 of the address phase, these pins tr ansmit the address of a transaction.[...]

Package Mechan ical Specific ations and Pi n Informati on 76 Datasheet BSEL[2:0] Output BSEL[2:0] (B us Select) are use d to sele ct the processor input clock frequency . Ta b l e 3 defines the possible combination s of the signals and the frequency associated with ea ch combination. The re quired frequency is determined by the processor , chipset [...]

Datasheet 77 Package Mechanical Specifications and Pi n Information DINV[3:0]# Input/ Output DINV[3:0]# (Data Bus Inv ersio n) are source synchronous and in dicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals are activa ted when the data on the data bus is inverted. The bus agent in verts the data bus signals if more than half the b[...]

Package Mechan ical Specific ations and Pi n Informati on 78 Datasheet FERR#/PBE# Output FERR# (Floating-point Error )/PBE#(P ending Break Ev ent) is a mul tiplexed s ignal and its meaning is qualified with STPCLK #. When STPCLK# is not asserted, FERR#/ PBE# indicates a floating point when the processor detects an unmasked floating- point error . F[...]

Datasheet 79 Package Mechanical Specifications and Pi n Information LINT[1:0] Input LINT[1:0] (Lo cal APIC Interrupt) must conne ct the appropriate pi ns o f a l l AP I C B u s agents. When th e APIC is disabled, the LINT0 si gnal becomes IN TR, a maskable interrupt request signal, and LINT1 beco mes NMI, a nonmaskable interru pt. INTR and NMI are [...]

Package Mechan ical Specific ations and Pi n Informati on 80 Datasheet RESET# Input Asserting the RESET# signal resets the pr ocessor to a known state and invalidates its internal cac hes without writin g back any of their contents. F or a power-on Reset, RESET# must stay active for at least two milliseconds after V CC and BCLK have reached their p[...]

Datasheet 81 Package Mechanical Specifications and Pi n Information § THERMTRIP# Output The processor protects itself from catastrophic ov erhe ating by use of an internal thermal sensor . This sensor is set wel l above t he normal oper ating temper ature to ensure that there are n o false trips. The processo r stops all execution when the junctio[...]

Package Mechan ical Specific ations and Pi n Informati on 82 Datasheet[...]

Datasheet 83 Thermal Specifications and Design Co nsiderations 5 Thermal Specifications and Design Considerations Maintaining the proper thermal environmen t is k ey to reliable, long-term system operation. A complete thermal solution in cludes both component and system level thermal management features. The system/processor thermal solution should[...]

Thermal Specifications and Design Considerations 84 Datasheet 3. As measured by th e activ ation of the on-d ie Intel Thermal M onitor . The Intel The rmal Monitor’ s automatic mode is used to i ndicate that t he maximum T J has been reached. R efer to Section 5.1 for details. 4. The Intel The rmal Monitor automa tic mode must be e nabled for the[...]

Datasheet 85 Thermal Specifications and Design Co nsiderations 5.1.1 Thermal Diode The processor incorporates an on-die PNP transistor whose base emitter ju nction is used as a thermal diode, with its collector shorted to ground. The therm al diode can be read by an off -die analog/digital converter (a thermal sensor) located on the motherboard or [...]

Thermal Specifications and Design Considerations 86 Datasheet NOTES: 1. Intel does not support or re commend operation of the thermal diode under revers e bias. Intel does not support or recomm end operation of the thermal diode when t he processor power supplies are not within th eir specifie d toler ance r ange. 2. Characteri zed across a temper [...]

Datasheet 87 Thermal Specifications and Design Co nsiderations NOTES: 1. Intel does not s upport or rec ommend oper ation of the th ermal diode under reverse bias. 2. Same as I FW in Ta b l e 2 7 . 3. Characterized acro ss a temperature r ange of 50-100°C. 4. Not 100% tes ted. Specified by design char acterization. 5. The ideality factor , n Q, re[...]

Thermal Specifications and Design Considerations 88 Datasheet If the n trim value used to calculate the T offset differs from the n trim valu e used to in a temperature sensing device, the T error(nf ) may not be accurate. If desired, the T offset can be adjusted by calculating n actual and then recalculating the offset using the n trim as defined [...]

Datasheet 89 Thermal Specifications and Design Co nsiderations Intel Thermal Monitor 1 and 2 can co-exist wi thin the processor . If both Intel Thermal Monitor 1 and 2 bits are enabled in the auto-throttle MSR, Intel Thermal Monitor 2 takes precedence over Intel Thermal Monitor 1. However , if Force Intel Thermal Monitor 1 over Intel Thermal Monito[...]

Thermal Specifications and Design Considerations 90 Datasheet Unlike tr aditional thermal devices, the DTS will output a temperature relativ e to the maximum supported operating temperature of the processor (T J,ma x ). It is the responsibility of software to con vert th e relative temper ature to an absolute temperature. The temper ature returned [...]

Datasheet 91 Thermal Specifications and Design Co nsiderations When PROCHO T# is driven by an external agent, if only Intel Thermal Monitor 1 is enabled on both cores, then both processor cores will hav e their core clocks modulated. If Intel Thermal Monitor 2 is enabled on bo th cores, then both processor cores will enter the lowest progr ammed In[...]

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Datasheet 1 1 Coordination of Core-Level L ow-Power States at the Package Level ................ ............. .... 11 2 Voltage Identification Definition ................. ...... ......... ........ ......... ........ ........... ........ .... 19 3 BSEL[2:0] E ncoding for BCLK Frequency ................... .......... ......... .......... ..........[...]

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Datasheet 1 1 Package-Lev el Low-Powe r States ........ ........ ........... ........ ........ ........... ........ ........... ...... 11 2 Core Low-Power States ................. ......... .......... ......... .......... ......... ........ ........... ........ .. 12 3 4-MB and Fused 2-MB Micro-FCPGA Processor Pack age Drawing (Sheet 1 of 2) .. ...[...]

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Datasheet 1 1I n t r o d u c t i o n ......... ......... ........ ......... .......... ........ ......... ........ ........... ........ ......... ........ .... 7 1.1 Terminology ........... ........ ........... ........ ........ ........... ........ ......... .......... ......... .......... 8 1.2 Referen ces ............. .......... ......... .....[...]

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