Texas Instruments TMS320TCI6486 manuel d'utilisation

TMS320C6472/TMS320TCI6486 DSP Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) Module User's Guide Literature Number: SPRUEF8F March 2006 – Revised November 2010[...]

2 SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated[...]

Preface ...................................................................................................................................... 10 1 Introduction ...................................................................................................................... 11 1.1 Purpose of the Peripheral .....................................[...]

www.ti.com 4.11 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) ................. 86 4.12 MDIO User Access Register 0 (USERACCESS0) ................................................................ 87 4.13 MDIO User PHY Select Register 0 (USERPHYSEL0) ............................................................ 88 4.14 MD[...]

www.ti.com 5.43 MAC Address Low Bytes Register (MACADDRLO) ............................................................. 141 5.44 MAC Address High Bytes Register (MACADDRHI) ............................................................. 142 5.45 MAC Index Register (MACINDEX) ...........................................................................[...]

www.ti.com List of Figures 1 EMAC and MDIO Block Diagram ........................................................................................ 12 2 Ethernet Configuration with MII Interface .............................................................................. 18 3 Ethernet Configuration with RMII Interface ..............................[...]

www.ti.com 48 Receive Teardown Register (RXTEARDOWN) ...................................................................... 100 49 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) .............................................. 101 50 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) ..........................................[...]

www.ti.com List of Tables 1 Serial Management Interface Pins ...................................................................................... 13 2 EMAC1_EN Pin Description ............................................................................................. 13 3 EMAC Clock Specifications ...............................................[...]

www.ti.com 47 MAC Input Vector Register (MACINVECTOR) Field Descriptions ................................................ 105 48 MAC End-of-Interrupt Vector Register (MACEOIVECTOR) Field Descriptions .................................. 106 49 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions ........................ 107 [...]

Preface SPRUEF8F – March 2006 – Revised November 2010 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) and Physical layer (PHY) device Management Data Input/Output (MDIO) module integrated with TMS320TCI6486/TMS320C6472 devices. Included are the features of the EMAC[...]

User's Guide SPRUEF8F – March 2006 – Revised November 2010 C6472/TCI6486 EMAC/MDIO 1 Introduction This document provides a functional description of the Ethernet Media Access Controller (EMAC) and Physical layer (PHY) device Management Data Input/Output (MDIO) module integrated with TMS320TCI6486/TMS320C6472 devices. Included are the featu[...]

EMIC0 CPPIbuffer manager+ CPPIRAM0 EMAC0 DMA memory transfercontrol Peripheral bus MDIO EMAC1 CPPIbuffer manager+ CPPIRAM1 EMIC1 T oGEMs T oGEMs MII0/GMII0 RGMII0 RMII0 S3MII0 T oPHYs RGMII1 RMII1 S3MII1 DMA memory transfercontrol EMAC Control0 Module EMAC Control1 Module Introduction www.ti.com • Single MDI[...]

www.ti.com Introduction The EMAC module provides an efficient interface between the TCI6486/C6472 core processor and the networked community. The EMAC supports 10Base-T (10 Mbits/sec) and 100Base-TX (100 Mbits/sec) in either half- or full-duplex mode, and 1000Base-T (1000 Mbits/sec) in full-duplex mode, with hardware flow control and quality-of-ser[...]

Introduction www.ti.com Table 2. EMAC1_EN Pin Description (continued) Value Description 1 EMAC1 is enabled and used. Pulls on EMAC1 I/O are disabled (except RGMII pins) and the corresponding I/O buffers are powered up except RGMII output-only pins. NOTE: RGMII buffers are HSTL buffers with no internal pulls. RGMII output only pins will always be po[...]

www.ti.com EMAC Functional Architecture 2 EMAC Functional Architecture This section discusses the architecture and basic function of the EMAC peripheral. 2.1 Clock Control The frequencies for the transmit and receive clocks are fixed by the IEEE 802.3 specification, as shown below: • 2.5 MHz at 10 Mbps • 25 MHz at 100 Mbps • 125 MHz at 1000 M[...]

EMAC Functional Architecture www.ti.com 2.1.3 GMII Clocking The GMII interface is available only on EMAC0 and requires two clock sources generated internally, the peripheral bus clock and the RFTCLK inputs to the EMAC module. SYSCLK14 is programmed to /4 for this interface to provide a 125-MHz clock to the RFTCLK input of EMAC. The GMII interface i[...]

www.ti.com EMAC Functional Architecture 2.3 System-Level Connections On the TCI6486/C6472 device, EMAC0 and EMAC1 support the following different types of interfaces to physical layer devices (PHYs) or switches. Each EMAC can be configured to only one interface at any given time. EMAC0 interface is selected by programming MACSEL0 [2:0] pins (see Ta[...]

MTCLK MTXD[3−0] MTXEN MCOL MCRS MRCLK MRXD[3−0] MRXDV MRXER MDCLK MDIO 2.5 MHZ or 25 MHz Physical layer device (PHY) System core EMAC MDIO T ransformer RJ-45 EMAC Functional Architecture www.ti.com Table 6. MACSEL0[2:0], MACSEL1[1:0], and EMAC1_EN Decoding (continued) MACSEL02 MACSEL01 MACSEL00 MACSEL11 MACSEL10 EMAC_EN EMAC0 EMAC1 1 0 0 1 1 1 [...]

www.ti.com EMAC Functional Architecture Table 7. EMAC and MDIO Signals for MII Interface Signal Name I/O Description MTCLK I Transmit clock (MTCLK). The transmit clock is a continuous clock that provides the timing reference for transmit operations. The MTXD and MTXEN signals are tied to this clock. The clock is generated by the PHY and is 2.5 MHz [...]

MDCLK MDIO RMTXD[1−0] RMTXEN RMCRSDV RMRXD[1−0] RMRXER Physical layer device (PHY) EMAC MDIO System core RMREFCLK RMREFCLK 50-MHz zero-delay clock buffer 50-MHz XO EMAC Functional Architecture www.ti.com 2.3.2 Reduced Media Independent Interface (RMII) Connections Figure 3 shows a TCI6486/C6472 device with integrated EMAC and MDIO interfaced to[...]

MTCLK MTXD[7−0] MTXEN MCOL MCRS MRCLK MRXD[7−0] MRXDV MRXER MDCLK MDIO Physical layer device (PHY) System core T ransformer 2.5 MHz, 25 MHz, or 125 MHz RJ−45 EMAC MDIO GMTCLK www.ti.com EMAC Functional Architecture Table 8. EMAC and MDIO Signals for RMII Interface (continued) Signal Name I/O Description RMRXER I Receive error (RMRXER). The re[...]

EMAC Functional Architecture www.ti.com Table 9. EMAC and MDIO Signals for GMII Interface Signal Name I/O Description MTCLK I Transmit clock (MTCLK). The transmit clock is a continuous clock that provides the timing reference for transmit operations in 10/100 Mbps mode. The MTXD and MTXEN signals are tied to this clock when in 10/100 Mbps mode. The[...]

RGTXC RGTXD[3−0] RGTXCTL RGREFCLK RGRXC RGRXD[3−0] RGRXCTL RGMDCLK RGMDIO Physical layer device (PHY) System core T ransformer 2.5 MHz 25 MHz, or 125 MHz RJ−45 EMAC MDIO www.ti.com EMAC Functional Architecture Figure 5. Ethernet Configuration with RGMII Interface The RGMII interface is a reduced pin alternative to the GMII interface. The data[...]

EMAC Functional Architecture www.ti.com Table 10. EMAC and MDIO Signals for RGMII Interface (continued) Signal Name I/O Description RGRXCTL I Receive control (RGRXCTL). The receive control data has the receive data valid (MRXDV) signal on the rising edge of the receive clock, and a derivative of receive data valid and receive error (MRXER) on the f[...]

TX_CLK TXD TX_SYNC RX_CLK RXD RX_SYNC MDCLK MDIO EMAC MDIO System core Physical layer device (PHY) MHZ_125_CLK 125-MHz zero-delay clockbuffer 125-MHz XO www.ti.com EMAC Functional Architecture 2.3.5 Source Synchronous Serial Media Independent Interface (S3MII) Connections Figure 6 shows a TCI6486/C6472 device with an integrated EMAC and MDIO int[...]

EMAC Functional Architecture www.ti.com Table 11 summarizes the individual EMAC and MDIO signals for the S3MII interface. Table 11. EMAC and MDIO Signals for S3MII Interface Signal Name I/O Description TX_CLK O Transmit clock. The transmit clock is a continuous clock that provides the timing reference for transmit operations. The TXD and TX_SYNC si[...]

TXD TX_SYNC TX_CLK RXD RX_SYNC RX_CLK MHZ_125_CLK Device #1 TXD TX_SYNC TX_CLK RXD RX_SYNC RX_CLK MHZ_125_CLK Device #2 TXD TX_SYNC TX_CLK RXD RX_SYNC RX_CLK MHZ_125_CLK Device #n 125-MHz zero-delay clock buffer 125-MHz XO Low-skew buffer Zero-delay clock buffer External logic element S3MII multi-PHY TX_CLK TX_SYNC P0_TXD P0_RXD P1_TXD P1_RXD Pn_TX[...]

TXD TX_SYNC TX_CLK RXD RX_SYNC RX_CLK MHZ_125_CLK Device #1 TXD TX_SYNC TX_CLK RXD RX_SYNC RX_CLK MHZ_125_CLK Device #2 TXD TX_SYNC TX_CLK RXD RX_SYNC RX_CLK MHZ_125_CLK Device #n 125-MHz zero-delay clock buffer 125-MHz XO Low-skew buffer Zero-delay clock buffer External logic element S3MII switch TX_CLK TX_SYNC P0_TXD P0_RXD P1_TXD P1_RXD Pn_TXD P[...]

Preamble SFD Destination Source Len Data 7 1 6 6 2 46 − (RXMAXLEN - 18) 4 FCS Number of bytes Legend: SFD = Start Frame Delimiter; FCS = Frame Check Sequence (CRC) www.ti.com EMAC Functional Architecture 2.4 Ethernet Protocol Overview Ethernet provides a reliable, connectionless service to a networking application. A brief overview of the etherne[...]

EMAC Functional Architecture www.ti.com 2.4.2 Multiple Access Protocol Nodes in an ethernet local area network are interconnected by a broadcast channel. As a result, when an EMAC port transmits a frame, all of the adapters on the local network receive the frame. Carrier sense multiple access with collision detection (CSMA/CD) algorithms are used w[...]

www.ti.com EMAC Functional Architecture 2.5 Programming Interface 2.5.1 Packet Buffer Descriptors The buffer descriptor is a central part of the EMAC module. It determines how the application software describes ethernet packets to be sent and empty buffers to be filled with incoming packet data. The basic descriptor format is shown in Figure 10 and[...]

SOP | EOP 60 0 60 pBuffer pNext Packet A 60 bytes 0 SOP Packet B Fragment 1 512 bytes 512 1514 pBuffer pNext EOP 0 0 −−− Packet B Fragment 3 500 bytes 502 pBuffer −−− 500 pNext −−− pBuffer pNext Packet B Fragment 2 502 bytes SOP | EOP 0 Packet C 1514 bytes 1514 pBuffer pNext (NULL) 1514 EMAC Functional Architecture www.ti.com For [...]

www.ti.com EMAC Functional Architecture To add a descriptor or a linked list of descriptors to an EMAC descriptor queue for the first time, the software application writes the pointer to the descriptor or first descriptor of a list to the corresponding HDP register. Note that the last descriptor in the list must have its next pointer cleared so tha[...]

EMAC Functional Architecture www.ti.com 2.5.4 Transmit Buffer Descriptor Format A transmit (TX) buffer descriptor ( Figure 12 ) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 1 shows the transmit buffer descriptor described by a C structure. Figure 12. Transmit Desc[...]

www.ti.com EMAC Functional Architecture 2.5.4.1 Next Descriptor Pointer The next descriptor pointer indicates the 32-bit word aligned memory address of the next buffer descriptor in the transmit queue. The pointer creates a linked list of buffer descriptors. If the value of this pointer is zero, then the current buffer is the last buffer in the que[...]

EMAC Functional Architecture www.ti.com 2.5.4.7 End-of-Packet (EOP) Flag When set, this flag indicates that the descriptor points to the last packet buffer for a given packet. For a single fragment packet, both the start-of-packet (SOP) and EOP flags are set. Otherwise, the descriptor pointing to the last packet buffer for the packet sets the EOP f[...]

www.ti.com EMAC Functional Architecture 2.5.5 Receive Buffer Descriptor Format A receive (RX) buffer descriptor ( Figure 13 ) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 2 shows the receive descriptor described by a C structure. Figure 13. Receive Descriptor Form[...]

EMAC Functional Architecture www.ti.com 2.5.5.1 Next Descriptor Pointer The next descriptor pointer indicates the 32-bit word aligned memory address of the next buffer descriptor in the receive queue. The pointer creates a linked list of buffer descriptors. If the value of the pointer is zero, then the current buffer is the last buffer in the queue[...]

www.ti.com EMAC Functional Architecture 2.5.5.7 End-of-Packet (EOP) Flag When set, this flag indicates that the descriptor points to the last packet buffer for a given packet. For a single fragment packet, both the start-of-packet (SOP) and EOP flags are set. Otherwise, the descriptor pointing to the last packet buffer for the packet has the EOP fl[...]

EMAC Functional Architecture www.ti.com 2.5.5.16 Control Flag The EMAC sets this flag in the SOP buffer descriptor if the received packet is an EMAC control frame and was not discarded because the RXCMFEN bit was set in the RXMBPENABLE register. 2.5.5.17 Overrun Flag The EMAC sets this flag in the SOP buffer descriptor if the received packet was ab[...]

TXpacerandinterruptcombiner RXpacerandinterruptcombiner MACTXINT0 MACRXINT0 Commoninterruptcombiner MACINT0 TXpacerandinterruptcombiner MACTXINT1 RXpacerandinterruptcombiner MACRXINT1 Commoninterruptcombiner MACINT1 TXpacerandinterruptcombiner MACTXINT2 RXpacerandinter[...]

Pacingblock T imed- delaySM DIV_NEXT DivideSM EVT_TIMED EVT_DIV EVT_OUT PS_TICK EVT_IN EMAC Functional Architecture www.ti.com 2.7.1 Pacing Block In simple terms, interrupt pacing represents delaying the initial EMAC events to CPU interrupt based on certain criteria. The pacing block is the basic building block for the interrupt pacing ope[...]

W aiting Delay T ime=0 T ime=0 Output EVT_PULSE=0 && DIV_NEXT=1 EVT_PULSE=1&& TIME< TIME_CFG EVT_PULSE=1&& DIV_NEXT=1 PS_TICK=1&& TIME< TIME_CFG &&DIV_NEXT=0 EVT_PULSE=1 && TIME < TIME_CFG EVT_PULSE=0(or) EVT_PULSE=1&& TIME>= TIME_CFG Increment time T ime[...]

W aiting Count Output EVT_PULSE=0(or)EVT_PULSE=1&& CNT >=CNT_CFG&& TIME_CFGI=0 Increment CNT CNT=1 EVT_PULSE=0 &&CR=0 EVT_PULSE=0 && CR=1 EVT_PULSE=1 && CNT < CNT_CFG && CR=0 EVT_PULSE=1 && CNT < CNT_CFG CNT=1 NEXT_ DIV=1 CNT=1 EVT_PULSE=1&& CR=1&[...]

Pacingblock TXEVT[0] Pacingblock TXEVT[1] EW_INTCTL[8] EW_INTCTL[9] Pacingblock TXEVT[2] Pacingblock TXEVT[3] EW_INTCTL[10] EW_INTCTL[1 1] Pacingblock TXEVT[4] Pacingblock TXEVT[5] EW_INTCTL[12] EW_INTCTL[13] Pacingblock TXEVT[6] Pacingblock TXEVT[7] EW_INTCTL[14] EW_INTCTL[15] PS_TICK EW_INTCTL[15:8] MACTXINT T ransmitpa[...]

Pacingblock RXEVT[0] Pacingblock RXEVT[1] EW_INTCTL[16] EW_INTCTL[17] Pacingblock RXEVT[2] Pacingblock RXEVT[3] EW_INTCTL[18] EW_INTCTL[19] Pacingblock RXEVT[4] Pacingblock RXEVT[5] EW_INTCTL[20] EW_INTCTL[21] Pacingblock RXEVT[6] Pacingblock RXEVT[7] EW_INTCTL[22] EW_INTCTL[23] PS_TICK EW_INTCTL[23:16] MACRXINT Receivepa[...]

EW_INTCTL[1] EW_INTCTL[2] EW_INTCTL[3] EW_INTCTL[4] EW_INTCTL[4:1] MACINT Commoninterruptcombinerblock HOST ST A T MDIO_LINT MDIO_USER www.ti.com EMAC Functional Architecture 2.7.6 Common Interrupt Combiner (CIC) The common interrupt combiner (CIC) block performs following functions: • Combines the two common interrupts from EMAC (HOST a[...]

EMIC module Control registers andlogic PHY monitoring Peripheral clock MDIO clock generator USERINT MDIO interface PHY polling MDCLK MDIO LINKINT Configurationbus EMAC Functional Architecture www.ti.com Figure 21. MDIO Module Block Diagram 2.8.1.1 MDIO Clock Generator The MDIO clock generator controls the MDIO clock based on a divide-down of [...]

www.ti.com EMAC Functional Architecture 2.8.2 MDIO Module Operational Overview The MDIO module implements the 802.3 serial management interface to simultaneously interrogate and control up to two Ethernet PHYs, using a shared two-wired bus. It separately performs auto-detection and records the current link status of up to 32 PHYs, polling all 32 MD[...]

EMAC Functional Architecture www.ti.com 2.8.2.2 Writing Data to a PHY Register The MDIO module includes a user access register (USERACCESS n ) to directly access a specified PHY device. To write a PHY register, perform the following: 1. Ensure that the GO bit in the USERACCESS n register is cleared. 2. Write to the GO, WRITE, REGADR, PHYADR, and DA[...]

www.ti.com EMAC Functional Architecture The implementation of these macros using the register layer Chip Support Library (CSL) is shown in Example 3 (USERACCESS0 is assumed). Note that this implementation does not check the ACK bit on PHY register reads; in other words, it does not follow the procedure outlined in Section 2.8.2.3 . As the ALIVE reg[...]

Clockand resetlogic Receive DMA engine Interrupt controller T ransmit DMA engine Control registers EMIC Receive FIFO MAC receiver State RAM Statistics T ransmit FIFO MAC transmitter Receive address SYNC RMII0,RMII1 RGMII0,RGMII1 MII0/GMII0 S3MII0,S3MII1 Configurationbus CPPI buffer manager Configurationbus EMAC Functional Archi[...]

www.ti.com EMAC Functional Architecture can be sent to only a single channel. • The transmit path: – Transmit DMA engine The transmit DMA engine performs the data transfer between the device internal or external memory and the transmit FIFO. It interfaces to the processor through the bus arbiter in the CPPI buffer manager. This DMA engine is to[...]

EMAC Functional Architecture www.ti.com An interrupt is issued to the CPU whenever a transmit or receive operation has completed. However, it is not necessary for the CPU to service the interrupt while there are additional resources available. In other words, the EMAC continues to receive Ethernet packets until its receive descriptor list has been [...]

www.ti.com EMAC Functional Architecture Receive buffer flow control is triggered when the number of free buffers in any enabled receive channel (RX n FREEBUFFER) is less than or equal to the channel flow control threshold register (RX n FLOWTHRESH) value. Receive flow control is independent of receive QOS, except that both use the free buffer value[...]

EMAC Functional Architecture www.ti.com • Zero padding to 64-byte data length (EMAC transmits only 64-byte pause frames). • The 32-bit frame-check sequence (CRC word). All quantities are hexadecimal and are transmitted most-significant-byte first. The least-significant-bit (LSB) is transferred first in each byte. If the RXBUFFERFLOWEN bit in th[...]

www.ti.com EMAC Functional Architecture 2.10.2.5 Back Off The EMAC implements the 802.3 binary exponential back-off algorithm. 2.10.2.6 Transmit Flow Control When enabled, incoming pause frames are acted upon to prevent the EMAC from transmitting any further frames. Incoming pause frames are only acted upon when the FULLDUPLEX and TXFLOWEN bits in [...]

EMAC Functional Architecture www.ti.com 2.10.2.7 Speed, Duplex, and Pause Frame Support The MAC can operate in half-duplex or full-duplex mode at 10 Mbps or 100 Mbps, and can operate in full duplex only in 1000 Mbps. Pause frame support is included in 10/100/1000 Mbps modes as configured by the host. 2.11 Packet Receive Operation 2.11.1 Receive DMA[...]

www.ti.com EMAC Functional Architecture A MAC address location in RAM is 53 bits wide and consists of: • 48 bits of the MAC address • 3 bits for the channel to which a valid address match will be transferred. The channel is a don't care if the MATCHFILT bit is cleared. • A valid bit • A match or filter bit First, write the index into t[...]

EMAC Functional Architecture www.ti.com 2.11.6 Receive Channel Teardown The host commands a receive channel teardown by writing the channel number to the RXTEARDOWN register. When a teardown command is issued to an enabled receive channel, the following occurs: • Any current frame in reception completes normally. • The TDOWNCMPLT flag is set in[...]

www.ti.com EMAC Functional Architecture 2.11.8 Promiscuous Receive Mode When the promiscuous receive mode is enabled by setting the RXCAFEN bit in the RXMBPENABLE register, non-address matching frames that would normally be filtered are transferred to the promiscuous channel. Address matching frames that would normally be filtered due to errors are[...]

EMAC Functional Architecture www.ti.com Table 14. Receive Frame Treatment Summary (continued) Address RXMBPENABLE Bits Match RXCAFEN RXCEFEN RXCMFEN RXCSFEN Frame Treatment 1 X 1 1 0 Proper/oversize/jabber/code/align/CRC data and control frames transferred to address match channel. No undersized/fragment frames are transferred. 1 X 1 1 1 All addres[...]

www.ti.com EMAC Functional Architecture • Initialize the TX n HDP registers to zero. • Enable the desired transmit interrupts using the TXINTMASKSET and TXINTMASKCLEAR registers. • Set the appropriate configuration bits in the MACCONTROL register. • Set up the transmit channel(s) buffer descriptors in host memory. • Enable the transmit DM[...]

EMAC Functional Architecture www.ti.com For example, for 1000-Mbps operation, these restrictions translate into the following rules: • For the short-term average, each 64-byte memory read/write request from the EMAC must be serviced in no more than 0.512 m s. • Any single latency event in request servicing can be no longer than (0.512 * TXCELLT[...]

www.ti.com EMAC Functional Architecture 2.16 Initialization 2.16.1 Enabling the EMAC/MDIO Peripheral When the device is powered on, the EMAC peripheral is disabled. Prior to EMAC-specific initialization, the EMAC must be enabled; otherwise its registers cannot be written, and the reads will all return a value of zero. The interface to be used (MII,[...]

EMAC Functional Architecture www.ti.com If the MDIO module must operate on an interrupt basis, the interrupts can be enabled at this time using the USERINTMASKSET register for register access and the USERPHYSEL n register if a target PHY is already known. Once the MDIO state machine has been initialized and enabled, it starts polling all 32 PHY add[...]

www.ti.com EMAC Functional Architecture Configuration register (EMACCFG), found at device level. 20. Enable the device interrupt in EW_INTCTL. 2.17 Interrupt Support 2.17.1 EMAC Module Interrupt Events and Requests The EMAC/MDIO generates 18 interrupt events, as follows: • TXPEND n : Transmit packet completion interrupt for transmit channels 7 th[...]

EMAC Functional Architecture www.ti.com Upon interrupt reception, the CPU processes one or more packets from the buffer chain and then acknowledges one or more interrupt(s) by writing the address of the last buffer descriptor processed to the queue's associated RX completion pointer in the receive DMA state RAM. The data written by the host (b[...]

www.ti.com EMAC Functional Architecture 2.17.2.1 Link Change Interrupt The MDIO module asserts a link change interrupt (LINKINT) if there is a change in the link state of the PHY corresponding to the address in the PHYADRMON bits in the USERPHYSEL n register, and if the LINKINTENB bit is also set in USERPHYSEL n . This interrupt event is also captu[...]

EMAC Functional Architecture www.ti.com When the emulation suspend state is entered, the EMAC will stop processing receive and transmit frames at the next frame boundary. Any frame currently in reception or transmission will be completed normally without suspension. For transmission, any complete or partial frame in the transmit cell FIFO will be t[...]

www.ti.com EMIC Module Registers 3 EMIC Module Registers 3.1 EW_INTCTL Registers There are six EW_INTCTL registers (one per C64x+ megamodule). These registers, shown in Figure 23 , reside in the configuration space of the respective Ethernet wrappers. This register controls generation of MACTXINT, MACRXINT, and MACINT interrupts for each core. The [...]

EMIC Module Registers www.ti.com Figure 24. RPCFG Register 31 28 27 16 Reserved TIME_CFG 0000 R/W-0000 0000 1 5 87 43210 CNT_CFG Reserved TU CU TR CR R/W-0000 0000 0000 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 17. RPCFG Register Field Descriptions Bit Field Value Description 31-28 Reserved Reser[...]

www.ti.com EMIC Module Registers 3.2.2 RPSTAT Registers There are eight RPSTAT registers (RPSTAT0 thru RPSTAT7), one per receive event. This register configuration is common to all C64x+ megamodules. The RPSTAT register details are shown in Figure 25 and described in Table 18 . Figure 25. RPSTAT Register 31 28 27 16 Reserved TIME 0000 R-0000 0000 1[...]

EMIC Module Registers www.ti.com 3.3 TPIC Registers 3.3.1 TPCFG Registers There are eight TPCFG registers (TPCFG0 through TPCFG7), one per transmit event. This register configuration is common to all C64x+ megamodules. The TPCFG register details are shown in Figure 26 and described in Table 19 . Figure 26. TPCFG Register 31 28 27 16 Reserved TIME_C[...]

www.ti.com EMIC Module Registers 3.3.2 TPSTAT Registers There are eight TPSTAT registers (TPSTAT0 through TPSTAT7), one per transmit event. This register configuration is common to all C64x+mega modules. The TPSTAT register details are shown in Figure 27 and described in Table 20 . Figure 27. TPSTAT Register 31 28 27 16 Reserved TIME 0000 R-0000 00[...]

MDIO Registers www.ti.com 4 MDIO Registers 4.1 Introduction Table 21 lists the memory-mapped registers for the Management Data Input/Output (MDIO). For the memory address of these registers, see the TMS320TCI6486 Communications Infrastructure Digital Signal Processor data manual ( SPRS300 ) or the TMS320C6472 Fixed-Point Digital Signal Processor da[...]

www.ti.com MDIO Registers 4.2 MDIO Version Register (VERSION) The MDIO version register (VERSION) is shown in Figure 29 and described in Table 22 . Figure 29. MDIO Version Register (VERSION) 31 16 MODID R-7 15 8 7 0 REVMAJ REVMIN R-1 R-3 LEGEND: R = Read only; R/W = Read/Write; - n = value after reset Table 22. MDIO Version Register (VERSION) Field[...]

MDIO Registers www.ti.com 4.3 MDIO Control Register (CONTROL) The MDIO control register (CONTROL) is shown in Figure 30 and described in Table 23 . Figure 30. MDIO Control Register (CONTROL) 31 30 29 28 24 23 21 20 19 18 17 16 FAULT IDLE ENABLE Reserved HIGHEST_USER_CHANNEL Reserved PREAMBLE FAULT Reserved ENB R-1 R/W-0 R-0 R-1 R-0 R/W-0 R/WC-0 R/W[...]

www.ti.com MDIO Registers 4.4 PHY Acknowledge Status Register (ALIVE) The PHY acknowledge status register (ALIVE) is shown in Figure 31 and described in Table 24 . Figure 31. PHY Acknowledge Status Register (ALIVE) 31 16 ALIVE R/WC-0 15 0 ALIVE R/WC-0 LEGEND: R/W = Read/Write; R/WC = Read/Write 1 to clear; - n = value after reset Table 24. PHY Ackn[...]

MDIO Registers www.ti.com 4.5 PHY Link Status Register (LINK) The PHY link status register (LINK) is shown in Figure 32 and described in Table 25 . Figure 32. PHY Link Status Register (LINK) 31 16 LINK R-0 15 0 LINK R-0 LEGEND: R = Read only; - n = value after reset Table 25. PHY Link Status Register (LINK) Field Descriptions Bit Field Value Descri[...]

www.ti.com MDIO Registers 4.6 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) The MDIO link status change interrupt (unmasked) register (LINKINTRAW) is shown in Figure 33 and described in Table 26 . Figure 33. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) 31 16 Reserved R-0 15 2 1 0 Reserved LINKINTRAW R-0 R/[...]

MDIO Registers www.ti.com 4.7 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) The MDIO link status change interrupt (masked) register (LINKINTMASKED) is shown in Figure 34 and described in Table 27 . Figure 34. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) 31 16 Reserved R-0 15 2 1 0 LINKINT Reserved MASKED[...]

www.ti.com MDIO Registers 4.8 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) The MDIO user command complete interrupt (unmasked) register (USERINTRAW) is shown in Figure 35 and described in Table 28 . Figure 35. MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) 31 16 Reserved R-0 15 2 1 0 Reserved USERINTR[...]

MDIO Registers www.ti.com 4.9 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) The MDIO user command complete interrupt (masked) register (USERINTMASKED) is shown in Figure 36 and described in Table 29 . Figure 36. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) 31 16 Reserved R-0 15 2 1 0 USERINT Reserv[...]

www.ti.com MDIO Registers 4.10 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) The MDIO user command complete interrupt mask set register (USERINTMASKSET) is shown in Figure 37 and described in Table 30 . Figure 37. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) 31 16 Reserved R-0 15 2 1 0 USERINT Re[...]

MDIO Registers www.ti.com 4.11 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in Figure 38 and described in Table 31 . Figure 38. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) 31 16 Reserved R-0 15 2 1 [...]

www.ti.com MDIO Registers 4.12 MDIO User Access Register 0 (USERACCESS0) The MDIO user access register 0 (USERACCESS0) is shown in Figure 39 and described in Table 32 . Figure 39. MDIO User Access Register 0 (USERACCESS0) 31 30 29 28 26 25 21 20 16 GO WRITE ACK Reserved REGADR PHYADR R/WS-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 15 0 DATA R/W-0 LEGEND: R = Re[...]

MDIO Registers www.ti.com 4.13 MDIO User PHY Select Register 0 (USERPHYSEL0) The MDIO user PHY select register 0 (USERPHYSEL0) is shown in Figure 40 and described in Table 33 . Figure 40. MDIO User PHY Select Register 0 (USERPHYSEL0) 31 16 Reserved R-0 15 8 7 6 5 4 0 Reserved LINKSEL LINKINTENB Reserved PHYADRMON R-0 R/W-0 R/W-0 R-0 R/W-0 LEGEND: R[...]

www.ti.com MDIO Registers 4.14 MDIO User Access Register 1 (USERACCESS1) The MDIO user access register 1 (USERACCESS1) is shown in Figure 41 and described in Table 34 . Figure 41. MDIO User Access Register 1 (USERACCESS1) 31 30 29 28 26 25 21 20 16 GO WRITE ACK Reserved REGADR PHYADR R/WS-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 15 0 DATA R/W-0 LEGEND: R = Re[...]

MDIO Registers www.ti.com 4.15 MDIO User PHY Select Register 1 (USERPHYSEL1) The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 42 and described in Table 35 . Figure 42. MDIO User PHY Select Register 1 (USERPHYSEL1) 31 16 Reserved R-0 15 8 7 6 5 4 0 Reserved LINKSEL LINKINTENB Reserved PHYADRMON R-0 R/W-0 R/W-0 R-0 R/W-0 LEGEND: R[...]

www.ti.com EMAC Port Registers 5 EMAC Port Registers Table 36 lists the memory-mapped registers for the Ethernet Media Access Controller (EMAC). For the memory address of these registers, see the TMS320TCI6486 Communications Infrastructure Digital Signal Processor data manual ( SPRS300 ) or the TMS320C6472 Fixed-Point Digital Signal Processor data [...]

EMAC Port Registers www.ti.com Table 36. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description See 15Ch RX7FREEBUFFER Receive Channel 7 Free Buffer Count Register Section 5.28 160h MACCONTROL MAC Control Register Section 5.29 164h MACSTATUS MAC Status Register Section 5.30 168h EMCONTROL Emulation Control[...]

www.ti.com EMAC Port Registers Table 36. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description See 65Ch TX7CP Transmit Channel 7 Completion Pointer (Interrupt Section 5.48 Acknowledge) Register 660h RX0CP Receive Channel 0 Completion Pointer (Interrupt Section 5.49 Acknowledge) Register 664h RX1CP Receive[...]

EMAC Port Registers www.ti.com Table 36. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description See 27Ch FRAME1024TUP Transmit and Receive 1024 to RXMAXLEN Octet Frames Section 5.50.32 Register 280h NETOCTETS Network Octet Frames Register Section 5.50.33 284h RXSOFOVERRUNS Receive FIFO or DMA Start-of-Fram[...]

www.ti.com EMAC Port Registers 5.1 Transmit Identification and Version Register (TXIDVER) The transmit identification and version register (TXIDVER) is shown in Figure 43 and described in Table 37 . Figure 43. Transmit Identification and Version Register (TXIDVER) 31 16 TXIDENT 0x000C 15 11 10 8 7 0 RTLVER TXMAJORVER TXMINORVER 0x01 0x02 0x08 LEGEN[...]

EMAC Port Registers www.ti.com 5.2 Transmit Control Register (TXCONTROL) The transmit control register (TXCONTROL) is shown in Figure 44 and described in Table 38 . Figure 44. Transmit Control Register (TXCONTROL) 31 16 Reserved R-0 15 1 0 Reserved TXEN R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 38. Transmit Co[...]

www.ti.com EMAC Port Registers 5.3 Transmit Teardown Register (TXTEARDOWN) The transmit teardown register (TXTEARDOWN) is shown in Figure 45 and described in Table 39 . Figure 45. Transmit Teardown Register (TXTEARDOWN) 31 30 16 TXTD Reserved NRDY R-0 15 3 2 0 Reserved TXTDNCH R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after res[...]

EMAC Port Registers www.ti.com 5.4 Receive Identification and Version Register (RXIDVER) The receive identification and version register (RXIDVER) is shown in Figure 46 and described in Table 40 . Figure 46. Receive Identification and Version Register (RXIDVER) 31 16 RXIDENT 0x000C 15 11 10 8 7 0 RTLVER RXMAJORVER RXMINORVER 0x01 0x02 0x08 LEGEND: [...]

www.ti.com EMAC Port Registers 5.5 Receive Control Register (RXCONTROL) The receive control register (RXCONTROL) is shown in Figure 47 and described in Table 41 . Figure 47. Receive Control Register (RXCONTROL) 31 16 Reserved R-0 15 1 0 Reserved RXEN R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 41. Receive Contro[...]

EMAC Port Registers www.ti.com 5.6 Receive Teardown Register (RXTEARDOWN) The receive teardown register (RXTEARDOWN) is shown in Figure 48 and described in Table 42 . Figure 48. Receive Teardown Register (RXTEARDOWN) 31 16 RXTD Reserved NRDY R-0 15 3 2 0 Reserved RXTDNCH R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Tab[...]

www.ti.com EMAC Port Registers 5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) The transmit interrupt status (unmasked) register (TXINTSTATRAW) is shown in Figure 49 and described in Table 43 . Figure 49. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) 31 16 Reserved R-0 1 5 876543210 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 Re[...]

EMAC Port Registers www.ti.com 5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) The transmit interrupt status (masked) register (TXINTSTATMASKED) is shown in Figure 50 and described in Table 44 . Figure 50. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) 31 16 Reserved R-0 1 5 876543210 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0[...]

www.ti.com EMAC Port Registers 5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET) The transmit interrupt mask set register (TXINTMASKSET) is shown in Figure 51 and described in Table 45 . Figure 51. Transmit Interrupt Mask Set Register (TXINTMASKSET) 31 24 Reserved R-0 23 22 21 20 19 18 17 16 TX7PULSE TX6PULSE TX5PULSE TX4PULSE TX3PULSE TX2PUL[...]

EMAC Port Registers www.ti.com 5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) The transmit interrupt mask clear register (TXINTMASKCLEAR) is shown in Figure 52 and described in Table 46 . Figure 52. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) 31 24 Reserved R-0 23 22 21 20 19 18 17 16 TX7PULSE TX6PULSE TX5PULSE TX4PULSE TX[...]

www.ti.com EMAC Port Registers 5.11 MAC Input Vector Register (MACINVECTOR) The MAC input vector register (MACINVECTOR) is shown in Figure 53 and described in Table 47 . Figure 53. MAC Input Vector Register (MACINVECTOR) 31 30 29 18 17 16 USER LINK HOST STAT Reserved INT INT PEND PEND R-0 R-0 R-0 R-0 R-0 15 8 7 0 RXPEND TXPEND R-0 R-0 LEGEND: R = R[...]

EMAC Port Registers www.ti.com 5.12 MAC End-of-Interrupt Vector Register (MACEOIVECTOR) The MAC end-of-interrupt vector register (MACEOIVECTOR) is shown in Figure 54 and described in Table 48 . Figure 54. MAC End-of-Interrupt Vector Register (MACEOIVECTOR) 31 5 4 0 Reserved MAC_EOI_VECTOR R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = val[...]

www.ti.com EMAC Port Registers 5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) The receive interrupt status (unmasked) register (RXINTSTATRAW) is shown in Figure 55 and described in Table 49 . Figure 55. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) 31 16 Reserved R-0 1 5 876543210 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 Rese[...]

EMAC Port Registers www.ti.com 5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) The receive interrupt status (masked) register (RXINTSTATMASKED) is shown in Figure 56 and described in Table 50 . Figure 56. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) 31 16 Reserved R-0 1 5 876543210 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 R[...]

www.ti.com EMAC Port Registers 5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) The receive interrupt mask set register (RXINTMASKSET) is shown in Figure 57 and described in Table 51 . Figure 57. Receive Interrupt Mask Set Register (RXINTMASKSET) 31 24 Reserved R-0 23 22 21 20 19 18 17 16 RX7PULSE RX6PULSE RX5PULSE RX4PULSE RX3PULSE RX2PULSE[...]

EMAC Port Registers www.ti.com 5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 58 and described in Table 52 . Figure 58. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) 31 24 Reserved R-0 23 22 21 20 19 18 17 16 RX7PULSE RX6PULSE RX5PULSE RX4PULSE RX3PU[...]

www.ti.com EMAC Port Registers 5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) The MAC interrupt status (unmasked) register (MACINTSTATRAW) is shown in Figure 59 and described in Table 53 . Figure 59. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) 31 16 Reserved R-0 15 2 1 0 HOST STAT Reserved PEND PEND R-0 R-0 R-0 LEGEND: R[...]

EMAC Port Registers www.ti.com 5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) The MAC interrupt status (masked) register (MACINTSTATMASKED) is shown in Figure 60 and described in Table 54 . Figure 60. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) 31 16 Reserved R-0 15 2 1 0 HOST STAT Reserved PEND PEND R-0 R-0 R-0 LEGEND[...]

www.ti.com EMAC Port Registers 5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure 61 and described in Table 55 . Figure 61. MAC Interrupt Mask Set Register (MACINTMASKSET) 31 16 Reserved R-0 15 2 1 0 HOST STAT Reserved MASK MASK R-0 R/WS-0 R/WS-0 LEGEND: R = Read only; R/W = R[...]

EMAC Port Registers www.ti.com 5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) The MAC interrupt mask clear register (MACINTMASKCLEAR) is shown in Figure 62 and described in Table 56 . Figure 62. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) 31 16 Reserved R-0 15 2 1 0 HOST STAT Reserved MASK MASK R-0 R/WC-0 R/WC-0 LEGEND: R = Read o[...]

www.ti.com EMAC Port Registers 5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) The receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) is shown in Figure 63 and described in Table 57 . Figure 63. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) 31 30 29 28 27 [...]

EMAC Port Registers www.ti.com Table 57. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions (continued) Bit Field Value Description 22 RXCEFEN Receive copy error frames enable bit. Enables frames containing errors to be transferred to memory. The appropriate error bit will be set in the frame EOP buffer[...]

www.ti.com EMAC Port Registers Table 57. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions (continued) Bit Field Value Description 2-0 RXMULTCH 0-3h Receive multicast channel select 0 Select channel 0 to receive multicast frames 1h Select channel 1 to receive multicast frames 2h Select channel 2 to rec[...]

EMAC Port Registers www.ti.com 5.22 Receive Unicast Enable Set Register (RXUNICASTSET) The receive unicast enable set register (RXUNICASTSET) is shown in Figure 64 and described in Table 58 . Figure 64. Receive Unicast Enable Set Register (RXUNICASTSET) 31 16 Reserved R-0 15 8 7 6 5 4 3 2 1 0 Reserved RXCH7EN RXCH6EN RXCH5EN RXCH4EN RXCH3EN RXCH2EN[...]

www.ti.com EMAC Port Registers 5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 65 and described in Table 59 . Figure 65. Receive Unicast Clear Register (RXUNICASTCLEAR) 31 16 Reserved R-0 15 8 7 6 5 4 3 2 1 0 Reserved RXCH7EN RXCH6EN RXCH5EN RXCH4EN RXCH3EN RXCH2EN RXCH1EN [...]

EMAC Port Registers www.ti.com 5.24 Receive Maximum Length Register (RXMAXLEN) The receive maximum length register (RXMAXLEN) is shown in Figure 66 and described in Table 60 . Figure 66. Receive Maximum Length Register (RXMAXLEN) 31 16 Reserved R-0 15 0 RXMAXLEN R/W-1518 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 60. Rec[...]

www.ti.com EMAC Port Registers 5.25 Receive Buffer Offset Register (RXBUFFEROFFSET) The receive buffer offset register (RXBUFFEROFFSET) is shown in Figure 67 and described in Table 61 . Figure 67. Receive Buffer Offset Register (RXBUFFEROFFSET) 31 16 Reserved R-0 15 0 RXBUFFEROFFSET R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after r[...]

EMAC Port Registers www.ti.com 5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) is shown in Figure 68 and described in Table 62 . Figure 68. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) 31 16 Reserved R-0 15 8 7 0 Re[...]

www.ti.com EMAC Port Registers 5.27 Receive Channel 0-7 Flow Control Threshold Register (RX n FLOWTHRESH) The receive channel 0-7 flow control threshold register (RX n FLOWTHRESH) is shown in Figure 69 and described in Table 63 . Figure 69. Receive Channel n Flow Control Threshold Register (RX n FLOWTHRESH) 31 16 Reserved R-0 15 8 7 0 Reserved RX n[...]

EMAC Port Registers www.ti.com 5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER) The receive channel 0-7 free buffer count register (RXnFREEBUFFER) is shown in Figure 70 and described in Table 64 . Figure 70. Receive Channel n Free Buffer Count Register (RX n FREEBUFFER) 31 16 Reserved R-0 15 0 RX n FREEBUF WI-0 tLEGEND: R = Read [...]

www.ti.com EMAC Port Registers 5.29 MAC Control Register (MACCONTROL) The MAC control register (MACCONTROL) is shown in Figure 71 and described in Table 65 . Figure 71. MAC Control Register (MACCONTROL) 31 24 Reserved R-0 23 19 18 17 16 Reserved RGMIIEN GIGFORCE RMIIDUPLEXMODE R-0 R/W-0 R/W-0 R/W-0 15 14 13 12 11 10 9 8 RXFIFO RMIISPEED RXOFFLENBLO[...]

EMAC Port Registers www.ti.com Table 65. MAC Control Register (MACCONTROL) Field Descriptions (continued) Bit Field Value Description 12 RXFIFOFLOWEN Receive FIFO flow control enable 0 Receive flow control disabled. For full-duplex mode, no outgoing pause frames are sent. 1 Receive flow control enabled. For full-duplex mode, outgoing pause frames a[...]

www.ti.com EMAC Port Registers 5.30 MAC Status Register (MACSTATUS) The MAC status register (MACSTATUS) is shown in Figure 72 and described in Table 66 . Figure 72. MAC Status Register (MACSTATUS) 31 30 24 IDLE Reserved R-0 R-0 23 20 19 18 16 TXERRCODE Reserved TXERRCH R-0 R-0 R-0 15 12 11 10 8 RXERRCODE Reserved RXERRCH R-0 R-0 R-0 7 5 4 3 2 1 0 R[...]

EMAC Port Registers www.ti.com Table 66. MAC Status Register (MACSTATUS) Field Descriptions (continued) Bit Field Value Description 15-12 RXERRCODE Receive host error code. These bits indicate that EMAC detected receive DMA related host errors. The host should read this field after a host error interrupt (HOSTPEND) to determine the error. Host erro[...]

www.ti.com EMAC Port Registers 5.31 Emulation Control Register (EMCONTROL) The emulation control register (EMCONTROL) is shown in Figure 73 and described in Table 67 . Figure 73. Emulation Control Register (EMCONTROL) 31 16 Reserved R-0 15 2 1 0 Reserved SOFT FREE R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Tabl[...]

EMAC Port Registers www.ti.com 5.32 FIFO Control Register (FIFOCONTROL) The FIFO control register (FIFOCONTROL) is shown in Figure 74 and described in Table 68 . Figure 74. FIFO Control Register (FIFOCONTROL) 31 23 22 16 Reserved RXFIFOFLOWTHRESH R-0 R/W-2 15 5 4 0 Reserved TXCELLTHRESH R-0 R/W-24 LEGEND: R/W = Read/Write; R = Read only; - n = valu[...]

www.ti.com EMAC Port Registers 5.33 MAC Configuration Register (MACCONFIG) The MAC configuration register (MACCONFIG) is shown in Figure 75 and described in Table 69 . Figure 75. MAC Configuration Register (MACCONFIG) 31 24 23 16 TXCELLDEPTH RXCELLDEPTH R-24 R-68 15 8 7 0 ADDRESSTYPE MACCFIG R-2 R-3 LEGEND: R/W = Read/Write; R = Read only; - n = va[...]

EMAC Port Registers www.ti.com 5.34 Soft Reset Register (SOFTRESET) The soft reset register (SOFTRESET) is shown in Figure 76 and described in Table 70 . Figure 76. Soft Reset Register (SOFTRESET) 31 16 Reserved R-0 15 1 0 Reserved SOFTRESET R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 70. Soft Reset Register (SO[...]

www.ti.com EMAC Port Registers 5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) The MAC source address low bytes register (MACSRCADDRLO) is shown in Figure 77 and described in Table 71 . Figure 77. MAC Source Address Low Bytes Register (MACSRCADDRLO) 31 16 Reserved R-0 15 8 7 0 MACSRCADDR0 MACSRCADDR1 R/W-0 R/W-0 LEGEND: R/W = Read/Write; [...]

EMAC Port Registers www.ti.com 5.36 MAC Source Address High Bytes Register (MACSRCADDRHI) The MAC source address high bytes register (MACSRCADDRHI) is shown in Figure 78 and described in Table 72 . Figure 78. MAC Source Address High Bytes Register (MACSRCADDRHI) 31 24 23 16 MACSRCADDR2 MACSRCADDR3 R/W-0 R/W-0 15 8 7 0 MACSRCADDR4 MACSRCADDR5 R/W-0 [...]

www.ti.com EMAC Port Registers 5.37 MAC Hash Address Register 1 (MACHASH1) The MAC hash registers allow group addressed frames to be accepted on the basis of a hash function of the address. The hash function creates a 6-bit data value (hash_fun) from the 48-bit destination address (DA) as follows: Hash_fun(0)=DA(0) XOR DA(6) XOR DA(12) XOR DA(18) X[...]

EMAC Port Registers www.ti.com 5.38 MAC Hash Address Register 2 (MACHASH2) The MAC hash address register 2 (MACHASH2) is shown in Figure 80 and described in Table 74 . Figure 80. MAC Hash Address Register 2 (MACHASH2) 31 16 MACHASH2 R/W-0 15 0 MACHASH2 R/W-0 LEGEND: R/W = Read/Write; - n = value after reset Table 74. MAC Hash Address Register 2 (MA[...]

www.ti.com EMAC Port Registers 5.39 Back Off Test Register (BOFFTEST) The back off test register (BOFFTEST) is shown in Figure 81 and described in Table 75 . Figure 81. Back Off Test Register (BOFFTEST) 31 26 25 16 Reserved RNDNUM R-0 R-0 15 12 11 10 9 0 COLLCOUNT Reserved TXBACKOFF R-0 R-0 R-0 LEGEND: R = Read only; - n = value after reset Table 7[...]

EMAC Port Registers www.ti.com 5.40 Transmit Pacing Algorithm Test Register (TPACETEST) The transmit pacing algorithm test register (TPACETEST) is shown in Figure 82 and described in Table 76 . Figure 82. Transmit Pacing Algorithm Test Register (TPACETEST) 31 16 Reserved R-0 15 5 4 0 Reserved PACEVAL R-0 R-0 LEGEND: R = Read only; - n = value after[...]

www.ti.com EMAC Port Registers 5.41 Receive Pause Timer Register (RXPAUSE) The receive pause timer register (RXPAUSE) is shown in Figure 83 and described in Table 77 . Figure 83. Receive Pause Timer Register (RXPAUSE) 31 16 Reserved R-0 15 0 PAUSETIMER R-0 LEGEND: R = Read only; - n = value after reset Table 77. Receive Pause Timer Register (RXPAUS[...]

EMAC Port Registers www.ti.com 5.42 Transmit Pause Timer Register (TXPAUSE) The transmit pause timer register (TXPAUSE) is shown in Figure 84 and described in Table 78 . Figure 84. Transmit Pause Timer Register (TXPAUSE) 31 16 Reserved R-0 15 0 PAUSETIMER R-0 LEGEND: R = Read only; - n = value after reset Table 78. Transmit Pause Timer Register (TX[...]

www.ti.com EMAC Port Registers 5.43 MAC Address Low Bytes Register (MACADDRLO) The MAC address low bytes register (MACADDRLO) is shown in Figure 85 and described in Table 79 . Figure 85. MAC Address Low Bytes Register (MACADDRLO) 31 21 20 19 18 16 MATCH Reserved VALID CHANNEL FILT R-0 R/W-x R/W-x R/W-x 15 8 7 0 MACADDR0 MACADDR1 R/W-0 R/W-0 LEGEND:[...]

EMAC Port Registers www.ti.com 5.44 MAC Address High Bytes Register (MACADDRHI) The MAC address high bytes register (MACADDRHI) is shown in Figure 86 and described in Table 80 . Figure 86. MAC Address High Bytes Register (MACADDRHI) 31 24 23 16 MACADDR2 MACADDR3 R/W-0 R/W-0 15 8 7 0 MACADDR4 MACADDR5 R/W-0 R/W-0 LEGEND: R/W = Read/Write; - n = valu[...]

www.ti.com EMAC Port Registers 5.45 MAC Index Register (MACINDEX) The MAC index register (MACINDEX) is shown in Figure 87 and described in Table 81 . Figure 87. MAC Index Register (MACINDEX) 31 16 Reserved R-0 15 5 4 0 Reserved MACINDEX R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 81. MAC Index Register (MACINDEX[...]

EMAC Port Registers www.ti.com 5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP) The transmit channel 0-7 DMA head descriptor pointer register (TX n HDP) is shown in Figure 88 and described in Table 82 . Figure 88. Transmit Channel n DMA Head Descriptor Pointer Register (TX n HDP) 31 16 TX n HDP R/W-x 15 0 TX n HDP R/W-x LEGEN[...]

www.ti.com EMAC Port Registers 5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RXnHDP) The receive channel 0-7 DMA head descriptor pointer register (RX n HDP) is shown in Figure 89 and described in Table 83 . Figure 89. Receive Channel n DMA Head Descriptor Pointer Register (RX n HDP) 31 16 RX n HDP R/W-x 15 0 RX n HDP R/W-x LEGEND: [...]

EMAC Port Registers www.ti.com 5.48 Transmit Channel 0-7 Completion Pointer Register (TX n CP) The transmit channel 0-7 completion pointer register (TX n CP) is shown in Figure 90 and described in Table 84 . Figure 90. Transmit Channel n Completion Pointer Register (TX n CP) 31 16 TX n CP R/W-x 15 0 TX n CP R/W-x LEGEND: R/W = Read/Write; - n = val[...]

www.ti.com EMAC Port Registers 5.49 Receive Channel 0-7 Completion Pointer Register (RX n CP) The receive channel 0-7 completion pointer register (RX n CP) is shown in Figure 91 and described in Table 85 . Figure 91. Receive Channel n Completion Pointer Register (RX n CP) 31 16 RX n CP R/W-x 15 0 RX n CP R/W-x LEGEND: R/W = Read/Write; - n = value [...]

EMAC Port Registers www.ti.com 5.50 Network Statistics Registers The EMAC has a set of statistics that record events associated with frame traffic. The statistics values are cleared to zero 38 clocks after the rising edge of reset. When the GMIIEN bit in the MACCONTROL register is set, all statistics registers are write-to-decrement. The value writ[...]

www.ti.com EMAC Port Registers 5.50.3 Multicast Receive Frames Register (RXMCASTFRAMES) The total number of good multicast frames received on the EMAC. A good multicast frame is defined as having all of the following: • Any data or MAC control frame that was destined for any multicast address other than FF-FF-FF-FF-FF-FFh • Was of length 64 to [...]

EMAC Port Registers www.ti.com 5.50.7 Receive Oversized Frames Register (RXOVERSIZED) The total number of oversized frames received on the EMAC. An oversized frame is defined as having all of the following: • Was any data or MAC control frame that matched a unicast, broadcast, or multicast address, or matched due to promiscuous mode • Was great[...]

www.ti.com EMAC Port Registers 5.50.11 Filtered Receive Frames Register (RXFILTERED) The total number of frames received on the EMAC that the EMAC address matching process indicated should be discarded. Such a frame is defined as having all of the following: • Was any data frame (not MAC control frame) destined for any unicast, broadcast, or mult[...]

EMAC Port Registers www.ti.com 5.50.15 Broadcast Transmit Frames Register (TXBCASTFRAMES) The total number of good broadcast frames transmitted on the EMAC. A good broadcast frame is defined as having all of the following: • Any data or MAC control frame destined for address FF-FF-FF-FF-FF-FFh only • Was of any length • Had no late or excessi[...]

www.ti.com EMAC Port Registers • Was any size • Had no carrier loss and no underrun • Experienced one collision before successful transmission. The collision was not late. CRC errors have no effect on this statistic. 5.50.21 Transmit Multiple Collision Frames Register (TXMULTICOLL) The total number of frames transmitted on the EMAC that exper[...]

EMAC Port Registers www.ti.com 5.50.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE) The total number of frames on the EMAC that experienced carrier loss. Such a frame is defined as having all of the following: • Was any data or MAC control frame destined for any unicast, broadcast, or multicast address • Was any size • The carrier [...]

www.ti.com EMAC Port Registers 5.50.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511) The total number of 256-byte to 511-byte frames received and transmitted on the EMAC. Such a frame is defined as having all of the following: • Any data or MAC control frame that was destined for any unicast, broadcast, or multicast address[...]

EMAC Port Registers www.ti.com 5.50.34 Receive FIFO or DMA Start-of-Frame Overruns Register (RXSOFOVERRUNS) The total number of frames received on the EMAC that had either a FIFO or DMA start-of-frame (SOF) overrun. An SOF overrun frame is defined as having all of the following: • Was any data or MAC control frame that matched a unicast, broadcas[...]

www.ti.com Appendix A Glossary Broadcast MAC Address— A special Ethernet MAC address used to send data to all Ethernet devices on the local network. The broadcast address is FFh-FFh-FFh-FFh-FFh-FFh. The LSB of the first byte is odd, qualifying it as a group address; however, its value is reserved for broadcast. It is classified separately by the [...]

Appendix A www.ti.com Jumbo Packets— Jumbo frames are defined as those packets whose length exceeds the standard Ethernet MTU, which is 1500 kbytes. For the C64x+ devices, it is recommended not to use packets exceeding 35K in length. The PHY that you use can place additional limits on to the length of the packets that you can transfer in a system[...]

www.ti.com Appendix B Revision History This revision history highlights the technical changes made to the document in this revision. Table 87. EMAC/MDIO Revision History See Additions/Modifications/Deletions Figure 52 Modified TXINTMASKCLEAR register figure Table 46 Modified TXINTMASKCLEAR register table Figure 57 Modified RXINTMASKSET register fig[...]

IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders[...]