Texas Instruments TMS320TCI648x manuel d'utilisation

TMS320TCI648x Serial RapidIO (SRIO) User's Guide Literature Number: SPRUE13A September 2006[...]

2 SPRUE13A – September 2006 Submit Documentation Feedback[...]

Contents Preface .............................................................................................................................. 14 1 Overview .................................................................................................................. 16 1.1 General RapidIO System ...............................................[...]

5.23 LSU Interrupt Condition Clear Register (LSU_ICCR) .................................................... 141 5.24 Error, Reset, and Special Event Interrupt Condition Status Register (ERR_RST_EVNT_ICSR) .................................................................................... 142 5.25 Error, Reset, and Special Event Interrupt Condition[...]

5.69 Port Link Maintenance Request CSR n (SP n _LM_REQ) ................................................ 200 5.70 Port Link Maintenance Response CSR n (SP n _LM_RESP) ............................................ 201 5.71 Port Local AckID Status CSR n (SP n _ACKID_STAT) ................................................... 202 5.72 Port Error and Stat[...]

List of Figures 1 RapidIO Architectural Hierarchy .......................................................................................... 17 2 RapidIO Interconnect Architecture ....................................................................................... 18 3 Serial RapidIO Device to Device Interface Diagrams ..........................[...]

50 RX CPPI Interrupt Condition Status and Clear Registers ............................................................. 89 51 TX CPPI Interrupt Condition Status and Clear Registers ............................................................. 89 52 LSU Interrupt Condition Status and Clear Registers ..................................................[...]

102 LSU n FLOW_MASK Fields .............................................................................................. 162 103 Queue n Transmit DMA Head Descriptor Pointer Register (QUEUE n _TXDMA_HDP) ......................... 164 104 Queue n Transmit DMA Completion Pointer Register (QUEUE n _TXDMA_CP) ................................. 165 105 [...]

155 Port IP Mode CSR (SP_IP_MODE) - Address Offset 12004h ...................................................... 231 156 Port IP Prescaler Register (IP_PRESCAL) - Address Offset 12008h ............................................. 233 157 Port-Write-In Capture CSRs ....................................................................................[...]

List of Tables 1 TI Devices Supported By This Document ............................................................................... 20 2 Registers Checked for Multicast DeviceID .............................................................................. 21 3 Packet Types ........................................................................[...]

50 RapidIO DEVICEID1 Register (DEVICEID_REG1) Field Descriptions ............................................ 121 51 RapidIO DEVICEID2 Register (DEVICEID_REG2) Field Descriptions ............................................ 122 52 PF_16B_CNTL Registers ................................................................................................ [...]

99 LSU n _REG6 Registers and the Associated LSUs ................................................................... 161 100 LSU n Control Register 6 (LSU n _REG6) Field Descriptions ........................................................ 161 101 LSU n _FLOW_MASKS Registers and the Associated LSUs ..................................................[...]

150 Error Reporting Block Header Register (ERR_RPT_BH) Field Descriptions ..................................... 209 151 Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions ...................................... 210 152 Logical/Transport Layer Error Enable CSR (ERR_EN) Field Descriptions ....................................... 212 [...]

Preface SPRUE13A – September 2006 Read This First About This Manual This document describes the Serial RapidIO ® (SRIO) peripheral on the TMS320TCI648x™ devices. Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number represents 40 hexadecimal ([...]

www.ti.com Related Documentation From Texas Instruments Trademarks TMS320TCI648x, C6000, TMS320C62x, TMS320C67x, TMS320C6000, Code Composer Studio are trademarks of Texas Instruments. RapidIO is a registered trademark of RapidIO Trade Association. InfiniBand is a trademark of the InfiniBand Trade Association. SPRUE13A – September 2006 Read This F[...]

1 Overview 1.1 General RapidIO System 1.1.1 RapidIO Architectural Hierarchy User's Guide SPRUE13A – September 2006 Serial RapidIO (SRIO) The RapidIO peripheral used in the TMS320TCI648x is called a serial RapidIO (SRIO). This chapter describes the general operation of a RapidIO system, how this module is connected to the outside world, the d[...]

www.ti.com Globally shared memory spec logical Future Message passing system I/O Logicalspecification Informationnecessaryfortheendpoint toprocessthetransaction(i.e.,transaction type,size,physicaladdress) toendinthesystem(i.e.,routingaddress) Informationtotransportpacketfrom[...]

www.ti.com 1.1.2 RapidIO Interconnect Architecture HostSubsystem I/OControlSubsystem DSP Farm TDM,GMII,Utopia CommunicationsSubsystem PCISubsystem InfiniBand HCA ™ T oSystem Area Network Memory Memory Memory Memory RapidIO RapidIO RapidIO RapidIO RapidIO Backplane PCI RapidIO RapidIO RapidIO RapidIO Switch Control Processor I[...]

www.ti.com SerialRapidIO1xDeviceto1xDeviceInterfaceDiagram SerialRapidIO4xDeviceto4xDeviceInterfaceDiagram 1xDevice TD[0] TD[0] RD[0] RD[0] TD[0] TD[0] 1xDevice RD[0] RD[0] RD[0-3] RD[0-3] 4xDevice TD[0-3] RD[0-3] RD[0-3] TD[0-3] 4xDevice TD[0-3] TD[0-3] 1.2 RapidIO Feature Support in SRIO[...]

www.ti.com 1.3 Standards 1.4 External Devices Requirements 1.5 TI Devices Supported By This Document Overview Features Not Supported: • Compliance with the Global Shared Memory specification (GSM) • 8/16 LP-LVDS compatible • Destination support of RapidIO Atomic Operations • Simultaneous mixing of frequencies between 1x ports (all ports mus[...]

www.ti.com 2 SRIO Functional Description 2.1 Overview 2.1.1 Peripheral Data Flow SRIO Functional Description This peripheral is designed to be an externally driven slave module that is capable of acting as a master in the DSP system. This means that an external device can push (burst write) data to the DSP as needed, without having to generate an i[...]

www.ti.com 1.25to3.125Gbps differentialdata RX Clock recovery S2P 10b Clk 8b/10b decode 8b Clock recovery RX 8b 8b/10b decode 10b Clk S2P Clock recovery RX 8b 8b/10b decode 10b Clk S2P Clock recovery RX 8b 8b/10b decode 10b Clk S2P PLL TX TX TX TX P2S P2S P2S P2S 8b 8b 8b 8b 10b 8b/10b coding Clk 8b/10b coding 8b/10b coding 8b/10b codin[...]

www.ti.com Initiator Request PacketIssued Operation Completedfor Master Acknowledge Symbol Acknowledge Symbol Response Packet Forwarded RequestPacket Forwarded Acknowledge Symbol Acknowledge Symbol ResponsePacket Issued Fabric T arget T arget Completes Operation Operation IssuedBy Master 2.1.2.2 Example Packet – Streaming Write SRI[...]

www.ti.com double-word0 4 double-wordn-1 acklD rsv prio tt ftype destID sourcelD address rsrv xamsbs double-word1 ... double-wordn-2 CRC PHY LOG TRA LOG TRA PHY 5 3 2 2 8 8 29 1 2 64 64 (n-4)*64 64 64 16 16 n*64+32 16 4 2 10 LOG PHY 10 TRA 2 4 9 * 6 4 + 32 LOG TRA 16 PHY 16 double-word0 5 a c k l D sourcelD rsv 3 prio 2 ftype tt 2 4 [...]

www.ti.com 2.1.2.4 SRIO Packet Type 2.2 SRIO Pins SRIO Functional Description The type of received packet determines how the packet routing is handled. Reserved or undefined packet types are destroyed before being processed by the logical layer functional blocks. This prevents erroneous allocation of resources to them. Unsupported packet types are [...]

www.ti.com 2.3 Functional Operation 2.3.1 Component Block Diagram SRIO Functional Description Table 4. Pin Description Pin Signal Pin Name Count Direction Description RIOTX3/ RIOTX3 2 Output Transmit Data – Differential point-to-point unidirectional bus. Transmits packet data to a receiving device’s RX pins. Most significant bits in 1 port 4X d[...]

www.ti.com Port0 8x276 TX 8x276RX 8x276RX 8x276 TX Port1 8x276 TX 8x276RX Port2 8x276RX 8x276 TX Port3 Physical layer buffers SERDES0 SERDES1 SERDES2 SERDES3 SERDES differential signals 4xmode datapath TXbuffering 32x276B 8buffersper1Xport[...]

www.ti.com 2.3.2 SERDES Macro and its Configurations 2.3.2.1 Enabling the PLL SRIO Functional Description SRIO offers many benefits to customers by allowing a scalable non-proprietary interface. With the use of TI’s SERDES macros, the peripheral is very adaptable and bandwidth scalable. The same peripheral can be used for all three frequency node[...]

www.ti.com SRIO Functional Description Table 5. SERDES Macro Configuration Register 0 (SERDES_CFG0_CNTL) Field Descriptions Bit Field Value Description 31–10 Reserved 0000h Reserved 9–8 LB Loop bandwidth. Specify loop bandwidth settings. Jitter on the reference clock will degrade both the transmit eye and receiver jitter tolerance thereby impai[...]

www.ti.com 2.3.2.2 Enabling the Receiver SRIO Functional Description Table 6. Line Rate versus PLL Output Clock Frequency Rate Line Rate PLL Output Frequency RATESCALE Full x Gbps 0.5x GHz 0.5 Half x Gbps x GHz 1 Quarter x Gbps 2x GHz 2 RIOCLK and RIOCLK FREQ = LINERATE × RATESCALE MPY The rate is defined by the RATE bits of the SERDES_CFGRX n _CN[...]

www.ti.com SRIO Functional Description The clock recovery algorithms listed in the CDR bits operate to adjust the clocks used to sample the received message so that the data samples are taken midway between data transitions. The second order algorithm can be optionally disabled, and both can be configured to optimize their dynamics. Both algorithms[...]

www.ti.com SRIO Functional Description Table 9. SERDES Receive Channel Configuration Register n (SERDES_CFGRX n _CNTL) Field Descriptions (continued) Bit Field Value Description 25–24 Reserved 00b Always write 0s to these reserved bits. 23 Reserved 0 This read-only bit returns 0 when read. 22–19 EQ 0000b–1111b Equalizer. Enables and configure[...]

www.ti.com 2.3.2.3 Enabling the Transmitter SRIO Functional Description Table 9. SERDES Receive Channel Configuration Register n (SERDES_CFGRX n _CNTL) Field Descriptions (continued) Bit Field Value Description 4–2 BUSWIDTH 000b Bus width. Always write 000b to this field, to indicate a 10-bit-wide parallel bus to the clock. All other values are r[...]

www.ti.com SRIO Functional Description Table 11. SERDES Transmit Channel Configuration Register n (SERDES_CFGTX n _CNTL) Field Descriptions (continued) Bit Field Value Description 15–12 DE 0000b–1111b De-emphasis. Selects one of 15 output de-emphasis settings from 4.76 to 71.42%. De-emphasis provides a means to compensate for high frequency att[...]

www.ti.com 2.3.2.4 SERDES Configuration Example 2.3.3 Direct I/O Operation SRIO Functional Description Table 13. SWING Bits of SERDES_CFGTX n _CNTL SWING Bits Amplitude (mV dfpp ) 000b 125 001b 250 010b 500 011b 625 100b 750 101b 1000 110b 1125 111b 1250 //full sample rate at 3.125 Gbps //SERDES reference clock (RIOCLK) 125 MHz //MPY = 12.5 125MHz [...]

www.ti.com LSU _REG0 n RapidIO AddressMSB Control 31 RapidIO AddressLSB/Config_offset Control 31 0 LSU _REG1 n DSP Address Control 31 0 LSU _REG2 n RSV Control 31 0 LSU _REG3 n 12 11 Byte_count OutPortID Control 31 0 LSU _REG4 n 1 7 InterruptReq 30 Priority 29 28 xambs 27 26 IDSize 25 24 DestID 23 8 RSV DrbllInfo Command 31 0 LSU _RE[...]

www.ti.com SRIO Functional Description Table 14. LSU Control/Command Register Fields (continued) LSU Register Field RapidIO Packet Header Field DestID RapidIO destinationID field specifying the target device. Packet Type 4 MSBs: 4-bit ftype field for all packets 4 LSBs: 4-bit trans field for packet types 2, 5, and 8 OutPortID Not available in Rapid[...]

www.ti.com LSU _REG1 n T0 T1 T2 T3 T4 T5 Tn V alid LSU _REG2 n V alid LSU _REG3 n V alid LSU _REG4 n V alid LSU _REG5 n V alid Rdy/BSY Completion V alid V alid After T ransactionCompletes SRIO Functional Description Figure 13. LSU Registers Timing The following code illustrates an LSU registers programming example. SRIO_REGS->LSU1_REG0 = CSL_[...]

www.ti.com Source Address DMA Read Destination Address Count ByteCount DSP Address RSV InterruptReq 0 0 1 7 23 8 DestID 25 24 IDSize 27 26 xambs 29 28 Priority OutPortID 31 30 HopCount Drbll 31 16 15 Packet 8 7 0 RapioIO Address/Config_offset NodeID CRC 16 Count*8 payload 2 xamsbs 1 wrptr 29 address 32 extaddr 8 srcTID 4 wrsize 4 [...]

www.ti.com LSU2 LSU4 LSU3 LSU1 MMRcommand UDI Load/Storemodule RapidIOtransport andphysicallayers Portxtransmission FIFOqueues TX FIFO RX FIFO Peripheralboundary Configbus access Writetransfer descriptors CPU I/O pins L2memory =SharedresourceforCPPIandMAU Shared TX buffer Shared RX buffer Respon[...]

www.ti.com SRIO Functional Description Data leaves the shared TX buffer sequentially in order of receipt, not based on the packet priority. However, if fabric congestion occurs, priority can affect the order in which the data leaves the TX FIFOs. A reordering mechanism exists here, which transmits the highest priority packets first if RETRY acknowl[...]

www.ti.com 2.3.3.3 Direct I/O RX Operation SRIO Functional Description Segmentation: The LSU handles two types of segmentation of outbound requests. The first type is when the Byte_Count of Read/Write requests exceeds 256 bytes (up to 4K bytes). The second type is when Read/Write request RapidIO address is non-64-bit aligned. In both cases, the out[...]

www.ti.com 2.3.3.4 Reset and Power Down State 2.3.4 Message Passing SRIO Functional Description So the general flow is as follows: • Previously, the control/command registers were written and the request packet was sent • Response Packet Type13, Trans != 0001b arrives at module interface, and is handled sequentially (not based on priority) • [...]

www.ti.com 2.3.4.1 RX Operation Mailbox1...64 fromRapidIOpacket Header-Receivedonany inputport Mailboxmapper Q15 Q2 Q1 Q0 Queueassignabletoanycore Packetsequence Message n A Packet manager n+1 B n+2 B n + 3 C n+4 D n+5 B n+6 E Bufferdescriptor queues: Descriptorpermessage Allpriorities Dedicated[...]

www.ti.com acklD rsv prio tt ftype ftype=101 1 destID sourcelD msglen ssize msgseg/xmbox double-word0 double-word1 ... double-wordn-2 double-wordn-1 CRC PHY LOG TRA LOG TRA PHY 5 3 2 2 4 8 8 4 4 4 64 64 (n-4)*64 64 64 16 16 n*64+16 16 4 2 10 n*64+64 letter 2 mbox 2 SRIO Functional Description Figure 17. Message Request Packet This[...]

www.ti.com SRIO Functional Description Figure 18. Mailbox to Queue Mapping Register Pair Mailbox to Queue Mapping Register L n (RXU_MAP_L n ) 31 30 29 24 23 22 21 16 LETTER_MASK MAILBOX_MASK LETTER MAILBOX R/W-11 R/W-111111 R/W-00 R/W-000000 15 0 SOURCEID R/W-0000h Mailbox to Queue Mapping Register H n (RXU_MAP_H n ) 31 Reserved R-0 10 9 8 7 6 5 2 [...]

www.ti.com 31 0 1 2 15 23 7 27 1 1 19 3 29 o w n e r s h i p t e a r d o w n e o p e o q s o p 3 reserved cc message_length 13 21 5 25 9 17 1 30 14 22 6 26 10 18 2 28 12 20 4 24 8 16 0 BitFields next_descriptor_pointer buffer_pointer src_id pri tt reserved mailbox Word Offset SRIO Functional Description If a RX message’s length is greater than[...]

www.ti.com SRIO Functional Description Table 18. RX Buffer Descriptor Field Descriptions (continued) Field Description ownership Ownership: Indicates ownership of the message and is valid only on sop. This bit is set by the DSP core and cleared by the port when the message has been transmitted. The DSP core uses this bit to reclaim buffers. 0: The [...]

www.ti.com Switch Switch Endpoint Endpoint C0 C0 B0 B0 B2 B2 A1 A1 B1 B1 A0 A0 Open Open Open Open Open Open Open Full Open Open Full Full Retry Retry Retry Retry Retry Retry Accept Retry Retry Retry Action Action Retry Retry Scenario A -Default ScenarioB-Inordermode Dataflowdestinedforthe sameRXqueue RXqueue?[...]

www.ti.com SRIO Functional Description In addition, multiple messages can be interleaved at the receive port due to ordering within a connected switch’s output queue. This can occur when using a single or multiple priorities. The RX CPPI block can handle simultaneous interleaved multi-segment messages. This implies that state information (write p[...]

www.ti.com CPPIblock CPU DMA Configbusaccess L2memory Bu ffe r de sc ri pto r dual-port SR AM (N x2 0B ) Da ta b uff er Peripheralboundary 32 32 32 128 C P P I c o nt r o l r e g i s t e r s 2.3.4.2 TX Operation SRIO Functional Description Figure 21. CPPI Boundary Diagram Outgoing messages are handled similarly, with buffer descripto[...]

www.ti.com 31 0 1 2 15 23 7 27 1 1 19 3 29 o w n e r s h i p t e a r d o w n e o p e o q s o p 3 reserved retry_count cc message_length 13 21 5 25 9 17 1 30 14 22 6 26 10 18 2 28 12 20 4 24 8 16 0 BitFields next_descriptor_pointer buffer_pointer dest_id pri tt ssize mailbox port_id Word Offset SRIO Functional Description Table 20. TX DMA State C[...]

www.ti.com SRIO Functional Description Table 21. TX Buffer Descriptor Field Definitions (continued) Field Description retry_count Message Retry Count: Set by the DSP core to indicate the total number of retries allowed for this message, including all segments. Decremented by the port each time a message is retried. 000000b: Infinite Retries 000001b[...]

www.ti.com SRIO Functional Description Table 21. TX Buffer Descriptor Field Definitions (continued) Field Description ssize RIO standard message payload size. Indicates how the hardware should segment the outgoing message by specifying the maximum number of double-words per packet. If the message is a multi-segment message, this field remains the s[...]

www.ti.com SRIO Functional Description TX_Queue_Map has been programmed to send two messages from Queue 0 before moving to Queue 1, it will re-attempt to send the same message from Queue 0 before moving on. Whether it is successful or not, the next attempt will come from Queue 1. Within a given queue, the hardware will always try to send the head b[...]

www.ti.com SRIO Functional Description Figure 23. Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh) TX_QUEUE_CNTL0 - Address Offset 7E0h <-------------------------------- TX_Queue_Map3 -----------------------------> <-------------------------------- TX_Queue_Map2 -----------------------------> 31 28 27 24 23 20 19 [...]

www.ti.com SRIO Functional Description Table 22. Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh) (continued) Field Pair Register[Bits] Field Value Description TX_Queue_Map2 TX_QUEUE_CNTL0[19–16] Queue Pointer 0h to Fh Pointer to a queue. This pointer can be programmed to point to any one of the 16 TX buffer descriptor queu[...]

www.ti.com SRIO Functional Description Table 22. Weighted Round Robin Programming Registers (Address Offset 7E0h–7ECh) (continued) Field Pair Register[Bits] Field Value Description TX_Queue_Map11 TX_QUEUE_CNTL2[27–24] Queue Pointer 0h to Fh Pointer to a queue. This pointer can be programmed to point to any one of the 16 TX buffer descriptor que[...]

www.ti.com 2.3.4.3 Reset and Power Down State SRIO Functional Description A transaction timeout is used by all outgoing message and direct I/O packets. It has the same value and is analogous to the request-to-response timer discussed in the RX CPPI and LSU sections, which is defined by the 24-bit value in the port response time-out CSR (See Section[...]

www.ti.com 2.3.4.4 Message Passing Software Requirements SRIO Functional Description Software performs the following functions for messaging: RX Operation • Assigns Mailbox-to-queue mapping and allowable SourceIDs/mailbox- Queue Mapping • Sets up associated buffer descriptor memory – CPPI RAM or L2 RAM • Link-lists the buffer descriptors, n[...]

www.ti.com SRIO Functional Description Initialization Example SRIO_REGS->Queue0_RXDMA_HDP = 0 ; SRIO_REGS->Queue1_RXDMA_HDP = 0 ; SRIO_REGS->Queue2_RXDMA_HDP = 0 ; SRIO_REGS->Queue3_RXDMA_HDP = 0 ; SRIO_REGS->Queue4_RXDMA_HDP = 0 ; SRIO_REGS->Queue5_RXDMA_HDP = 0 ; SRIO_REGS->Queue6_RXDMA_HDP = 0 ; SRIO_REGS->Queue7_RXDMA_HD[...]

www.ti.com Descriptor Descriptor Buffer Buffer PortRXDMA state RXqueueheaddescriptor pointer SRIO Functional Description Figure 24. RX Buffer Descriptors TX Buffer Descriptor TX_DESCP0_0->TXDESC0 = CSL_FMK( SRIO_TXDESC0_N_POINTER,(int )TX_DESCP0_1 ); //link to TX_DESCP0_1 TX_DESCP0_0->TXDESC1 = CSL_FMK( SRIO_TXDESC1_B_POINTER,([...]

www.ti.com Descriptor Descriptor Buffer Buffer Port TXDMA state TXqueueheaddescriptor pointer 2.3.5 Maintenance 2.3.6 Doorbell Operation SRIO Functional Description Figure 25. TX Buffer Descriptors Start Message Passing SRIO_REGS->Queue0_RXDMA_HDP = (int )RX_DESCP0_0 ; SRIO_REGS->Queue0_TXDMA_HDP = (int )TX_DESCP0_0 ; The type 8 M[...]

www.ti.com acklD rsv prio tt 1010 destID sourcelD Reserved srcTID Reserved DoorbellReg# rsv Doorbellbit CRC PHY LOG TRA LOG TRA PHY 5 3 2 2 4 8 8 8 8 9 2 1 4 16 16 32 16 4 2 10 info(msb) 8 info(lsb) 8 SRIO Functional Description for any desired purpose; see the RapidIO Interconnect Specification , Section 3.1.4, Type 10 Packet Format[...]

www.ti.com 2.3.7 Atomic Operations 2.3.8 Congestion Control SRIO Functional Description SRIO_REGS->LSU1_REG0 = CSL_FMK( SRIO_LSU1_REG0_RAPIDIO_ADDRESS_MSB,0 ); SRIO_REGS->LSU1_REG1 = CSL_FMK( SRIO_LSU1_REG1_ADDRESS_LSB_CONFIG_OFFSET, 0); SRIO_REGS->LSU1_REG2 = CSL_FMK( SRIO_LSU1_REG2_DSP_ADDRESS, 0); SRIO_REGS->LSU1_REG3 = CSL_FMK( SRIO[...]

www.ti.com 2.3.8.1 Detailed Description Reserved FLOW_CNTL0 31-18 R-0x00000 TT 17-16 R/W-01 FLOW_CNTL_ID 15-0 R/W-0x0000 Reserved FLOW_CNTL1 31-18 R-0x00000 TT 17-16 R/W-01 FLOW_CNTL_ID 15-0 R/W-0x0000 Reserved FLOW_CNTL2 31-18 R-0x00000 TT 17-16 R/W-01 FLOW_CNTL_ID 15-0 R/W-0x0000 Reserved FLOW_CNTL15 31-18 R-0x00000 TT 17-16 R/W-01 FLOW_CNTL_ID 1[...]

www.ti.com Reserved RIO_LSUn_FLOW_MASKS (AddressOffsets:0x041C, 0x043C,0x045C,0x047C) 31-16 R,0x0000 LSUnFlowMask 15-0 R/W ,0xFFFF TXQueue1 FlowMask RIO_TX_CPPI_FLOW_MASKS0 (AddressOffsets:0x0704) 31-16 R/W ,0xFFFF TXQueue0 FlowMask 15-0 R/W ,0xFFFF TXQueue3 FlowMask RIO_TX_CPPI_FLOW_MASKS1 ([...]

www.ti.com 2.3.9 Endianness SRIO Functional Description Table 25. Fields Within Each Flow Mask Bit Field Value Description 15 FL15 0 TX source does not support Flow 15 from table entry 1 TX source supports Flow 15 from table entry 14 FL14 0 TX source does not support Flow 14 from table entry 1 TX source supports Flow 14 from table entry 13 FL13 0 T[...]

www.ti.com 2.3.9.1 Translation for MMR space A0 A0 A2 A2 A1 A1 A3 A3 L2offset0x0 DSP definedMMR offset0x1000 Byte lane0 31 Byte lane3 DMA 32b 0 2.3.9.2 Endian Conversion (TMS320TCI6482) RapidIOdefinedbitpositions A0 A1 A2 A3 31 0 MMRoffset0x0000 B0 B1 B2 B3 MMRoffset0x0004 C0 C1 C2 C3 MMRoffset0x0008 D0 [...]

www.ti.com 2.3.10 Reset and Power Down SRIO Functional Description The RapidIO peripheral allows independent software controlled shutdown for the logical blocks listed in Table 26 . With the exception of BLK0_EN for the memory-mapped registers (MMRs), when the BLK n _EN signals are deasserted, the clocks are gated to these blocks, effectively provi[...]

www.ti.com 2.3.10.1 Reset and Power Down Summary 2.3.10.2 Enable and Enable Status Registers SRIO Functional Description After reset, the state of the peripheral depends on the default register values. Software can also perform a hard reset of each logical block within the peripheral via the GBL_EN and BLK n _EN bits. The GBL_EN bit resets the peri[...]

www.ti.com SRIO Functional Description Table 27. Global Enable and Global Enable Status Field Descriptions Register (Bit) Field Value Description GBL_EN(31–1) Reserved 0 These read-only bits return 0s when read. GBL_EN(0) EN Global enable. This bit controls reset to all clock domains within the peripheral. 0 The peripheral is to be disabled (held[...]

www.ti.com SRIO Functional Description Figure 35. BLK0_EN_STAT (Address 003Ch) 31 1 0 Reserved EN_STAT R-0 R-1 LEGEND: R = Read, W = Write, - n = Value after reset Figure 36. BLK1_EN (Address 0040h) 31 1 0 Reserved EN R-0 R/W-1 LEGEND: R = Read, W = Write, - n = Value after reset Figure 37. BLK1_EN_STAT (Address 0044h) 31 1 0 Reserved EN_STAT R-0 R[...]

www.ti.com 2.3.10.3 Software Shutdown Details 2.3.11 Emulation SRIO Functional Description Power consumption is minimized for all logical blocks that are in shutdown. In addition to simply asserting the appropriate reset signal to each logical block within the peripheral, clocks are gated off to the corresponding logical block as well. Clocks are a[...]

www.ti.com 2.3.12 TX Buffers, Credit, and Packet Reordering 2.3.12.1 Multiple Ports With 1x Operation SRIO Functional Description Table 29. Peripheral Control Register (PCR) Field Descriptions (continued) Bit Field Value Description 1 SOFT Soft stop. This bit and the FREE bit determine how the SRIO peripheral behaves during emulation halts. 0 Hard [...]

www.ti.com 2.3.12.2 Single Port With 1x or 4x Operation 2.3.12.3 Unavailable Outbound Credit SRIO Functional Description The physical layer buffers act like a FIFO unless there is a retry of a packet from the connected device, in which case a re-ordering algorithm is used. The algorithm searches backward through the buffer group for the first packe[...]

www.ti.com 2.3.13 Initialization Example 2.3.13.1 Enabling the SRIO Peripheral 2.3.13.2 PLL, Ports, Device ID and Data Rate Initializations SRIO Functional Description For multi-segment messages, if the transfer is unsuccessful after 256 times of credit request for the first segment, the TXU moves to the next queue in the round-robin loop. The TXU [...]

www.ti.com 2.3.13.3 Peripheral Initializations SRIO Functional Description SRIO_REGS->SERDES_CFG0_CNTL = 0x00000013; SRIO_REGS->SERDES_CFG1_CNTL = 0x00000000; SRIO_REGS->SERDES_CFG2_CNTL = 0x00000000; SRIO_REGS->SERDES_CFG3_CNTL = 0x00000000; SRIO_REGS->SERDES_CFGRX0_CNTL = 0x00081121 ; // enable rx, half rate SRIO_REGS->SERDES_CF[...]

www.ti.com 2.3.14 Bootload Capability 2.3.14.1 Configuration and Operation SRIO Functional Description SRIO_REGS->SP_RT_CTL = 0xFFFFFF00; // long SRIO_REGS->SP_GEN_CTL = 0x40000000; // agent, master, undiscovered SRIO_REGS->SP0_CTL = 0x00600000; // enable i/o SRIO_REGS->SP1_CTL = 0x00600000; // enable i/o SRIO_REGS->SP2_CTL = 0x00600[...]

www.ti.com Boot Program Host Controller Optional I2C EEPROM DSP ROM 1xRapidIO 2.3.14.2 Bootload Data Movement 2.3.14.3 Device Wakeup 2.3.15 RX Multicast Support, Daisy Chain Operation and Packet Forwarding 2.3.15.1 RX Multicast Support SRIO Functional Description 4. DSP executes idle instruction. 5. RapidIO ports send Idle control symbols to tra[...]

www.ti.com 2.3.15.2 Daisy Chain Operation and Packet Forwarding 2.3.15.3 Enabling Multicast and Packet Forwarding SRIO Functional Description Table 31. Multicast DeviceID Operation Local DeviceID Multicast DeviceID Device Register Offset Register Offset Endpoint Device Requirements TMS320TCI6482 0080h 0084h Accepts discrete multiple DestIDs from in[...]

www.ti.com SRIO Functional Description Figure 43. Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTL n ) Offsets 0x0094, 0x009C, 0x00A4, 0x00AC 31 18 17 16 OUT_BOUND_ Reserved PORT R-0 R/W-3 15 8 8BIT_DEVID_UP_BOUND R/W-FFh 7 0 8BIT_DEVID_LOW_BOUND R/W-FFh LEGEND: R/W = Read/Write; R = Read only; - n = Value after reset Table 33. Packet [...]

www.ti.com 3 Logical/Transport Error Handling and Logging Logical/Transport Error Handling and Logging Error management registers allow detection and logging of logical/transport layer errors. The detectable errors are captured in the logical layer error detect CSR (see Figure 44 ). Table 34 names the functional block(s) involved for each detectabl[...]

www.ti.com Logical/Transport Error Handling and Logging Table 34. Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions (continued) Bit Field Value Description 25 MSG_REQ_TIMEOUT Message request timeout (endpoint device only) 0 A timeout has not been detected by RXU. 1 A timeout has been detected by the RXU. A required message reque[...]

www.ti.com 4 Interrupt Conditions 4.1 CPU Interrupts 4.2 General Description acklD rsv prio tt 1010 destID sourcelD Reserved srcTID Reserved DoorbellReg# rsv Doorbellbit CRC PHY LOG TRA LOG TRA PHY 5 3 2 2 4 8 8 8 8 9 2 1 4 16 16 32 16 4 2 10 info(msb) 8 info(lsb) 8 Interrupt Conditions This section defines the CPU interrupt capabili[...]

www.ti.com 4.3 Interrupt Condition Status and Clear Registers Interrupt Conditions The DOORBELL packet’s 16-bit INFO field indicates which DOORBELL register interrupt bit to set. There are four DOORBELL registers, each currently with 16 bits, allowing 64 interrupt sources or circular buffers (see Table 23 for assignment of the 16 bits of DOORBELL[...]

www.ti.com 4.3.1 Doorbell Interrupt Condition Status and Clear Registers Interrupt Conditions Table 35. Interrupt Condition Status and Clear Bits Field Access Reset Value Value Function ICSx R 0 0 Condition not present 1 Condition present ICCx W 0 0 No effect 1 Clear the condition status bit (ICSx) The interrupt condition status registers (ICSRs) a[...]

www.ti.com 4.3.2 CPPI Interrupt Condition Status and Clear Registers Interrupt Conditions Figure 48. Doorbell 2 Interrupt Condition Status and Clear Registers Doorbell 2 Interrupt Condition Status Register (DOORBELL2_ICSR) (Address Offset 0220h) 31 16 Reserved R-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICS15 ICS14 ICS13 ICS12 ICS11 ICS10 ICS9 ICS8 I[...]

www.ti.com 4.3.3 LSU Interrupt Condition Status and Clear Registers Interrupt Conditions For transmission, the clearing of any ICSR bit is dependent on the CPU writing to the CP register for the queue (QUEUE n _TXDMA_CP). The CPU acknowledges the interrupt after reclaiming all available buffer descriptors by writing the CP value. This value is comp[...]

www.ti.com Interrupt Conditions Figure 52. LSU Interrupt Condition Status and Clear Registers LSU Interrupt Condition Status Register (LSU_ICSR) (Address Offset 0260h) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ICS31 ICS30 ICS29 ICS28 ICS27 ICS26 ICS25 ICS24 ICS23 ICS22 ICS21 ICS20 ICS19 ICS18 ICS17 ICS16 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-[...]

www.ti.com 4.3.4 Error, Reset, and Special Event Interrupt Condition Status and Clear Registers Interrupt Conditions Table 36. Interrupt Conditions Shown in LSU_ICSR and Cleared With LSU_ICCR (continued) Bit Associated LSU Interrupt Condition 6 LSU1 Retry Doorbell response received or Atomic test-and-swap was not allowed (semaphore in use) 5 LSU1 T[...]

www.ti.com Interrupt Conditions The interrupt status bits found in the ERR_RST_EVNT (0x0270) can be cleared by writing to the ICCR register (0x0278) in the same manner as other interrupts. However, in order for new event detection and interrupt generation to occur for these special interrupts, additional register bits must be cleared. The following[...]

www.ti.com 4.4 Interrupt Condition Routing Registers 4.4.1 Doorbell Interrupt Condition Routing Registers Interrupt Conditions Table 38. Interrupt Clearing Sequence for Special Event Interrupts (continued) Interrupt Function 1 st Step 2 nd Step 3 rd Step Port 3 Error Write 1 to clear: Write 1 to clear any of the Write 1 to clear: (TMS320TCI6482 Onl[...]

www.ti.com 4.4.1.1 CPPI Interrupt Condition Routing Registers Interrupt Conditions When doorbell packets are received by the SRIO peripheral, these ICRRs route doorbell interrupt requests to interrupt destinations. For example, if ICS6 = 1 in DOORBELL2_ICSR and ICR6 = 0010b in DOORBELL2_ICRR, the interrupt request from Doorbell 2, bit 6 is sent to [...]

www.ti.com 4.4.1.2 LSU Interrupt Condition Routing Registers Interrupt Conditions Figure 56. TX CPPI Interrupt Condition Routing Registers TX CPPI Interrupt Condition Routing Register (TX_CPPI_ICRR) (Address Offset 02D0h) 31 28 27 24 23 20 19 16 ICR7 ICR6 ICR5 ICR4 R/W-0000 R/W-0000 R/W-0000 R/W-0000 15 12 11 8 7 4 3 0 ICR3 ICR2 ICR1 ICR0 R/W-0000 [...]

www.ti.com 4.4.1.3 Error, Reset, and Special Event Interrupt Condition Routing Registers Interrupt Conditions Figure 57. LSU Interrupt Condition Routing Registers LSU Interrupt Condition Routing Register 0 (LSU_ICRR0) (Address Offset 02E0h) 31 28 27 24 23 20 19 16 ICR7 ICR6 ICR5 ICR4 R/W-0000 R/W-0000 R/W-0000 R/W-0000 15 12 11 8 7 4 3 0 ICR3 ICR2 [...]

www.ti.com 4.5 Interrupt Status Decode Registers Interrupt Conditions Figure 58. Error, Reset, and Special Event Interrupt Condition Routing Registers Error, Reset, and Special Event ICRR (ERR_RST_EVNT_ICRR) (Address Offset 02F0h) 31 Reserved R-0 12 11 8 7 4 3 0 Reserved ICR2 ICR1 ICR0 R-0 R/W-0000 R/W-0000 R/W-0000 Error, Reset, & Special Even[...]

www.ti.com Interrupt Conditions each bit in the ISDR. Bits within the LSU interrupt condition status register (ICSR) are logically grouped for a given core and ORed together into a single bit (bit 31) of the decode register. Similarly, the bits within the Error, Reset, and Special Event ICSR are ORed together into bit 30 of the decode register. The[...]

www.ti.com 4.6 Interrupt Generation 4.7 Interrupt Pacing Interrupt Conditions Figure 61. Example Diagram of Interrupt Status Decode Register Mapping The following are suggestions for minimizing the number of register reads to identifying the interrupt source: • Dedicate each doorbell ICSR to one core. The CPU can then determine the interrupt sour[...]

www.ti.com 4.8 Interrupt Handling Interrupt Conditions immediately starts down-counting each time the CPU writes these registers. When the rate control counter register is written, and the counter value reaches zero (note that the CPU may write zero immediately for a zero count), the interrupt pulse generation logic is allowed to fire a single puls[...]

www.ti.com Interrupt Conditions Interrupt Handler temp1 = SRIO_REGS->TX_CPPI_ICSR; if ((temp1 & 0x00000001) == 0x00000001) { SRIO_REGS->Queue0_TXDMA_CP = (int )TX_DESCP0_0; } temp2 = SRIO_REGS->RX_CPPI_ICSR; if ((temp2 & 0x00000001) == 0x00000001) { SRIO_REGS->Queue0_RXDMA_CP = (int )RX_DESCP0_0; } SRIO_REGS->DOORBELL0_ICCR=0[...]

www.ti.com 5 SRIO Registers 5.1 Introduction SRIO Registers Table 40 lists the names and address offsets of the memory-mapped registers for the Serial RapidIO (SRIO) peripheral. See the device-specific data manual for the exact memory addresses of these registers. Table 40. Serial RapidIO (SRIO) Registers Offset Acronym Register Description Section[...]

www.ti.com SRIO Registers Table 40. Serial RapidIO (SRIO) Registers (continued) Offset Acronym Register Description Section 011Ch SERDES_CFGTX3_CNTL SERDES Transmit Channel Configuration Register 3 Section 5.14 0120h SERDES_CFG0_CNTL SERDES Macro Configuration Register 0 Section 5.15 0124h SERDES_CFG1_CNTL SERDES Macro Configuration Register 1 Sect[...]

www.ti.com SRIO Registers Table 40. Serial RapidIO (SRIO) Registers (continued) Offset Acronym Register Description Section 030Ch INTDST3_DECODE INTDST Interrupt Status Decode Register 3 Section 5.31 0310h INTDST4_DECODE INTDST Interrupt Status Decode Register 4 Section 5.31 0314h INTDST5_DECODE INTDST Interrupt Status Decode Register 5 Section 5.3[...]

www.ti.com SRIO Registers Table 40. Serial RapidIO (SRIO) Registers (continued) Offset Acronym Register Description Section 0504h QUEUE1_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 1 Section 5.41 0508h QUEUE2_TXDMA_HDP Queue Transmit DMA Head Descriptor Pointer Register 2 Section 5.41 050Ch QUEUE3_TXDMA_HDP Queue Transmit DMA Head[...]

www.ti.com SRIO Registers Table 40. Serial RapidIO (SRIO) Registers (continued) Offset Acronym Register Description Section 063Ch QUEUE15_RXDMA_HDP Queue Receive DMA Head Descriptor Pointer Register 15 Section 5.43 0680h QUEUE0_RXDMA_CP Queue Receive DMA Completion Pointer Register 0 Section 5.44 0684h QUEUE1_RXDMA_CP Queue Receive DMA Completion P[...]

www.ti.com SRIO Registers Table 40. Serial RapidIO (SRIO) Registers (continued) Offset Acronym Register Description Section 0838h RXU_MAP_L7 MailBox-to-Queue Mapping Register L7 Section 5.50 083Ch RXU_MAP_H7 MailBox-to-Queue Mapping Register H7 Section 5.50 0840h RXU_MAP_L8 MailBox-to-Queue Mapping Register L8 Section 5.50 0844h RXU_MAP_H8 MailBox-[...]

www.ti.com SRIO Registers Table 40. Serial RapidIO (SRIO) Registers (continued) Offset Acronym Register Description Section 08F0h RXU_MAP_L30 MailBox-to-Queue Mapping Register L30 Section 5.50 08F4h RXU_MAP_H30 MailBox-to-Queue Mapping Register H30 Section 5.50 08F8h RXU_MAP_L31 MailBox-to-Queue Mapping Register L31 Section 5.50 08FCh RXU_MAP_H31 M[...]

www.ti.com SRIO Registers Table 40. Serial RapidIO (SRIO) Registers (continued) Offset Acronym Register Description Section 117Ch SP1_CTL Port 1 Control CSR Section 5.73 1180h SP2_LM_REQ Port 2 Link Maintenance Request CSR Section 5.69 1184h SP2_LM_RESP Port 2 Link Maintenance Response CSR Section 5.70 1188h SP2_ACKID_STAT Port 2 Local AckID Status[...]

www.ti.com SRIO Registers Table 40. Serial RapidIO (SRIO) Registers (continued) Offset Acronym Register Description Section 2100h SP3_ERR_DET Port 3 Error Detect CSR Section 5.82 2104h SP3_RATE_EN Port 3 Error Enable CSR Section 5.83 2108h SP3_ERR_ATTR_CAPT_DBG0 Port 3 Attributes Error Capture CSR 0 Section 5.84 210Ch SP3_ERR_CAPT_DBG1 Port 3 Packe[...]

www.ti.com 5.2 Peripheral Identification Register (PID) SRIO Registers The peripheral identification register (PID) is a read-only register that contains the ID and ID revision number for that peripheral. The PID stores version information used to identify the peripheral. Writes have no effect to this register. The values are hard coded and will no[...]

www.ti.com 5.3 Peripheral Control Register (PCR) SRIO Registers The peripheral control register (PCR) contains a bit that enables or disables data flow in the logical layer of the entire peripheral. In addition, the PCR has emulation control bits that control the peripheral behavior during emulation halts. PCR is shown in Figure 64 and described in[...]

www.ti.com 5.4 Peripheral Settings Control Register (PER_SET_CNTL) SRIO Registers The peripheral settings control register (PER_SET_CNTL) is shown in Figure 65 and described in Table 43 . For additional programming information, see Section 2.3.12 . Figure 65. Peripheral Settings Control Register (PER_SET_CNTL) (Address Offset 0020h) 31 27 26 25 24 [...]

www.ti.com SRIO Registers Table 43. Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions (continued) Bit Field Value Description 17–15 TX_PRI1_WM 000b–111b Transmit credit threshold. Sets the required number of logical layer TX buffers needed to send priority 1 packets across the UDI. This is valid for all ports in 1x mode onl[...]

www.ti.com SRIO Registers Table 43. Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions (continued) Bit Field Value Description 3 ENPLL4 0 Not used. Should always be programmed as "0". See Section 2.3.2.1 to enable SERDES PLL. 2 ENPLL3 0 Not used. Should always be programmed as "0". See Section 2.3.2.1 to enab[...]

www.ti.com 5.5 Peripheral Global Enable Register (GBL_EN) SRIO Registers GBL_EN is implemented with a single enable bit for the entire SRIO peripheral. This bit is logically ORed with the reset input to the module and is fanned out to all logical blocks within the peripheral. GBL_EN is shown in Figure 66 and described in Table 44 . For additional p[...]

www.ti.com 5.6 Peripheral Global Enable Status Register (GBL_EN_STAT) SRIO Registers The peripheral global enable status register (GBL_EN_STAT) is shown in Figure 67 and described in Table 45 . For additional programming information, see Section 2.3.10 . Figure 67. Peripheral Global Enable Status Register (GBL_EN_STAT) - Address 0034h 31 24 Reserve[...]

www.ti.com SRIO Registers Table 45. Peripheral Global Enable Status Register (GBL_EN_STAT) Field Descriptions (continued) Bit Field Value Description 1 BLK0_EN_STAT Block 0 enable status. Logical block 0 is the set of memory-mapped registers (MMRs) for the SRIO peripheral. 0 Logical block 0 is in reset with its clock off. 1 Logical block 0 is enabl[...]

www.ti.com 5.7 Block n Enable Register (BLK n_EN) SRIO Registers There are nine of these registers, one for each of nine logical blocks in the peripheral. The registers and the blocks they support are listed in Table 46 . The general form for a block n enable register (BLK n _EN) is shown in Figure 68 and described in Table 47 . For additional prog[...]

www.ti.com 5.8 Block n Enable Status Register (BLK n_EN_STAT) SRIO Registers There are nine of these registers, one for each of nine logical blocks in the peripheral. The registers and the blocks they support are listed in Table 48 . The general form for a block n enable status register (BLK n _EN_STAT) is shown in Figure 69 and described in Table [...]

www.ti.com 5.9 RapidIO DEVICEID1 Register (DEVICEID_REG1) SRIO Registers The RapidIO DEVICEID1 register (DEVICEID_REG1) is shown in Figure 70 and described in Table 50 . Figure 70. RapidIO DEVICEID1 Register (DEVICEID_REG1) (Offset 0080h) 31 24 23 16 Reserved 8BNODEID R-00h R/W-FFh 15 0 16BNODEID R/W-FFFFh LEGEND: R/W = Read/Write; R = Read only; -[...]

www.ti.com 5.10 RapidIO DEVICEID2 Register (DEVICEID_REG2) SRIO Registers The RapidIO DEVICEID2 register (DEVICEID_REG2 is shown in Figure 71 and described in Table 51 . For additional programming information, see Section 2.3.15.1 and Section 2.3.15.3 . Figure 71. RapidIO DEVICEID2 Register (DEVICEID_REG2) (Offset 0x0084) 31 24 23 16 Reserved 8BNOD[...]

www.ti.com 5.11 Packet Forwarding Register n for 16-Bit Device IDs (PF_16B_CNTL n) SRIO Registers There are four of these registers (see Table 52 ). The general form of a packet forwarding register for 16-bit DeviceIDs is shown in Figure 72 and described in Table 53 . For additional programming information, see Section 2.3.15 and Section 2.3.15.3 .[...]

www.ti.com 5.12 Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTL n) SRIO Registers There are four of these registers (see Table 54 ). The general form of a packet forwarding register for 16-bit DeviceIDs is shown in Figure 73 and described in Table 55 . For additiona programming information see Section 2.3.15 and and Section 2.3.15.3 .[...]

www.ti.com 5.13 SERDES Receive Channel Configuration Register n (SERDES_CFGRX n_CNTL) SRIO Registers There are four of these registers, to support four ports (see ). The general form for a SERDES receive channel configuration register is summarized by Figure 74 and Table 57 . See Section 2.3.2.2 for a complete explanation of the programming of thes[...]

www.ti.com SRIO Registers Table 57. SERDES Receive Channel Configuration Register n (SERDES_CFGRX n _CNTL) Field Descriptions (continued) Bit Field Value Description 15–14 LOS Loss of signal. Enables loss of signal detection with 2 selectable thresholds. 00b Disabled. Loss of signal detection disabled. 01b High threshold. Loss of signal detection[...]

www.ti.com SRIO Registers Table 58. EQ Bits (continued) CFGRX[22–19] Low Freq Gain Zero Freq (at e 28 (min)) 1000b Adaptive 1084MHz 1001b 805MHz 1010b 573MHz 1011b 402MHz 1100b 304MHz 1101b 216MHz 1110b 156MHz 1111b 135MHz SPRUE13A – September 2006 Serial RapidIO (SRIO) 127 Submit Documentation Feedback[...]

www.ti.com 5.14 SERDES Transmit Channel Configuration Register n (SERDES_CFGTX n_CNTL) SRIO Registers There are four of these registers, to support four ports (see Table 59 ). The general form for a SERDES transmit channel configuration register is summarized by Figure 75 and Table 60 . See Section 2.3.2.3 for a complete explanation of the programm[...]

www.ti.com SRIO Registers Table 60. SERDES Transmit Channel Configuration Register n (SERDES_CFGTX n _CNTL) Field Descriptions (continued) Bit Field Value Description 0 ENTX Enable transmitter 0 Disable this transmitter. 1 Enable this transmitter. Table 61. DE Bits of SERDES_CFGTX n _CNTL Amplitude Reduction DE Bits % dB 0000b 0 0 0001b 4.76 –0.4[...]

www.ti.com 5.15 SERDES Macro Configuration Register n (SERDES_CFG n_CNTL) SRIO Registers There are four of these registers, to support four ports (see Table 63 ). The general form for a SERDES transmit channel configuration register is summarized by Figure 76 and Table 64 . See Section 2.3.2.1 for a complete explanation of the programming of this r[...]

www.ti.com SRIO Registers Table 64. SERDES Macro Configuration Register n (SERDES_CFG n _CNTL) Field Descriptions (continued) Bit Field Value Description 5–1 MPY PLL multiply. Select PLL multiply factors between 4 and 60. 00000b 4x 00001b 5x 00010b 6x 00011b Reserved 00100b 8x 00101b 10x 00110b 12x 00111b 12.5x 01000b 15x 01001b 20x 01010b 25x 01[...]

www.ti.com 5.16 DOORBELL n Interrupt Condition Status Register (DOORBELL n_ICSR) SRIO Registers The four doorbell interrupts are mapped to these registers (see Table 65 ). The general form of a doorbell interrupt condition status register is shown in Figure 77 and described in Table 66 . For additional programming information, see Section 4.3.1 and[...]

www.ti.com 5.17 DOORBELL n Interrupt Condition Clear Register (DOORBELL n_ICCR) SRIO Registers The four doorbells interrupts that are mapped are cleared by this register (see Table 67 ). The general form of a doorbell interrupt condition clear register is shown in Figure 78 and described in Table 68 . For additional programming information, see Sec[...]

www.ti.com 5.18 RX CPPI Interrupt Status Register (RX_CPPI_ICSR) SRIO Registers The bits in this register indicate any active interrupt requests from RX buffer descriptor queues. The RX CPPI interrupt status register (RX_CPPI_ICSR) is shown in Figure 79 and described in Table 69 . For additional programming information, see Section 4.3.2 . Figure 7[...]

www.ti.com 5.19 RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) SRIO Registers This register is used to clear bits in RX_CPPI_ICSR to acknowledge interrupts from the RX buffer descriptor queues. The RX CPPI interrupt clear register (RX_CPPI_ICCR) is shown in Figure 80 and described in Table 70 . For additional programming information, see Section 4[...]

www.ti.com 5.20 TX CPPI Interrupt Status Register (TX_CPPI_ICSR) SRIO Registers The bits in this register indicate any active interrupt requests from TX buffer descriptor queues. TX_CPPI_ICSR is shown in Figure 81 and described in Table 71 . Figure 81. TX CPPI Interrupt Condition Status Register (TX_CPPI_ICSR) - Address Offset 0250h 31 16 Reserved [...]

www.ti.com 5.21 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) SRIO Registers This register is used to clear bits in TX_CPPI_ICSR to acknowledge interrupts from the TX buffer descriptor queues. TX_CPPI_ICCR is shown in Figure 82 and described in Table 72 . Figure 82. TX CPPI Interrupt Condition Clear Register (TX_CPPI_ICCR) - Address Offset 0258h [...]

www.ti.com 5.22 LSU Interrupt Condition Status Register (LSU_ICSR) SRIO Registers Each of the status bits in this register indicates the occurrence of a particular type of transaction interrupt condition for a particular LSU. LSU_ICSR is shown in Figure 83 and described in Table 73 . For additional programming information, see Section 4.3.3 . Figur[...]

www.ti.com SRIO Registers Table 73. LSU Interrupt Condition Status Register (LSU_ICSR) Field Descriptions (continued) Bit Field Value Description 19 ICS19 0 LSU3 interrupt condition not detected. 1 LSU3 interrupt condition detected. Transaction was not sent due to unsupported transaction type or invalid field encoding. 18 ICS18 0 LSU3 interrupt con[...]

www.ti.com SRIO Registers Table 73. LSU Interrupt Condition Status Register (LSU_ICSR) Field Descriptions (continued) Bit Field Value Description 1 ICS1 0 LSU1 interrupt condition not detected. 1 LSU1 interrupt condition detected. Non-posted transaction received ERROR response, or error in response payload. 0 ICS0 0 LSU1 interrupt condition not det[...]

www.ti.com 5.23 LSU Interrupt Condition Clear Register (LSU_ICCR) SRIO Registers Setting a bit in this register clears the corresponding bit in LSU_ICSR, to acknowledge the interrupt. LSU_ICCR is shown in Figure 84 and described in Table 74 . For additional programming information, see Section 4.3.3 . Figure 84. LSU Interrupt Condition Clear Regist[...]

www.ti.com 5.24 Error, Reset, and Special Event Interrupt Condition Status Register SRIO Registers (ERR_RST_EVNT_ICSR) Each of the nonreserved bits in this register indicate the status of a particular interrupt condition in one or more of the SRIO ports. ERR_RST_EVNT_ICSR is shown in Figure 85 and described in Table 75 . For additional programming [...]

www.ti.com 5.25 Error, Reset, and Special Event Interrupt Condition Clear Register SRIO Registers (ERR_RST_EVNT_ICCR) Each bit in this register is used to clear the corresponding status bit in ERR_RST_EVNT_ICSR. The field of ERR_RST_EVNT_ICCR are shown in Figure 86 and described in Table 76 . For additional programming information, see Section 4.3.[...]

www.ti.com 5.26 DOORBELL n Interrupt Condition Routing Registers (DOORBELL n_ICRR and SRIO Registers DOORBELL n_ICRR2) When doorbell packets are received by the SRIO peripheral, these ICRRs route doorbell interrupt requests from the associated doorbell ICSR to user-selected interrupt destinations. Each of the four doorbells can be mapped to these r[...]

www.ti.com 5.27 RX CPPI Interrupt Condition Routing Registers (RX_CPPI_ICRR and RX_CPPI_ICRR2) SRIO Registers Figure 88 and Table 79 summarize the ICRRs for the RXU. These registers route queue interrupts to interrupt destinations. For example, if ICS6 = 1 in RX_CPPI_ICSR and ICR6 = 0010b in RX_CPPI_ICRR, the interrupt request from RX buffer descri[...]

www.ti.com 5.28 TX CPPI Interrupt Condition Routing Registers (TX_CPPI_ICRR and TX_CPPI_ICRR2) SRIO Registers Figure 89 and Table 80 summarize the ICRRs for the TXU. These registers route queue interrupts to interrupt destinations. For example, if ICS6 = 1 in TX_CPPI_ICSR and ICR6 = 0011b in TX_CPPI_ICRR, the interrupt request from TX buffer descri[...]

www.ti.com 5.29 LSU Interrupt Condition Routing Registers (LSU_ICRR0–LSU_ICRR3) SRIO Registers Figure 90 shows the ICRRs for the LSU interrupt requests, and Table 81 shows the general description for an ICRx field in any of the four registers. These registers route LSU interrupt requests from LSU_ICSR to interrupt destinations. For example, if IC[...]

www.ti.com SRIO Registers Table 81. LSU Interrupt Condition Routing Register Field Descriptions Field Value Description ICR x Interrupt condition routing. Routes the associated LSU interrupt request to one of eight interrupt (x = 0 to 31) destinations (INTDST0–INTDST7). Bits ICR0–ICR7 are for LSU1; bits ICR8–ICR15, for LSU2; bits ICR16–ICR2[...]

www.ti.com 5.30 Error, Reset, and Special Event Interrupt Condition Routing Registers SRIO Registers (ERR_RST_EVNT_ICRR, ERR_RST_EVNT_ICRR2, and ERR_RST_EVNT_ICRR3) The ICRRs shown in Figure 91 route port interrupt requests from ERR_RST_EVNT_ICSR to interrupt destinations. For example, if ICS8 = 1 in ERR_RST_EVNT_ICSR and ICR8 = 0001b in ERR_RST_EV[...]

www.ti.com 5.31 Interrupt Status Decode Register (INTDST n_DECODE) SRIO Registers There are eight of these registers, one for each interrupt destination (see Table 83 ). This type of register is shown in Figure 92 and described in Table 84 . Interrupt sources are mapped to an interrupt decode register only if the ICRRs routes the interrupt source t[...]

www.ti.com SRIO Registers Table 84. Interrupt Status Decode Register (INTDST n _DECODE) Field Descriptions (continued) Bit Field Value Description 27 ISD27 0 No interrupt request routed to this bit. 1 Interrupt request detected. Possible interrupt sources: • TX buffer descriptor queue 4 (bit 4 of TX_CPPI_ICSR) • RX buffer descriptor queue 4 (bi[...]

www.ti.com SRIO Registers Table 84. Interrupt Status Decode Register (INTDST n _DECODE) Field Descriptions (continued) Bit Field Value Description 15 ISD15 0 No interrupt request routed to this bit. 1 Interrupt request detected. Possible interrupt sources: • Doorbell 0, bit 15 (bit 15 of DOORBELL0_ICSR) • Doorbell 1, bit 15 (bit 15 of DOORBELL1[...]

www.ti.com SRIO Registers Table 84. Interrupt Status Decode Register (INTDST n _DECODE) Field Descriptions (continued) Bit Field Value Description 7 ISD7 0 No interrupt request routed to this bit. 1 Interrupt request detected. Possible interrupt sources: • Doorbell 0, bit 7 (bit 7 of DOORBELL0_ICSR) • Doorbell 1, bit 7 (bit 7 of DOORBELL1_ICSR)[...]

www.ti.com 5.32 INTDST n Interrupt Rate Control Register (INTDST n_RATE_CNTL) SRIO Registers There are eight interrupt rate control registers, one for each interrupt destination (see Table 85 ). Figure 93 and Table 86 provide a general description for an interrupt rate control register. These registers are used to set the rate at which an interrupt[...]

www.ti.com 5.33 LSU n Control Register 0 (LSU n_REG0) SRIO Registers There are four of these registers, one for each LSU (see Table 87 ). The general description for an LSU control register 0 is shown in Figure 94 and described in Table 88 . For additional programming see Section 2.3.3 . Table 87. LSU n _REG0 Registers and the Associated LSUs Regis[...]

www.ti.com 5.34 LSU n Control Register 1 (LSU n_REG1) SRIO Registers There are four of these registers, one for each LSU (see ). This register's content is shown in Figure 95 and described in Table 90 . For additional programming see Section 2.3.3 . Table 89. LSU n _REG1 Registers and the Associated LSUs Register Address Offset Associated LSU [...]

www.ti.com 5.35 LSU n Control Register 2 (LSU n_REG2) SRIO Registers There are four of these registers, one for each LSU (see Table 91 ). LSU n _REG2 is shown in Figure 96 and described in Table 92 . For additional programming see Section 2.3.3 . Table 91. LSU n _REG2 Registers and the Associated LSUs Register Address Offset Associated LSU LSU1_REG[...]

www.ti.com 5.36 LSU n Control Register 3 (LSU n_REG3) SRIO Registers There are four of these registers, one for each LSU (see Table 93 ). LSU n _REG3 is shown in Figure 97 and described in Table 94 . For additional programming see Section 2.3.3 . Table 93. LSU n _REG3 Registers and the Associated LSUs Register Address Offset Associated LSU LSU1_REG[...]

www.ti.com 5.37 LSU n Control Register 4 (LSU n_REG4) SRIO Registers There are four of these registers, one for each LSU (see Table 95 ). LSU n _REG4 is shown in Figure 98 and described in Table 96 . For additional programming see Section 2.3.3 . Table 95. LSU n _REG4 Registers and the Associated LSUs Register Address Offset Associated LSU LSU1_REG[...]

www.ti.com 5.38 LSU n Control Register 5 (LSU n_REG5) SRIO Registers There are four of these registers, one for each LSU (see Table 97 ). LSU n _REG5 is shown in Figure 99 and described in Table 98 . For additional programming see Section 2.3.3 . Table 97. LSU n _REG5 Registers and the Associated LSUs Register Address Offset Associated LSU LSU1_REG[...]

www.ti.com 5.39 LSU n Control Register 6 (LSU n_REG6) SRIO Registers There are four of these registers, one for each LSU (see Table 99 ). LSU n _REG6 is shown in Figure 100 and described in Table 100 . For additional programming see Section 2.3.3 . Table 99. LSU n _REG6 Registers and the Associated LSUs Register Address Offset Associated LSU LSU1_R[...]

www.ti.com 5.40 LSU n Congestion Control Flow Mask Register (LSU n_FLOW_MASKS) SRIO Registers There are four of these registers, one for each LSU (see Table 101 ). The fields of an LSU n _FLOW_MASKS register are summarized by Figure 101 and described in Table 102 . The 16 bits within each FLOW_MASK field are summarized by Figure 102 and Table 103 .[...]

www.ti.com SRIO Registers Table 103. LSU n FLOW_MASK Fields (continued) Bit Field Value Description 8 FL8 0 LSU n does not support Flow 8 from table entry 1 LSU n supports Flow 8 from table entry 7 FL7 0 LSU n does not support Flow 7 from table entry 1 LSU n supports Flow 7 from table entry 6 FL6 0 LSU n does not support Flow 6 from table entry 1 L[...]

www.ti.com 5.41 Queue n Transmit DMA Head Descriptor Pointer Register (QUEUE n_TXDMA_HDP) SRIO Registers There are sixteen of these registers (see Table 104 ). QUEUE n _TXDMA_HDP is shown in Figure 103 and described in Table 105 . For additional programming information, see Section 2.3.4.2 . Table 104. QUEUE n _TXDMA_HDP Registers Register Address [...]

www.ti.com 5.42 Queue n Transmit DMA Completion Pointer Register (QUEUE n_TXDMA_CP) SRIO Registers There are sixteen of these registers (see Table 106 ). QUEUE n _TXDMA_CP is shown in Figure 104 and described in Table 107 . For additional programming information, see Section 2.3.4.2 . Table 106. QUEUE n _TXDMA_CP Registers Register Address Offset Q[...]

www.ti.com 5.43 Queue n Receive DMA Head Descriptor Pointer Register (QUEUE n_RXDMA_HDP) SRIO Registers There are sixteen of these registers (see Table 108 ). QUEUE n _RXDMA_HDP is shown in Figure 105 and described in Table 109 . For additional programming information, see Section 2.3.4.1 . Table 108. QUEUE n _RXDMA_HDP Registers Register Address O[...]

www.ti.com 5.44 Queue n Receive DMA Completion Pointer Register (QUEUE n_RXDMA_CP) SRIO Registers There are sixteen of these registers (see Table 110 ). QUEUE n _RXDMA_CP is shown in Figure 106 and described in Table 111 . For additional programming information, see Section 2.3.4.1 . Table 110. QUEUE n _RXDMA_CP Registers Register Address Offset QU[...]

www.ti.com 5.45 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) SRIO Registers Each bit in this register corresponds to one of the 16 TX buffer descriptor queues. If a 1 is written to a bit, the teardown process is initiated for the associated queue. TX_QUEUE_TEAR_DOWN is shown in Figure 107 and described in Table 112 . Figure 107. Transmit Q[...]

www.ti.com 5.46 Transmit CPPI Supported Flow Mask Registers (TX_CPPI_FLOW_MASKS[0–7]) SRIO Registers Each of the eight TX CPPI flow mask registers holds the flow masks for two TX descriptor buffer queues (see Table 113 ). Figure 108 shows the registers, and Figure 109 shows the general form of a flow mask. Each bit of a flow mask selects or desel[...]

www.ti.com SRIO Registers Figure 108. Transmit CPPI Supported Flow Mask Registers Transmit CPPI Supported Flow Mask Register 0 (TX_CPPI_FLOW_MASKS0) 31 16 15 0 QUEUE1_FLOW_MASK QUEUE0_FLOW_MASK R/W-FFh R/W-FFh Transmit CPPI Supported Flow Mask Register 1 (TX_CPPI_FLOW_MASKS1) 31 16 15 0 QUEUE3_FLOW_MASK QUEUE2_FLOW_MASK R/W-FFh R/W-FFh Transmit CPP[...]

www.ti.com SRIO Registers Table 114. TX Queue n FLOW_MASK Field Descriptions (continued) Bit Field Value Description 12 FL12 0 Queue n does not support Flow 12 from table entry 1 Queue n supports Flow 12 from table entry 11 FL11 0 Queue n does not support Flow 11 from table entry 1 Queue n supports Flow 11 from table entry 10 FL10 0 Queue n does no[...]

www.ti.com 5.47 Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) SRIO Registers Each of this register's bits corresponds to one of the 16 RX buffer descriptor queues. If a 1 is written to a bit, the teardown process is started for the associated queue. RX_QUEUE_TEAR_DOWN is shown in Figure 110 and described in Table 115 . For additional pr[...]

www.ti.com 5.48 Receive CPPI Control Register (RX_CPPI_CNTL) SRIO Registers Each bit in this register indicates whether the associated RX buffer descriptor queue must receive messages in the order the source device attempts to transmit them. RX_CPPI_CNTL is shown in and described in Table 116 . For additional programming information, see Section 2.[...]

www.ti.com 5.49 Transmit CPPI Weighted Round Robin Control Registers (TX_QUEUE_CNTL[0–3]) SRIO Registers The transmission order among TX buffer descriptor queues is based on the programmable weighted round-robin scheme explained in Section 2.3.4.2 . As part of this scheme, software must program the 16 mappers to determine the order in which the q[...]

www.ti.com SRIO Registers Table 117. Transmit CPPI Weighted Round Robin Control Register Field Descriptions Field Pair Register[Bits] Field Value Description TX_Queue_Map0 TX_QUEUE_CNTL0[3–0] Queue Pointer 0h to Fh Pointer to a queue. This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues. TX_QUEUE_CNTL0[7–4] N[...]

www.ti.com SRIO Registers Table 117. Transmit CPPI Weighted Round Robin Control Register Field Descriptions (continued) Field Pair Register[Bits] Field Value Description TX_Queue_Map9 TX_QUEUE_CNTL2[11–8] Queue Pointer 0h to Fh Pointer to a queue. This pointer can be programmed to point to any one of the 16 TX buffer descriptor queues. TX_QUEUE_C[...]

www.ti.com 5.50 Mailbox to Queue Mapping Registers (RXU_MAP_L n and RXU_MAP_H n) SRIO Registers Messages addressed to any of the 64 mailbox locations can be received on any of the RapidIO ports simultaneously. Packets are handled sequentially in order of receipt. A block of 32 mappers directs the inbound messages to the appropriate RX queues. After[...]

www.ti.com SRIO Registers Table 118. Mailbox to Queue Mapping Registers and the Associated RX Mappers (continued) Register Address Offset Associated RX Mapper RXU_MAP_L18 0890h Mapper 18 RXU_MAP_H18 0894h Mapper 18 RXU_MAP_L19 0898h Mapper 19 RXU_MAP_H19 089Ch Mapper 19 RXU_MAP_L20 08A0h Mapper 20 RXU_MAP_H20 08A4h Mapper 20 RXU_MAP_L21 08A8h Mappe[...]

www.ti.com SRIO Registers Figure 113. Mailbox to Queue Mapping Register Pair Mailbox to Queue Mapping Register L n (RXU_MAP_L n ) 31 30 29 24 23 22 21 16 LETTER_MASK MAILBOX_MASK LETTER MAILBOX R/W-11 R/W-111111 R/W-00 R/W-000000 15 0 SOURCEID R/W-0000h Mailbox to Queue Mapping Register H n (RXU_MAP_H n ) 31 Reserved R-0 10 9 8 7 6 5 2 1 0 SEGMENT_[...]

www.ti.com SRIO Registers Table 120. Mailbox-to-Queue Mapping Register H n (RXU_MAP_H n ) Field Descriptions (continued) Bit Field Value Description 7–6 Reserved 0 These read-only bits return 0s when read. 5–2 QUEUE_ID 0–15 Queue identification number. This field selects which of the 16 RX buffer queues is associated with mapper n . 1 PROMISC[...]

www.ti.com 5.51 Flow Control Table Entry Register n (FLOW_CNTL n) SRIO Registers There are sixteen of these registers (see Table 121 ). FLOW_CNTL n is shown in Figure 114 and described in Table 122 . For additional programming information, see Section 2.3.8 . Table 121. FLOW_CNTL n Registers Register Address Offset FLOW_CNTL0 0900h FLOW_CNTL1 0904h[...]

www.ti.com 5.52 Device Identity CAR (DEV_ID) SRIO Registers The device identity CAR (DEV_ID) is shown in Figure 115 and described in Table 123 . Writes have no effect to this register. The values are hard coded and will not change from their reset state. Figure 115. Device Identity CAR (DEV_ID) - Address Offset 1000h 31 16 15 0 DEVICEIDENTITY DEVIC[...]

www.ti.com 5.53 Device Information CAR (DEV_INFO) SRIO Registers The device information CAR (DEV_INFO) is shown in Figure 116 and described in Table 124 . Writes have no effect to this register. The values are hard coded and will not change from their reset state. Figure 116. Device Information CAR (DEV_INFO) - Address Offset 1004h 31 0 DEVICEREV R[...]

www.ti.com 5.54 Assembly Identity CAR (ASBLY_ID) SRIO Registers The assembly identity CAR (ASBLY_ID) is shown in Figure 117 and described in Table 125 . Writes have no effect to this register. The values are hard coded and will not change from their reset state. Figure 117. Assembly Identity CAR (ASBLY_ID) - Address Offset 1008h 31 16 15 0 ASSY_IDE[...]

www.ti.com 5.55 Assembly Information CAR (ASBLY_INFO) SRIO Registers The assembly information CAR (ASBLY_INFO) is shown in Figure 118 and described in Table 126 . This register is used by SERDES vendor to designate endpoints among the various function blocks of registers. Writes have no effect to this register. The values are hard coded and will no[...]

www.ti.com 5.56 Processing Element Features CAR (PE_FEAT) SRIO Registers The processing element features CAR (PE_FEAT) is shown in Figure 119 and described in Table 127 . Figure 119. Processing Element Features CAR (PE_FEAT) - Address Offset 1010h 31 30 29 28 27 24 BRIDGE MEMORY PROCESSOR SWITCH Reserved R-0 R-0 R-1 R-0 R-0h 23 16 Reserved R-00h 15[...]

www.ti.com SRIO Registers Table 127. Processing Element Features CAR (PE_FEAT) Field Descriptions (continued) Bit Field Value Description 2–0 EXTENDED_ADDRESSING_SUPPORT Indicates the number address bits supported by the PE both as a source and target of an operation. All PEs shall at minimum support 34 bit addresses. Encodings other than below a[...]

www.ti.com 5.57 Source Operations CAR (SRC_OP) SRIO Registers The source operations CAR (SRC_OP) is shown in Figure 120 and described in Table 128 . Figure 120. Source Operations CAR (SRC_OP) - Address Offset 1018h 31 24 Reserved R-0 23 18 17 16 Reserved IMPLMNT_DEFINED_2 R-0 R-00 15 14 13 12 11 10 9 8 STREAM_ WRITE_WITH_ ATOMIC_TEST_ READ WRITE DA[...]

www.ti.com 5.58 Destination Operations CAR (DEST_OP) SRIO Registers The destination operations CAR (DEST_OP) is shown in Figure 121 and described in Table 129 . Figure 121. Destination Operations CAR (DEST_OP) - Address Offset 101Ch 31 24 Reserved R-0 23 18 17 16 Reserved IMPLMNT_DEFINED_2 R-0 R-00 15 14 13 12 11 10 9 8 WRITE_WITH_ ATOMIC_TEST_ REA[...]

www.ti.com 5.59 Processing Element Logical Layer Control CSR (PE_LL_CTL) SRIO Registers The processing element logical layer control CSR (PE_LL_CTL) is shown in Figure 122 and described in Table 130 . Figure 122. Processing Element Logical Layer Control CSR (PE_LL_CTL) - Address Offset 104Ch 31 16 Reserved R-0 15 3 2 0 EXTENDED_ Reserved ADDRESSING[...]

www.ti.com 5.60 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) SRIO Registers The local configuration space base address 0 CSR (LCL_CFG_HBAR) is shown in Figure 123 and described in Table 131 . Figure 123. Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) - Address Offset 1058h 31 30 0 Reserved LCSBA R-0 R-00000000h LEGEND: R[...]

www.ti.com 5.61 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) SRIO Registers The local configuration space base address 1 CSR (LCL_CFG_BAR) is shown in Figure 124 and described in Table 132 . Figure 124. Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) - Address Offset 105Ch 31 0 LCSBA R-00000000h LEGEND: R = Read only; - n =[...]

www.ti.com 5.62 Base Device ID CSR (BASE_ID) SRIO Registers The base device ID CSR (BASE_ID) is shown in Figure 125 and described in Table 133 . Figure 125. Base Device ID CSR (BASE_ID) - Address Offset 1060h 31 24 23 16 Reserved BASE_DEVICEID R-00h R/W-FFh 15 0 LARGE_BASE_DEVICEID R/W-FFFFh LEGEND: R/W = Read/Write; R = Read only; - n = Value afte[...]

www.ti.com 5.63 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) SRIO Registers See Section 2.4.2 of the RapidIO Common Transport Specification for a description of this register. It provides a lock function that is write-once/reset-able. The host base device ID lock CSR (HOST_BASE_ID_LOCK) is shown in Figure 126 and described in Table 134 . Figure[...]

www.ti.com 5.64 Component Tag CSR (COMP_TAG) SRIO Registers The component Tag CSR (COMP_TAG) is shown in Figure 127 and described in Table 135 . Figure 127. Component Tag CSR (COMP_TAG) - Address Offset 106Ch 31 0 COMPONENT_TAG R/W-00000000h LEGEND: R/W = Read/Write; - n = Value after reset Table 135. Component Tag CSR (COMP_TAG) Field Descriptions[...]

www.ti.com 5.65 1x/4x LP Serial Port Maintenance Block Header Register (SP_MB_HEAD) SRIO Registers The 1x/4x LP_Serial port maintenance block header register (SP_MB_HEAD) is shown in Figure 128 and described in Table 136 . Figure 128. 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) - Address Offset 1100h 31 16 15 0 EF_PTR EF_ID [...]

www.ti.com 5.66 Port Link Time-Out Control CSR (SP_LT_CTL) SRIO Registers The port link time-out control CSR (SP_LT_CTL) is shown in Figure 129 and described in Table 137 . Figure 129. Port Link Time-Out Control CSR (SP_LT_CTL) - Address Offset 1120h 31 TIMEOUT_VALUE R/W-FFFFFFh 8 7 0 TIMEOUT_VALUE Reserved R/W-FFFFFFh R-00h LEGEND: R/W = Read/Writ[...]

www.ti.com 5.67 Port Response Time-Out Control CSR (SP_RT_CTL) SRIO Registers The port response time-out control CSR (SP_RT_CTL) is shown in Figure 130 and described in Table 138 For additional programming information, see Section 2.3.3.3 and Section 2.3.3 . Figure 130. Port Response Time-Out Control CSR (SP_RT_CTL) - Address Offset 1124h 31 TIMEOU[...]

www.ti.com 5.68 Port General Control CSR (SP_GEN_CTL) SRIO Registers The port general control CSR (SP_GEN_CTL) is shown in Figure 131 and described in Table 139 . Figure 131. Port General Control CSR (SP_GEN_CTL) - Address Offset 113Ch 31 30 29 28 0 MASTER_ HOST DISCOVERED Reserved ENABLE R/W-0 R/W-0 R/W-0 R-0 LEGEND: R/W = Read/Write; R = Read onl[...]

www.ti.com 5.69 Port Link Maintenance Request CSR n (SP n_LM_REQ) SRIO Registers Each of the four ports is supported by a register of this type (see Table 140 ). SP n _LM_REQ is shown in Figure 132 and described in Table 141 . Table 140. SPn_LM_REQ Registers and the Associated Ports Register Address Offset Associated Port SP0_LM_REQ 1140h Port 0 SP[...]

www.ti.com 5.70 Port Link Maintenance Response CSR n (SP n_LM_RESP) SRIO Registers Each of the four ports is supported by a register of this type (see Table 142 ). The port link maintenance response CSR n (SP n _LM_RESP) is shown in Figure 133 and described in Table 143 . Table 142. SPn_LM_RESP Registers and the Associated Ports Register Address Of[...]

www.ti.com 5.71 Port Local AckID Status CSR n (SP n_ACKID_STAT) SRIO Registers Each of the four ports is supported by a register of this type (see Table 144 ). The port local ackID status CSR n (SP n _ACKID_STAT) is shown in Figure 134 and described in Table 145 . Table 144. SP n _ACKID_STAT Registers and the Associated Ports Register Address Offse[...]

www.ti.com 5.72 Port Error and Status CSR n (SP n_ERR_STAT) SRIO Registers Each of the four ports is supported by a register of this type (see Table 146 ). The port error and status CSR n (SP n _ERR_STAT) is shown in Figure 135 and described in Table 147 . Table 146. SP n _ERR_STAT Registers and the Associated Ports Register Address Offset Associat[...]

www.ti.com SRIO Registers Table 147. Port Error and Status CSR n (SP n _ERR_STAT) Field Descriptions (continued) Bit Field Value Description 23–21 Reserved 0 These read-only bits return 0s when read. 20 OUTPUT_RETRY_ENC Output retry condition encountered. Once set, the OUTPUT_RETRY_ENC bit remains set until software writes a 1 to it. 0 The output[...]

www.ti.com SRIO Registers Table 147. Port Error and Status CSR n (SP n _ERR_STAT) Field Descriptions (continued) Bit Field Value Description 1 PORT_OK Port OK. This bit is a read-only bit. 0 Port not-OK condition 1 Port OK condition. The input and output ports are initialized, and the port is exchanging error-free control symbols with the attached [...]

www.ti.com 5.73 Port Control CSR n (SP n_CTL) SRIO Registers Each of the four ports is supported by a register of this type (see Table 148 ). The port control CSR n (SP n _CTL) is shown in Figure 136 and described in Table 149 . To change from 1 lane to 4 lanes there are 2 registers that need to be programmed. The SP_IP_MODE (offset 0x12004) bits 3[...]

www.ti.com SRIO Registers Table 149. Port Control CSR n (SP n _CTL) Field Descriptions (continued) Bit Field Value Description 26–24 PORT_WIDTH_OVERRIDE Port width override. This read-only field is available as a software means to override the hardware width. 000b No override 001b Reserved 010b Force single lane, lane 0 011b Force single lane, la[...]

www.ti.com SRIO Registers Table 149. Port Control CSR n (SP n _CTL) Field Descriptions (continued) Bit Field Value Description 0 PORT_TYPE 1 Port type. This read-only bit indicates that the port is a serial port rather than a parallel port. Serial RapidIO (SRIO) 208 SPRUE13A – September 2006 Submit Documentation Feedback[...]

www.ti.com 5.74 Error Reporting Block Header Register (ERR_RPT_BH) SRIO Registers The Error Reporting Block Header Register (ERR_RPT_BH) is shown in Figure 137 and described in Table 150 . Figure 137. Error Reporting Block Header Register (ERR_RPT_BH) - Address Offset 2000h 31 16 15 0 EF_PTR EF_ID R-0000h R-0007h LEGEND: R = Read only; - n = Value [...]

www.ti.com 5.75 Logical/Transport Layer Error Detect CSR (ERR_DET) SRIO Registers This register allows for the detection of logical/transport layer errors. The detectable errors are captured in the fields shown in Figure 138 and described in Table 151 . For additional programming information, see Section 3 . Figure 138. Logical/Transport Layer Erro[...]

www.ti.com SRIO Registers Table 151. Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions (continued) Bit Field Value Description 25 MSG_REQ_TIMEOUT Message request timeout (endpoint device only) 0 A timeout has not been detected by RXU. 1 A timeout has been detected by the RXU. A required message request has not been received by t[...]

www.ti.com 5.76 Logical/Transport Layer Error Enable CSR (ERR_EN) SRIO Registers The logical/transport layer error enable CSR (ERR_EN) is shown in Figure 139 and described in Table 152 . Figure 139. Logical/Transport Layer Error Enable CSR (ERR_EN) - Address Offset 200Ch 31 30 29 28 27 26 25 24 IO_ERR_ MSG_ERR_ Reserved ERR_MSG_ ILL_TRANS_ Reserved[...]

www.ti.com SRIO Registers Table 152. Logical/Transport Layer Error Enable CSR (ERR_EN) Field Descriptions (continued) Bit Field Value Description 24 PKT_RESP_TIMEOUT_ENABLE Packet response time-out error reporting enable 0 Disable reporting of a packet response time-out error. 1 Enable reporting of a packet response time-out error (endpoint device [...]

www.ti.com 5.77 Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) SRIO Registers The logical/transport layer high address capture CSR (H_ADDR_CAPT) is shown in Figure 140 and described in Table 153 . Figure 140. Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) - Address Offset 2010h 31 0 ADDRESS_63_32 R-00000000h LEGEND: [...]

www.ti.com 5.78 Logical/Transport Layer Address Capture CSR (ADDR_CAPT) SRIO Registers The logical/transport layer address capture CSR (ADDR_CAPT) is shown in Figure 141 and described in Table 154 . Figure 141. Logical/Transport Layer Address Capture CSR (ADDR_CAPT) - Address Offset 2014h 31 16 ADDRESS_31_3 R-0000h 15 3 2 1 0 ADDRESS_31_3 Reserved [...]

www.ti.com 5.79 Logical/Transport Layer Device ID Capture CSR (ID_CAPT) SRIO Registers The logical/transport layer device ID capture CSR (ID_CAPT) is shown in Figure 142 and described in Table 155 . Figure 142. Logical/Transport Layer Device ID Capture CSR (ID_CAPT) - Address Offset 2018h 31 24 23 16 MSB_DESTID DESTID R-00h R-00h 15 8 7 0 MSB_SOURC[...]

www.ti.com 5.80 Logical/Transport Layer Control Capture CSR (CTRL_CAPT) SRIO Registers The logical/transport layer control capture CSR (CTRL_CAPT) is shown in Figure 143 and described in Table 156 . Figure 143. Logical/Transport Layer Control Capture CSR (CTRL_CAPT) - Address Offset 201Ch 31 28 27 24 23 16 FTYPE TTYPE MSGINFO R-0h R-0h R-00h 15 0 I[...]

www.ti.com 5.81 Port-Write Target Device ID CSR (PW_TGT_ID) SRIO Registers The port-write target device ID CSR (PW_TGT_ID) is shown in Figure 144 and described in Table 157 . For additional programming information, see Section 2.3.5 . Figure 144. Port-Write Target Device ID CSR (PW_TGT_ID) - Address Offset 2028h 31 24 23 16 DEVICEID_MSB DEVICEID R/[...]

www.ti.com 5.82 Port Error Detect CSR n (SP n_ERR_DET) SRIO Registers Each of the four ports is supported by a register of this type (see Table 158 ). The port error detect CSR n (SP n _ERR_DET) is shown in Figure 145 and described in Table 159 . Table 158. SP n _ERR_DET Registers and the Associated Ports Register Address Offset Associated Port SP0[...]

www.ti.com SRIO Registers Table 159. Port Error Detect CSR n (SP n _ERR_DET) Field Descriptions (continued) Bit Field Value Description 20 RCVD_PKT_NOT_ACCPT Packet-not-accepted control symbol 0 The port did not receive a packet-not-accepted acknowledge control symbol. 1 The port received a packet-not-accepted acknowledge control symbol. 19 PKT_UNE[...]

www.ti.com 5.83 Port Error Rate Enable CSR n (SP n_RATE_EN) SRIO Registers Each of the four ports is supported by a register of this type (see Table 160 ). The port error rate enable CSR n (SP n _RATE_EN) is shown in Figure 146 and described in Table 161 . Table 160. SP n _RATE_EN Registers and the Associated Ports Register Address Offset Associate[...]

www.ti.com SRIO Registers Table 161. Port Error Rate Enable CSR n (SP n _RATE_EN) Field Descriptions (continued) Bit Field Value Description 19 PKT_UNEXPECTED_ACKID_EN Rate counting enable for packets with unexpected ackIDs 0 Disable error rate counting of packets with unexpected/out-of-sequence ackIDs 1 Enable error rate counting of packets with u[...]

www.ti.com 5.84 Port n Attributes Error Capture CSR 0 (SP n_ERR_ATTR_CAPT_DBG0) SRIO Registers Each of the four ports is supported by a register of this type (see ). The port n attributes error capture CSR 0 (SP n _ERR_ATTR_CAPT_DBG0) is shown in Figure 147 and described in Table 163 . Table 162. SP n _ERR_ATTR_CAPT_DBG0 Registers and the Associate[...]

www.ti.com 5.85 Port n Error Capture CSR 1 (SP n_ERR_CAPT_DBG1) SRIO Registers Each of the four ports is supported by a register of this type (see Table 164 ). SP n _ERR_CAPT_DBG1 is shown in Figure 148 and described in Table 165 . Table 164. SP n _ERR_CAPT_DBG1 Registers and the Associated Ports Register Address Offset Associated Port SP0_ERR_CAPT[...]

www.ti.com 5.86 Port n Error Capture CSR 2 (SP n_ERR_CAPT_DBG2) SRIO Registers Each of the four ports is supported by a register of this type (see Table 166 ). SP n _ERR_CAPT_DBG2 is shown in Figure 149 and described in Table 167 . Table 166. SP n _ERR_CAPT_DBG2 Registers and the Associated Ports Register Address Offset Associated Port SP0_ERR_CAPT[...]

www.ti.com 5.87 Port n Error Capture CSR 3 (SP n_ERR_CAPT_DBG3) SRIO Registers Each of the four ports is supported by a register of this type (see Table 168 ). SP n _ERR_CAPT_DBG3 is shown in Figure 150 and described in Table 169 . Table 168. SP n _ERR_CAPT_DBG3 Registers and the Associated Ports Register Address Offset Associated Port SP0_ERR_CAPT[...]

www.ti.com 5.88 Port n Error Capture CSR 4 (SP n_ERR_CAPT_DBG4) SRIO Registers Each of the four ports is supported by a register of this type (see Table 170 ). The port n packet/control symbol error capture CSR 4 (SP n _ERR_CAPT_DBG4) is shown in Figure 151 and described in Table 171 . Table 170. SP n _ERR_CAPT_DBG4 Registers and the Associated Por[...]

www.ti.com 5.89 Port Error Rate CSR n (SP n_ERR_RATE) SRIO Registers Each of the four ports is supported by a register of this type (see Table 172 ). SP n _ERR_RATE is shown in Figure 152 and described in Table 173 . Table 172. SP n _ERR_RATE Registers and the Associated Ports Register Address Offset Associated Port SP0_ERR_RATE 2068h Port 0 SP1_ER[...]

www.ti.com 5.90 Port Error Rate Threshold CSR n (SP n_ERR_THRESH) SRIO Registers Each of the four ports is supported by a register of this type (see ). The port error rate threshold CSR n (SP n _ERR_THRESH) is shown in Figure 153 and described in Table 175 . Table 174. SP n _ERR_THRESH Registers and the Associated Ports Register Address Offset Asso[...]

www.ti.com 5.91 Port IP Discovery Timer for 4x Mode Register (SP_IP_DISCOVERY_TIMER) SRIO Registers The port IP discovery timer for 4x mode register (SP_IP_DISCOVERY_TIMER) is shown in Figure 154 and described in Table 176 . Figure 154. Port IP Discovery Timer for 4x Mode Register (SP_IP_DISCOVERY_TIMER) - Address Offset 12000h 31 28 27 24 23 20 19[...]

www.ti.com 5.92 Port IP Mode CSR (SP_IP_MODE) SRIO Registers The port IP mode CSR (SP_IP_MODE) is shown in Figure 155 and described in Table 177 . For additional programming information, see Section 2.3.13.2 . Figure 155. Port IP Mode CSR (SP_IP_MODE) - Address Offset 12004h 31 30 29 28 27 26 25 24 16 IDLE_ TX_ PW_ TGT_ SELF_ SP_MODE ERR_ FIFO_ Res[...]

www.ti.com SRIO Registers Table 177. Port IP Mode CSR (SP_IP_MODE) Field Descriptions (continued) Bit Field Value Description 3 RST_EN Reset Interrupt Enable. If enabled, the interrupt signal is High when the 4 reset control symbols are received in a sequence 0 Reset interrupt disable 1 Reset interrupt enable 2 RST_CS Reset received status bit. It [...]

www.ti.com 5.93 Port IP Prescaler Register (IP_PRESCAL) SRIO Registers The port IP prescaler register (IP_PRESCAL) is shown in Figure 156 and described in Table 178 . This register defines a prescaler for different frequencies of the DMA clock. The purpose of this register is to keep the timers of SP_LT_CTL (offset 01120h), SP0_ERR_RATE through SP3[...]

www.ti.com 5.94 Port-Write-In Capture CSRs (SP_IP_PW_IN_CAPT[0–3]) SRIO Registers Four registers are used to capture the incoming 128-bit payload of a Port-Write. These four registers are shown in Figure 157 . As can be seen in Table 179 , each of the registers captures one of the four 32-bit words of the payload. Figure 157. Port-Write-In Captur[...]

www.ti.com 5.95 Port Reset Option CSR n (SP n_RST_OPT) SRIO Registers Each of the four ports is supported by a register of this type (see Table 180 ). SP n _RST_OPT is shown in Figure 158 and described in Table 181 . Table 180. SP n _RST_OPT Registers and the Associated Ports Register Address Offset Associated Port SP0_RST_OPT 14000h Port 0 SP1_RST[...]

www.ti.com 5.96 Port Control Independent Register n (SP n_CTL_INDEP) SRIO Registers Each of the four ports is supported by a register of this type (see Table 182 ). The port control independent register n (SP n _CTL_INDEP) is shown in Figure 159 and described in Table 183 . Table 182. SP n _CTL_INDEP Registers and the Associated Ports Register Addr[...]

www.ti.com SRIO Registers Table 183. Port Control Independent Register n (SP n _CTL_INDEP) Field Descriptions (continued) Bit Field Value Description 23 DEBUG Mode of operation. 0 Normal mode 1 Debug mode. The debug mode unlocks capture registers for write and enable debug packet generator feature. 22 SEND_DBG_PKT Send debug packet. Write 1 to forc[...]

www.ti.com 5.97 Port Silence Timer n Register (SP n_SILENCE_TIMER) SRIO Registers Each of the four ports is supported by a register of this type (see Table 184 ). The port silence timer n register (SP n _SILENCE_TIMER) is shown in Figure 160 and described in Table 185 . Table 184. SP n _SILENCE_TIMER Registers and the Associated Ports Register Addr[...]

www.ti.com 5.98 Port Multicast-Event Control Symbol Request Register n (SP n_MULT_EVNT_CS) SRIO Registers Each of the four ports is supported by a register of this type (see Table 186 ). The port multicast-event control symbol request register n (SP n _MULT_EVNT_CS) is shown in Figure 161 and described in Table 187 . Table 186. SP n _MULT_EVNT_CS R[...]

www.ti.com 5.99 Port Control Symbol Transmit n Register (SP n_CS_TX) SRIO Registers Each of the four ports is supported by a register of this type (see Table 188 ). The port control symbol transmit n register (SP n _CS_TX) is shown in Figure 162 and described in Table 189 . Table 188. SP n _CS_TX Registers and the Associated Ports Register Address [...]

Index SPRUE13A – September 2006 Index 1x/4x LP serial port maintenance block header register next expected ackID field 202 196 output port next transmitted ackID field 202 1x/4x mode selection field for ports 231 output port unacknowledged ackID status field 202 1X_MODE field of PER_SET_SNTL 113 unexpected ackID in control symbol at port n 2 MSBs[...]

SRIO Registers BYTE_COUNT field of LSUn_REG3 158 B bad CRC in control symbol at port n C rate counting enable field 221 CAPTURE0 field of SPn_ERR_CAPT_DBG1 224 status field 219 CAPTURE1 field of SPn_ERR_CAPT_DBG2 225 bad CRC in packet at port n CAPTURE2 field of SPn_ERR_CAPT_DBG3 226 rate counting enable field 222 CAPTURE3 field of SPn_ERR_CAPT_DBG[...]

SRIO Registers at port n requesting interrupt with INTERRUPT_REQ field 159 CRC errors rate counting enable field 222 bad CRC in control symbol at port n status field 220 rate counting enable field 221 bad CRC in control symbol at port n status field 219 rate counting enable field 221 bad CRC in packet at port n status field 219 rate counting enable[...]

SRIO Registers DEV_INFO 183 doorbell interrupt condition status registers 132 DEVICE_VENDORIDENTITY field of DEV_ID 182 DOORBELLn_ICCR 133 DEVICEID_MSB field of PW_TGT_ID 218 DOORBELLn_ICRR 144 DEVICEID_REG1 121 DOORBELLn_ICRR2 144 DEVICEID_REG2 122 DOORBELLn_ICSR 132 device ID capture CSR for logical/transport errors 216 doorbell operation 63 devi[...]

SRIO Registers ENPLL2 field of PER_SET_CNTL 113 register 142 ENPLL3 field of PER_SET_CNTL 113 ERROR response ENPLL4 field of PER_SET_CNTL 113 during direct I/O reception 42 during message passing 43 ENPLL field of SERDES_CFGn_CNTL 130 error status interrupt to the CPU 85 ENRX field of SERDES_CFGRXn_CNTL 125 error type field for port n error capture[...]

SRIO Registers interrupt condition clearing 86 G interrupt condition clear registers GBL_EN 116 for CPPI interrupt conditions 135 , 137 GBL_EN_STAT 117 for doorbell interrupt conditions 133 global enable bit 116 for error, reset, and special event (port) interrupt global enable status bit 118 conditions 143 global enabling/disabling of all logical [...]

SRIO Registers limiting which devices can access a mailbox 45 LSU_ICSR 138 line rate versus PLL output clock frequency 29 LSU congestion control flow mask register 162 LINK_STATUS field of SPn_LM_RESP 201 LSU control register 0 155 LINK_TIMEOUT_EN field of SPn_RATE_EN 221 LSU control register 1 156 LINK_TIMEOUT field of SPn_ERR_DET 219 LSU control [...]

SRIO Registers MAX_RETRY_ERR field of SPn_CTL_INDEP 236 MMRs enable bit 119 MAX_RETRY_THR field of SPn_CTL_INDEP 236 MMRs enable status bits 118 , 120 maximum packet size exceeded at port n mode selection field for ports 231 MPY field of SERDES_CFGn_CNTL 130 rate counting enable field 222 status field 220 MPY value versus frequency range 30 maximum[...]

SRIO Registers OUTBOUND_ACKID field of SPn_ACKID_STAT 202 packet response timeout at LSU or TXU outbound credit 75 reporting enable field 213 status field 211 outbound port number for packet forwarding 124 packets out-of-order reception of message packets 49 bad CRC in packet at port n out-of-order responses during message-passing TX operation 58 r[...]

SRIO Registers in SRIO component block diagram 26 port multicast-event control symbol request registers 239 PID register 111 port n error capture pins/differential signals 25 control information field 224 PKT_RESP_TIMEOUT_ENABLE field of ERR_EN 212 packet header bytes 0 to 3 field 224 PKT_RSPNS_TIMEOUT field of ERR_DET 210 packet header bytes 4 to [...]

SRIO Registers PW_DIS field of SP_IP_MODE 231 read support for destination device 189 PW_EN field of SP_IP_MODE 231 read support for source device 188 PW_IRQ field of SP_IP_MODE 231 READ transactions during direct I/O transmission 41 PW_TGT_ID 218 receive CPPI control register 173 PW_TIMER field of SP_IP_DISCOVERY_TIMER 230 receive CPPI interrupt c[...]

SRIO Registers SERDES macros for doorbell interrupt conditions 144 for error, reset, and special event (port) interrupt configuration example 35 conditions 149 description 28 for LSU interrupt conditions 147 enable bits 115 RST_CS field of SP_IP_MODE 231 in SRIO component block diagram 26 RST_EN field of SP_IP_MODE 231 in SRIO peripheral block diag[...]

SRIO Registers SPn_ERR_CAPT_DBG1 224 SWING field of SERDES_CFGTXn_CNTL 128 SPn_ERR_CAPT_DBG2 225 switch capability field 186 SPn_ERR_CAPT_DBG3 226 SWITCH field of PE_FEAT 186 SPn_ERR_CAPT_DBG4 227 SWRITE packet Ftype and Ttype 25 SPn_ERR_DET 219 symbol alignment field 126 SPn_ERR_RATE 228 T SPn_ERR_STAT 203 target IDs. See destination IDs 218 SPn_E[...]

SRIO Registers transmitter enabling for SERDES macro status field 219 unexpected ackID in packet at port n introduction 33 transmitter enable bit 129 rate counting enable field 222 transport error handling and logging 83 status field 220 transport layer unexpected acknowledge control symbol at port n content in SRIO data stream 22 rate counting ena[...]

SRIO Registers Xoff 65 Xon 65 SPRUE13A – September 2006 Index 255 Submit Documentation Feedback[...]

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