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Cypress Semiconductor CY7C1338G manual

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Table of contents for the manual

  • Page 1

    4-Mbit (128K x 32) Flow-Through Sync SRAM CY7C1338G Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05521 Rev . *D Revised July 5, 2006 Features • 128K x 32 common I/O • 3.3V core power supply (V DD ) • 2.5V or 3.3V I/O supply (V DDQ ) • Fast clock-to-output times —[...]

  • Page 2

    CY7C1338G Document #: 38-05521 Rev . *D Page 2 of 17 Selection Guide 133 MHz 100 MHz Unit Maximum Access T i me 6.5 8.0 ns Maximum Operating Current 225 205 mA Maximum S tandby Cu rrent 40 40 mA Pin Configurations 100-Pin TQFP Pinout A A A A A 1 A 0 NC/72M NC/36M V SS V DD NC/9M A A A A A A NC DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B D[...]

  • Page 3

    CY7C1338G Document #: 38-05521 Rev . *D Page 3 of 17 Pin Definitions Name I/O Description A0, A1, A Input- Synchronous Address Inputs used to select one of th e 128K address location s. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW , and CE 1 , CE 2 , and CE 3 are sampled active. A [1:0] feed the 2-bit counter . BW A , BW B BW[...]

  • Page 4

    CY7C1338G Document #: 38-05521 Rev . *D Page 4 of 17 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge o f the clock. Maximum access delay from the clock rise (t C0 ) is 6.5 ns (133-M Hz d evi ce ). The CY7C1338G supports secondary cache in syste ms utilizing either a linear or interleaved burst s[...]

  • Page 5

    CY7C1338G Document #: 38-05521 Rev . *D Page 5 of 17 Single Write Accesses Initiated by ADSP This access is initiated when the following cond itions are satisfied at clock rise: (1) CE 1 , CE 2 , CE 3 are all asserted active, and (2) ADSP is asserted LOW . T he addresses presented are loaded into the address register and the burst inputs (GW , BWE [...]

  • Page 6

    CY7C1338G Document #: 38-05521 Rev . *D Page 6 of 17 T ruth T able [2, 3, 4, 5, 6] Cycle Desc ri ption Address Used CE 1 CE 2 CE 3 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselected Cycle, Power-down None H X X L X L X X X L-H T ri-S tate Deselected Cycle, Power-down None L L X L L X X X X L-H T ri-S tate Deselected Cycle, Power-down None L X H L L X X X [...]

  • Page 7

    CY7C1338G Document #: 38-05521 Rev . *D Page 7 of 17 Partial T ruth T able for Read/W rite [2, 7] Function GW BWE BW D BW C BW B BW A R e a d H HXXXX R e a d H L HHHH W r i t e B y t e A H L HHH L Wri t e B y t e B H L H H L H Write Bytes B, A H L H H L L W r i t e B y t e C HLHLH H Write Bytes C, A H L H L H L Write Bytes C, B H L H L L H Write By[...]

  • Page 8

    CY7C1338G Document #: 38-05521 Rev . *D Page 8 of 17 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. .............. ...... –65°C to + 150°C Ambient T e mperature with Power Applied ........... ............................ ...... –55 °C to +125°C Supply V o[...]

  • Page 9

    CY7C1338G Document #: 38-05521 Rev . *D Page 9 of 17 Cap acit ance [10] Parameter Description T est C onditions 100 TQFP Max. 1 19 BGA Max. Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V DD = 3.3V . V DDQ = 3.3V 55 p F C CLK Clock Input Capacit ance 5 5 pF C I/O Input/Output Capacitance 5 7 pF Thermal Resist ance [10] Parameter Des cription [...]

  • Page 10

    CY7C1338G Document #: 38-05521 Rev . *D Page 10 of 17 Switching Characteristics Over the Operating Range [1 1, 12, 13, 14, 15, 16] Parameter Description –133 –100 Unit Min. Max . Mi n. Max. t POWER V DD (T ypical) to the first Access [1 1] 11 m s Clock t CYC Clock Cycle T ime 7.5 10 ns t CH Clock HIGH 2.5 4.0 ns t CL Clock LOW 2.5 4.0 ns Output[...]

  • Page 11

    CY7C1338G Document #: 38-05521 Rev . *D Page 1 1 of 17 Timing Diagrams Read Cycle Timing [17] Note: 17. On this diagram, when CE is LOW : CE 1 is LOW , CE 2 is HIGH and CE 3 is LOW . When CE is HIGH: CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A1 t CEH t CES Data Out (Q) High-Z t CLZ t DOH t CDV t [...]

  • Page 12

    CY7C1338G Document #: 38-05521 Rev . *D Page 12 of 17 Write Cycle T iming [17, 18] Note: 18. Full width write can be initiated by either GW LO W ; or by GW HIGH, BWE LOW and BW [A:D] LOW . Timing Diagrams (continued) t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A1 t CEH t CES High-Z BURST READ BURST WRITE D(A2) D(A2 + 1) D(A2 + 1) D(A1) D(A3) [...]

  • Page 13

    CY7C1338G Document #: 38-05521 Rev . *D Page 13 of 17 Read/Write T iming [17, 19, 20] Notes: 19. The data bus (Q) remains in hig h-Z following a WRIT E cycle, unl ess a new read access is initiated by ADSP or ADSC . 20. GW is HIGH. Timing Diagrams (continued) t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A2 t CEH t CES Single WRITE D(A3) A3 A4 [...]

  • Page 14

    CY7C1338G Document #: 38-05521 Rev . *D Page 14 of 17 ZZ Mode T iming [21, 22] Notes: 21. Device must be deselected when entering ZZ mode. See Cycle Descr iptions table for all possible signal conditions to deselect the device. 22. DQs are in high-Z whe n exiting ZZ sleep mode. Timing Diagrams (continued) t ZZ I SUPPLY CLK ZZ t ZZREC A LL INPUTS (e[...]

  • Page 15

    CY7C1338G Document #: 38-05521 Rev . *D Page 15 of 17 Ordering Information Not all of the speed, package and temperature ranges are av ailable. Please contact your local sales representative or visit www .cyp ress.com for a ctual produc ts offered. Speed (MHz) Ordering Code Package Diagram Part and Package T ype Operating Range 133 CY7C1338G-133AXC[...]

  • Page 16

    CY7C1338G Document #: 38-05521 Rev . *D Page 16 of 17 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress prod uct. Nor do[...]

  • Page 17

    CY7C1338G Document #: 38-05521 Rev . *D Page 17 of 17 Document History Page Document Title: CY7C1338G 4-Mbit (128K x 32) Flow-Through Sync SRAM Document Number: 38 -05521 REV . ECN NO. I ssue Date Orig. of Change Descripti on of Change ** 224369 See ECN RKF New data sheet *A 278513 See ECN VBL Del eted 66 MHz Changed TQFP to PB-Free TQFP in Orderin[...]