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Cypress Semiconductor CY7C1522AV18 manual

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  • Page 1

    72-Mbit DDR-II SIO SRAM 2-W ord Burst Architecture CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 001-06981 Rev . *D Revised June 14, 2 008 Features ■ 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36) ■ 300 MHz clock f[...]

  • Page 2

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 2 of 30 Logic Block Diagram (CY7C1522A V18) Logic Block Diagram (CY7C1529A V18) 4M x 8 Array CLK A (21:0) Gen. K K Control Logic Address Register D [7:0] Read Add. Decode Read Data Reg. LD Q [7:0] Reg. Reg. Reg. 8 16 8 NWS [1:0] V REF Write Add. Decode Wri[...]

  • Page 3

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 3 of 30 Logic Block Diagram (CY7C1523A V18) Logic Block Diagram (CY7C1524A V18) 2M x 18 Array CLK A (20:0) Gen. K K Control Logic Address Register D [17:0] Read Add. Decode Read Data Reg. LD Q [17:0] Reg. Reg. Reg. 18 36 18 BWS [1:0] V REF Write Add. Decod[...]

  • Page 4

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 4 of 30 Pin Configuration The pin configuration for CY7C1522A V18, CY7C1529 A V18, CY7C1523A V18, and CY7C1 524A V18 follow . [1] 165-Ball FBGA (15 x 17 x 1 .4 mm) Pinout CY7C1522A V18 (8M x 8) 123456789 10 11 A CQ AA R / W NWS 1 K NC/144M LD AA C Q B NC N[...]

  • Page 5

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 5 of 30 CY7C1523A V18 (4M x 18) 123456789 10 11 A CQ NC/144M A R/W BWS 1 K NC/28 8M LD AA C Q B NC Q9 D9 A NC K BWS 0 AN C N C Q 8 C NC NC D10 V SS AAA V SS NC Q7 D8 D NC D1 1 Q 10 V SS V SS V SS V SS V SS NC NC D7 E NC NC Q1 1 V DDQ V SS V SS V SS V DD Q [...]

  • Page 6

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 6 of 30 Pin Definitions Pin Name IO Pin Description D [x:0] Input- Synchronous Data Input Signals. Sampled on the rising edge of K and K clocks during val id write opera tions. CY7C1522A V18 - D [7:0] CY7C1529A V18 - D [8:0] CY7C1523A V18 - D [17:0] CY7C15[...]

  • Page 7

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 7 of 30 CQ Echo Clock CQ Referenced with Respect to C . This is a free-running clock and is synchronized to the input clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timi ngs for the echo clocks is [...]

  • Page 8

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 8 of 30 Functional Overview The CY7C1522A V18, CY7C1529A V18, CY7C1523A V18, and CY7C1524A V18 are synchronous pipelined Burst SRAMs equipped with a DDR-II Separate IO interface, which operates with a read latency of one and half cycles when DOFF pin is ti[...]

  • Page 9

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 9 of 30 synchronized to the output clock of the DDR-II. In the single clock mode, CQ is generated with respect to K and CQ is g enerated with respect to K . The timing for the echo clocks is shown in Switching Characteristics on page 23. DLL These chips us[...]

  • Page 10

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 10 of 30 T ruth T able The truth table for CY7C1522A V18, CY7C1529A V18 , CY7C1523A V18, and CY7C1524A V18 follows. [2, 3, 4, 5, 6, 7] Operation K LD R/W DQ DQ Write Cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges.[...]

  • Page 11

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 1 1 of 30 Write Cycle Descriptions The write cycle description tabl e for CY7C1529A V18 follows. [2, 8] BWS 0 K K Comments L L–H – During the Data portion of a write sequence, the single byte (D [8:0] ) is writ te n in to the device. L – L–H During[...]

  • Page 12

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 12 of 30 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA p ackage. This part is fully comp liant with IEEE S tandard #1 149.1-2001. The T AP operates using JEDEC standard 1.8V IO[...]

  • Page 13

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 13 of 30 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister . It also place s the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the T AP controller enters the [...]

  • Page 14

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 14 of 30 T AP Controller St ate Diagram The state diagram for the T AP controller follows. [9] TEST -LOGIC RESET TEST -LOGIC/ IDLE SELECT DR-SCAN CAPTURE-DR SHIFT -DR EXIT1-DR P AUSE-DR EXIT2-DR UPDA TE-DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 [...]

  • Page 15

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 15 of 30 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [10, 1 1, 12] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V oltage I OH = − 2.0 mA 1.4 V V OH2 Output HIGH V oltage I OH = − 100 ?[...]

  • Page 16

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 16 of 30 T AP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Max Unit t TCYC TCK Clock Cycle Time 50 ns t TF TCK Clock Frequency 20 MHz t TH TCK Clock HIGH 20 ns t TL TCK Clock LOW 20 ns Setup Times t TMSS TMS Setu[...]

  • Page 17

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 17 of 30 Identification R egi ster Definitions Instruction Field Va l u e De scription CY7C1522A V18 CY7C1529A V18 CY7C1523A V18 CY7C1524A V18 Revision Numb er (31:29) 000 000 000 000 V ersion number . Cypress Device ID (28:12) 1 10 10100010000100 1 101010[...]

  • Page 18

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 18 of 30 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bum p ID 0 6R 28 10G 56 6A 84 1J 1 6 P2 9 9 G 5 7 5 B8 5 2 J 2 6N 30 1 1F 58 5A 86 3K 3 7P 31 1 1G 59 4A 87 3J 4 7 N3 2 9 F 6 0 5 C8 8 2 K 5 7R 33 10F 61 4B 89 1K 6 8R 34 1 1E 62 [...]

  • Page 19

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 19 of 30 Power Up Sequence in DDR-II SRAM DDR-II SRAMs must be power ed up and initialized in a predefined manner to prevent unde fined operation s. Power Up Sequence ■ Apply power and drive DO FF either HIGH or LOW (All other inputs can be HIGH or LOW).[...]

  • Page 20

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 20 of 30 Maximum Ratings Exceeding maximum ratin gs may impair the useful life of the device. These user guidelines are not teste d. S torage T emperature ............. ................. ... –65°C to +150°C Ambient T empe r at ur e with Power Applied..[...]

  • Page 21

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 21 of 30 I DD [19] V DD Operating Supply V DD = Max, I OUT = 0 mA, f = f MAX = 1/t CYC 200MHz (x8) 700 mA (x9) 700 (x18) 700 (x36) 750 167MHz (x8) 650 mA (x9) 650 (x18) 650 (x36) 650 I SB1 Automatic Power down Current Max V DD , Both Ports Deselected, V IN[...]

  • Page 22

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 22 of 30 Cap acit ance T ested initially and after any design or process change that may affect these parameters. Parameter Description T est Condit ions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.8V , V DDQ = 1.5V 5.5 pF C CLK Cloc[...]

  • Page 23

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 23 of 30 Switching Characteristics Over the Operating Range [20, 21] Cypress Parameter Consor tium Parameter Description 300 MHz 278 MHz 250 MHz 20 0 MHz 167 MHz Unit Min Max Min Max Min Max Min Max Min Max t POWER V DD (T ypical) to the First Access [22] [...]

  • Page 24

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 24 of 30 Output T imes t CO t CHQV C/C Clock Rise (or K/K in single clock mode) to Data V alid – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns t DOH t CHQX Data Output Hold af ter Output C/C Clock Rise (Active to Active) –0.45 – – 0.45 – –0.45 ?[...]

  • Page 25

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 25 of 30 Switching W aveforms Figure 5. Read/Write/Deselect Sequence [2 7, 28, 29 ] K 123 4 5 6 7 8 K LD R/W A Q D C C# READ (burst of 2) READ (burst of 2) READ (burst of 2) WRITE (burst of 2) WRITE (burst of 2) t KHCH t KHCH NOP NOP CQ CQ# t KH t KHKH t C[...]

  • Page 26

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 26 of 30 Ordering Information Not all of the speed, package and temperature range s are ava ilable. Please contact your local sales representative or visit www .cypress.com for actual products offered. Spee d (MHz) Ordering Code Package Diagram Package T y[...]

  • Page 27

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 27 of 30 250 CY7C1522A V18-250BZC 5 1-85195 165-Ball Fine Pi tch Ball Grid Array (15 x 17 x 1.4 mm) Commercial CY7C1529A V18-250BZC CY7C1523A V18-250BZC CY7C1524A V18-250BZC CY7C1522A V18-250BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 [...]

  • Page 28

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 28 of 30 167 CY7C1522A V18-167BZC 5 1-85195 165-Ball Fine Pi tch Ball Grid Array (15 x 17 x 1.4 mm) Commercial CY7C1529A V18-167BZC CY7C1523A V18-167BZC CY7C1524A V18-167BZC CY7C1522A V18-167BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 [...]

  • Page 29

    CY7C1522A V18, CY7C1529A V18 CY7C1523A V18, CY7C1524A V18 Document #: 001-06981 Rev . *D Page 29 of 30 Package Diagram Figure 6. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85195 !  0).#/2.%2 ¼ ¼   ?[...]

  • Page 30

    Document #: 001-06981 Rev . *D Revised June 14, 2008 Page 30 of 30 QDR RAMs an d Quad Data Rate RAMs comp rise a new family of product s developed by Cypress, I DT , NEC, R enesas, and Sa msung. All pr oduct and comp any names mentioned i n this documen t are the tr ad emarks of their resp ectiv e ho lders. CY7C1522A V18, CY7C1529A V18 CY7C1523A V1[...]