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Marvell Integrated Controller 88F6281 manual

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Table of contents for the manual

  • Page 1

    Marvell. Moving Forward Faster Doc. No. MV -S104859-U0, Rev . E December 2, 2008, Preliminary Document Classification: Proprietary Information Cover 88F6281 Integrated Controller Hardware Specifications[...]

  • Page 2

    Document Conventions Note: Provides related infor mation or information of special impor tance. Caution: Indicates potential damage to hardwar e or software, or loss of data. Wa r n i n g : Indicates a risk of personal injury . Document St atus Doc S tatus: Preliminary T e chnical Publication: 0.xx For more information, visit our website at: www.ma[...]

  • Page 3

    88F6281 Integrated Controller Hardware Specifications Copyright © 2008 Marvell Doc. No. MV -S104859-U0 Rev . E December 2, 2008, Preliminary Document Classification: Prop rietary Information Page 3 PRODUCT OVERVIEW The Marve ll ® 88F6281 is a high-performance, highly integrated controlle r . The 88F6 281 is based on the Marvell proprietary , ARMv[...]

  • Page 4

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 4 Document Classification: Proprietary Information December 2, 2008, Preliminary FEATURES  The 88F6281 includes: • High-performance CPU core, running at up to 1.5 GHz, with integrated, f our-way , se t-associative L1 16-KB I-cache/16-KB D-cache and [...]

  • Page 5

    Features Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 5 • Priority queuing on receive based on Destination Address (DA), VLAN T ag, and IP T OS • Layer 2/3/4 frame encapsulation detection • TCP/IP checksum on rece ive and transmit • Supports pr[...]

  • Page 6

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 6 Document Classification: Proprietary Information December 2, 2008, Preliminary  I 2 S-specific features • Sample rates of 44.1/48/96 kHz • I 2 S input and I 2 S output operate at the same sample rate • 16/24-bit depths • I 2 S in and I 2 S o[...]

  • Page 7

    Features Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 7 x16 x8 TDM Usage Mod el Exam p le: VoIP Gateway PCI Expre ss Mini Ca rd W i-Fi SD Card USB Host SATA Port Multip lier HDD Audio A/D – D/A GbE PHY FXS FXO NAND Flash SPI Flash (op.) On Board DDR2[...]

  • Page 8

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 8 Document Classification: Proprietary Information December 2, 2008, Preliminary T able of Content s Product Overview .............. ............. ................ ............. ................ ............. ................ .......... .................[...]

  • Page 9

    T able of Content s Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 9 8 Electrical Specifications (Pre liminary) ..... ................. ............. ................ ............. ................ ...... 7 5 8.1 Absolute Maximum Ratings ......... ......[...]

  • Page 10

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 10 Document Classification: Proprietary Information December 2, 20 08, Prelimin ary List of T a bles 1 Pin and Signal Descriptions ........... ................ ............. ................. ............ ................. ............ . ......... 17 Tab[...]

  • Page 11

    List of T ables Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 1 1 7 JTAG Interface .............. ............. ................ ............. ................ ............. ................ ........... ............... ... 73 Table 33: Supported JTAG In[...]

  • Page 12

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 12 Document Classification: Proprietary Information December 2, 20 08, Prelimin ary 10 Package ............... ............. ................ ............. ................ ............. ................ ............. ... ..................... 130 Table [...]

  • Page 13

    List of Figures Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 13 List of Figures 1 Pin and Signal Descriptions ........... ................ ............. ................. ............ ................. ............ . ........ 17 Figure 1: 88F6281 Pin L[...]

  • Page 14

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 14 Document Classification: Proprietary Information December 2, 20 08, Prelimin ary Figure 28: Inter-IC Sound (I2S) T est Circuit ............ ...................... ....................... ................... ........ . ...............107 Figure 29: Int[...]

  • Page 15

    Preface About this Document Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 15 Preface About this Document This datasheet provides th e hardware specificat ions for the 88F6281 integrated con troller . The hardware specifications include detailed pin in f[...]

  • Page 16

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 16 Document Classification: Proprietary Information December 2, 20 08, Prelimin ary  RFC 1321 (The MD5 Message-Digest Algorithm)  RFC 1851 – The ESP T riple DES T ransform  RFC 2104 (HMAC: Keyed-Hashing for Message Authentication).  RFC 240[...]

  • Page 17

    Pin and Signal Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 17 1 Pin and Signal Descriptions This section provides the pin logic d iagram for th e 88F6281 de vice and a detailed description of th e pin assignments and thei r functionality [...]

  • Page 18

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 18 Document Classification: Proprietary Information December 2, 20 08, Prelimin ary 1.1 Pin Logic Figure 1: 88F6281 Pin Logic Diagram NOTE: The GE_TXCLKOUT pin is an input only when used as the MII/MMII T ransmit Clock. For details about MPP configuratio[...]

  • Page 19

    Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 19 1.2 Pin Descriptions This section details all the pins for the different interfaces prov idin g a functional description of each pin and pi n at tributes. T ab[...]

  • Page 20

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 20 Document Classification: Proprietary Information December 2, 2008, Preliminary RTC RT C_ NAND Flash NF_ MPP N/A TWSI TW_ UART UA0_ UA1_ Audio AU_ SPI SPI_ SDIO SD_ TDM TDM_ PTP PTP_ T able 2: Interface Pin Prefix Codes (C ontinued) Interface Prefix[...]

  • Page 21

    Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 21 1.2.1 Power Supply Pins T able 3 p rovides the voltage levels for the various interface pin s. These do not include the analog power supplies for the PLLs or P[...]

  • Page 22

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 22 Document Classification: Proprietary Information December 2, 2008, Preliminary PEX_A V DD I Power PCI Express PHY quiet power su pply 1.8V NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Des ign Guide for power supply filteri ng recommendations. [...]

  • Page 23

    Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 23 1.2.2 Miscellaneous Pin Assignment The Miscellaneou s signal list contains clock and reset, test, and relate d signals. T able 4: Miscellaneous Pin Assignment [...]

  • Page 24

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 24 Document Classification: Proprietary Information December 2, 2008, Preliminary 1.2.3 DDR SDRAM Interface Pin Assignment s T able 5: DDR SDRAM Interface Pin Assignment s Pin Name I/O Pin Ty p e Power Rail Description M_CLKOUT M_CLKOUTn O SSTL VDD_M SDR[...]

  • Page 25

    Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 25 M_ST A RTBURST O SSTL VDD_M St art Burst 88F6281 indication of st arting a burst read transacti on. Asserted with the first M_CA Sn cycle of SDRAM access. NOTE[...]

  • Page 26

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 26 Document Classification: Proprietary Information December 2, 2008, Preliminary 1.2.4 PCI Express Interface Pin Assignment s T able 6: PCI Express Inte rface Pin Assignment s Pin Name I/O Pin Ty p e Power Rail Description PEX_CLK_P/N I/O HCSL PEX_A VDD[...]

  • Page 27

    Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 27 1.2.5 SA T A Interface Pin Assignments T able 7: SA T A Port Interface Pin Assignment Pin Name I/ O Pin Ty p e Power Rail Description SA T A0_T_P/ N SA T A1_T_[...]

  • Page 28

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 28 Document Classification: Proprietary Information December 2, 2008, Preliminary 1.2.6 Gigabit Ethernet Port Interface Pin Assignment s For additional information about the Gi gabit Ethernet port pin functions refer to Section 4.2, Gigabit Ethernet (GbE[...]

  • Page 29

    Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 29 GE_RXD[3:0] I CMOS VDD_GE_A RGMII Receive Data Contains t he recei ve data nibble input s that are synchronous to GE_RXCLK input rising/falli ng edge. MII/MMII[...]

  • Page 30

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 30 Document Classification: Proprietary Information December 2, 2008, Preliminary MPP[27:24]/ GE1[7:4] I CMOS V DD_GE_B RGMII Receive Dat a Contains t he recei ve data nibble input s that are synchronous to GE_RXCLK input rising/falli ng edge. MII/MMII R[...]

  • Page 31

    Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 31 MPP[32]/GE1[12] I/O CMOS VDD_GE_B RGMII T ransmit Clock RGMII transmit refere nce output clock for GE_TXD[3:0] and GE_TXCTL Provides 125 MHz, 25 MHz or 2.5 MHz[...]

  • Page 32

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 32 Document Classification: Proprietary Information December 2, 2008, Preliminary 1.2.7 Serial Management In terface (SMI) Interface Pin Assignment s T able 9: Serial Management In terface (SMI) Pin Assignment s Pin Name I/O Pin Ty p e Power Rail Descrip[...]

  • Page 33

    Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 33 1.2.8 USB 2.0 Interface Pin Assignment s T able 10: USB 2.0 Interface Pin Assignment s Pin Name I/O Pin Ty p e Power Rail Description USB_DP USB_DM I/O CML USB[...]

  • Page 34

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 34 Document Classification: Proprietary Information December 2, 2008, Preliminary 1.2.9 JT AG Interface Pin Assignment T able 1 1: JT AG Pin Assignmen t Pin Name I/O Pin Ty p e Power Rail Description JT_CLK I CMOS VDDO JT AG Clock Clock input f or the JT[...]

  • Page 35

    Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 35 1.2.10 Real Ti me Clock (RTC ) Interface Pin Assignment s T able 12: RTC Interface Pin Assignment s Pin Name I/O Pin Ty p e Power Rail Description RTC_XIN I An[...]

  • Page 36

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 36 Document Classification: Proprietary Information December 2, 2008, Preliminary 1.2.1 1 NA ND F lash Interface Pin Assignment T able 13: NAND Flash Interface Pin Assignment Pin Name I/O Pin Ty p e Power Rail Description NF_IO[7:0] I/O CMOS VDDO Data I [...]

  • Page 37

    Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 37 1.2.12 MPP Interface Pin Assignment T able 14: MPP Interface Pin Assignment Pin Name I/O Pin Ty p e Power Rail Description MPP[19:0] t/s I/O CMOS VDDO Multi Pu[...]

  • Page 38

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 38 Document Classification: Proprietary Information December 2, 2008, Preliminary 1.2.13 T wo-Wire Serial Interface (TWSI) Interface Note All of the TWSI signals are mu ltiplexed on the MPP pi ns (see Section 4, Pin Mul tiplexing, on page 51 ). T able 15[...]

  • Page 39

    Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 39 1.2.14 UART Interface Note All of the UART signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexi ng, on page 51 ). T able 16: UART Port 0/1 In[...]

  • Page 40

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 40 Document Classification: Proprietary Information December 2, 2008, Preliminary 1.2.15 Audio (S/PDIF / I 2 S) Interface Note  All of the Audio signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing, on page 51 ).  If the Audio i[...]

  • Page 41

    Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 41 1.2.16 Serial Peripheral Interface (SPI) Interface Note All of the SPI signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing, on page 51 ). [...]

  • Page 42

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 42 Document Classification: Proprietary Information December 2, 2008, Preliminary 1.2.17 Secure Digit al Input/Output (SDIO) Interface Note All of the SDIO signals are mult iplexed on the MPP pins (see Section 4, Pin Multiplexing, on page 51 ). T able 19[...]

  • Page 43

    Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 43 1.2.18 T ime Division Multiplexing (TDM) Interface Note  All of the TDM signals are multiplexed on the MPP pin s (see Section 4, Pin Multiplexing, on page 5[...]

  • Page 44

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 44 Document Classification: Proprietary Information December 2, 2008, Preliminary TDM_SPI_MOSI O CMOS VDDO / VDD_GE_B Serial SP I data from the host to the codec for re gister access. When TDM_SPI_CS is asserted low , the dat a is driven from the host on[...]

  • Page 45

    Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 45 1.2.19 T ransport Stream (TS) Interface Note  All of the TS signals are multiplexed on the MPP pin s (see Section 4, Pin Multiplexing, on page 51 ).  The[...]

  • Page 46

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 46 Document Classification: Proprietary Information December 2, 2008, Preliminary TSMP[7] I/O CMOS VDDO/ VDD_GE_B • Parallel Mode: TS0_DA T A[2 ]: Port0 T S Data bit 2 • Serial Mode: TS1_SYNC: P ort1 Sync/Fram e S tart Indicator or Packet Clock. The [...]

  • Page 47

    Pin and Signal Descriptions Pin Descriptions Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 47 1.2.20 Precise Timing Protocol (PTP) Interface Note All of the PTP si gnals are multiplexed o n the MPP pin s (see Section 4, Pin Multiplex ing, on page 51 ). [...]

  • Page 48

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 48 Document Classification: Proprietary Information December 2, 2008, Preliminary 1.3 Internal Pull-up and Pull-down Pins Some pins of the device package are connected to internal pull-up and pul l-down resistor s. When these pins are Not Connected (NC) [...]

  • Page 49

    Unused Interface S trapping Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 49 2 Unused Interface S trapping T able 2 4 lists the signal strapping to be used for systems in which some of the device interfaces are unused (not connected). T able 24: Unused [...]

  • Page 50

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 50 Document Classification: Proprietary Information December 2, 2008, Preliminary 3 88F6281 Pin Map and Pin List The 88F6281 pin list is provided as an Excel file attachment. T o open the att ached Excel pin list file, double-click the pin icons below: 8[...]

  • Page 51

    Pin Multiplexing Multi-Purpose Pins Functional Summary Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 51 4 Pin Multiplexing 4.1 Multi-Purpose Pins Functional Summary The 88F6281 device contains 50 Multi-Purpose Pins (MPP). Each one can be assigned to a d[...]

  • Page 52

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 52 Document Classification: Proprietary Information December 2, 2008, Preliminary MPP pins can be assigned to different functionalit ies through the MPP Co ntrol register , as shown in T able 25 . T able 26 l ists the functionality of the MPP pins, as de[...]

  • Page 53

    Pin Multiplexing Multi-Purpose Pins Functional Summary Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 53 T able 26: MPP Function Summary P i n nam e 0x 0 0x 1 0x 2 0x 3 0x 4 0x 5 0x C 0x D MPP[0 ] G PI O [0 ] (in/ out ) NF_IO[2] (in/ out ) SPI _SC n (out[...]

  • Page 54

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 54 Document Classification: Proprietary Information December 2, 2008, Preliminary T able 26: MPP Function Summa ry (Continued) MPP[1 8 ] GP O[ 18] (out onl y ) NF_IO[0] (in/ out ) ------ MPP[1 9 ] GP O[ 19] (out onl y ) NF_IO[1] (in/ out ) ------ MPP[2 0[...]

  • Page 55

    Pin Multiplexing Multi-Purpose Pins Functional Summary Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 55 T able 26: MPP Function Summa ry (Continued) MPP[3 6 ] GP IO[ 36] (in/ out ) T SMP[0 ] (in/ out ) T D M_ SPI _ CS1 (out ) - AU _ SPD I F I (i n) --- [...]

  • Page 56

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 56 Document Classification: Proprietary Information December 2, 2008, Preliminary Note  For MPPs assigned as NAND flash and SPI flash, wake-up mode after reset depends on Boot mod e (see the Boot Devi ce field in T able 32, Reset Configuration, on pag[...]

  • Page 57

    Pin Multiplexing Gigabit Ethern et (GbE) Pi ns Multiplexing on MPP Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 57 4.2 Gigabit Ethernet (GbE) Pins Multiplexing on MPP The 88F6281 has 14 dedicated pins for its GbE port. (12 RGMII pins, an MDC pin, and a[...]

  • Page 58

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 58 Document Classification: Proprietary Information December 2, 2008, Preliminary MPP_34 / GE1[14] NA MII1_TXEN (out) NA NA MPP_35 / GE1[15] NA MII1_RXERR (in) NA NA T able 27: Ethernet Port s Pins Multiplexing (Contin ued) Pin Name 1xGMII RGMII0+MII1/ M[...]

  • Page 59

    Pin Multiplexing TSMP (TS Multiplexing Pins) on MPP Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 59 4.3 TSMP (TS Multiplexing Pins) on MPP The TS interface can be configured to one of five mo des:  One or two serial in interfaces  One or two seri[...]

  • Page 60

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 60 Document Classification: Proprietary Information December 2, 2008, Preliminary 5 Clocking T able 29 lists the clocks in the 88F6281. T able 29: 88F6281Clocks Clock T ype Description CPU PLL • Reference clock: REF_CLK_XIN (25 MHz) • Derivative cloc[...]

  • Page 61

    Clocking Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 61 The following table lists the supported combinations of the CPU_C LK Frequ ency select, CPU_CLK to DDR CLK ra tio, and to CPU_CLK to CPU L2 clock ratio (see Section 6.5, Pins Sample Configuration[...]

  • Page 62

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 62 Document Classification: Proprietary Information December 2, 2008, Preliminary 5.1 S pread Spectrum Clock Generator (SSCG) The SSCG (S pread S pectrum Clock Generator) may be used to generate the spread spectrum clock for the PLL input. See SSCG Disab[...]

  • Page 63

    System Power Up/Down and Reset Setting s Power-Up/Down Seque nce Requirements Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 63 6 System Power Up/Down and Reset Settings This section provid es information about the de vice powe r-up/down sequence and con[...]

  • Page 64

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 64 Document Classification: Proprietary Information December 2, 2008, Preliminary Figure 2: Power-Up Sequence Example 6.1.2 Power-Down Sequence Requirement s There are no special requirements for the core supp ly to go down before non-core power, or for [...]

  • Page 65

    System Power Up/Down and Reset Setting s Hardware Reset Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 65 6.2.1 Reset Out Signal The device has a n optional SYSRST_OUT n output si gna l, multip lexed on an MPP pin, that is used as a reset request from th[...]

  • Page 66

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 66 Document Classification: Proprietary Information December 2, 2008, Preliminary 6.3 PCI Express Reset 6.3.1 PCI Express Root Complex Reset As a Root Complex, the d evice may generate a Hot Reset to the PCI Express port. Upo n CPU setting the PCI Expres[...]

  • Page 67

    System Power Up/Down and Reset Setting s Pins Sample Configurat ion Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 67 In each row of Ta b l e 3 2 , the order of the pins is from MSb to LSb (e.g., for in the row CPU_CLK Frequency Select, MPP[2] is the MSB[...]

  • Page 68

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 68 Document Classification: Proprietary Information December 2, 2008, Preliminary MPP[33], NF_ALE, NF_REn, NF_CLE CPU_CLK to DDR CLK Ratio 0x0–0x3 = Reserved 0x4 = 3:1 0x5 = Reserved 0x6 = 4:1 0x7 = 4.5:1 0x8 = 5:1 0x9 = 6:1 0xA–0xF = Reserved NOTE: [...]

  • Page 69

    System Power Up/Down and Reset Setting s Pins Sample Configurat ion Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 69 GE_TXD[2:0] B oot Device 0x0 = Reserved 0x1 = Reserved 0x2 = Boot from SPI flas h (SPI_CSn on MPP[7] ) 0x3 = Reserved 0x4 = Boot from SP[...]

  • Page 70

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 70 Document Classification: Proprietary Information December 2, 2008, Preliminary 6.6 Serial ROM Initialization The device supports initialization of ALL of its inte rnal and configuration re g isters through the TWSI master interfac e. If serial ROM ini[...]

  • Page 71

    System Power Up/Down and Reset Setting s Boot Sequence Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 71 The serial ROM initialization logic reads eight byte s at a time. It performs address decoding on the 32-bit address being read, and based on ad dres[...]

  • Page 72

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 72 Document Classification: Proprietary Information December 2, 2008, Preliminary Upon completing the above sequence, th e internal CPU rese t is de-asserted, and the CPU starts executing boot code from th e boot device (SPI flash, NAND flash, or interna[...]

  • Page 73

    JT AG Inte rfa ce T AP Controller Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 73 7 JT AG Interface T o enable board testing, the devi ce supports a te st mode operatio n through its JT AG boundary scan interface. The JT AG interface is IEEE 1 149.1 st[...]

  • Page 74

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 74 Document Classification: Proprietary Information December 2, 2008, Preliminary 7.3 Byp ass Register The Bypass register (BR) is a single bit serial shif t register that connects TDI to TDO, when the IR holds the Bypass command, and the T AP FSM is in [...]

  • Page 75

    Electrical Specifications (Preliminary) Absolute Maximum Ratings Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 75 8 Electrical S pecifications (Preliminary) 8.1 Absolute Maximum Ratings Note The numbers specified in this section are PRELIMINARY and SUBJ[...]

  • Page 76

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 76 Document Classification: Proprietary Information December 2, 2008, Preliminary RTC_A VDD -0.5 2.2 V Analog supply for: RTC int er fa ce T C -40 125 ° C Case temperature T STG -40 125 ° C Storage temper ature T able 35: Absolute Maximum Ratings (Cont[...]

  • Page 77

    Electrical Specifications (Preliminary) Recommended Op erating Cond iti ons Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 77 8.2 Recommended Operating Conditions T able 36: Recommended Operating Conditions Parameter Min Ty p Max Units Co mments VDD 0.95[...]

  • Page 78

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 78 Document Classification: Proprietary Information December 2, 2008, Preliminary XT AL_A VDD 1.7 1.8 1.9 V Analog supply for: Internal clock i nverter for cryst al support and curre nt source for SA T A and USB PHYs RTC_A VDD 1.7 1.8 1.9 V Analog supply[...]

  • Page 79

    Electrical Specifications (Preliminary) Thermal Power Dissipation Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 79 8.3 Thermal Power Dissip ation The purpose of the Thermal Power Dissipation table is to support system engineering in ther ma l design. . [...]

  • Page 80

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 80 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.4 Current Consumption The purpose of the Current Consum ption table is to support board power design and power module selection. . Notes: 1. Current in mA is calculated u[...]

  • Page 81

    Electri ca l Specif ic at io ns DC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 81 8.5 DC Electrical S pecifications 8.5.1 General 3.3V (CMOS) DC Electrical Sp ecifications The DC electrical specificati ons in Ta b l e 3 9 are[...]

  • Page 82

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 82 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.5.2 RGMII, SMI and REF_CLK_XI N 1.8V (CMOS) DC Electrical S pecifications In the following t able, for the RGMII inte rface, VDDIO means the VDD_GE_A power rail. In the f[...]

  • Page 83

    Electri ca l Specif ic at io ns DC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 83 8.5.3 SDRAM DDR2 Interface DC Electrical Specifications In the following table, VREF is VDD_ M/2 and VDDIO means the VDD_M pow er rail. T able [...]

  • Page 84

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 84 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.5.4 T wo-Wire Serial Interface (TWSI) 3.3V DC Electrical S pecifications In the following table, VDDIO means the VDDO power rail. T able 42: TWSI Interface 3.3V DC Electr[...]

  • Page 85

    Electri ca l Specif ic at io ns DC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 85 8.5.6 T ime Division Multiplexing (TDM) 3.3V DC Electrical S pecifications In the following table VDDIO means the either the VDDO or the VDD_GE[...]

  • Page 86

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 86 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.6 AC Electrical S pecifications See Section 8.7, Differential Interface Elec trical Ch aracteristics, o n page 1 18 for differential interface specifications. 8.6.1 Refer[...]

  • Page 87

    Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 87 Notes: 1. Slew rate is d efined from 20% to 80% of the reference clock signal. 2. For additional information regarding configuri ng this clock,[...]

  • Page 88

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 88 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.6.2 SDRAM DDR2 Interface AC Timing 8.6.2.1 SDRAM DDR2 In terface AC Timing T able T able 46: SDRAM DDR2 Interface AC T iming T able Mi n Ma x C loc k f r equenc y f C K M[...]

  • Page 89

    Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 89 T able 47: SDRAM DDR2 Interface Address T iming T able Mi n Ma x A ddres s and C ontr ol v ali d output ti m e bef ore C LK-C Lk n r ising edge[...]

  • Page 90

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 90 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.6.2.2 SDRAM DDR2 Clock Specifications T able 48: SDRAM DDR 2 Clock Specifications D e s c r ipti on S y m bol M i n M ax U nits N ote s C l oc k period j i tter tJI T (pe[...]

  • Page 91

    Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 91 8.6.2.3 SDRAM DDR2 In terface T est Circuit Figure 5: SDRAM DDR2 Interface T est Circuit 8.6.2.4 SDRAM DDR2 Inte rface AC Timing Diagrams Figur[...]

  • Page 92

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 92 Document Classification: Proprietary Information December 2, 2008, Preliminary Figure 7: SDRAM DDR2 Interface Address and Con trol AC Timing Diagram Figure 8: SDRAM DDR2 Interf ace Read AC Timing Dia gram ADDRESS/ CONTROL tIPW tAOVB tAOVA CLKn CLK tCL[...]

  • Page 93

    Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 93 8.6.3 Reduced Gigabit Media Independent Interface (RGMII) AC Timing 8.6.3.1 RGMII AC Timing T able T able 49: RGMII 10/100/1000 AC Timing T abl[...]

  • Page 94

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 94 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.6.3.2 RGMII T est Circuit Figure 9: RGMII Te s t C i r c u i t 8.6.3.3 RGMII AC Timing Diagram Figure 10: RGMII AC Timing Diagram CL Test Point (At Tr ansmitte r) TX DATA[...]

  • Page 95

    Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 95 8.6.4 Gigabit Media Independen t Interface (GMII) AC T iming 8.6.4.1 GMII AC Timing T able T able 51: GMII AC Timing T able 8.6.4.2 GMII T est [...]

  • Page 96

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 96 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.6.4.3 GMII AC Timing Diagrams Figure 12: GMII Output AC T iming Diagram Figure 13: GMII Input AC Timing Diagram GTX_CLK TXD, TX_EN, TX_ER VIH(min) VIL(max) VIH(min) VIL(m[...]

  • Page 97

    Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 97 8.6.5 Media Independent Interfac e/Marvell Media Independent Interface (MII/MMII) AC Timing 8.6.5.1 MII/MMII MAC Mode AC Timing T able T able 5[...]

  • Page 98

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 98 Document Classification: Proprietary Information December 2, 2008, Preliminary Figure 16: MII/MMII MAC Mode Input AC Timin g Diagram tHD Vih( min) Vih( min) Vil(m ax) tSU RX_CLK RXD, RX_ EN, RX_E R[...]

  • Page 99

    Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 99 8.6.6 Serial Management In terface (SMI) AC Timing 8.6.6.1 SMI Master M ode AC Timing T able T able 53: SMI Master Mode AC Timing T able 8.6.6.[...]

  • Page 100

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 100 Document Classification: Proprietary Information December 2, 2008, Preliminary Figure 18: MDC Master Mode T est Circuit 8.6.6.3 SMI Master M ode AC Timing Diagrams Figure 19: SMI Master Mode Output AC T iming Diagram Figure 20: SMI Master Mode Input [...]

  • Page 101

    Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 101 8.6.7 JT AG Interface AC Timing 8.6.7.1 JT AG Interface AC Timing T able T able 54: JT AG Interface AC Timing T able 8.6.7.2 JT AG Interface [...]

  • Page 102

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 102 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.6.7.3 JT AG Interface AC Timing Diagrams Figure 22: JT AG Interface Output Delay AC Timing Diagra m Figure 23: JT AG Interface Input AC T iming Diagram JTCK TDO Tprop (m[...]

  • Page 103

    Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 103 8.6.8 T wo-Wire Serial Interface (TWSI) AC T iming 8.6.8.1 TWSI AC Timing T able T able 55: TWSI Master AC T iming T able T able 56: TWSI Sla[...]

  • Page 104

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 104 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.6.8.2 TWSI T est Circuit Figure 24: TWSI T e st Circuit 8.6.8.3 TWSI AC Timing Diagrams Figure 25: TWSI Output Delay AC Timing Diagram Figure 26: TWSI Input AC Timing Di[...]

  • Page 105

    Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 105 8.6.9 Sony/Philip s Digit al Inter connect Format (S/PDIF) AC Ti m i n g 8.6.9.1 S/PDIF AC Timing T able T able 57: S/PDIF AC Timing T able D[...]

  • Page 106

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 106 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.6.9.2 S/PDIF T est Circuit Figure 27: S/PDIF T est Circuit CL Test Point[...]

  • Page 107

    Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 107 8.6.10 Inter-IC Sound Interface (I 2 S) AC T iming 8.6.10.1 Inter-IC Sound (I 2 S) AC T iming T able T able 58: Inter-IC Sound (I 2 S) AC T i[...]

  • Page 108

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 108 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.6.10.3 Inter-IC Sound (I 2 S) AC T iming Diagra ms Figure 29: Inter-IC Sound (I 2 S) Output Delay AC Timing Diagram Figure 30: Inter-IC Sound (I 2 S) Input AC T iming Di[...]

  • Page 109

    Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 109 8.6.1 1 Time Division Multiplexi ng (TDM) Interface AC T iming 8.6.1 1.1 TDM Interface AC Timing T able T able 59: TDM Interface AC Timing T [...]

  • Page 110

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 1 10 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.6.1 1.3 TDM Interface Timing Diagrams Figure 32: TDM Interface Outpu t De lay AC Timing Diagram Figure 33: TDM Interface Input De lay AC Timing Diagram tD PCLK DTX tC t[...]

  • Page 111

    Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Cl assification: Proprietary Information Page 1 1 1 8.6.12 Serial Peripheral Interface (SPI) AC Timing 8.6.12.1 SPI (Master M ode) AC Timing T able T able 60: SPI (Master Mode) AC Ti ming T ab[...]

  • Page 112

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 1 12 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.6.12.3 SPI (Master Mode) Timing Diagrams Figure 35: SPI (Master Mode) Output AC Timing Diagram Figure 36: SPI (Master Mode) Input AC Ti ming Diagram SCLK tCL tCH Data O[...]

  • Page 113

    Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 1 13 8.6.13 Secure Digit al Input/Outp ut (SDIO) Interface AC Timing 8.6.13.1 Secure Digi tal Input/Output (SDI O) AC T iming T able T able 61: SD[...]

  • Page 114

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 1 14 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.6.13.3 Secure Digital Input/Output (SDI O) AC T iming Diagrams Figure 38: SDIO Host in High Spe ed Mode Output AC Timing Diagram Figure 39: SDIO Host in High S pe ed Mo[...]

  • Page 115

    Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 1 15 8.6.14 T ransport Stream (T S) Interface AC Timing 8.6.14.1 T ransport S tream Interface AC Timing T able T able 62: T ransport S tream Outpu[...]

  • Page 116

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 1 16 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.6.14.2 T ransport S tream Interface T est Circuit Figure 40: T ran sp ort Stream Interface T est Ci rcuit 8.6.14.3 T ransport S tream Interface Timing Diagrams Figure 4[...]

  • Page 117

    Electri ca l Specif ic at io ns AC Electrical Specifications Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 1 17 Figure 42: T ran sp ort Stream Input Interface AC Timing Dia gram Vih(m in) Vil (max) Vih(m in) Vil (max) tSU tLO W tH IG H Clo ck Data In tH[...]

  • Page 118

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 1 18 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.7 Differential Interface Electrical Characteristics This section provides the reference clock, AC, and DC characteristics for the following differential interfaces: [...]

  • Page 119

    Electri ca l Specif ic at io ns Differential Interface Electrical Characteristics Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, Preliminary Document Clas sification: Proprietary Information Page 1 19 PCI Express Interface S pread Spectrum Re quirements T able 65: PCI Express Interface S pread S pectrum Requirement s S [...]

  • Page 120

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 120 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.7.2 PCI Express Interface Electrical Characteristics 8.7.2.1 PCI Express Interface Driver and Receiver Characteristics T able 66: PCI Express Interface Driver and Receiv[...]

  • Page 121

    Electri ca l Specif ic at io ns Differential Interface Electrical Characteristics Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 121 8.7.2.2 PCI Express Interface T est Circuit Figure 43: PCI Express Inter face T est Circuit When m easuring Transmit ter[...]

  • Page 122

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 122 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.7.3 SA T A Interface Electrical Characteristics The driver and receiver characteristics for the SA T A-I Interface Gen1i Mode and the SA T A-II Interface Gen2i Mode are [...]

  • Page 123

    Electri ca l Specif ic at io ns Differential Interface Electrical Characteristics Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 123 8.7.3.1 SA T A-I Interface Ge n1i Mode Driver and Receiver Characteristics T able 67: SA T A-I Interface Gen1i Mode Driv[...]

  • Page 124

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 124 Document Classification: Proprietary Information December 2, 2008, Preliminary 8.7.3.2 SA T A-II Interface Gen2i Mode Driver and Receiver Characteristics T able 68: SA T A-II Interface Gen2i Mode Driver and Receiv er Characteristics D e s cr ipt ion [...]

  • Page 125

    Electri ca l Specif ic at io ns Differential Interface Electrical Characteristics Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 125 8.7.4 USB Electrical Characteristics 8.7.4.1 USB Driver and Receiver Characteristics T able 69: USB Low Speed Driver and[...]

  • Page 126

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 126 Document Classification: Proprietary Information December 2, 2008, Preliminary T able 70: USB Full Speed Driver and Receiver Characteristics Mi n Ma x Baud R ate BR M bps - Baud rate toleranc e Bppm - 2500.0 2500.0 ppm - O uput s i ngl e ended hi gh [...]

  • Page 127

    Electri ca l Specif ic at io ns Differential Interface Electrical Characteristics Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 127 T able 71: USB High Speed Driver and Receiver Charac teristics 8.7.4.2 USB Interface Driver W aveforms Figure 44: Low/Fu[...]

  • Page 128

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 128 Document Classification: Proprietary Information December 2, 2008, Preliminary Figure 45: High Sp eed TX Eye Diagram Pattern T emplate Figure 46: High Sp eed RX Eye Diagram Pattern T emplate +40 0mV Diff erential - 400m V Diff erential 0 Volts Diffe [...]

  • Page 129

    Thermal Dat a (Preliminary) Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 129 9 Thermal Dat a (Preliminary) T able 7 2 provides the p ackage thermal data for the de vice. This dat a is derived from simula tions that were run according to the JEDEC stan[...]

  • Page 130

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 130 Document Classification: Proprietary Information December 2, 2008, Preliminary 10 Package This section provides the 88F6281 package drawing an d dimensions. Figure 47: HSBGA 288-pin Package and Dimensions[...]

  • Page 131

    Package Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 131 T able 73: HSBGA 288-pin Package Dimensions Symbol Common Dime nsion (in millimeters) Package HSBGA Body size X D 19.000 Y E 19.000 Ball pitch Xe D 1 . 0 0 0 Ye E 1 . 0 0 0 T otal thickness A 1.[...]

  • Page 132

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 132 Document Classification: Proprietary Information December 2, 2008, Preliminary 11 Part Order Numbering/Package Marking 1 1 .1 Part Order Numbering Figure 48 shows the part order nu mbering scheme for the 88F6281. Refer to Marvell Field Application En[...]

  • Page 133

    Part Order Numberi ng/Package Markin g Package Marking Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 133 1 1 .2 Package Marking Figure 49 shows a samp le Commercial package marking a nd pin 1 location for the 88F6281. Figure 49: Commercial Package Mar [...]

  • Page 134

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 134 Document Classification: Proprietary Information December 2, 2008, Preliminary A Revision History T able 75: Revision Histor y Revision Date Comment s E Dec ember 2 , 2008 Revision 1. In Figure 1, 88F62 81 Pin Logic Diagram, on p age 18 , changed the[...]

  • Page 135

    Revision History Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 135 17. In T able 36, Recommended Operating Conditio ns, on page 77 : • For VHV , revised the two p arameters to VHV (dur ing eFuse Burning mode) and VHV (during eFuse Read ing mode) and [...]

  • Page 136

    88F6281 Hardware S pecifications Doc. No. MV -S104859-U0 Rev . E Copyright © 2008 Marvell Page 136 Document Classification: Proprietary Information December 2, 2008, Preliminary 17. In Section 4.1, Multi-Purpose Pins Functional Summary , on p age 51 : • Changed all references to MPP[0 ] and MPP[1 1] from GPI to GPIO. • Changed the MPP[6] row i[...]

  • Page 137

    Revision History Copyright © 2008 Marvell Doc. No. MV-S1 04859-U0 Rev . E December 2, 2008, P reliminary D ocument Classification: Proprietary Information Page 137 38. Revised Figure 25, TWSI Output Delay AC T iming Dia gram, on p age 104 so that it shows SDA t OV relative to the SCK falling edge, as sho wn in the two tables that proceed the f igu[...]

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    Marvell. Moving Forw ard Faster Marvell Semiconductor, Inc. 5488 Marvell Lane Santa Clara, CA 95054, USA Tel: 1.408.222.2500 Fax: 1.408.752.9028 www.marvell.com Contact I NFORMATION[...]